Indent of forever body is incorrect
Status: Beta
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mballance
I use Ctrl + I to auto format SystemVerilog files by SVE 1.9.9.
I find the following code is incorrectly indented:
module a; initial begin forever@(posedge clk) begin if(b) begin end end end endmodule
The "if" block is incorrectly indented by 16 whitespaces. The correct whitespaces count should be the count of "forever" block indent whitespaces (8) plus 4, i.e., 12. The attached file is the example file.
Fixed in 2.0.0
Thanks.