#487 Indent of forever body is incorrect

[Meng-Yuan Huang]

I use Ctrl + I to auto format SystemVerilog files by SVE 1.9.9.
I find the following code is incorrectly indented:

module a;
    initial begin
        forever@(posedge clk) begin
                if(b) begin
                end
            end
    end
endmodule

The "if" block is incorrectly indented by 16 whitespaces. The correct whitespaces count should be the count of "forever" block indent whitespaces (8) plus 4, i.e., 12. The attached file is the example file.

[StevenAZ]

Fixed in 2.0.0

[Meng-Yuan Huang]

Thanks.