sim-sim

HDL Analyzer and Netlist Architect (HANA): An open source analysis and synthesis tool for design written in Verilog 2001 HDL

Project Activity

See All Activity >

License

GNU General Public License version 2.0 (GPLv2)

Follow sim-sim

sim-sim Web Site

Other Useful Business Software

Level Up Your Cyber Defense with External Threat Management

See every risk before it hits. From exposed data to dark web chatter. All in one unified view.

Move beyond alerts. Gain full visibility, context, and control over your external attack surface to stay ahead of every threat.

Try for Free

Rate This Project

User Ratings

4.0 out of 5 stars

★★★★★

★★★★

★★★

★★

★

ease 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 5 / 5

features 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 4 / 5

design 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 3 / 5

support 1 of 5 2 of 5 3 of 5 4 of 5 5 of 5 2 / 5

User Reviews

Filter Reviews:

All

frewcen Edited 2013-10-02

sim-sim is perfect tool for synthesis, although I have noticed some problems with output formatting, netlist optimalization and absence of documentation.
xtofb Posted 2013-07-20

This is AWESOME indeed. But it is hard to find and it really could use some documentation...
ivanhutchins Posted 2013-06-01

Sim-sim works excellent.

1 user found this review helpful.
clifford_wolf Posted 2012-05-23

This project is AWESOME! Please present it more prominently so others can find it easier. At first I didn't try it because there was so little information here..

Additional Project Details

Operating Systems

Linux

User Interface

Programming Language

C++, Perl, VHDL/Verilog, Yacc

Registered

2006-07-12

Report inappropriate content