the sdasstm8 assembler code is in error for the following 2 instructions:
div x,y code 0x62 instead of 0x65
jrxx . (conditonnal jump to istself) give a relative address short of 1 byte. It jump after the 0x90 prefix. It is ok for no prefix jrxx instructions.
I just tested a small sample program using current SDCC. div x, y is assembled to 0x62, just as the STM8 CPU programming manual says it should.
DIV X,Y is not a valid instruction and should trigger an error message. The valid instruction is DIVW X,Y with opcode 0x65. opcode 0x62 is for DIV X,A
Regarding jrh, etc: These actually seem wrong according to the STM8 CPU programming manual. However, before changing it in the assembler, I'd like to see this verified on real hardware (the 2-byte jrxx instructions add the 2 to the pc before addign the offset, so what about these 0x90-prefixed 3-byte jrxx? Do they also add 2, like the manual says, or 3, like the assembler assumes??
Last edit: Philipp Klaus Krause 2020-04-29
Using the assembler in the STVP tool, it looks like the 0x90-prefixed opcodes add 3.
So 0x8000 + 2 + 6 = 0x8008.
So 0x8010 + 3 + 5 = 0x8018.
And an example for a conditional "jump to self":
So 0x8020 + 3 - 3 = 0x8020.
The PM0044 Rev 2 manual says on JRxx:
In the instruction list lgth is listed as 2 or 3 depending on the 0x90 prefix.
Funnily enough, for the JRH instruction used in the example above, the manual shows a 0x29 opcode in the overview list. But 0x29 is the JRV instruction in the same list. The specific table in the JRxx section lists JRH correctly as 0x90 0x29.
For the instruction JRH . it should be 90 29 FD as it is it jump to 29 which is JRV