Re: [Scst-devel] Weird SSD performance

[Bart V. A. <bva...@ac...>]

On 06/26/14 02:39, Matteo Tescione wrote:
> However, if I try multiple mask like 6 or FE, FC and the like, the irq are
> not spread along those multiple cpu mask. ie the ssd controller on irq 48
> keeps going on CPU1, and never on CPU2.

Most x86-64 systems do not support spreading processing of a single
interrupt over multiple CPU cores. This is why an interrupt is processed
by the CPU core whose number corresponds to the lowest bit that has been
set in /proc/irq/<n>/smp_affinity.

More information about this topic can be found in the Intel x86-64
Architecture Software Developer Manual. The relevant sections are those
about physical and logical interrupt delivery destination mode of the
APIC. This piece of kernel code from arch/x86/kernel/apic/apic_flat_64.c
controls which mode is chosen:

static int physflat_probe(void)
{
    if (apic == &apic_physflat || num_possible_cpus() > 8)
        return 1;

    return 0;
}

In other words, logical destination mode (the mode in which interrupt
spreading is possible) is only chosen on systems with <= 8 CPU cores. So
far I have only encountered one x86-64 motherboard that actually spread
interrupts over CPU cores, namely the ASUS P5Q Deluxe motherboard.

Bart.