Re: [Scst-devel] Marvell MV64460/64461/64462 HBA

[Vladislav B. <vs...@vl...>]

Hi Ravi,

Ravi Shankar, on 03/25/2010 05:06 PM wrote:
> Andy Yan, on 03/24/2010 12:12 PM wrote:
>> Vlad, Thanks, I missed the message. The MV64xx chip can handle Max
>> 64 SG entry
> 
> Do you mean it can handle <=64 SG  entries?  If so, why it works for 
> Jayaraman with 256?
> 
>> and I have a suggestion with this issue long time ago, can SCST
>> split the request SG list and then send to low level target driver
>> for such case?
> 
> Hmm, I don't remember you asked about it..
> 
> Yes, it's possible, but will need some effort, so, before doing it
> I'd like to be 100% sure that the limit is really so low.
> 
> Hi Vlad/Andy,
> 
> Newer x86 HW such as Nehalem EX/Boxboro IOH chipset supports DVMA. As
> such should scst modified to take advantage of single SG entry ?. The
> IOMMU and PCI nexus driver manages SG page list and OS sees only
> single SG/cookie.
> 
> I can look into porting this to scst if you wish.

It would be a good idea. AFAIK, IOMMU should be transparent for drivers, 
so, most likely, there only thing you need to do is to check if the 
system supports IOMMU and, if yes, increase in struct scst_tgt_template 
SG entries limitation sg_tablesize to a higher value up to no limit 
(0xFFFF).

BTW, IOMMU might be the reason why mvsas_tgt works for Jayaraman after 
64->256 increasing scst_tgt_template.sg_tablesize.

Thanks,
Vlad