Re: [Qucs-bugs] New bug in Qucs Verilog-A modelling system

[Guilherme B. T. <gui...@gm...>]

Hi Mike,

Not yet solved, but this might work: 
https://sourceforge.net/p/qucs/bugs/150/
I will try to test it on the following days.

Regards,
Guilherme

On 4/24/14, 11:33 AM, mike brinson wrote:
> While working on new RF component models for Qucs a bug has emerged
> which causes Qucs to core dump.
>
> The problem occurs when ASCO is used to optimize circuit performance,
> where the circuit includes a compiled Verilog-A model constructed using the new dynamic_loader system.
>
> In the case of a simple 2 resistor voltage divider small signal AC analysis works without problems.
> However, when R2 set to 50 Ohms and R1 is optimized in the region 1 Ohm to 100 Ohms to give Vres  0.5 V, Qucs core dumps. (Vinput AC is set to 1V)
>
> I have also tested Qucs/ASCO using a similar circuit but with transient analysis.  The same result occurs.
>
> Also please note if R1 is replaced by a subcircuit made up of standard Qucs parts optimization using ASCO works without problems.
>
>   
> Mike Brinson
>
>
> mbr...@ya...
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