Reported by Mike Brinson:
While working on new RF component models for Qucs a bug has emerged
which causes Qucs to core dump.
The problem occurs when ASCO is used to optimize circuit performance,
where the circuit includes a compiled Verilog-A model constructed using the new dynamic_loader system.
In the case of a simple 2 resistor voltage divider small signal AC analysis works without problems.
However, when R2 set to 50 Ohms and R1 is optimized in the region 1 Ohm to 100 Ohms to give Vres 0.5 V, Qucs core dumps. (Vinput AC is set to 1V)
I have also tested Qucs/ASCO using a similar circuit but with transient analysis. The same result occurs.
Also please note if R1 is replaced by a subcircuit made up of standard Qucs parts optimization using ASCO works without problems.
For security reasons
qucsatorrequires the path and the name of the dynamic objects (compiled VA models).Currently
ascodoes not propagate arguments down to the simulator.One alternative is to use a
general.shwrapping script to callqucsatorwith the required arguments.Looking into the ASCO code
errfunc.cfile:Not sure how the
general.shwould work on Windows.No, the general.sh will not work. To patch asco is also not ideal.
Asco call the qucastor inside error function. Hence, several function calls will need to be modified just to pass the remaining qucs arguments (-p -m).
Perhaps annotation of the netlist with (-p -m) dynamic VA modules is better. If the netlist is annotated the arguments can be ignored. Looking into it.
See current workaround in branch: dyload-annotate
If dynamic modules are loaded and used on the netlist, the project path and module names are appended to the netlist as comments.
Something like
Qucsator then looks for
--pathand--moduleto extract the data. This is a bit inefficient as the netlist has to be read in advance. Alternatives: check for a configuration file, use environment variables, do the check during normal netlist parse.I believe it make sense to annotate the netlist directly. Specially if one thinks about hierarhical projects, with multiple modules living in different locations (situation not yet tested).
merged into master