It appears that in the QP ARM-CM port is doing things based on __ARM_ARCH that are not applicable to the Microchip SAML11 which is ARMv8-M. This causes QP to crash during initialization.
It seems like the threadX port uses a special macro called TX_PORT_USE_BASEPRI and freeRTOS does something similar.
I'm not sure if there are other issues throughout the code I'll encounter yet. I'm using arm-none-eabi-g++ toolchain.
Here are the available ARM flags, I'm not sure there is a way to tell if it's available or not directly, maybe it is available for some M23s:
https://developer.arm.com/documentation/101754/0623/armclang-Reference/Other-Compiler-specific-Features/Predefined-macros?lang=en
Here is the ARM M23 technical reference manual that does not mention the BASEPRI register
https://www.bing.com/ck/a?!&&p=9677a783b3f9b0968c8939a5196524cecd92d31c1d61012f7e72ee0357a55ce3JmltdHM9MTczMzM1NjgwMA&ptn=3&ver=2&hsh=4&fclid=1e813af7-5639-6c4d-23be-2fc257946dc0&psq=ARM+Cortex-M23+Processor+Technical+Reference+Manual&u=a1aHR0cHM6Ly9kZXZlbG9wZXIuYXJtLmNvbS9kb2N1bWVudGF0aW9uL2RkaTA1NTAvYy8&ntb=1
Note that the ARMv8-M reference manual does mention it... so that's confusing.
I'm not sure where else it could have issues yet, hoping you could provide some guidance.
Anonymous
Thank you for reporting.
The existing QP ports to ARM Cortex-M indeed use only the
__ARM_ARCHpre-defined macro, and here only two cases:__ARM_ARCH == 6(ARMv6-M, Corex-M0/M0+/M1)__ARM_ARCH > 6(ARMv7-M and higher)Case 2. assumes the presence of the
BASEPRIregister, which is then used for a selective critical section.The existing ports have been tried with ARMv8-M, and work very well for Cortex-M33. In fact, the STM32 NUCLEO-U545RE (Cortex-M33) board has become now the default target for all examples and tests.
But the QP ports have not been tried on Cortex-M23 just yet. And indeed, I don't see
BASEPRIlisted in the "M23 Programmers Model".I'm not sure yet how to approach this. It seems that ARM Ltd. always invents a way to break their own rules...
--MMS
The QP/C/C++ ports to ARM Cortex-M have been restructured to treat BASEPRI separately from the ARM architecture. New macro
QF_USE_BASPRIhas been introduced, which controls the use of BASEPRI. The macro also allows you to configure the BASEPRI threshold. Also, the macroQF_USE_BASPRIhas been added to theqp_config.h/hppfiles for Cortex-M.All these changes have been pushed to GitHub repos:
Examples have also been updated accordingly (with new
qp_config.h/hppfiles):Please check it out and perhaps post to this bug ticket how this works for you. (You need to comment out
QF_USE_BASPRIdefinition inqp_config.h/hppfor your Cortex-M23).--MMS
Yeah they sure do invent ways to do that haha!
I re-integrated the software with the new code you wrote as a submodule. I can confirm that it works ( at least for this simple example I'm running with a blinky LED )!
The changes in 8.0.1 resolve this ticket (#369, and also #368).
Thank you very much!
Hi Alexander,
Thank you for confirming and reporting in the first place.
This ticket will be kept open until the official QP release with the fixes.
--MMS
Current QP ARM Cortex-M ports (in QP/C and QP/C++) assume that ARMv8-M supports the BASEPRI register. However, Cortex-M23 does NOT have BASEPRI, which is an exception.
This issue will be fixed by decoupling the critical section implementation (based on PRIMASK or BASEPRI) from the ARM architecture. The critical section policy for ARM-CM will be configurable by the macro
QF_USE_BASEPRI. When this macro is defined, critical section will be based on BASEPRI, whereas the BASEPRI-threshold for "kernel unaware" ISRs will be determined by the numerical value ofQF_USE_BASEPRI. This implementation is already available on GitHub:--MMS
Fixed in QP/C/C++ 8.0.1.
--MMS