Open Programmer / Discussion / Open Discussion: [16F18xxx & 152xx] OPGUI cannot write configuration registers1-5

Alberto Maccioni - 2025-05-03

Source combination was fine.
I'm noticing that the options were exchanged somehow.
152XX use bulk erase without payload, so using 0x20 is not correct.
Try again with this file, I put 0x0 now, so it does regular bulk erase with proper address.

{"16F15214,16F15224,16F15244,16F15254,16F15274", PIC16,8.5,1,Read16F18xxx,{0x1000,0,0,0},0,Write16F18xxx,{0x1000,0,0x0},0},

It would then exhibit the old bug of writing the first line wrong, but at this point I'm not sure what was working and what was not.
Here the line if you want to try the reboot option

{"16F15214,16F15224,16F15244,16F15254,16F15274", PIC16,8.5,1,Read16F18xxx,{0x1000,0,0,0},0,Write16F18xxx,{0x1000,0,0x40},0},

deviceRW.c
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- Dan Skareda - 2025-05-03
  
  Yes, there is an error with your deviceRW.c file, which is why only the first line of code is not written. However, the erase runs fine.
  If I replace 0x0 with 0x40 (in deviceRW.c), then everything is fine and the code is flashed correctly.
  
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  - Alberto Maccioni - 2025-05-05
    
    So it seems that the workaround will stay.
    Apart from this, are there other devices that still have problems?
    
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    - Dan Skareda - 2025-05-06
      
      I will try all 21 different device types, however it would be very helpful if you could generate file opgui.exe for windows from the latest versions of the files.
      
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      - Alberto Maccioni - 2025-05-06
        
        Sure, here the file
        
        opgui.exe
        
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        Dan Skareda - 2025-05-08
        
        1) Please add the type of circuit 18F06Q20. It is not in the list. I couldn't try it.
        2) Programming the chip 16F17115 and 16F17126 does not work. No code is programmed. It seems that erase works correctly, but any programming does not. See. log.txt
        3) 16LF1705 - I tried to program the blink project, the result was all zeros everywhere. Then I used the erase function, but there are still all zeros everywhere.
        4) I have the opportunity to get DSPIC33CK256MP505 and PIC32MX130F256B. Will you support them in the future? Or we could try it together...
        5) ok: 10f322, 12f1572, 12f1840, 12f509, 12f617, 16f13115, 16f1503, 16f15214, 16f15225, 16f15325, 16f15355, 16f18014, 16f18015, 16f18026, 16f18115, 16f18325, 18f16q41, 18f25k50.
        
        Last edit: Dan Skareda 2025-05-08
        
        Log.txt
        
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        Alberto Maccioni - 2025-05-08
        
        Lots of points today!
        18F06Q20: it has a flash lock feature so I did not want to add support without trying it myself; I may implement just the regular read/write.
        16F1711X: it seems I made the same mistake as with 180xx, bulk erase with payload; easily fixable (attached file).
        16LF1705: strange since I verified the 16F1703; I will try again my chip.
        DSPIC33CK256MP505: I have to check if the algorithm is similar to other dsPIC33.
        PIC32MX130F256B: once I tried a PIC32 but had some difficulties; then realized that most ARM designs come with a bootloader, so nobody would ever need support for it; until now.
        List of models: good to know that they work. I can't turn them "verified" because in case of problems I wouldn't be able to troubleshoot myself, but I'm thinking about starting a "user verified" thread.
        
        Last edit: Alberto Maccioni 2025-05-08
        
        deviceRW.c
        
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        Dan Skareda - 2025-05-09
        
        1) Both 16F171xx devices can be programmed fine with your latest modification.
        2) I tried 18F06Q20 with device option 18F06Q40 and programming (and subsequent reading) went without errors and the led blinked. The programmer only reported unknown device.
        3) As for 16LF1705, programming is fine. I found a short circuit on my breadboard with smd device. After removing the short circuit, everything is fine.
        4) list of models verified by users - great idea - how about marking devices verified by users in blue in the overall list of models?
        
        So please add model 18F06Q20 and you can release the next version. :-)
        
        Last edit: Dan Skareda 2025-05-09
        
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        Alberto Maccioni - 2025-05-10
        
        I will try with full support, but first I need a few bits of info.
        When you compile for 18F06Q20 is CONFIG14 (SAFLOCK) specified in the hex file? I guess it depends from what you write in the source.
        Can you provide two files with and without SAFLOCK bit set?
        
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        Dan Skareda - 2025-05-10
        
        My program that made the LED blink is attached. According to the datasheet, config9 and config14 are one-way bits that can be set to 0 (after the "allow program access" sequence), but never to 1 again. Just basic device support (erase and program) without setting the safe bit would be enough. ;-) Switching SAFLOCK to 0 means that I will never clear config9 to 0xFF again if I change it somehow. Maybe you meant the SAFSZ register config9, which can be reset to 0xFF if SAFLOCK=1. I would prefer not to switch SAFLOCK (config14) to 0.
        
        Last edit: Dan Skareda 2025-05-11
        
        18f06q20_blink_RC3.c
        
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        Alberto Maccioni - 2025-05-11
        
        I just want to verify how the compiler handles config14 in a hex file.
        I added support for the additional Program access Enable, although it will rarely be used (if at all), because, as you wrote, it makes the device unwritable.
        In the end this feature will probably gain a general device option, disabled by default.
        
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        Dan Skareda - 2025-05-11
        
        I guess I don't understand you now. I'm using MPLAB X IDE. Here is the original version of the program for 18f06q20 that was flashed, without CONFIG14:
        
        :04000000FEEF7FF0A0
        :101600000000600E00017A6F806B8F9604012A97AC
        :1016100095969576210E016E760EE82EFED7012E58
        :10162000FCD700D009EF0BF0FEEF7FF0000101EFD7
        :021630000BF0BD
        :04FFFC0016EF0BF001
        :020000040030CA
        :07000000ECFFFFFFFFFFFF13
        :03000800FFFFFFFF8
        :00000001FF
        
        Here is the version with CONFIG14 that I added: #pragma config SAFLOCK = OFF (edit: and with CONFIG9: #pragma config SAFSZ = 0xFF)
        
        :04000000FEEF7FF0A0
        :101600000000600E00017A6F806B8F9604012A97AC
        :1016100095969576210E016E760EE82EFED7012E58
        :10162000FCD700D009EF0BF0FEEF7FF0000101EFD7
        :021630000BF0BD
        :04FFFC0016EF0BF001
        :020000040030CA
        :07000000ECFFFFFFFFFFFF13
        :03000800FFFFFFF8
        :02001800FFFFE8
        :00000001FF
        
        Last edit: Dan Skareda 2025-05-12
        
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        Alberto Maccioni - 2025-05-11
        
        So config14 won't even be included as FF unless you declare it.
        What it SAFLOCK = ON ?
        
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        Dan Skareda - 2025-05-12
        
        SAFLOCK: Storage Area Flash (SAF) Lock Enable bit
        – 1 = OFF: SAF Lock disabled
        – 0 = ON: SAF Lock enabled, SAF areas are locked and the SAFSZ bits cannot be erased.
        
        Here is the version with CONFIG14 that I added: #pragma config SAFLOCK = ON and with CONFIG9: #pragma config SAFSZ = 0xFF
        (If I upload this code to the device, I will never change SAFLOCK to OFF again)
        
        :04000000FEEF7FF0A0
        :101600000000600E00017A6F806B8F9604012A97AC
        :1016100095969576210E016E760EE82EFED7012E58
        :10162000FCD700D009EF0BF0FEEF7FF0000101EFD7
        :021630000BF0BD
        :04FFFC0016EF0BF001
        :020000040030CA
        :07000000ECFFFFFFFFFFFF13
        :03000800FFFFFFF8
        :02001800FEFFE9
        :00000001FF
        
        Here is the version with CONFIG14 that I added: #pragma config SAFLOCK = OFF and with CONFIG9: #pragma config SAFSZ = 0x80 (just an example so that it is recognizable in hex code)
        
        04000000FEEF7FF0A0
        :101600000000600E00017A6F806B8F9604012A97AC
        :1016100095969576210E016E760EE82EFED7012E58
        :10162000FCD700D009EF0BF0FEEF7FF0000101EFD7
        :021630000BF0BD
        :04FFFC0016EF0BF001
        :020000040030CA
        :07000000ECFFFFFFFFFFFF13
        :03000800FFFFFFF8
        :02001800FF8067
        :00000001FF
        
        Last edit: Dan Skareda 2025-05-12
        
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        Alberto Maccioni - 2025-05-13
        
        These sources should support Q20.
        Write of SAFZ and SAFLOCK is only attempted if they are not empty and if error count is zero.
        
        deviceRW.c
        
        fileIO.c
        
        progP18.c
        
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        Dan Skareda - 2025-05-14
        
        I read hex file ( with CONFIG14 that I added: #pragma config SAFLOCK = OFF and with CONFIG9: #pragma config SAFSZ = 0x80):
        
        :04000000FEEF7FF0A0 :101600000000600E00017A6F806B8F9604012A97AC :1016100095969576210E016E760EE82EFED7012E58 :10162000FCD700D009EF0BF0FEEF7FF0000101EFD7 :021630000BF0BD :04FFFC0016EF0BF001 :020000040030CA :07000000ECFFFFFFFFFFFF13 :03000800FFFFFFF8 :02001800FF8067 :00000001FF
        
        This is what was displayed in opgui:
        
        CONFIG: [0x300000] 0xEC [0x300001] 0xFF [0x300002] 0xFF [0x300003] 0xFF [0x300004] 0xFF [0x300005] 0xFF [0x300006] 0xFF [0x300007] 0xFF [0x300008] 0xFF [0x300009] 0xFF [0x30000A] 0xFF [0x30000B] 0xFF [0x300019] 0x80 Code memory: 0000: FE EF 7F F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 1600: 00 00 60 0E 00 01 7A 6F 80 6B 8F 96 04 01 2A 97 95 96 95 76 21 0E 01 6E 76 0E E8 2E FE D7 01 2E 1620: FC D7 00 D0 09 EF 0B F0 FE EF 7F F0 00 01 01 EF 0B F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FFE0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 16 EF 0B F0
        
        I wrote it to device and then read the contents of device:
        
        CONFIG: CONFIG1: 0xEC CONFIG2: 0xFF CONFIG3: 0xFF CONFIG4: 0xFF CONFIG5: 0xFF CONFIG6: 0xFF CONFIG7: 0xFF CONFIG8: 0xFF CONFIG9: 0xFF CONFIG10: 0xFF Code memory: 0000: FE EF 7F F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 1600: 00 00 60 0E 00 01 7A 6F 80 6B 8F 96 04 01 2A 97 95 96 95 76 21 0E 01 6E 76 0E E8 2E FE D7 01 2E 1620: FC D7 00 D0 09 EF 0B F0 FE EF 7F F0 00 01 01 EF 0B F0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FFE0: FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF 16 EF 0B F0
        
        Config9 is not 0x80, but 0xFF. Is this okay?
        
        (I also have a new device 32mx130f256b. Is it possible to add this series to the programmer?)
        
        Last edit: Dan Skareda 2025-05-14
        
        log.txt
        
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        Alberto Maccioni - 2025-05-14
        
        For reasons I really cannot understand, the progression of config# and address is interrupted after config8 (0x300007); next is config10 (0x300008), 11 and 12. Another jump and you get config14 (0x300018) and finally config9 (0x300019).
        This is only on Q20 devices.
        Clearly I did not implement a custom counter, and probably never will.
        By the way, SAFSZ is not written unless also SAFLOCK is.
        So in your case everything seems fine and exactly as expected.
        
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        Anonymous - 2025-05-15
        
        Ah, that's great. Basic support is fine and blink works. :-) I'm happy. Thank you for your effort and work - the programmer will be very useful.
        
        Dan Skareda
        
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Anonymous - 2025-04-15

(
there is a little error in deviceRW.c +67 : missing a comma between "16F15223""16F15224"
)
attila

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- Alberto Maccioni - 2025-04-15
  
  Good catch. Fixed
  
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[16F18xxx & 152xx] OPGUI cannot write configuration registers1-5

An USB programmer for PIC, dsPIC, AVR, serial memories

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[16F18xxx & 152xx] OPGUI cannot write configuration registers1-5

[16F18xxx & 152xx] OPGUI cannot write configuration registers1-5

An USB programmer for PIC, dsPIC, AVR, serial memories

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[16F18xxx & 152xx] OPGUI cannot write configuration registers1-5