Well, as it often happens, when you look at circuits with an oscilloscope there's a good chance to find surprises.
In fact, as in a picture posted above, when VDD rises also VPP is pulled to ~4V until the HV source is enabled; then it rises to ~12V.
Since this only happens when the target device is present, there has to be an internal pull-up on RESET: of course, it is well described in the datasheet, but I did not read it before or just forgot about it.
Anyways, it appears that VPP has to stay below some threshold for a few us past VDD, otherwise the device will not enter program mode; this can be accomplished by loading VPP with either a resistor or a capacitor.
I post here the results of 10k, 82pF, 220nF; all of them are fine and allow a correct entry in program mode.
Which one is better? What do you think?
Hi Alberto, Is this the program error 'VUSB too low'? Anyways about your plots, assuming the blue line is VDD why on 220nf VPP is 0V ? Is there no targer device? and in the 10K one why VPP is just like 1V. In conclusion I think the cap solution of 220nF and 82pF looks correct.
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VUSB too low appears when VPP is 0 on the programmer side; this message is not formally correct, it will be changed.
Regarding the plots, imagine there's a pull-up resistor from VDD to RESET pin (i.e. VPP); the value is in the order of 50k, although I think it's a pmos so there are deviations from this value as voltage changes. A 220nF capacitor is charged with a time constant of 11ms, so for the first few hundreds of us you see ~0V.
In case of 10k pull-down the voltage is ~5*10/60=0.83V
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In the end I will add a 10k resistor to statically counter the internal pull-up; this way there are no timing constraints and the logic voltage is always as expected: 0 when VPP is disbled or VPP when enabled.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Anonymous
Anonymous
-
2021-02-22
When using an Arduino to program an ATtiny, you have to provide a
a capacitor to ground which provides a longer reset pulse. Once the
cap is added, programming is consistent Good luck.
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This is a completely different scenario, and a high voltage programmer; timings are flexible, no need to use a hardware hack.
The root cause here is that an internal pull-up is stronger than the pull-down on the programmer, so the most obvious solution is to make the latter even stronger.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
Well, as it often happens, when you look at circuits with an oscilloscope there's a good chance to find surprises.
In fact, as in a picture posted above, when VDD rises also VPP is pulled to ~4V until the HV source is enabled; then it rises to ~12V.
Since this only happens when the target device is present, there has to be an internal pull-up on RESET: of course, it is well described in the datasheet, but I did not read it before or just forgot about it.
Anyways, it appears that VPP has to stay below some threshold for a few us past VDD, otherwise the device will not enter program mode; this can be accomplished by loading VPP with either a resistor or a capacitor.
I post here the results of 10k, 82pF, 220nF; all of them are fine and allow a correct entry in program mode.
Which one is better? What do you think?
Hi Alberto, Is this the program error 'VUSB too low'? Anyways about your plots, assuming the blue line is VDD why on 220nf VPP is 0V ? Is there no targer device? and in the 10K one why VPP is just like 1V. In conclusion I think the cap solution of 220nF and 82pF looks correct.
VUSB too low appears when VPP is 0 on the programmer side; this message is not formally correct, it will be changed.
Regarding the plots, imagine there's a pull-up resistor from VDD to RESET pin (i.e. VPP); the value is in the order of 50k, although I think it's a pmos so there are deviations from this value as voltage changes. A 220nF capacitor is charged with a time constant of 11ms, so for the first few hundreds of us you see ~0V.
In case of 10k pull-down the voltage is ~5*10/60=0.83V
In the end I will add a 10k resistor to statically counter the internal pull-up; this way there are no timing constraints and the logic voltage is always as expected: 0 when VPP is disbled or VPP when enabled.
Where did you add this resistor exactly?
From VPP to GND on the expansion board.
When using an Arduino to program an ATtiny, you have to provide a
a capacitor to ground which provides a longer reset pulse. Once the
cap is added, programming is consistent Good luck.
This is a completely different scenario, and a high voltage programmer; timings are flexible, no need to use a hardware hack.
The root cause here is that an internal pull-up is stronger than the pull-down on the programmer, so the most obvious solution is to make the latter even stronger.