I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ?
Changes there periodically get upstreamed to here (the master OpenOCD project).
As far as I know, cJTAG support has been added there.
I don't think that SWD support will ever be added given that it's arm proprietary and not part of the RISC-V debug specification.
Do you know of a RISC-V implementation with SWD support?
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
That seems to be about using ESP32 as an SWD debug interface.
Not about debugging ESP32 using SWD.
And nothing there is obviously about the RISC-V based ESP32-C3.
As such, I don't see its relevance in this thread?
Again, I ask you, can you point to any RISC-V implementation that supports SWD?
I'm not aware of any.
Last edit: Tommy Murphy 2022-12-29
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Agree with Tommy, SWD is ARM proprietary protocol part of ARM CoreSight,
Nevertheless, somewhere or sometimes we could have a SoC that integrates together some ARM core with some RISC-V cores. In this hybrid SoC the debug port can either be:
a JTAG chain with two TAPs (one for ARM and the other for RISC-V (this is supported by current OpenOCD code), or
a single JTAG/SWD TAP based on ARM CoreSight DAP. One of the AP (access ports) could be a JTAG-AP where the debug of the RISC-V core gets accessible. (today OpenOCD does not support JTAG-AP yet)
So far I have not seen anything like that.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
FWIW, Some Microchip FPGAs/SoC FPGAs can support hard and/or soft IP Cortex-M and RISC-V CPUs. But my recollection (from working for Microchip in the past) is that neither supports SWD. Certainly there is no SWD debug access to the RISC-V.
Last edit: Tommy Murphy 2022-12-29
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[Working on the assumption that SWD is Serial Wire Debugging, not Single Wire Debugging. There is a reference for the latter when I did a goggle search]
Second Tommy's observation that there is no SWD access to RISC-V. I do not remember recalling any mention of SWD in the RISC-V Debug Specification.
Also, pardon my ignorance, I do not remember ARM making it available as international standard or take any steps to license it to other device manufacturers not using ARM's ISA. If I am correct, then RISC-V-based device will not be able to use it. I am saying this because this can be the second reason why SWD is not supported for RISC-V device in OpenOCD, i.e. not possible to get any RISC-V hard or soft IP that uses SWD.
Happy New Year.
Cinly
From: Tommy Murphy tm1234@users.sourceforge.net
Sent: Friday, December 30, 2022 2:06 AM
To: openocd-devel@lists.sourceforge.net
Subject: [openocd:tickets] Re: #378 SWD support for RISCV artchitecture
FWIW, Some Microchip FPGAs/SoC FPGAs can support hard and/or soft IP Cortex-M and RISC-V CPUs. But my recollection (from working for Microchip in the past) is that neither supported SWD. Certainly there is no SWD debug access to the RISC-V.
Status: new
Milestone: 0.10.0
Labels: openocd
Created: Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta
Last Updated: Thu Dec 29, 2022 05:20 PM UTC
Owner: nobody
Hi,
I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ?
"[A] single JTAG/SWD TAP based on ARM CoreSight DAP. One of the AP (access ports) could be a JTAG-AP where the debug of the RISC-V core gets accessible. (today OpenOCD does not support JTAG-AP yet)"
This is an interesting idea, and certainly possible, i.e. attaching a JTAG-AP to RISC-V. However, I believe if someone has a hybrid SoC that integrates ARM core with RISC-V cores, without explicit permission from ARM, then SWD can only access to ARM cores. Of course, the usual "I am not a lawyer" disclaimer applies here.
Your hybrid SoC idea led me to think about getting the ARM core as the intermediary controller for the RISC-V part, i.e. SWD->ARM core-> RISC-V core. Instinctively I say it is unlikely to be permitted, and is definitely something for the lawyers to sort out.
From: Antonio Borneo borneoa@users.sourceforge.net
Sent: Friday, December 30, 2022 1:20 AM
To: openocd-devel@lists.sourceforge.net
Subject: [openocd:tickets] #378 SWD support for RISCV artchitecture
Agree with Tommy, SWD is ARM proprietary protocol part of ARM CoreSight,
Nevertheless, somewhere or sometimes we could have a SoC that integrates together some ARM core with some RISC-V cores. In this hybrid SoC the debug port can either be:
a JTAG chain with two TAPs (one for ARM and the other for RISC-V (this is supported by current OpenOCD code), or
a single JTAG/SWD TAP based on ARM CoreSight DAP. One of the AP (access ports) could be a JTAG-AP where the debug of the RISC-V core gets accessible. (today OpenOCD does not support JTAG-AP yet)
Status: new
Milestone: 0.10.0
Labels: openocd
Created: Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta
Last Updated: Thu Dec 29, 2022 01:24 PM UTC
Owner: nobody
Hi,
I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ?
Though this is a off-topic. I have got some queries hence posting
I have came across custom SOCs where there is a single ARM Coresight DAP and a riscv processor connected on APB bus on a particular APB port.
ARM debug can be achieved using openocd, any idea on how riscv debug can be achieved here ? As there is no separate riscv tap how to ask openocd to look for riscv debug registers from a particular APB port and base address ?
Cinly, from your comment it looks like this type of functionality is not supported in openocd but i have seen a separate version of openocd-riscv. Apparently that is helping to attach to ARM core as well, is there any way to debug riscv with that version in this scenario ?
I see some custom debuggers does support this type if debug but that all are license and paid basis.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
For SOC having combination of ARM and RISCV or any other peripheral connected on APB bus, ARM being a primary debug chip is accessible via DAP and debug can be done/supported using Openocd but is there any way to select a peripheral having its own debugbase connected on APB-AP ?
I did some investigation on the CH32V series. It seems that they have their own custom protocol completely unrelated to ARM SWD. I have seen it referred to as RVSWD. To complicate things even further, their CH32V003 uses a different single wire transport protocol.
Last edit: Marek Vrbka 2024-01-29
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Cinly,
yes, that's a grey area out of tech domain and more on lawyer sides.
But I see Risc-V cores used as control integrated in HW accelerators, like GPUs or AI. People that build SoCs could feel comfortable keeping the ARM main processor while integrating such third-party accelerators.
This kind of hybrid SoC are going to get common, and I agree with recent statement from Risc-V CEO: "Risc-V is inevitable!".
And ARM has to face the reality. If they are not flexible enough to allow such hybrid SoC, more people will consider to drop ARM completely.
Then, on which config will lawyers agree? A SoC with two independent debug ports? Two independent TAPs on the same JTAG chain? An ARM DAP with a bridge JTAG-AP? I don't know, we will see it. Probably sooner than we expect. Here we are just speculating and bla-bla.
Having the ARM core as intermediate controller for the Risc-V... possible but hard to use during SoC verification. You need one core (ARM one) up and running to test the other cores. Designer will prefer a direct path to each core.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
While the article reports a SoC with Risc-V + Cortex-M33, I think this should be a dual silicon chips in a single package because I don't believe the same technology can fit for both 800MHz CPU and WiFi/BT radio.
For me the Cortex-M33 is in the same chip with the WiFi/BT, while Risc-V and the other digital functions are in another chip.
Anyway, some hybrid is popping out.
If you would like to refer to this comment somewhere else in this project, copy and paste the following link:
I was looking at the pin out on the tweet to see whether it use JTAG or SWD. All I can find is USB, so no guidance there. Either signals can be routed through USB I believe. I know JTAG can, but my limited knowledge means I am not sure about SWD.
From: Antonio Borneo borneoa@users.sourceforge.net
Sent: Friday, March 10, 2023 7:08 AM
To: openocd-devel@lists.sourceforge.net
Subject: [openocd:tickets] #378 SWD support for RISCV artchitecture
While the article reports a SoC with Risc-V + Cortex-M33, I think this should be a dual silicon chips in a single package because I don't believe the same technology can fit for both 800MHz CPU and WiFi/BT radio.
For me the Cortex-M33 is in the same chip with the WiFi/BT, while Risc-V and the other digital functions are in another chip.
Anyway, some hybrid is popping out.
Status: new
Milestone: 0.10.0
Labels: openocd
Created: Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta
Last Updated: Sat Jan 07, 2023 11:34 AM UTC
Owner: nobody
Hi,
I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ?
You probably want to look at the RISC-V OpenOCD fork for latest RISC-V support.
https://github.com/riscv/riscv-openocd
Changes there periodically get upstreamed to here (the master OpenOCD project).
As far as I know, cJTAG support has been added there.
I don't think that SWD support will ever be added given that it's arm proprietary and not part of the RISC-V debug specification.
Do you know of a RISC-V implementation with SWD support?
oh ok. Will check on cJTAG support under this link (https://github.com/riscv/riscv-openocd)
i think ESP32 might have SWD support (not sure though).
You mean ESP32-C3?
I don't think so.
As far as I can see it only has JTAG.
https://www.espressif.com/en/products/socs/esp32-c3
https://docs.espressif.com/projects/esp-idf/en/v5.0/esp32c3/api-guides/jtag-debugging/index.html
Last edit: Tommy Murphy 2022-12-28
i found this thread for SWD debug support using SPI for esp32 (have not tried anything though)
https://esp32.com/viewtopic.php?t=3627
That seems to be about using ESP32 as an SWD debug interface.
Not about debugging ESP32 using SWD.
And nothing there is obviously about the RISC-V based ESP32-C3.
As such, I don't see its relevance in this thread?
Again, I ask you, can you point to any RISC-V implementation that supports SWD?
I'm not aware of any.
Last edit: Tommy Murphy 2022-12-29
Agree with Tommy, SWD is ARM proprietary protocol part of ARM CoreSight,
Nevertheless, somewhere or sometimes we could have a SoC that integrates together some ARM core with some RISC-V cores. In this hybrid SoC the debug port can either be:
a JTAG chain with two TAPs (one for ARM and the other for RISC-V (this is supported by current OpenOCD code), or
a single JTAG/SWD TAP based on ARM CoreSight DAP. One of the AP (access ports) could be a JTAG-AP where the debug of the RISC-V core gets accessible. (today OpenOCD does not support JTAG-AP yet)
So far I have not seen anything like that.
FWIW, Some Microchip FPGAs/SoC FPGAs can support hard and/or soft IP Cortex-M and RISC-V CPUs. But my recollection (from working for Microchip in the past) is that neither supports SWD. Certainly there is no SWD debug access to the RISC-V.
Last edit: Tommy Murphy 2022-12-29
Hi,
[Working on the assumption that SWD is Serial Wire Debugging, not Single Wire Debugging. There is a reference for the latter when I did a goggle search]
Second Tommy's observation that there is no SWD access to RISC-V. I do not remember recalling any mention of SWD in the RISC-V Debug Specification.
Also, pardon my ignorance, I do not remember ARM making it available as international standard or take any steps to license it to other device manufacturers not using ARM's ISA. If I am correct, then RISC-V-based device will not be able to use it. I am saying this because this can be the second reason why SWD is not supported for RISC-V device in OpenOCD, i.e. not possible to get any RISC-V hard or soft IP that uses SWD.
Happy New Year.
Cinly
From: Tommy Murphy tm1234@users.sourceforge.net
Sent: Friday, December 30, 2022 2:06 AM
To: openocd-devel@lists.sourceforge.net
Subject: [openocd:tickets] Re: #378 SWD support for RISCV artchitecture
FWIW, Some Microchip FPGAs/SoC FPGAs can support hard and/or soft IP Cortex-M and RISC-V CPUs. But my recollection (from working for Microchip in the past) is that neither supported SWD. Certainly there is no SWD debug access to the RISC-V.
[tickets:#378]https://sourceforge.net/p/openocd/tickets/378/ SWD support for RISCV artchitecture
Status: new
Milestone: 0.10.0
Labels: openocd
Created: Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta
Last Updated: Thu Dec 29, 2022 05:20 PM UTC
Owner: nobody
Hi,
I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ?
Sent from sourceforge.net because openocd-devel@lists.sourceforge.netopenocd-devel@lists.sourceforge.net is subscribed to https://sourceforge.net/p/openocd/tickets/
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Related
Tickets: #378
HI Antonio,
With reference to your second point,
"[A] single JTAG/SWD TAP based on ARM CoreSight DAP. One of the AP (access ports) could be a JTAG-AP where the debug of the RISC-V core gets accessible. (today OpenOCD does not support JTAG-AP yet)"
This is an interesting idea, and certainly possible, i.e. attaching a JTAG-AP to RISC-V. However, I believe if someone has a hybrid SoC that integrates ARM core with RISC-V cores, without explicit permission from ARM, then SWD can only access to ARM cores. Of course, the usual "I am not a lawyer" disclaimer applies here.
Your hybrid SoC idea led me to think about getting the ARM core as the intermediary controller for the RISC-V part, i.e. SWD->ARM core-> RISC-V core. Instinctively I say it is unlikely to be permitted, and is definitely something for the lawyers to sort out.
From: Antonio Borneo borneoa@users.sourceforge.net
Sent: Friday, December 30, 2022 1:20 AM
To: openocd-devel@lists.sourceforge.net
Subject: [openocd:tickets] #378 SWD support for RISCV artchitecture
Agree with Tommy, SWD is ARM proprietary protocol part of ARM CoreSight,
Nevertheless, somewhere or sometimes we could have a SoC that integrates together some ARM core with some RISC-V cores. In this hybrid SoC the debug port can either be:
So far I have not seen anything like that.
[tickets:#378]https://sourceforge.net/p/openocd/tickets/378/ SWD support for RISCV artchitecture
Status: new
Milestone: 0.10.0
Labels: openocd
Created: Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta
Last Updated: Thu Dec 29, 2022 01:24 PM UTC
Owner: nobody
Hi,
I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ?
Sent from sourceforge.net because openocd-devel@lists.sourceforge.netopenocd-devel@lists.sourceforge.net is subscribed to https://sourceforge.net/p/openocd/tickets/
To unsubscribe from further messages, a project admin can change settings at https://sourceforge.net/p/openocd/admin/tickets/options. Or, if this is a mailing list, you can unsubscribe from the mailing list.
Related
Tickets: #378
Though this is a off-topic. I have got some queries hence posting
I have came across custom SOCs where there is a single ARM Coresight DAP and a riscv processor connected on APB bus on a particular APB port.
ARM debug can be achieved using openocd, any idea on how riscv debug can be achieved here ? As there is no separate riscv tap how to ask openocd to look for riscv debug registers from a particular APB port and base address ?
Cinly, from your comment it looks like this type of functionality is not supported in openocd but i have seen a separate version of openocd-riscv. Apparently that is helping to attach to ARM core as well, is there any way to debug riscv with that version in this scenario ?
I see some custom debuggers does support this type if debug but that all are license and paid basis.
Do you happen to mean the WCH CH32VXXX MCUs by any chance? If so then maybe this is of relevance?
I seem to recall other discussion of this recently (last year) but can't find anything via a quick search of the mailing lists.
Example SOC: https://www.nordicsemi.com/Products/nRF54H20 - This is with combination of ARM and RISCV core on an SOC.
CH32V seems to be a RISCV based SOC only.
For SOC having combination of ARM and RISCV or any other peripheral connected on APB bus, ARM being a primary debug chip is accessible via DAP and debug can be done/supported using Openocd but is there any way to select a peripheral having its own debugbase connected on APB-AP ?
I came across interesting old ticket whre some conversation has happened for peripherals connected on APB port
https://sourceforge.net/p/openocd/mailman/openocd-devel/thread/n2qvvu$m6n$1@ger.gmane.org/
Ashi, does the first statement reference the same SoC like the second one?
nRF have not yet released any product specification about 54 series. Do you know some details?
I did some investigation on the CH32V series. It seems that they have their own custom protocol completely unrelated to ARM SWD. I have seen it referred to as RVSWD. To complicate things even further, their CH32V003 uses a different single wire transport protocol.
Last edit: Marek Vrbka 2024-01-29
Cinly,
yes, that's a grey area out of tech domain and more on lawyer sides.
But I see Risc-V cores used as control integrated in HW accelerators, like GPUs or AI. People that build SoCs could feel comfortable keeping the ARM main processor while integrating such third-party accelerators.
This kind of hybrid SoC are going to get common, and I agree with recent statement from Risc-V CEO: "Risc-V is inevitable!".
And ARM has to face the reality. If they are not flexible enough to allow such hybrid SoC, more people will consider to drop ARM completely.
Then, on which config will lawyers agree? A SoC with two independent debug ports? Two independent TAPs on the same JTAG chain? An ARM DAP with a bridge JTAG-AP? I don't know, we will see it. Probably sooner than we expect. Here we are just speculating and bla-bla.
Having the ARM core as intermediate controller for the Risc-V... possible but hard to use during SoC verification. You need one core (ARM one) up and running to test the other cores. Designer will prefer a direct path to each core.
One update on the (almost off-topic) discussion started with this ticket
"Allwinner R128 wireless SoC features 64-bit RISC-V core, Arm Cortex-M33 core, and HiFi 5 audio DSP"
https://www.cnx-software.com/2023/03/06/allwinner-r128-wireless-soc-features-64-bit-risc-v-core-arm-cortex-m33-core-and-hifi-5-audio-dsp/
While the article reports a SoC with Risc-V + Cortex-M33, I think this should be a dual silicon chips in a single package because I don't believe the same technology can fit for both 800MHz CPU and WiFi/BT radio.
For me the Cortex-M33 is in the same chip with the WiFi/BT, while Risc-V and the other digital functions are in another chip.
Anyway, some hybrid is popping out.
Interesting development.
I was looking at the pin out on the tweet to see whether it use JTAG or SWD. All I can find is USB, so no guidance there. Either signals can be routed through USB I believe. I know JTAG can, but my limited knowledge means I am not sure about SWD.
From: Antonio Borneo borneoa@users.sourceforge.net
Sent: Friday, March 10, 2023 7:08 AM
To: openocd-devel@lists.sourceforge.net
Subject: [openocd:tickets] #378 SWD support for RISCV artchitecture
One update on the (almost off-topic) discussion started with this ticket
"Allwinner R128 wireless SoC features 64-bit RISC-V core, Arm Cortex-M33 core, and HiFi 5 audio DSP"
https://www.cnx-software.com/2023/03/06/allwinner-r128-wireless-soc-features-64-bit-risc-v-core-arm-cortex-m33-core-and-hifi-5-audio-dsp/
While the article reports a SoC with Risc-V + Cortex-M33, I think this should be a dual silicon chips in a single package because I don't believe the same technology can fit for both 800MHz CPU and WiFi/BT radio.
For me the Cortex-M33 is in the same chip with the WiFi/BT, while Risc-V and the other digital functions are in another chip.
Anyway, some hybrid is popping out.
[tickets:#378]https://sourceforge.net/p/openocd/tickets/378/ SWD support for RISCV artchitecture
Status: new
Milestone: 0.10.0
Labels: openocd
Created: Wed Dec 28, 2022 07:00 AM UTC by Ashi Gupta
Last Updated: Sat Jan 07, 2023 11:34 AM UTC
Owner: nobody
Hi,
I want to know if SWD debug support has been added for RISCV architecture in openocd ? So far i know that JTAG support is only available. If not any plans in doing so ?
Sent from sourceforge.net because openocd-devel@lists.sourceforge.netopenocd-devel@lists.sourceforge.net is subscribed to https://sourceforge.net/p/openocd/tickets/
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Related
Tickets: #378