Cinly Ooi

Interesting development. I was looking at the pin out on the tweet to see whether it use JTAG or SWD. All I can find is USB, so no guidance there. Either signals can be routed through USB I believe. I know JTAG can, but my limited knowledge means I am not sure about SWD. From: Antonio Borneo borneoa@users.sourceforge.net Sent: Friday, March 10, 2023 7:08 AM To: openocd-devel@lists.sourceforge.net Subject: [openocd:tickets] #378 SWD support for RISCV artchitecture One update on the (almost off-topic)...

HI Antonio, With reference to your second point, "[A] single JTAG/SWD TAP based on ARM CoreSight DAP. One of the AP (access ports) could be a JTAG-AP where the debug of the RISC-V core gets accessible. (today OpenOCD does not support JTAG-AP yet)" This is an interesting idea, and certainly possible, i.e. attaching a JTAG-AP to RISC-V. However, I believe if someone has a hybrid SoC that integrates ARM core with RISC-V cores, without explicit permission from ARM, then SWD can only access to ARM cores....

Hi, [Working on the assumption that SWD is Serial Wire Debugging, not Single Wire Debugging. There is a reference for the latter when I did a goggle search] Second Tommy's observation that there is no SWD access to RISC-V. I do not remember recalling any mention of SWD in the RISC-V Debug Specification. Also, pardon my ignorance, I do not remember ARM making it available as international standard or take any steps to license it to other device manufacturers not using ARM's ISA. If I am correct, then...