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From: OpenOCD-Gerrit <ope...@us...> - 2022-03-12 09:41:48
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via de4f52179c513cba194079f9fe1ce3a0532bdc9f (commit)
via 9f1b4bbe706b3df40793a9573d7f6471a2442222 (commit)
from 4ea21b95f9562ae13ef200461180bc72bbad8926 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit de4f52179c513cba194079f9fe1ce3a0532bdc9f
Author: Nishanth Menon <nm...@ti...>
Date: Thu Oct 14 09:57:22 2021 -0500
tcl/board: Add J721s2 EVM basic support
Add basic connection details with J721s2 EVM.
For further details, see https://www.ti.com/lit/zip/sprr439
Signed-off-by: Nishanth Menon <nm...@ti...>
Change-Id: I68f8818c492ea6e07c14f2da305671c26da801cb
Reviewed-on: https://review.openocd.org/c/openocd/+/6797
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/ti_j721s2evm.cfg b/tcl/board/ti_j721s2evm.cfg
new file mode 100644
index 000000000..72418b57b
--- /dev/null
+++ b/tcl/board/ti_j721s2evm.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2021 Texas Instruments Incorporated - http://www.ti.com/
+#
+# Texas Instruments J721s2 EVM
+# Link(SoM): https://www.ti.com/lit/zip/sprr439
+#
+
+# J721s2 EVM has an xds110 onboard.
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+# default JTAG configuration has only SRST and no TRST
+reset_config srst_only srst_push_pull
+
+# delay after SRST goes inactive
+adapter srst delay 20
+
+if { ![info exists SOC] } {
+ set SOC j721s2
+}
+
+source [find target/ti_k3.cfg]
+
+adapter speed 2500
commit 9f1b4bbe706b3df40793a9573d7f6471a2442222
Author: Nishanth Menon <nm...@ti...>
Date: Thu Oct 14 09:55:49 2021 -0500
tcl/target/ti_k3: Add J721S2 SoC
Add support for the latest in TI k3 family J721S2 SoC.
For further details, see http://www.ti.com/lit/pdf/spruj28
Signed-off-by: Nishanth Menon <nm...@ti...>
Change-Id: I608ab4513ffb6b5c4166ba423e7d0dddbbb3bbfd
Reviewed-on: https://review.openocd.org/c/openocd/+/6796
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index f2267ca12..604083758 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -114,6 +114,26 @@ switch $_soc {
# M3 CTI base
set CM3_CTIBASE {0x20001000}
}
+ j721s2 {
+ set _CHIPNAME j721s2
+ set _K3_DAP_TAPID 0x0bb7502f
+
+ # J721s2 has 1 cluster of 2 A72 cores.
+ set _armv8_cpu_name a72
+ set _armv8_cores 2
+
+ # J721s2 has 3 clusters of 2 R5 cores each.
+ set _r5_cores 6
+
+ # sysctrl CTI base
+ set CM3_CTIBASE {0x20001000}
+ # Sysctrl power-ap unlock offsets
+ set _sysctrl_ap_unlock_offsets {0xf0 0x78}
+
+ # M4 processor
+ set _gp_mcu_cores 1
+ set _gp_mcu_ap_unlock_offsets {0xf0 0x7c}
+ }
default {
echo "'$_soc' is invalid!"
}
-----------------------------------------------------------------------
Summary of changes:
tcl/board/{ti_j721evm.cfg => ti_j721s2evm.cfg} | 9 +++++----
tcl/target/ti_k3.cfg | 20 ++++++++++++++++++++
2 files changed, 25 insertions(+), 4 deletions(-)
copy tcl/board/{ti_j721evm.cfg => ti_j721s2evm.cfg} (62%)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-03-12 09:41:23
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4ea21b95f9562ae13ef200461180bc72bbad8926 (commit)
via 3ba2b515b528094b43d5be5056b9e52f1dc33969 (commit)
from 4b12c9e8c507a1ba748de32c9ab9f3e7654c22b4 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4ea21b95f9562ae13ef200461180bc72bbad8926
Author: Nishanth Menon <nm...@ti...>
Date: Tue Mar 1 09:09:55 2022 -0600
tcl/target/ti_k3: Add a gdb-attach event hook for armv8 and simplify startup function
Since we can detect the type of target as well, reuse the _cpu_no_smp_up
function name and use the target name to simplify the _up function and
maintain consistency with what we introduced for r5.
Lets introduce gdb-attach event in a much cleaner fashion.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
While at it, fix a minor type of s/are/as in "Set Default target are
core 0" and simplify the foreach usage.
Signed-off-by: Nishanth Menon <nm...@ti...>
Change-Id: I3259b7c3ae4c71b06d921edfaefe17c03bb673dc
Reviewed-on: https://review.openocd.org/c/openocd/+/6616
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 883197b14..f2267ca12 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -154,6 +154,16 @@ proc _cpu_no_smp_up {} {
$_current_target $_current_type dbginit
}
+proc _armv8_smp_up {} {
+ for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
+ $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
+ $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+ $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
+ }
+ # Set Default target as core 0
+ targets $::_TARGETNAME.$::_armv8_cpu_name.0
+}
+
set _v8_smp_targets ""
for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
@@ -165,6 +175,20 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
+
+ if { $_v8_smp_debug == 0 } {
+ $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+ _cpu_no_smp_up
+ # gdb-attach default rule
+ halt 1000
+ }
+ } else {
+ $_TARGETNAME.$_armv8_cpu_name.$_core configure -event gdb-attach {
+ _armv8_smp_up
+ # gdb-attach default rule
+ halt 1000
+ }
+ }
}
# Setup ARMV8 proc commands based on CPU to prevent people confusing SoCs
@@ -174,22 +198,15 @@ set _armv8_smp_cmd "$_armv8_cpu_name"_smp
if { $_v8_smp_debug == 0 } {
proc $_armv8_up_cmd { args } {
- foreach { _core } [set args] {
- $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
- $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
+ foreach _core $args {
+ targets $_core
+ _cpu_no_smp_up
}
}
} else {
proc $_armv8_smp_cmd { args } {
- for { set _core 0 } { $_core < $::_armv8_cores } { incr _core } {
- $::_TARGETNAME.$::_armv8_cpu_name.$_core arp_examine
- $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 dbginit
- $::_TARGETNAME.$::_armv8_cpu_name.$_core aarch64 smp on
- }
- # Set Default target are core 0
- targets $::_TARGETNAME.$::_armv8_cpu_name.0
+ _armv8_smp_up
}
-
# Declare SMP
target smp $:::_v8_smp_targets
}
commit 3ba2b515b528094b43d5be5056b9e52f1dc33969
Author: Nishanth Menon <nm...@ti...>
Date: Mon Oct 4 09:20:34 2021 -0500
tcl/target/ti_k3: Add a gdb-attach event hook for r5 and simplify startup function
Since we can detect the type of target as well, make the attach
function name generic for the follow on cleanup patch on armv8 to use
as well.
Lets introduce gdb-attach event in a much cleaner fashion. We can
introduce a simpler r5_up function since we now have more descriptive
core names making the individual descriptive procs redundant.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
Signed-off-by: Nishanth Menon <nm...@ti...>
Change-Id: I31506bb2b86e63638082640eb72aa7c4c9575e93
Reviewed-on: https://review.openocd.org/c/openocd/+/6617
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 6c2c2e1da..883197b14 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -64,9 +64,6 @@ switch $_soc {
# AM654 has 1 cluster of 2 R5s cores.
set _r5_cores 2
- set _mcu_r5_cores 2
- set _main0_r5_cores 0
- set _main1_r5_cores 0
set R5_NAMES {mcu_r5.0 mcu_r5.1}
# Sysctrl power-ap unlock offsets
@@ -84,9 +81,6 @@ switch $_soc {
# AM642 has 2 cluster of 2 R5s cores.
set _r5_cores 4
- set _mcu_r5_cores 0
- set _main0_r5_cores 2
- set _main1_r5_cores 2
set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
@@ -103,9 +97,6 @@ switch $_soc {
# J721E has 3 clusters of 2 R5 cores each.
set _r5_cores 6
- set _mcu_r5_cores 2
- set _main0_r5_cores 2
- set _main1_r5_cores 2
}
j7200 {
set _CHIPNAME j7200
@@ -117,9 +108,6 @@ switch $_soc {
# J7200 has 2 clusters of 2 R5 cores each.
set _r5_cores 4
- set _mcu_r5_cores 2
- set _main0_r5_cores 2
- set _main1_r5_cores 0
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
@@ -158,6 +146,14 @@ $_TARGETNAME.sysctrl configure -event gdb-attach {
halt 1000
}
+proc _cpu_no_smp_up {} {
+ set _current_target [target current]
+ set _current_type [$_current_target cget -type]
+
+ $_current_target arp_examine
+ $_current_target $_current_type dbginit
+}
+
set _v8_smp_targets ""
for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
@@ -206,32 +202,18 @@ for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
# inactive core examination will fail - wait till startup of additional core
target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
-}
-if { $_mcu_r5_cores != 0 } {
- proc mcu_r5_up { args } {
- foreach { _core } [set args] {
- $::_TARGETNAME.mcu_r5.$_core arp_examine
- $::_TARGETNAME.mcu_r5.$_core cortex_r4 dbginit
- }
- }
-}
-
-if { $_main0_r5_cores != 0 } {
- proc main0_r5_up { args } {
- foreach { _core } [set args] {
- $::_TARGETNAME.main0_r5.$_core arp_examine
- $::_TARGETNAME.main0_r5.$_core cortex_r4 dbginit
- }
+ $_TARGETNAME.$_r5_name configure -event gdb-attach {
+ _cpu_no_smp_up
+ # gdb-attach default rule
+ halt 1000
}
}
-if { $_main1_r5_cores != 0 } {
- proc main1_r5_up { args } {
- foreach { _core } [set args] {
- $::_TARGETNAME.main1_r5.$_core arp_examine
- $::_TARGETNAME.main1_r5.$_core cortex_r4 dbginit
- }
+proc r5_up { args } {
+ foreach _core $args {
+ targets $_core
+ _cpu_no_smp_up
}
}
-----------------------------------------------------------------------
Summary of changes:
tcl/target/ti_k3.cfg | 89 ++++++++++++++++++++++++++--------------------------
1 file changed, 44 insertions(+), 45 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-03-12 09:40:59
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4b12c9e8c507a1ba748de32c9ab9f3e7654c22b4 (commit)
via 4ddca7dd7186a908397570a25f7ad7454bab3a20 (commit)
from 77b02b89ae689867bb38e11d3fa6ff59c8d22357 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4b12c9e8c507a1ba748de32c9ab9f3e7654c22b4
Author: Nishanth Menon <nm...@ti...>
Date: Mon Oct 4 09:03:49 2021 -0500
tcl/target/ti_k3: Rename R5 targets to be more descriptive
R5 targets are currently named r5.0..n and the only way for user to
determine the actual type is external documentation. Lets just rename
the target names to make them descriptive to not require external
documentation for finding which R5 to connect to.
NOTE: we leave the _mcu_r5_cores _main0_r5_cores _main1_r5_cores alone
for now to allow existing startup proc functions to work, but we will
drop it in the follow on patch.
Previously:
Info : starting gdb server for j721e.cpu.r5.0 on 3336
Info : Listening on port 3336 for gdb connections
Info : starting gdb server for j721e.cpu.r5.1 on 3337
Info : Listening on port 3337 for gdb connections
Info : starting gdb server for j721e.cpu.r5.2 on 3338
Info : Listening on port 3338 for gdb connections
Info : starting gdb server for j721e.cpu.r5.3 on 3339
Info : Listening on port 3339 for gdb connections
Info : starting gdb server for j721e.cpu.r5.4 on 3340
Info : Listening on port 3340 for gdb connections
Info : starting gdb server for j721e.cpu.r5.5 on 3341
Info : Listening on port 3341 for gdb connections
With this patch:
Info : starting gdb server for j721e.cpu.mcu_r5.0 on 3336
Info : Listening on port 3336 for gdb connections
Info : starting gdb server for j721e.cpu.mcu_r5.1 on 3337
Info : Listening on port 3337 for gdb connections
Info : starting gdb server for j721e.cpu.main0_r5.0 on 3338
Info : Listening on port 3338 for gdb connections
Info : starting gdb server for j721e.cpu.main0_r5.1 on 3339
Info : Listening on port 3339 for gdb connections
Info : starting gdb server for j721e.cpu.main1_r5.0 on 3340
Info : Listening on port 3340 for gdb connections
Info : starting gdb server for j721e.cpu.main1_r5.1 on 3341
Info : Listening on port 3341 for gdb connections
Signed-off-by: Nishanth Menon <nm...@ti...>
Change-Id: I2989efe3ae3e16754f98fa1dc9363ec4c898f7c3
Reviewed-on: https://review.openocd.org/c/openocd/+/6627
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index e397d2255..6c2c2e1da 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -42,6 +42,7 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
# (0)MCU 0 (1)MCU 1 (2)MAIN_0_0 (3)MAIN_0_1 (4)MAIN_1_0 (5)MAIN_1_1
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
+set R5_NAMES {mcu_r5.0 mcu_r5.1 main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
# Finally an General Purpose(GP) MCU
set CM4_CTIBASE {0x20001000}
@@ -64,11 +65,9 @@ switch $_soc {
# AM654 has 1 cluster of 2 R5s cores.
set _r5_cores 2
set _mcu_r5_cores 2
- set _mcu_base_core_id 0
set _main0_r5_cores 0
- set _main0_base_core_id 0
set _main1_r5_cores 0
- set _main1_base_core_id 0
+ set R5_NAMES {mcu_r5.0 mcu_r5.1}
# Sysctrl power-ap unlock offsets
set _sysctrl_ap_unlock_offsets {0xf0 0x50}
@@ -86,11 +85,9 @@ switch $_soc {
# AM642 has 2 cluster of 2 R5s cores.
set _r5_cores 4
set _mcu_r5_cores 0
- set _mcu_base_core_id 0
set _main0_r5_cores 2
- set _main0_base_core_id 0
set _main1_r5_cores 2
- set _main1_base_core_id 2
+ set R5_NAMES {main0_r5.0 main0_r5.1 main1_r5.0 main1_r5.1}
set R5_DBGBASE {0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
@@ -107,11 +104,8 @@ switch $_soc {
# J721E has 3 clusters of 2 R5 cores each.
set _r5_cores 6
set _mcu_r5_cores 2
- set _mcu_base_core_id 0
set _main0_r5_cores 2
- set _main0_base_core_id 2
set _main1_r5_cores 2
- set _main1_base_core_id 4
}
j7200 {
set _CHIPNAME j7200
@@ -124,11 +118,8 @@ switch $_soc {
# J7200 has 2 clusters of 2 R5 cores each.
set _r5_cores 4
set _mcu_r5_cores 2
- set _mcu_base_core_id 0
set _main0_r5_cores 2
- set _main0_base_core_id 2
set _main1_r5_cores 0
- set _main1_base_core_id 0
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d110000 0x9d112000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d118000 0x9d119000}
@@ -208,20 +199,20 @@ if { $_v8_smp_debug == 0 } {
}
for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
- cti create $_CTINAME.r5.$_core -dap $_CHIPNAME.dap -ap-num 1 \
+ set _r5_name [lindex $R5_NAMES $_core]
+ cti create $_CTINAME.$_r5_name -dap $_CHIPNAME.dap -ap-num 1 \
-baseaddr [lindex $R5_CTIBASE $_core]
# inactive core examination will fail - wait till startup of additional core
- target create $_TARGETNAME.r5.$_core cortex_r4 -dap $_CHIPNAME.dap \
+ target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
}
if { $_mcu_r5_cores != 0 } {
proc mcu_r5_up { args } {
foreach { _core } [set args] {
- set _core [expr {$_core + $::_mcu_base_core_id}]
- $::_TARGETNAME.r5.$_core arp_examine
- $::_TARGETNAME.r5.$_core cortex_r4 dbginit
+ $::_TARGETNAME.mcu_r5.$_core arp_examine
+ $::_TARGETNAME.mcu_r5.$_core cortex_r4 dbginit
}
}
}
@@ -229,9 +220,8 @@ if { $_mcu_r5_cores != 0 } {
if { $_main0_r5_cores != 0 } {
proc main0_r5_up { args } {
foreach { _core } [set args] {
- set _core [expr {$_core + $::_main0_base_core_id}]
- $::_TARGETNAME.r5.$_core arp_examine
- $::_TARGETNAME.r5.$_core cortex_r4 dbginit
+ $::_TARGETNAME.main0_r5.$_core arp_examine
+ $::_TARGETNAME.main0_r5.$_core cortex_r4 dbginit
}
}
}
@@ -239,9 +229,8 @@ if { $_main0_r5_cores != 0 } {
if { $_main1_r5_cores != 0 } {
proc main1_r5_up { args } {
foreach { _core } [set args] {
- set _core [expr {$_core + $::_main1_base_core_id}]
- $::_TARGETNAME.r5.$_core arp_examine
- $::_TARGETNAME.r5.$_core cortex_r4 dbginit
+ $::_TARGETNAME.main1_r5.$_core arp_examine
+ $::_TARGETNAME.main1_r5.$_core cortex_r4 dbginit
}
}
}
commit 4ddca7dd7186a908397570a25f7ad7454bab3a20
Author: Nishanth Menon <nm...@ti...>
Date: Fri Oct 1 23:18:09 2021 -0500
tcl/target/ti_k3: Rename m4 target as general purpose mcu
The MCU is present on few of the SoCs and is meant as General Purpose
(GP) MCU of the system. Lets rename it to make clear what we are
debugging - esp when multiple MCUs are present in the system.
Signed-off-by: Nishanth Menon <nm...@ti...>
Change-Id: I16132d321daf6e9b1d893fe6f92026d5aa9eb152
Reviewed-on: https://review.openocd.org/c/openocd/+/6619
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index ee4a5c8b3..e397d2255 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -43,13 +43,13 @@ set ARMV8_CTIBASE {0x90420000 0x90520000 0x90820000 0x90920000}
set R5_DBGBASE {0x9d010000 0x9d012000 0x9d410000 0x9d412000 0x9d510000 0x9d512000}
set R5_CTIBASE {0x9d018000 0x9d019000 0x9d418000 0x9d419000 0x9d518000 0x9d519000}
-# Finally an M4F
+# Finally an General Purpose(GP) MCU
set CM4_CTIBASE {0x20001000}
-# M4 may be present on some very few SoCs
-set _mcu_m4_cores 0
-# M4 power-ap unlock offsets
-set _m4_ap_unlock_offsets {0xf0 0x60}
+# General Purpose MCU (M4) may be present on some very few SoCs
+set _gp_mcu_cores 0
+# General Purpose MCU power-ap unlock offsets
+set _gp_mcu_ap_unlock_offsets {0xf0 0x60}
# Set configuration overrides for each SOC
switch $_soc {
@@ -95,7 +95,7 @@ switch $_soc {
set R5_CTIBASE {0x9d418000 0x9d419000 0x9d518000 0x9d519000}
# M4 processor
- set _mcu_m4_cores 1
+ set _gp_mcu_cores 1
}
j721e {
set _CHIPNAME j721e
@@ -246,22 +246,22 @@ if { $_main1_r5_cores != 0 } {
}
}
-if { $_mcu_m4_cores != 0 } {
- cti create $_CTINAME.m4 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
- target create $_TARGETNAME.m4 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
- $_TARGETNAME.m4 configure -event reset-assert { }
+if { $_gp_mcu_cores != 0 } {
+ cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
+ target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+ $_TARGETNAME.gp_mcu configure -event reset-assert { }
- proc m4_up {} {
- # To access M4, we need to enable the JTAG access for the same.
+ proc gp_mcu_up {} {
+ # To access GP MCU, we need to enable the JTAG access for the same.
# Ensure Power-AP unlocked
- $::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 0] 0x00190000
- $::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 1] 0x00102098
+ $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 0] 0x00190000
+ $::_CHIPNAME.dap apreg 3 [lindex $::_gp_mcu_ap_unlock_offsets 1] 0x00102098
- $::_TARGETNAME.m4 arp_examine
+ $::_TARGETNAME.gp_mcu arp_examine
}
- $_TARGETNAME.m4 configure -event gdb-attach {
- m4_up
+ $_TARGETNAME.gp_mcu configure -event gdb-attach {
+ gp_mcu_up
# gdb-attach default rule
halt 1000
}
-----------------------------------------------------------------------
Summary of changes:
tcl/target/ti_k3.cfg | 69 ++++++++++++++++++++++------------------------------
1 file changed, 29 insertions(+), 40 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-03-12 09:40:17
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 77b02b89ae689867bb38e11d3fa6ff59c8d22357 (commit)
via c280c9835705a7d104996569068826a73b665010 (commit)
from 2b17a128841c9431f17aaad844f416eccd24f63f (commit)
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- Log -----------------------------------------------------------------
commit 77b02b89ae689867bb38e11d3fa6ff59c8d22357
Author: Nishanth Menon <nm...@ti...>
Date: Fri Oct 1 23:02:23 2021 -0500
tcl/target/ti_k3: Rename m3 target as sysctrl
The M3 is the system controller of the system. Lets rename it to make
clear what we are debugging - esp when multiple MCUs are present in the
system.
Signed-off-by: Nishanth Menon <nm...@ti...>
Change-Id: I4cd03b6068b8ce140fd254f9dd88151c4c7006d7
Reviewed-on: https://review.openocd.org/c/openocd/+/6618
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 8fb71482c..ee4a5c8b3 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -27,11 +27,11 @@ if { [info exists V8_SMP_DEBUG] } {
# Common Definitions
-# CM3 the very first processor - all current SoCs have it.
+# System Controller is the very first processor - all current SoCs have it.
set CM3_CTIBASE {0x3C016000}
-# M3 power-ap unlock offsets
-set _m3_ap_unlock_offsets {0xf0 0x44}
+# sysctrl power-ap unlock offsets
+set _sysctrl_ap_unlock_offsets {0xf0 0x44}
# All the ARMV8s are the next processors.
# CL0,CORE0 CL0,CORE1 CL1,CORE0 CL1,CORE1
@@ -70,8 +70,8 @@ switch $_soc {
set _main1_r5_cores 0
set _main1_base_core_id 0
- # M3 power-ap unlock offsets
- set _m3_ap_unlock_offsets {0xf0 0x50}
+ # Sysctrl power-ap unlock offsets
+ set _sysctrl_ap_unlock_offsets {0xf0 0x50}
}
am642 {
set _CHIPNAME am642
@@ -147,22 +147,22 @@ set _TARGETNAME $_CHIPNAME.cpu
set _CTINAME $_CHIPNAME.cti
-# M3 is always present
-cti create $_CTINAME.m3 -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
-target create $_TARGETNAME.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
-$_TARGETNAME.m3 configure -event reset-assert { }
+# sysctrl is always present
+cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
+$_TARGETNAME.sysctrl configure -event reset-assert { }
-proc m3_up {} {
- # To access M3, we need to enable the JTAG access for the same.
+proc sysctrl_up {} {
+ # To access sysctrl, we need to enable the JTAG access for the same.
# Ensure Power-AP unlocked
- $::_CHIPNAME.dap apreg 3 [lindex $::_m3_ap_unlock_offsets 0] 0x00190000
- $::_CHIPNAME.dap apreg 3 [lindex $::_m3_ap_unlock_offsets 1] 0x00102098
+ $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 0] 0x00190000
+ $::_CHIPNAME.dap apreg 3 [lindex $::_sysctrl_ap_unlock_offsets 1] 0x00102098
- $::_TARGETNAME.m3 arp_examine
+ $::_TARGETNAME.sysctrl arp_examine
}
-$_TARGETNAME.m3 configure -event gdb-attach {
- m3_up
+$_TARGETNAME.sysctrl configure -event gdb-attach {
+ sysctrl_up
# gdb-attach default rule
halt 1000
}
commit c280c9835705a7d104996569068826a73b665010
Author: Nishanth Menon <nm...@ti...>
Date: Fri Oct 1 22:48:34 2021 -0500
tcl/target/ti_k3: Add a gdb-attach event hook for m3 and m4
Add gdb-attach event to call the "up" function of m3 and m4 allowing for
more seamless integration with gdb for end users. We still retain _up
functions for non-gdb functionality.
NOTE: we add a halt 1000 to retain the default gdb-attach hook behavior
Suggested-by: Antonio Borneo <bor...@gm...>
Signed-off-by: Nishanth Menon <nm...@ti...>
Change-Id: I2e51fdbd8756f156551e589c748c3a338afa655c
Reviewed-on: https://review.openocd.org/c/openocd/+/6615
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 325ee0004..8fb71482c 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -161,6 +161,12 @@ proc m3_up {} {
$::_TARGETNAME.m3 arp_examine
}
+$_TARGETNAME.m3 configure -event gdb-attach {
+ m3_up
+ # gdb-attach default rule
+ halt 1000
+}
+
set _v8_smp_targets ""
for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
@@ -253,4 +259,10 @@ if { $_mcu_m4_cores != 0 } {
$::_TARGETNAME.m4 arp_examine
}
+
+ $_TARGETNAME.m4 configure -event gdb-attach {
+ m4_up
+ # gdb-attach default rule
+ halt 1000
+ }
}
-----------------------------------------------------------------------
Summary of changes:
tcl/target/ti_k3.cfg | 40 ++++++++++++++++++++++++++--------------
1 file changed, 26 insertions(+), 14 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-03-12 09:39:51
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 2b17a128841c9431f17aaad844f416eccd24f63f (commit)
from 4906176c77d70e89a7e1f7da54e4088c5966207f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 2b17a128841c9431f17aaad844f416eccd24f63f
Author: Nishanth Menon <nm...@ti...>
Date: Mon Oct 4 08:34:42 2021 -0500
tcl/target/ti_k3: Remove args from m3 and m4_up
args serve no purpose, so drop them.
Signed-off-by: Nishanth Menon <nm...@ti...>
Change-Id: I136394307016453d576cf524b0f02227ba26ef8a
Reviewed-on: https://review.openocd.org/c/openocd/+/6626
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index d2aa53160..325ee0004 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -152,7 +152,7 @@ cti create $_CTINAME.m3 -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTI
target create $_TARGETNAME.m3 cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
$_TARGETNAME.m3 configure -event reset-assert { }
-proc m3_up { args } {
+proc m3_up {} {
# To access M3, we need to enable the JTAG access for the same.
# Ensure Power-AP unlocked
$::_CHIPNAME.dap apreg 3 [lindex $::_m3_ap_unlock_offsets 0] 0x00190000
@@ -245,7 +245,7 @@ if { $_mcu_m4_cores != 0 } {
target create $_TARGETNAME.m4 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
$_TARGETNAME.m4 configure -event reset-assert { }
- proc m4_up { args } {
+ proc m4_up {} {
# To access M4, we need to enable the JTAG access for the same.
# Ensure Power-AP unlocked
$::_CHIPNAME.dap apreg 3 [lindex $::_m4_ap_unlock_offsets 0] 0x00190000
-----------------------------------------------------------------------
Summary of changes:
tcl/target/ti_k3.cfg | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: OpenOCD-Gerrit <ope...@us...> - 2022-03-12 09:37:43
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4906176c77d70e89a7e1f7da54e4088c5966207f (commit)
via f583f338b086ed3a1cd471e1fd8ef99589a64dae (commit)
from 57c1e491801c6e67cb8b429bcf5c0ecf1bcef27b (commit)
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- Log -----------------------------------------------------------------
commit 4906176c77d70e89a7e1f7da54e4088c5966207f
Author: Tarek BOCHKATI <tar...@gm...>
Date: Fri Feb 25 17:05:03 2022 +0100
cortex_m: use LOG_TARGET_XXX
Change-Id: I8be0f67442644031e6e8df3090d81af195caf82b
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6672
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 7125e9e83..108f7e790 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -185,7 +185,7 @@ static int cortex_m_load_core_reg_u32(struct target *target,
break;
cortex_m->slow_register_read = true; /* Polling (still) needed. */
if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
- LOG_ERROR("Timeout waiting for DCRDR transfer ready");
+ LOG_TARGET_ERROR(target, "Timeout waiting for DCRDR transfer ready");
return ERROR_TIMEOUT_REACHED;
}
keep_alive();
@@ -223,7 +223,7 @@ static int cortex_m_slow_read_all_regs(struct target *target)
}
if (!cortex_m->slow_register_read)
- LOG_DEBUG("Switching back to fast register reads");
+ LOG_TARGET_DEBUG(target, "Switching back to fast register reads");
return ERROR_OK;
}
@@ -319,7 +319,7 @@ static int cortex_m_fast_read_all_regs(struct target *target)
for (unsigned int i = 0; i < wi; i++) {
if ((dhcsr[i] & S_REGRDY) == 0) {
not_ready = true;
- LOG_DEBUG("Register %u was not ready during fast read", i);
+ LOG_TARGET_DEBUG(target, "Register %u was not ready during fast read", i);
}
cortex_m_cumulate_dhcsr_sticky(cortex_m, dhcsr[i]);
}
@@ -330,7 +330,7 @@ static int cortex_m_fast_read_all_regs(struct target *target)
return ERROR_TIMEOUT_REACHED;
}
- LOG_DEBUG("read %u 32-bit registers", wi);
+ LOG_TARGET_DEBUG(target, "read %u 32-bit registers", wi);
unsigned int ri = 0; /* read index from r_vals array */
for (reg_id = 0; reg_id < num_regs; reg_id++) {
@@ -403,7 +403,7 @@ static int cortex_m_store_core_reg_u32(struct target *target,
if (cortex_m->dcb_dhcsr & S_REGRDY)
break;
if (timeval_ms() > then + DHCSR_S_REGRDY_TIMEOUT) {
- LOG_ERROR("Timeout waiting for DCRDR transfer ready");
+ LOG_TARGET_ERROR(target, "Timeout waiting for DCRDR transfer ready");
return ERROR_TIMEOUT_REACHED;
}
keep_alive();
@@ -528,7 +528,7 @@ static int cortex_m_clear_halt(struct target *target)
retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
+ LOG_TARGET_DEBUG(target, "NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
return ERROR_OK;
}
@@ -550,7 +550,7 @@ static int cortex_m_single_step_core(struct target *target)
retval = cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG(" ");
+ LOG_TARGET_DEBUG(target, "single step");
/* restore dhcsr reg */
cortex_m_clear_halt(target);
@@ -590,7 +590,7 @@ static int cortex_m_endreset_event(struct target *target)
retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
+ LOG_TARGET_DEBUG(target, "DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
/* this register is used for emulated dcc channel */
retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
@@ -629,7 +629,7 @@ static int cortex_m_endreset_event(struct target *target)
/* Enable FPB */
retval = cortex_m_enable_fpb(target);
if (retval != ERROR_OK) {
- LOG_ERROR("Failed to enable the FPB");
+ LOG_TARGET_ERROR(target, "Failed to enable the FPB");
return retval;
}
@@ -766,7 +766,7 @@ static int cortex_m_examine_exception_reason(struct target *target)
}
retval = dap_run(swjdp);
if (retval == ERROR_OK)
- LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
+ LOG_TARGET_DEBUG(target, "%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32
", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32,
armv7m_exception_string(armv7m->exception_number),
shcsr, except_sr, cfsr, except_ar);
@@ -782,7 +782,7 @@ static int cortex_m_debug_entry(struct target *target)
struct arm *arm = &armv7m->arm;
struct reg *r;
- LOG_DEBUG(" ");
+ LOG_TARGET_DEBUG(target, " ");
/* Do this really early to minimize the window where the MASKINTS erratum
* can pile up pending interrupts. */
@@ -815,7 +815,7 @@ static int cortex_m_debug_entry(struct target *target)
retval = cortex_m_fast_read_all_regs(target);
if (retval == ERROR_TIMEOUT_REACHED) {
cortex_m->slow_register_read = true;
- LOG_DEBUG("Switched to slow register read");
+ LOG_TARGET_DEBUG(target, "Switched to slow register read");
}
}
@@ -855,7 +855,8 @@ static int cortex_m_debug_entry(struct target *target)
if (armv7m->exception_number)
cortex_m_examine_exception_reason(target);
- LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", cpu in %s state, target->state: %s",
+ LOG_TARGET_DEBUG(target, "entered debug state in core mode: %s at PC 0x%" PRIx32
+ ", cpu in %s state, target->state: %s",
arm_mode_name(arm->core_mode),
buf_get_u32(arm->pc->value, 0, 32),
secure_state ? "Secure" : "Non-Secure",
@@ -889,8 +890,7 @@ static int cortex_m_poll(struct target *target)
* section B1.5.15 "Unrecoverable exception cases".
*/
if (cortex_m->dcb_dhcsr & S_LOCKUP) {
- LOG_ERROR("%s -- clearing lockup after double fault",
- target_name(target));
+ LOG_TARGET_ERROR(target, "clearing lockup after double fault");
cortex_m_write_debug_halt_mask(target, C_HALT, 0);
target->debug_reason = DBG_REASON_DBGRQ;
@@ -909,7 +909,7 @@ static int cortex_m_poll(struct target *target)
cortex_m->dcb_dhcsr_cumulated_sticky &= ~S_RESET_ST;
if (target->state != TARGET_RESET) {
target->state = TARGET_RESET;
- LOG_INFO("%s: external reset detected", target_name(target));
+ LOG_TARGET_INFO(target, "external reset detected");
}
return ERROR_OK;
}
@@ -918,7 +918,7 @@ static int cortex_m_poll(struct target *target)
/* Cannot switch context while running so endreset is
* called with target->state == TARGET_RESET
*/
- LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32,
+ LOG_TARGET_DEBUG(target, "Exit from reset with dcb_dhcsr 0x%" PRIx32,
cortex_m->dcb_dhcsr);
retval = cortex_m_endreset_event(target);
if (retval != ERROR_OK) {
@@ -943,7 +943,6 @@ static int cortex_m_poll(struct target *target)
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
}
if (prev_target_state == TARGET_DEBUG_RUNNING) {
- LOG_DEBUG(" ");
retval = cortex_m_debug_entry(target);
if (retval != ERROR_OK)
return retval;
@@ -971,7 +970,7 @@ static int cortex_m_poll(struct target *target)
register_cache_invalidate(armv7m->arm.core_cache);
target->state = TARGET_RUNNING;
- LOG_WARNING("%s: external resume detected", target_name(target));
+ LOG_TARGET_WARNING(target, "external resume detected");
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
retval = ERROR_OK;
}
@@ -984,20 +983,19 @@ static int cortex_m_poll(struct target *target)
static int cortex_m_halt(struct target *target)
{
- LOG_DEBUG("target->state: %s",
- target_state_name(target));
+ LOG_TARGET_DEBUG(target, "target->state: %s", target_state_name(target));
if (target->state == TARGET_HALTED) {
- LOG_DEBUG("target was already halted");
+ LOG_TARGET_DEBUG(target, "target was already halted");
return ERROR_OK;
}
if (target->state == TARGET_UNKNOWN)
- LOG_WARNING("target was in unknown state when halt was requested");
+ LOG_TARGET_WARNING(target, "target was in unknown state when halt was requested");
if (target->state == TARGET_RESET) {
if ((jtag_get_reset_config() & RESET_SRST_PULLS_TRST) && jtag_get_srst()) {
- LOG_ERROR("can't request a halt while in reset if nSRST pulls nTRST");
+ LOG_TARGET_ERROR(target, "can't request a halt while in reset if nSRST pulls nTRST");
return ERROR_TARGET_FAILURE;
} else {
/* we came here in a reset_halt or reset_init sequence
@@ -1031,10 +1029,10 @@ static int cortex_m_soft_reset_halt(struct target *target)
* can be obtained by using 'reset halt' and 'cortex_m reset_config vectreset'.
* As this reset only uses VC_CORERESET it would only ever reset the cortex_m
* core, not the peripherals */
- LOG_DEBUG("soft_reset_halt is discouraged, please use 'reset halt' instead.");
+ LOG_TARGET_DEBUG(target, "soft_reset_halt is discouraged, please use 'reset halt' instead.");
if (!cortex_m->vectreset_supported) {
- LOG_ERROR("VECTRESET is not supported on this Cortex-M core");
+ LOG_TARGET_ERROR(target, "VECTRESET is not supported on this Cortex-M core");
return ERROR_FAIL;
}
@@ -1068,15 +1066,16 @@ static int cortex_m_soft_reset_halt(struct target *target)
return retval;
if ((cortex_m->dcb_dhcsr & S_HALT)
&& (cortex_m->nvic_dfsr & DFSR_VCATCH)) {
- LOG_DEBUG("system reset-halted, DHCSR 0x%08" PRIx32 ", DFSR 0x%08" PRIx32,
- cortex_m->dcb_dhcsr, cortex_m->nvic_dfsr);
+ LOG_TARGET_DEBUG(target, "system reset-halted, DHCSR 0x%08" PRIx32 ", DFSR 0x%08" PRIx32,
+ cortex_m->dcb_dhcsr, cortex_m->nvic_dfsr);
cortex_m_poll(target);
/* FIXME restore user's vector catch config */
return ERROR_OK;
- } else
- LOG_DEBUG("waiting for system reset-halt, "
+ } else {
+ LOG_TARGET_DEBUG(target, "waiting for system reset-halt, "
"DHCSR 0x%08" PRIx32 ", %d ms",
cortex_m->dcb_dhcsr, timeout);
+ }
}
timeout++;
alive_sleep(1);
@@ -1106,7 +1105,7 @@ static int cortex_m_resume(struct target *target, int current,
struct reg *r;
if (target->state != TARGET_HALTED) {
- LOG_WARNING("target not halted");
+ LOG_TARGET_WARNING(target, "target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1170,7 +1169,7 @@ static int cortex_m_resume(struct target *target, int current,
/* Single step past breakpoint at current address */
breakpoint = breakpoint_find(target, resume_pc);
if (breakpoint) {
- LOG_DEBUG("unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
+ LOG_TARGET_DEBUG(target, "unset breakpoint at " TARGET_ADDR_FMT " (ID: %" PRIu32 ")",
breakpoint->address,
breakpoint->unique_id);
cortex_m_unset_breakpoint(target, breakpoint);
@@ -1191,11 +1190,11 @@ static int cortex_m_resume(struct target *target, int current,
if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
- LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
+ LOG_TARGET_DEBUG(target, "target resumed at 0x%" PRIx32 "", resume_pc);
} else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
- LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
+ LOG_TARGET_DEBUG(target, "target debug resumed at 0x%" PRIx32 "", resume_pc);
}
return ERROR_OK;
@@ -1214,7 +1213,7 @@ static int cortex_m_step(struct target *target, int current,
bool isr_timed_out = false;
if (target->state != TARGET_HALTED) {
- LOG_WARNING("target not halted");
+ LOG_TARGET_WARNING(target, "target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1287,7 +1286,7 @@ static int cortex_m_step(struct target *target, int current,
*
*/
if ((pc_value & 0x02) && breakpoint_find(target, pc_value & ~0x03)) {
- LOG_DEBUG("Stepping over next instruction with interrupts disabled");
+ LOG_TARGET_DEBUG(target, "Stepping over next instruction with interrupts disabled");
cortex_m_write_debug_halt_mask(target, C_HALT | C_MASKINTS, 0);
cortex_m_write_debug_halt_mask(target, C_STEP, C_HALT);
/* Re-enable interrupts if appropriate */
@@ -1318,7 +1317,7 @@ static int cortex_m_step(struct target *target, int current,
cortex_m_set_maskints_for_halt(target);
} else {
/* Start the core */
- LOG_DEBUG("Starting core to serve pending interrupts");
+ LOG_TARGET_DEBUG(target, "Starting core to serve pending interrupts");
int64_t t_start = timeval_ms();
cortex_m_set_maskints_for_run(target);
cortex_m_write_debug_halt_mask(target, 0, C_HALT | C_STEP);
@@ -1342,7 +1341,7 @@ static int cortex_m_step(struct target *target, int current,
}
if (isr_timed_out) {
- LOG_DEBUG("Interrupt handlers didn't complete within time, "
+ LOG_TARGET_DEBUG(target, "Interrupt handlers didn't complete within time, "
"leaving target running");
} else {
/* Step over next instruction with interrupts disabled */
@@ -1377,7 +1376,7 @@ static int cortex_m_step(struct target *target, int current,
return ERROR_OK;
}
- LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
+ LOG_TARGET_DEBUG(target, "target stepped dcb_dhcsr = 0x%" PRIx32
" nvic_icsr = 0x%" PRIx32,
cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
@@ -1386,7 +1385,7 @@ static int cortex_m_step(struct target *target, int current,
return retval;
target_call_event_callbacks(target, TARGET_EVENT_HALTED);
- LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32
+ LOG_TARGET_DEBUG(target, "target stepped dcb_dhcsr = 0x%" PRIx32
" nvic_icsr = 0x%" PRIx32,
cortex_m->dcb_dhcsr, cortex_m->nvic_icsr);
@@ -1399,7 +1398,7 @@ static int cortex_m_assert_reset(struct target *target)
struct armv7m_common *armv7m = &cortex_m->armv7m;
enum cortex_m_soft_reset_config reset_config = cortex_m->soft_reset_config;
- LOG_DEBUG("target->state: %s",
+ LOG_TARGET_DEBUG(target, "target->state: %s",
target_state_name(target));
enum reset_types jtag_reset_config = jtag_get_reset_config();
@@ -1423,10 +1422,10 @@ static int cortex_m_assert_reset(struct target *target)
if (jtag_reset_config & RESET_HAS_SRST) {
adapter_assert_reset();
if (target->reset_halt)
- LOG_ERROR("Target not examined, will not halt after reset!");
+ LOG_TARGET_ERROR(target, "Target not examined, will not halt after reset!");
return ERROR_OK;
} else {
- LOG_ERROR("Target not examined, reset NOT asserted!");
+ LOG_TARGET_ERROR(target, "Target not examined, reset NOT asserted!");
return ERROR_FAIL;
}
}
@@ -1473,7 +1472,7 @@ static int cortex_m_assert_reset(struct target *target)
retval2 = mem_ap_write_atomic_u32(armv7m->debug_ap, DCB_DEMCR,
TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
if (retval != ERROR_OK || retval2 != ERROR_OK)
- LOG_INFO("AP write error, reset will not halt");
+ LOG_TARGET_INFO(target, "AP write error, reset will not halt");
}
if (jtag_reset_config & RESET_HAS_SRST) {
@@ -1493,15 +1492,15 @@ static int cortex_m_assert_reset(struct target *target)
if (!cortex_m->vectreset_supported
&& reset_config == CORTEX_M_RESET_VECTRESET) {
reset_config = CORTEX_M_RESET_SYSRESETREQ;
- LOG_WARNING("VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
- LOG_WARNING("Set 'cortex_m reset_config sysresetreq'.");
+ LOG_TARGET_WARNING(target, "VECTRESET is not supported on this Cortex-M core, using SYSRESETREQ instead.");
+ LOG_TARGET_WARNING(target, "Set 'cortex_m reset_config sysresetreq'.");
}
- LOG_DEBUG("Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
+ LOG_TARGET_DEBUG(target, "Using Cortex-M %s", (reset_config == CORTEX_M_RESET_SYSRESETREQ)
? "SYSRESETREQ" : "VECTRESET");
if (reset_config == CORTEX_M_RESET_VECTRESET) {
- LOG_WARNING("Only resetting the Cortex-M core, use a reset-init event "
+ LOG_TARGET_WARNING(target, "Only resetting the Cortex-M core, use a reset-init event "
"handler to reset any peripherals or configure hardware srst support.");
}
@@ -1510,11 +1509,11 @@ static int cortex_m_assert_reset(struct target *target)
AIRCR_VECTKEY | ((reset_config == CORTEX_M_RESET_SYSRESETREQ)
? AIRCR_SYSRESETREQ : AIRCR_VECTRESET));
if (retval3 != ERROR_OK)
- LOG_DEBUG("Ignoring AP write error right after reset");
+ LOG_TARGET_DEBUG(target, "Ignoring AP write error right after reset");
retval3 = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
if (retval3 != ERROR_OK) {
- LOG_ERROR("DP initialisation failed");
+ LOG_TARGET_ERROR(target, "DP initialisation failed");
/* The error return value must not be propagated in this case.
* SYSRESETREQ or VECTRESET have been possibly triggered
* so reset processing should continue */
@@ -1550,7 +1549,7 @@ static int cortex_m_deassert_reset(struct target *target)
{
struct armv7m_common *armv7m = &target_to_cm(target)->armv7m;
- LOG_DEBUG("target->state: %s",
+ LOG_TARGET_DEBUG(target, "target->state: %s",
target_state_name(target));
/* deassert reset lines */
@@ -1564,7 +1563,7 @@ static int cortex_m_deassert_reset(struct target *target)
int retval = dap_dp_init_or_reconnect(armv7m->debug_ap->dap);
if (retval != ERROR_OK) {
- LOG_ERROR("DP initialisation failed");
+ LOG_TARGET_ERROR(target, "DP initialisation failed");
return retval;
}
}
@@ -1580,7 +1579,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
if (breakpoint->set) {
- LOG_WARNING("breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
+ LOG_TARGET_WARNING(target, "breakpoint (BPID: %" PRIu32 ") already set", breakpoint->unique_id);
return ERROR_OK;
}
@@ -1589,35 +1588,36 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
while (comparator_list[fp_num].used && (fp_num < cortex_m->fp_num_code))
fp_num++;
if (fp_num >= cortex_m->fp_num_code) {
- LOG_ERROR("Can not find free FPB Comparator!");
+ LOG_TARGET_ERROR(target, "Can not find free FPB Comparator!");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
breakpoint->set = fp_num + 1;
fpcr_value = breakpoint->address | 1;
if (cortex_m->fp_rev == 0) {
if (breakpoint->address > 0x1FFFFFFF) {
- LOG_ERROR("Cortex-M Flash Patch Breakpoint rev.1 cannot handle HW breakpoint above address 0x1FFFFFFE");
+ LOG_TARGET_ERROR(target, "Cortex-M Flash Patch Breakpoint rev.1 "
+ "cannot handle HW breakpoint above address 0x1FFFFFFE");
return ERROR_FAIL;
}
uint32_t hilo;
hilo = (breakpoint->address & 0x2) ? FPCR_REPLACE_BKPT_HIGH : FPCR_REPLACE_BKPT_LOW;
fpcr_value = (fpcr_value & 0x1FFFFFFC) | hilo | 1;
} else if (cortex_m->fp_rev > 1) {
- LOG_ERROR("Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
+ LOG_TARGET_ERROR(target, "Unhandled Cortex-M Flash Patch Breakpoint architecture revision");
return ERROR_FAIL;
}
comparator_list[fp_num].used = true;
comparator_list[fp_num].fpcr_value = fpcr_value;
target_write_u32(target, comparator_list[fp_num].fpcr_address,
comparator_list[fp_num].fpcr_value);
- LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "",
+ LOG_TARGET_DEBUG(target, "fpc_num %i fpcr_value 0x%" PRIx32 "",
fp_num,
comparator_list[fp_num].fpcr_value);
if (!cortex_m->fpb_enabled) {
- LOG_DEBUG("FPB wasn't enabled, do it now");
+ LOG_TARGET_DEBUG(target, "FPB wasn't enabled, do it now");
retval = cortex_m_enable_fpb(target);
if (retval != ERROR_OK) {
- LOG_ERROR("Failed to enable the FPB");
+ LOG_TARGET_ERROR(target, "Failed to enable the FPB");
return retval;
}
@@ -1646,7 +1646,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
breakpoint->set = true;
}
- LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
+ LOG_TARGET_DEBUG(target, "BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
breakpoint->unique_id,
(int)(breakpoint->type),
breakpoint->address,
@@ -1663,11 +1663,11 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
struct cortex_m_fp_comparator *comparator_list = cortex_m->fp_comparator_list;
if (breakpoint->set <= 0) {
- LOG_WARNING("breakpoint not set");
+ LOG_TARGET_WARNING(target, "breakpoint not set");
return ERROR_OK;
}
- LOG_DEBUG("BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
+ LOG_TARGET_DEBUG(target, "BPID: %" PRIu32 ", Type: %d, Address: " TARGET_ADDR_FMT " Length: %d (set=%d)",
breakpoint->unique_id,
(int)(breakpoint->type),
breakpoint->address,
@@ -1677,7 +1677,7 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
if (breakpoint->type == BKPT_HARD) {
unsigned int fp_num = breakpoint->set - 1;
if (fp_num >= cortex_m->fp_num_code) {
- LOG_DEBUG("Invalid FP Comparator number in breakpoint");
+ LOG_TARGET_DEBUG(target, "Invalid FP Comparator number in breakpoint");
return ERROR_OK;
}
comparator_list[fp_num].used = false;
@@ -1700,12 +1700,12 @@ int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoi
int cortex_m_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
{
if (breakpoint->length == 3) {
- LOG_DEBUG("Using a two byte breakpoint for 32bit Thumb-2 request");
+ LOG_TARGET_DEBUG(target, "Using a two byte breakpoint for 32bit Thumb-2 request");
breakpoint->length = 2;
}
if ((breakpoint->length != 2)) {
- LOG_INFO("only breakpoints of two bytes length supported");
+ LOG_TARGET_INFO(target, "only breakpoints of two bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -1737,7 +1737,7 @@ static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *wat
comparator++, dwt_num++)
continue;
if (dwt_num >= cortex_m->dwt_num_comp) {
- LOG_ERROR("Can not find free DWT Comparator");
+ LOG_TARGET_ERROR(target, "Can not find free DWT Comparator");
return ERROR_FAIL;
}
comparator->used = true;
@@ -1795,7 +1795,7 @@ static int cortex_m_set_watchpoint(struct target *target, struct watchpoint *wat
target_write_u32(target, comparator->dwt_comparator_address + 8,
comparator->function);
- LOG_DEBUG("Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
+ LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%d 0x%08x 0x%x 0x%05x",
watchpoint->unique_id, dwt_num,
(unsigned) comparator->comp,
(unsigned) comparator->mask,
@@ -1809,19 +1809,19 @@ static int cortex_m_unset_watchpoint(struct target *target, struct watchpoint *w
struct cortex_m_dwt_comparator *comparator;
if (watchpoint->set <= 0) {
- LOG_WARNING("watchpoint (wpid: %d) not set",
+ LOG_TARGET_WARNING(target, "watchpoint (wpid: %d) not set",
watchpoint->unique_id);
return ERROR_OK;
}
unsigned int dwt_num = watchpoint->set - 1;
- LOG_DEBUG("Watchpoint (ID %d) DWT%d address: 0x%08x clear",
+ LOG_TARGET_DEBUG(target, "Watchpoint (ID %d) DWT%d address: 0x%08x clear",
watchpoint->unique_id, dwt_num,
(unsigned) watchpoint->address);
if (dwt_num >= cortex_m->dwt_num_comp) {
- LOG_DEBUG("Invalid DWT Comparator number in watchpoint");
+ LOG_TARGET_DEBUG(target, "Invalid DWT Comparator number in watchpoint");
return ERROR_OK;
}
@@ -1841,13 +1841,13 @@ int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint
struct cortex_m_common *cortex_m = target_to_cm(target);
if (cortex_m->dwt_comp_available < 1) {
- LOG_DEBUG("no comparators?");
+ LOG_TARGET_DEBUG(target, "no comparators?");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
/* hardware doesn't support data value masking */
if (watchpoint->mask != ~(uint32_t)0) {
- LOG_DEBUG("watchpoint value masks not supported");
+ LOG_TARGET_DEBUG(target, "watchpoint value masks not supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -1859,11 +1859,11 @@ int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint
break;
}
if (mask == 16) {
- LOG_DEBUG("unsupported watchpoint length");
+ LOG_TARGET_DEBUG(target, "unsupported watchpoint length");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (watchpoint->address & ((1 << mask) - 1)) {
- LOG_DEBUG("watchpoint address is unaligned");
+ LOG_TARGET_DEBUG(target, "watchpoint address is unaligned");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
@@ -1875,12 +1875,12 @@ int cortex_m_add_watchpoint(struct target *target, struct watchpoint *watchpoint
* the data, and another comparator (DATAVADDR0) matching addr.
*/
if (watchpoint->value) {
- LOG_DEBUG("data value watchpoint not YET supported");
+ LOG_TARGET_DEBUG(target, "data value watchpoint not YET supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
cortex_m->dwt_comp_available--;
- LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
+ LOG_TARGET_DEBUG(target, "dwt_comp_available: %d", cortex_m->dwt_comp_available);
return ERROR_OK;
}
@@ -1891,7 +1891,7 @@ int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpo
/* REVISIT why check? DWT can be updated with core running ... */
if (target->state != TARGET_HALTED) {
- LOG_WARNING("target not halted");
+ LOG_TARGET_WARNING(target, "target not halted");
return ERROR_TARGET_NOT_HALTED;
}
@@ -1899,7 +1899,7 @@ int cortex_m_remove_watchpoint(struct target *target, struct watchpoint *watchpo
cortex_m_unset_watchpoint(target, watchpoint);
cortex_m->dwt_comp_available++;
- LOG_DEBUG("dwt_comp_available: %d", cortex_m->dwt_comp_available);
+ LOG_TARGET_DEBUG(target, "dwt_comp_available: %d", cortex_m->dwt_comp_available);
return ERROR_OK;
}
@@ -2004,18 +2004,18 @@ int cortex_m_profiling(struct target *target, uint32_t *samples,
retval = target_read_u32(target, DWT_PCSR, ®_value);
if (retval != ERROR_OK) {
- LOG_ERROR("Error while reading PCSR");
+ LOG_TARGET_ERROR(target, "Error while reading PCSR");
return retval;
}
if (reg_value == 0) {
- LOG_INFO("PCSR sampling not supported on this processor.");
+ LOG_TARGET_INFO(target, "PCSR sampling not supported on this processor.");
return target_profiling_default(target, samples, max_num_samples, num_samples, seconds);
}
gettimeofday(&timeout, NULL);
timeval_add_time(&timeout, seconds, 0);
- LOG_INFO("Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
+ LOG_TARGET_INFO(target, "Starting Cortex-M profiling. Sampling DWT_PCSR as fast as we can...");
/* Make sure the target is running */
target_poll(target);
@@ -2023,7 +2023,7 @@ int cortex_m_profiling(struct target *target, uint32_t *samples,
retval = target_resume(target, 1, 0, 0, 0);
if (retval != ERROR_OK) {
- LOG_ERROR("Error while resuming target");
+ LOG_TARGET_ERROR(target, "Error while resuming target");
return retval;
}
@@ -2044,14 +2044,14 @@ int cortex_m_profiling(struct target *target, uint32_t *samples,
}
if (retval != ERROR_OK) {
- LOG_ERROR("Error while reading PCSR");
+ LOG_TARGET_ERROR(target, "Error while reading PCSR");
return retval;
}
gettimeofday(&now, NULL);
if (sample_count >= max_num_samples || timeval_compare(&now, &timeout) > 0) {
- LOG_INFO("Profiling completed. %" PRIu32 " samples.", sample_count);
+ LOG_TARGET_INFO(target, "Profiling completed. %" PRIu32 " samples.", sample_count);
break;
}
}
@@ -2162,14 +2162,14 @@ static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target
int reg;
target_read_u32(target, DWT_CTRL, &dwtcr);
- LOG_DEBUG("DWT_CTRL: 0x%" PRIx32, dwtcr);
+ LOG_TARGET_DEBUG(target, "DWT_CTRL: 0x%" PRIx32, dwtcr);
if (!dwtcr) {
- LOG_DEBUG("no DWT");
+ LOG_TARGET_DEBUG(target, "no DWT");
return;
}
target_read_u32(target, DWT_DEVARCH, &cm->dwt_devarch);
- LOG_DEBUG("DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
+ LOG_TARGET_DEBUG(target, "DWT_DEVARCH: 0x%" PRIx32, cm->dwt_devarch);
cm->dwt_num_comp = (dwtcr >> 28) & 0xF;
cm->dwt_comp_available = cm->dwt_num_comp;
@@ -2178,7 +2178,7 @@ static void cortex_m_dwt_setup(struct cortex_m_common *cm, struct target *target
if (!cm->dwt_comparator_list) {
fail0:
cm->dwt_num_comp = 0;
- LOG_ERROR("out of mem");
+ LOG_TARGET_ERROR(target, "out of mem");
return;
}
@@ -2216,7 +2216,7 @@ fail1:
*register_get_last_cache_p(&target->reg_cache) = cache;
cm->dwt_cache = cache;
- LOG_DEBUG("DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
+ LOG_TARGET_DEBUG(target, "DWT dwtcr 0x%" PRIx32 ", comp %d, watch%s",
dwtcr, cm->dwt_num_comp,
(dwtcr & (0xf << 24)) ? " only" : "/trigger");
@@ -2283,7 +2283,7 @@ int cortex_m_examine(struct target *target)
/* Search for the MEM-AP */
retval = cortex_m_find_mem_ap(swjdp, &armv7m->debug_ap);
if (retval != ERROR_OK) {
- LOG_ERROR("Could not find MEM-AP to control the core");
+ LOG_TARGET_ERROR(target, "Could not find MEM-AP to control the core");
return retval;
}
} else {
@@ -2316,14 +2316,13 @@ int cortex_m_examine(struct target *target)
}
if (!cortex_m->core_info) {
- LOG_ERROR("Cortex-M PARTNO 0x%x is unrecognized", core_partno);
+ LOG_TARGET_ERROR(target, "Cortex-M PARTNO 0x%x is unrecognized", core_partno);
return ERROR_FAIL;
}
armv7m->arm.arch = cortex_m->core_info->arch;
- LOG_INFO("%s: %s r%" PRId8 "p%" PRId8 " processor detected",
- target_name(target),
+ LOG_TARGET_INFO(target, "%s r%" PRId8 "p%" PRId8 " processor detected",
cortex_m->core_info->name,
(uint8_t)((cpuid >> 20) & 0xf),
(uint8_t)((cpuid >> 0) & 0xf));
@@ -2334,11 +2333,11 @@ int cortex_m_examine(struct target *target)
rev = (cpuid >> 20) & 0xf;
patch = (cpuid >> 0) & 0xf;
if ((rev == 0) && (patch < 2)) {
- LOG_WARNING("Silicon bug: single stepping may enter pending exception handler!");
+ LOG_TARGET_WARNING(target, "Silicon bug: single stepping may enter pending exception handler!");
cortex_m->maskints_erratum = true;
}
}
- LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
+ LOG_TARGET_DEBUG(target, "cpuid: 0x%8.8" PRIx32 "", cpuid);
if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV4) {
target_read_u32(target, MVFR0, &mvfr0);
@@ -2346,7 +2345,7 @@ int cortex_m_examine(struct target *target)
/* test for floating point feature on Cortex-M4 */
if ((mvfr0 == MVFR0_DEFAULT_M4) && (mvfr1 == MVFR1_DEFAULT_M4)) {
- LOG_DEBUG("%s floating point feature FPv4_SP found", cortex_m->core_info->name);
+ LOG_TARGET_DEBUG(target, "%s floating point feature FPv4_SP found", cortex_m->core_info->name);
armv7m->fp_feature = FPV4_SP;
}
} else if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV5) {
@@ -2355,10 +2354,10 @@ int cortex_m_examine(struct target *target)
/* test for floating point features on Cortex-M7 */
if ((mvfr0 == MVFR0_DEFAULT_M7_SP) && (mvfr1 == MVFR1_DEFAULT_M7_SP)) {
- LOG_DEBUG("%s floating point feature FPv5_SP found", cortex_m->core_info->name);
+ LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_SP found", cortex_m->core_info->name);
armv7m->fp_feature = FPV5_SP;
} else if ((mvfr0 == MVFR0_DEFAULT_M7_DP) && (mvfr1 == MVFR1_DEFAULT_M7_DP)) {
- LOG_DEBUG("%s floating point feature FPv5_DP found", cortex_m->core_info->name);
+ LOG_TARGET_DEBUG(target, "%s floating point feature FPv5_DP found", cortex_m->core_info->name);
armv7m->fp_feature = FPV5_DP;
}
}
@@ -2428,7 +2427,7 @@ int cortex_m_examine(struct target *target)
/* make sure we clear any breakpoints enabled on the target */
target_write_u32(target, cortex_m->fp_comparator_list[i].fpcr_address, 0);
}
- LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
+ LOG_TARGET_DEBUG(target, "FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i",
fpcr,
cortex_m->fp_num_code,
cortex_m->fp_num_lit);
@@ -2438,8 +2437,7 @@ int cortex_m_examine(struct target *target)
cortex_m_dwt_setup(cortex_m, target);
/* These hardware breakpoints only work for code in flash! */
- LOG_INFO("%s: target has %d breakpoints, %d watchpoints",
- target_name(target),
+ LOG_TARGET_INFO(target, "target has %d breakpoints, %d watchpoints",
cortex_m->fp_num_code,
cortex_m->dwt_num_comp);
}
@@ -2462,7 +2460,7 @@ static int cortex_m_dcc_read(struct target *target, uint8_t *value, uint8_t *ctr
*ctrl = (uint8_t)dcrdr;
*value = (uint8_t)(dcrdr >> 8);
- LOG_DEBUG("data 0x%x ctrl 0x%x", *value, *ctrl);
+ LOG_TARGET_DEBUG(target, "data 0x%x ctrl 0x%x", *value, *ctrl);
/* write ack back to software dcc register
* signify we have read data */
@@ -2569,7 +2567,7 @@ static int cortex_m_target_create(struct target *target, Jim_Interp *interp)
struct cortex_m_common *cortex_m = calloc(1, sizeof(struct cortex_m_common));
if (!cortex_m) {
- LOG_ERROR("No memory creating target");
+ LOG_TARGET_ERROR(target, "No memory creating target");
return ERROR_FAIL;
}
@@ -2626,7 +2624,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
return retval;
if (!target_was_examined(target)) {
- LOG_ERROR("Target not examined yet");
+ LOG_TARGET_ERROR(target, "Target not examined yet");
return ERROR_FAIL;
}
@@ -2655,7 +2653,7 @@ COMMAND_HANDLER(handle_cortex_m_vector_catch_command)
break;
}
if (i == ARRAY_SIZE(vec_ids)) {
- LOG_ERROR("No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
+ LOG_TARGET_ERROR(target, "No CM3 vector '%s'", CMD_ARGV[CMD_ARGC]);
return ERROR_COMMAND_SYNTAX_ERROR;
}
}
@@ -2745,7 +2743,7 @@ COMMAND_HANDLER(handle_cortex_m_reset_config_command)
else if (strcmp(*CMD_ARGV, "vectreset") == 0) {
if (target_was_examined(target)
&& !cortex_m->vectreset_supported)
- LOG_WARNING("VECTRESET is not supported on your Cortex-M core!");
+ LOG_TARGET_WARNING(target, "VECTRESET is not supported on your Cortex-M core!");
else
cortex_m->soft_reset_config = CORTEX_M_RESET_VECTRESET;
commit f583f338b086ed3a1cd471e1fd8ef99589a64dae
Author: Tarek BOCHKATI <tar...@gm...>
Date: Wed Sep 22 16:15:55 2021 +0100
tcl/stm32l5x|u5x: refactor common tcl code
both stm32l5x and stm32u5x configs are almost identical except
clock config.
while at there rename target procs to avoid issues with JTAG daisy
chaining.
Change-Id: Ibbb1dfeb91a7f8d5d45744cf57dca2877f60e0c5
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6596
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
diff --git a/tcl/target/stm32l5x.cfg b/tcl/target/stm32l5x.cfg
index 0616df1cb..c43b699d2 100644
--- a/tcl/target/stm32l5x.cfg
+++ b/tcl/target/stm32l5x.cfg
@@ -1,10 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# script for stm32l5x family
+# stm32l5x devices support both JTAG and SWD transports.
-#
-# stm32l5 devices support both JTAG and SWD transports.
-#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
@@ -14,78 +12,10 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME stm32l5x
}
-set _ENDIAN little
+source [find target/stm32x5x_common.cfg]
-# Work-area is a space in RAM used for flash programming
-# By default use 64kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x10000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- # See STM Document RM0438
- # RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
- # Corresponds to Cortex®-M33 JTAG debug port ID code
- set _CPUTAPID 0x0ba04477
- } {
- # SWD IDCODE (single drop, arm)
- set _CPUTAPID 0x0be12477
- }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-
-if {[using_jtag]} {
- jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
-
-# use non-secure RAM by default
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# create sec/ns flash and otp memories (sizes will be probed)
-flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
-
-# Common knowledges tells JTAG speed should be <= F_CPU/6.
-# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
-# the safe side.
-#
-# Note that there is a pretty wide band where things are
-# more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter speed 500
-
-adapter srst delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-proc is_secure {} {
- # read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
- set DSCSR [mrw 0xE000EE08]
- return [expr {($DSCSR & (1 << 16)) != 0}]
-}
-
-proc clock_config_110_mhz {} {
- set offset [expr {[is_secure] ? 0x10000000 : 0}]
+proc stm32l5x_clock_config {} {
+ set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
# MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
# RCC_APB1ENR1 = PWREN
mww [expr {0x40021058 + $offset}] 0x10000000
@@ -111,90 +41,8 @@ proc clock_config_110_mhz {} {
while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}
}
-proc ahb_ap_non_secure_access {} {
- # SPROT=1=Non Secure access, Priv=1
- [[target current] cget -dap] apcsw 0x4B000000 0x4F000000
-}
-
-proc ahb_ap_secure_access {} {
- # SPROT=0=Secure access, Priv=1
- [[target current] cget -dap] apcsw 0x0B000000 0x4F000000
-}
-
$_TARGETNAME configure -event reset-init {
- clock_config_110_mhz
+ stm32l5x_clock_config
# Boost JTAG frequency
adapter speed 4000
}
-
-$_TARGETNAME configure -event reset-start {
- # Reset clock is MSI (4 MHz)
- adapter speed 480
-}
-
-$_TARGETNAME configure -event examine-end {
- # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
- mmw 0xE0044004 0x00000006 0
-
- # Stop watchdog counters during halt
- # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
- mmw 0xE0044008 0x00001800 0
-}
-
-$_TARGETNAME configure -event halted {
- set secure [is_secure]
-
- if {$secure} {
- set secure_str "Secure"
- ahb_ap_secure_access
- } else {
- set secure_str "Non-Secure"
- ahb_ap_non_secure_access
- }
-
- # print the secure state only when it changes
- set _TARGETNAME [target current]
- global $_TARGETNAME.secure
-
- if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
- echo "CPU in $secure_str state"
- # update saved security state
- set $_TARGETNAME.secure $secure
- }
-}
-
-$_TARGETNAME configure -event gdb-flash-erase-start {
- set use_secure_workarea 0
- # check if FLASH_OPTR.TZEN is enabled
- set FLASH_OPTR [mrw 0x40022040]
- if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
- echo "TZEN option bit disabled"
- ahb_ap_non_secure_access
- } {
- ahb_ap_secure_access
- echo "TZEN option bit enabled"
-
- # check if FLASH_OPTR.RDP is not Level 0.5
- if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
- set use_secure_workarea 1
- }
- }
-
- set workarea_addr [$_TARGETNAME cget -work-area-phys]
- echo "workarea_addr $workarea_addr"
-
- if {$use_secure_workarea} {
- set workarea_addr [expr {$workarea_addr | 0x10000000}]
- } {
- set workarea_addr [expr {$workarea_addr & ~0x10000000}]
- }
-
- $_TARGETNAME configure -work-area-phys $workarea_addr
-}
-
-$_TARGETNAME configure -event trace-config {
- # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
- # change this value accordingly to configure trace pins
- # assignment
- mmw 0xE0044004 0x00000020 0
-}
diff --git a/tcl/target/stm32u5x.cfg b/tcl/target/stm32u5x.cfg
index 2c2c0e037..b627d4180 100644
--- a/tcl/target/stm32u5x.cfg
+++ b/tcl/target/stm32u5x.cfg
@@ -1,10 +1,8 @@
# SPDX-License-Identifier: GPL-2.0-or-later
# script for stm32u5x family
+# stm32u5x devices support both JTAG and SWD transports.
-#
-# stm32u5 devices support both JTAG and SWD transports.
-#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
@@ -14,78 +12,10 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME stm32u5x
}
-set _ENDIAN little
+source [find target/stm32x5x_common.cfg]
-# Work-area is a space in RAM used for flash programming
-# By default use 64kB
-if { [info exists WORKAREASIZE] } {
- set _WORKAREASIZE $WORKAREASIZE
-} else {
- set _WORKAREASIZE 0x10000
-}
-
-#jtag scan chain
-if { [info exists CPUTAPID] } {
- set _CPUTAPID $CPUTAPID
-} else {
- if { [using_jtag] } {
- # See STM Document RM0438
- # RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
- # Corresponds to Cortex®-M33 JTAG debug port ID code
- set _CPUTAPID 0x0ba04477
- } {
- # SWD IDCODE (single drop, arm)
- set _CPUTAPID 0x0be12477
- }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-
-if {[using_jtag]} {
- jtag newtap $_CHIPNAME bs -irlen 5
-}
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
-
-# use non-secure RAM by default
-$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-# create sec/ns flash and otp memories (sizes will be probed)
-flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
-flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
-
-# Common knowledges tells JTAG speed should be <= F_CPU/6.
-# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
-# the safe side.
-#
-# Note that there is a pretty wide band where things are
-# more or less stable, see http://openocd.zylin.com/#/c/3366/
-adapter speed 500
-
-adapter srst delay 100
-if {[using_jtag]} {
- jtag_ntrst_delay 100
-}
-
-reset_config srst_nogate
-
-if {![using_hla]} {
- # if srst is not fitted use SYSRESETREQ to
- # perform a soft reset
- cortex_m reset_config sysresetreq
-}
-
-proc is_secure {} {
- # read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
- set DSCSR [mrw 0xE000EE08]
- return [expr {($DSCSR & (1 << 16)) != 0}]
-}
-
-proc clock_config_160_mhz {} {
- set offset [expr {[is_secure] ? 0x10000000 : 0}]
+proc stm32u5x_clock_config {} {
+ set offset [expr {[stm32x5x_is_secure] ? 0x10000000 : 0}]
# MCU clock is at MSI 4MHz after reset, set MCU freq at 160 MHz with PLL
# Enable voltage range 1 for frequency above 100 Mhz
@@ -117,91 +47,8 @@ proc clock_config_160_mhz {} {
while {([mrw [expr {0x46020C1C + $offset}]] & 0x0C) != 0x0C} {}
}
-proc ahb_ap_non_secure_access {} {
- # SPROT=1=Non Secure access, Priv=1
- [[target current] cget -dap] apcsw 0x4B000000 0x4F000000
-}
-
-proc ahb_ap_secure_access {} {
- # SPROT=0=Secure access, Priv=1
- [[target current] cget -dap] apcsw 0x0B000000 0x4F000000
-}
-
$_TARGETNAME configure -event reset-init {
- clock_config_160_mhz
+ stm32u5x_clock_config
# Boost JTAG frequency
adapter speed 4000
}
-
-$_TARGETNAME configure -event reset-start {
- # Reset clock is MSI (4 MHz)
- adapter speed 480
-}
-
-$_TARGETNAME configure -event examine-end {
- # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
- mmw 0xE0044004 0x00000006 0
-
- # Stop watchdog counters during halt
- # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
- mmw 0xE0044008 0x00001800 0
-}
-
-$_TARGETNAME configure -event halted {
- set secure [is_secure]
-
- if {$secure} {
- set secure_str "Secure"
- ahb_ap_secure_access
- } else {
- set secure_str "Non-Secure"
- ahb_ap_non_secure_access
- }
-
- # print the secure state only when it changes
- set _TARGETNAME [target current]
- global $_TARGETNAME.secure
-
- if {![info exists $_TARGETNAME.secure] || $secure != [set $_TARGETNAME.secure]} {
- echo "CPU in $secure_str state"
- # update saved security state
- set $_TARGETNAME.secure $secure
- }
-}
-
-$_TARGETNAME configure -event gdb-flash-erase-start {
- set use_secure_workarea 0
- # check if FLASH_OPTR.TZEN is enabled
- set FLASH_OPTR [mrw 0x40022040]
- if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
- echo "TZEN option bit disabled"
- ahb_ap_non_secure_access
- } else {
- ahb_ap_secure_access
- echo "TZEN option bit enabled"
-
- # check if FLASH_OPTR.RDP is not Level 0.5
- if {[expr {$FLASH_OPTR & 0xFF}] != 0x55} {
- set use_secure_workarea 1
- }
- }
-
- set _TARGETNAME [target current]
- set workarea_addr [$_TARGETNAME cget -work-area-phys]
- echo "workarea_addr $workarea_addr"
-
- if {$use_secure_workarea} {
- set workarea_addr [expr {$workarea_addr | 0x10000000}]
- } else {
- set workarea_addr [expr {$workarea_addr & ~0x10000000}]
- }
-
- $_TARGETNAME configure -work-area-phys $workarea_addr
-}
-
-$_TARGETNAME configure -event trace-config {
- # Set TRACE_IOEN; TRACE_MODE is set to async; when using sync
- # change this value accordingly to configure trace pins
- # assignment
- mmw 0xE0044004 0x00000020 0
-}
diff --git a/tcl/target/stm32l5x.cfg b/tcl/target/stm32x5x_common.cfg
similarity index 63%
copy from tcl/target/stm32l5x.cfg
copy to tcl/target/stm32x5x_common.cfg
index 0616df1cb..276d0cca0 100644
--- a/tcl/target/stm32l5x.cfg
+++ b/tcl/target/stm32x5x_common.cfg
@@ -1,20 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-# script for stm32l5x family
-
-#
-# stm32l5 devices support both JTAG and SWD transports.
-#
-source [find target/swj-dp.tcl]
-source [find mem_helper.tcl]
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32l5x
-}
-
-set _ENDIAN little
+# common script for stm32l5x and stm32u5x families
# Work-area is a space in RAM used for flash programming
# By default use 64kB
@@ -29,8 +15,8 @@ if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
if { [using_jtag] } {
- # See STM Document RM0438
- # RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
+ # STM32L5x: RM0438 Rev5, Section 52.2.8 JTAG debug port - Table 425. JTAG-DP data registers
+ # STM32U5x: RM0456 Rev1, Section 65.2.8 JTAG debug port - Table 661. JTAG-DP data registers
# Corresponds to Cortex®-M33 JTAG debug port ID code
set _CPUTAPID 0x0ba04477
} {
@@ -47,7 +33,7 @@ if {[using_jtag]} {
}
set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
# use non-secure RAM by default
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
@@ -57,12 +43,12 @@ flash bank $_CHIPNAME.flash_ns stm32l4x 0x08000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.flash_alias_s stm32l4x 0x0C000000 0 0 0 $_TARGETNAME
flash bank $_CHIPNAME.otp stm32l4x 0x0BFA0000 0 0 0 $_TARGETNAME
-# Common knowledges tells JTAG speed should be <= F_CPU/6.
+# Common knowledge tells JTAG speed should be <= F_CPU/6.
# F_CPU after reset is MSI 4MHz, so use F_JTAG = 500 kHz to stay on
# the safe side.
#
# Note that there is a pretty wide band where things are
-# more or less stable, see http://openocd.zylin.com/#/c/3366/
+# more or less stable, see http://review.openocd.org/3366
adapter speed 500
adapter srst delay 100
@@ -78,55 +64,22 @@ if {![using_hla]} {
cortex_m reset_config sysresetreq
}
-proc is_secure {} {
- # read Debug Security Control and Status Regsiter (DSCSR) and check CDS (bit 16)
+proc stm32x5x_is_secure {} {
+ # read Debug Security Control and Status Register (DSCSR) and check CDS (bit 16)
set DSCSR [mrw 0xE000EE08]
return [expr {($DSCSR & (1 << 16)) != 0}]
}
-proc clock_config_110_mhz {} {
- set offset [expr {[is_secure] ? 0x10000000 : 0}]
- # MCU clock is MSI (4MHz) after reset, set MCU freq at 110 MHz with PLL
- # RCC_APB1ENR1 = PWREN
- mww [expr {0x40021058 + $offset}] 0x10000000
- # delay for register clock enable (read back reg)
- mrw [expr {0x40021058 + $offset}]
- # PWR_CR1 : VOS Range 0
- mww [expr {0x40007000 + $offset}] 0
- # while (PWR_SR2 & VOSF)
- while {([mrw [expr {0x40007014 + $offset}]] & 0x0400)} {}
- # FLASH_ACR : 5 WS for 110 MHz HCLK
- mww 0x40022000 0x00000005
- # RCC_PLLCFGR = PLLP=PLLQ=0, PLLR=00=2, PLLREN=1, PLLN=55, PLLM=0000=1, PLLSRC=MSI 4MHz
- # fVCO = 4 x 55 /1 = 220
- # SYSCLOCK = fVCO/PLLR = 220/2 = 110 MHz
- mww [expr {0x4002100C + $offset}] 0x01003711
- # RCC_CR |= PLLON
- mmw [expr {0x40021000 + $offset}] 0x01000000 0
- # while !(RCC_CR & PLLRDY)
- while {!([mrw [expr {0x40021000 + $offset}]] & 0x02000000)} {}
- # RCC_CFGR |= SW_PLL
- mmw [expr {0x40021008 + $offset}] 0x00000003 0
- # while ((RCC_CFGR & SWS) != PLL)
- while {([mrw [expr {0x40021008 + $offset}]] & 0x0C) != 0x0C} {}
-}
-
-proc ahb_ap_non_secure_access {} {
+proc stm32x5x_ahb_ap_non_secure_access {} {
# SPROT=1=Non Secure access, Priv=1
[[target current] cget -dap] apcsw 0x4B000000 0x4F000000
}
-proc ahb_ap_secure_access {} {
+proc stm32x5x_ahb_ap_secure_access {} {
# SPROT=0=Secure access, Priv=1
[[target current] cget -dap] apcsw 0x0B000000 0x4F000000
}
-$_TARGETNAME configure -event reset-init {
- clock_config_110_mhz
- # Boost JTAG frequency
- adapter speed 4000
-}
-
$_TARGETNAME configure -event reset-start {
# Reset clock is MSI (4 MHz)
adapter speed 480
@@ -142,14 +95,14 @@ $_TARGETNAME configure -event examine-end {
}
$_TARGETNAME configure -event halted {
- set secure [is_secure]
+ set secure [stm32x5x_is_secure]
if {$secure} {
set secure_str "Secure"
- ahb_ap_secure_access
+ stm32x5x_ahb_ap_secure_access
} else {
set secure_str "Non-Secure"
- ahb_ap_non_secure_access
+ stm32x5x_ahb_ap_non_secure_access
}
# print the secure state only when it changes
@@ -169,9 +122,9 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
set FLASH_OPTR [mrw 0x40022040]
if {[expr {$FLASH_OPTR & 0x80000000}] == 0} {
echo "TZEN option bit disabled"
- ahb_ap_non_secure_access
- } {
- ahb_ap_secure_access
+ stm32x5x_ahb_ap_non_secure_access
+ } else {
+ stm32x5x_ahb_ap_secure_access
echo "TZEN option bit enabled"
# check if FLASH_OPTR.RDP is not Level 0.5
@@ -180,12 +133,13 @@ $_TARGETNAME configure -event gdb-flash-erase-start {
}
}
+ set _TARGETNAME [target current]
set workarea_addr [$_TARGETNAME cget -work-area-phys]
echo "workarea_addr $workarea_addr"
if {$use_secure_workarea} {
set workarea_addr [expr {$workarea_addr | 0x10000000}]
- } {
+ } else {
set workarea_addr [expr {$workarea_addr & ~0x10000000}]
}
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_m.c | 210 +++++++++++------------
tcl/target/stm32l5x.cfg | 162 +----------------
tcl/target/stm32u5x.cfg | 163 +-----------------
tcl/target/{stm32l5x.cfg => stm32x5x_common.cfg} | 82 ++-------
4 files changed, 132 insertions(+), 485 deletions(-)
copy tcl/target/{stm32l5x.cfg => stm32x5x_common.cfg} (63%)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2022-03-12 09:33:40
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 57c1e491801c6e67cb8b429bcf5c0ecf1bcef27b (commit)
from 2586fec922ae9ea9bea345f40598e0367934d22c (commit)
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- Log -----------------------------------------------------------------
commit 57c1e491801c6e67cb8b429bcf5c0ecf1bcef27b
Author: Tomas Vanek <va...@fb...>
Date: Tue Nov 16 17:10:12 2021 +0100
flash/stm32f1x,f2x: fix endianess in slow fallback flash write
Use target_write_memory() instead of target_write_u16()
Change-Id: I2389fe7a5fa18c9bc9c1aad8b8ddd64608bf2566
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6705
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index 29a3b7e06..6972bae2d 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -592,10 +592,7 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
while (words_remaining > 0) {
- uint16_t value;
- memcpy(&value, buffer, sizeof(uint16_t));
-
- retval = target_write_u16(target, bank->base + offset, value);
+ retval = target_write_memory(target, bank->base + offset, 2, 1, buffer);
if (retval != ERROR_OK)
goto reset_pg_and_lock;
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index 58edca7e1..622ef3423 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -856,15 +856,12 @@ static int stm32x_write(struct flash_bank *bank, const uint8_t *buffer,
Wait for the BSY bit to be cleared
*/
while (words_remaining > 0) {
- uint16_t value;
- memcpy(&value, buffer + bytes_written, sizeof(uint16_t));
-
retval = target_write_u32(target, stm32x_get_flash_reg(bank, STM32_FLASH_CR),
FLASH_PG | FLASH_PSIZE_16);
if (retval != ERROR_OK)
return retval;
- retval = target_write_u16(target, address, value);
+ retval = target_write_memory(target, address, 2, 1, buffer + bytes_written);
if (retval != ERROR_OK)
return retval;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32f1x.c | 5 +----
src/flash/nor/stm32f2x.c | 5 +----
2 files changed, 2 insertions(+), 8 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-03-05 13:25:01
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 2586fec922ae9ea9bea345f40598e0367934d22c
Author: Marc Schink <de...@za...>
Date: Sat Feb 26 14:31:11 2022 +0100
target/arm_tpiu: Fix usage of 'tpiu create'
Change-Id: I1ffad65a9e6d76f4d7fbbe249d8af3beb7e7692b
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6860
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/arm_tpiu_swo.c b/src/target/arm_tpiu_swo.c
index 3738a3bf2..bfe908142 100644
--- a/src/target/arm_tpiu_swo.c
+++ b/src/target/arm_tpiu_swo.c
@@ -1161,7 +1161,7 @@ static const struct command_registration arm_tpiu_swo_subcommand_handlers[] = {
.name = "create",
.mode = COMMAND_ANY,
.jim_handler = jim_arm_tpiu_swo_create,
- .usage = "name [-dap dap] [-ap-num num] [-address baseaddr]",
+ .usage = "name [-dap dap] [-ap-num num] [-baseaddr baseaddr]",
.help = "Creates a new TPIU or SWO object",
},
{
-----------------------------------------------------------------------
Summary of changes:
src/target/arm_tpiu_swo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2022-03-05 13:24:06
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4a4ca07da7b53e589afe2f79d03787d89faf1d33 (commit)
from 29e2a7451638d5706daf13b12211b49baafa3c42 (commit)
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- Log -----------------------------------------------------------------
commit 4a4ca07da7b53e589afe2f79d03787d89faf1d33
Author: Marc Schink <de...@za...>
Date: Tue Jun 22 12:59:01 2021 +0200
target/arm_tpiu: Fix 'tpiu create' parameter check
The current implementation crashes when executing 'tpiu create'
without an object name due to an invalid memory access. Pass 'argv'
instead 'goi.argv' to fix the problem.
While at it, match the style of the error message to the style used for
other Tcl commands. Especially, make the 'name' parameter mandatory.
Change-Id: Ib2b233f8556934af61608ae93d6405585c2c40b7
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6329
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/target/arm_tpiu_swo.c b/src/target/arm_tpiu_swo.c
index 387ad9e9e..3738a3bf2 100644
--- a/src/target/arm_tpiu_swo.c
+++ b/src/target/arm_tpiu_swo.c
@@ -916,7 +916,7 @@ static int jim_arm_tpiu_swo_create(Jim_Interp *interp, int argc, Jim_Obj *const
struct jim_getopt_info goi;
jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
if (goi.argc < 1) {
- Jim_WrongNumArgs(goi.interp, 1, goi.argv, "?name? ..options...");
+ Jim_WrongNumArgs(interp, 1, argv, "name ?option option ...?");
return JIM_ERR;
}
-----------------------------------------------------------------------
Summary of changes:
src/target/arm_tpiu_swo.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2022-03-05 13:23:28
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 29e2a7451638d5706daf13b12211b49baafa3c42 (commit)
from e8e62c5aca494fa17a5e543831b8eef3740c9b1d (commit)
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- Log -----------------------------------------------------------------
commit 29e2a7451638d5706daf13b12211b49baafa3c42
Author: Marc Schink <de...@za...>
Date: Tue Jun 22 11:47:26 2021 +0200
target/arm_tpiu: Make error message easier to understand
Change-Id: Idddc31e34a67641c32d041c89d01fe2126ec5ddb
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6328
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/arm_tpiu_swo.c b/src/target/arm_tpiu_swo.c
index 024521364..387ad9e9e 100644
--- a/src/target/arm_tpiu_swo.c
+++ b/src/target/arm_tpiu_swo.c
@@ -886,7 +886,8 @@ static int arm_tpiu_swo_create(Jim_Interp *interp, struct arm_tpiu_swo_object *o
/* does this command exist? */
cmd = Jim_GetCommand(interp, Jim_NewStringObj(interp, obj->name, -1), JIM_NONE);
if (cmd) {
- Jim_SetResultFormatted(interp, "Command: %s Exists", obj->name);
+ Jim_SetResultFormatted(interp, "cannot create TPIU object because a command with name '%s' already exists",
+ obj->name);
return JIM_ERR;
}
-----------------------------------------------------------------------
Summary of changes:
src/target/arm_tpiu_swo.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2022-03-05 13:22:25
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit e8e62c5aca494fa17a5e543831b8eef3740c9b1d
Author: Marc Schink <de...@za...>
Date: Fri Jun 4 15:05:17 2021 +0200
target/tcl: Add get_reg function
Change-Id: Id1be9554d1df2c07cec3161a0fd3a586fdf18246
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/5312
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index c0df9c9ac..2bfa0deae 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5018,6 +5018,24 @@ set_reg @{pc 0 sp 0x1000@}
@end example
@end deffn
+@deffn {Command} {$target_name get_reg} [-force] list
+Get register values from the target and return them as Tcl dictionary with pairs
+of register names and values.
+If option "-force" is set, the register values are read directly from the
+target, bypassing any caching.
+
+@itemize
+@item @var{list} ... List of register names
+@end itemize
+
+For example, the following command retrieves the values from the program
+counter (pc) and stack pointer (sp) register:
+
+@example
+get_reg @{pc sp@}
+@end example
+@end deffn
+
@deffn {Command} {$target_name cget} queryparm
Each configuration parameter accepted by
@command{$target_name configure}
@@ -8521,6 +8539,24 @@ set_reg @{pc 0 sp 0x1000@}
@end example
@end deffn
+@deffn {Command} {get_reg} [-force] list
+Get register values from the target and return them as Tcl dictionary with pairs
+of register names and values.
+If option "-force" is set, the register values are read directly from the
+target, bypassing any caching.
+
+@itemize
+@item @var{list} ... List of register names
+@end itemize
+
+For example, the following command retrieves the values from the program
+counter (pc) and stack pointer (sp) register:
+
+@example
+get_reg @{pc sp@}
+@end example
+@end deffn
+
@deffn {Command} {halt} [ms]
@deffnx {Command} {wait_halt} [ms]
The @command{halt} command first sends a halt request to the target,
diff --git a/src/target/target.c b/src/target/target.c
index 1d26cb91c..b72dc53e3 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -4863,6 +4863,93 @@ void target_handle_event(struct target *target, enum target_event e)
}
}
+static int target_jim_get_reg(Jim_Interp *interp, int argc,
+ Jim_Obj * const *argv)
+{
+ bool force = false;
+
+ if (argc == 3) {
+ const char *option = Jim_GetString(argv[1], NULL);
+
+ if (!strcmp(option, "-force")) {
+ argc--;
+ argv++;
+ force = true;
+ } else {
+ Jim_SetResultFormatted(interp, "invalid option '%s'", option);
+ return JIM_ERR;
+ }
+ }
+
+ if (argc != 2) {
+ Jim_WrongNumArgs(interp, 1, argv, "[-force] list");
+ return JIM_ERR;
+ }
+
+ const int length = Jim_ListLength(interp, argv[1]);
+
+ Jim_Obj *result_dict = Jim_NewDictObj(interp, NULL, 0);
+
+ if (!result_dict)
+ return JIM_ERR;
+
+ struct command_context *cmd_ctx = current_command_context(interp);
+ assert(cmd_ctx != NULL);
+ const struct target *target = get_current_target(cmd_ctx);
+
+ for (int i = 0; i < length; i++) {
+ Jim_Obj *elem = Jim_ListGetIndex(interp, argv[1], i);
+
+ if (!elem)
+ return JIM_ERR;
+
+ const char *reg_name = Jim_String(elem);
+
+ struct reg *reg = register_get_by_name(target->reg_cache, reg_name,
+ false);
+
+ if (!reg || !reg->exist) {
+ Jim_SetResultFormatted(interp, "unknown register '%s'", reg_name);
+ return JIM_ERR;
+ }
+
+ if (force) {
+ int retval = reg->type->get(reg);
+
+ if (retval != ERROR_OK) {
+ Jim_SetResultFormatted(interp, "failed to read register '%s'",
+ reg_name);
+ return JIM_ERR;
+ }
+ }
+
+ char *reg_value = buf_to_hex_str(reg->value, reg->size);
+
+ if (!reg_value) {
+ LOG_ERROR("Failed to allocate memory");
+ return JIM_ERR;
+ }
+
+ char *tmp = alloc_printf("0x%s", reg_value);
+
+ free(reg_value);
+
+ if (!tmp) {
+ LOG_ERROR("Failed to allocate memory");
+ return JIM_ERR;
+ }
+
+ Jim_DictAddElement(interp, result_dict, elem,
+ Jim_NewStringObj(interp, tmp, -1));
+
+ free(tmp);
+ }
+
+ Jim_SetResult(interp, result_dict);
+
+ return JIM_OK;
+}
+
static int target_jim_set_reg(Jim_Interp *interp, int argc,
Jim_Obj * const *argv)
{
@@ -5696,6 +5783,13 @@ static const struct command_registration target_instance_command_handlers[] = {
"from target memory",
.usage = "arrayname bitwidth address count",
},
+ {
+ .name = "get_reg",
+ .mode = COMMAND_EXEC,
+ .jim_handler = target_jim_get_reg,
+ .help = "Get register values from the target",
+ .usage = "list",
+ },
{
.name = "set_reg",
.mode = COMMAND_EXEC,
@@ -6785,6 +6879,13 @@ static const struct command_registration target_exec_command_handlers[] = {
"and write the 8/16/32 bit values",
.usage = "arrayname bitwidth address count",
},
+ {
+ .name = "get_reg",
+ .mode = COMMAND_EXEC,
+ .jim_handler = target_jim_get_reg,
+ .help = "Get register values from the target",
+ .usage = "list",
+ },
{
.name = "set_reg",
.mode = COMMAND_EXEC,
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 36 +++++++++++++++++++
src/target/target.c | 101 ++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 137 insertions(+)
hooks/post-receive
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From: OpenOCD-Gerrit <ope...@us...> - 2022-03-05 13:20:29
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 8b740af10dd37b08c27588f34942154b817bf6fc (commit)
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- Log -----------------------------------------------------------------
commit da7328010165be6e0188100e79b9dab5c362e13b
Author: Marc Schink <de...@za...>
Date: Fri Jun 4 15:04:54 2021 +0200
target/tcl: Add set_reg function
Change-Id: I97a01b93046cb7af289792489f77f5580312585a
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/5313
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index fd4a81da2..c0df9c9ac 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5003,6 +5003,21 @@ and neither store nor return those values.
@end itemize
@end deffn
+@deffn {Command} {$target_name set_reg} dict
+Set register values of the target.
+
+@itemize
+@item @var{dict} ... Tcl dictionary with pairs of register names and values.
+@end itemize
+
+For example, the following command sets the value 0 to the program counter (pc)
+register and 0x1000 to the stack pointer (sp) register:
+
+@example
+set_reg @{pc 0 sp 0x1000@}
+@end example
+@end deffn
+
@deffn {Command} {$target_name cget} queryparm
Each configuration parameter accepted by
@command{$target_name configure}
@@ -8491,6 +8506,21 @@ Debug and trace infrastructure:
@end example
@end deffn
+@deffn {Command} {set_reg} dict
+Set register values of the target.
+
+@itemize
+@item @var{dict} ... Tcl dictionary with pairs of register names and values.
+@end itemize
+
+For example, the following command sets the value 0 to the program counter (pc)
+register and 0x1000 to the stack pointer (sp) register:
+
+@example
+set_reg @{pc 0 sp 0x1000@}
+@end example
+@end deffn
+
@deffn {Command} {halt} [ms]
@deffnx {Command} {wait_halt} [ms]
The @command{halt} command first sends a halt request to the target,
diff --git a/src/target/target.c b/src/target/target.c
index 6250d3031..1d26cb91c 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -4863,6 +4863,57 @@ void target_handle_event(struct target *target, enum target_event e)
}
}
+static int target_jim_set_reg(Jim_Interp *interp, int argc,
+ Jim_Obj * const *argv)
+{
+ if (argc != 2) {
+ Jim_WrongNumArgs(interp, 1, argv, "dict");
+ return JIM_ERR;
+ }
+
+ int tmp;
+ Jim_Obj **dict = Jim_DictPairs(interp, argv[1], &tmp);
+
+ if (!dict)
+ return JIM_ERR;
+
+ const unsigned int length = tmp;
+ struct command_context *cmd_ctx = current_command_context(interp);
+ assert(cmd_ctx);
+ const struct target *target = get_current_target(cmd_ctx);
+
+ for (unsigned int i = 0; i < length; i += 2) {
+ const char *reg_name = Jim_String(dict[i]);
+ const char *reg_value = Jim_String(dict[i + 1]);
+ struct reg *reg = register_get_by_name(target->reg_cache, reg_name,
+ false);
+
+ if (!reg || !reg->exist) {
+ Jim_SetResultFormatted(interp, "unknown register '%s'", reg_name);
+ return JIM_ERR;
+ }
+
+ uint8_t *buf = malloc(DIV_ROUND_UP(reg->size, 8));
+
+ if (!buf) {
+ LOG_ERROR("Failed to allocate memory");
+ return JIM_ERR;
+ }
+
+ str_to_buf(reg_value, strlen(reg_value), buf, reg->size, 0);
+ int retval = reg->type->set(reg, buf);
+ free(buf);
+
+ if (retval != ERROR_OK) {
+ Jim_SetResultFormatted(interp, "failed to set '%s' to register '%s'",
+ reg_value, reg_name);
+ return JIM_ERR;
+ }
+ }
+
+ return JIM_OK;
+}
+
/**
* Returns true only if the target has a handler for the specified event.
*/
@@ -5645,6 +5696,13 @@ static const struct command_registration target_instance_command_handlers[] = {
"from target memory",
.usage = "arrayname bitwidth address count",
},
+ {
+ .name = "set_reg",
+ .mode = COMMAND_EXEC,
+ .jim_handler = target_jim_set_reg,
+ .help = "Set target register values",
+ .usage = "dict",
+ },
{
.name = "eventlist",
.handler = handle_target_event_list,
@@ -6727,6 +6785,13 @@ static const struct command_registration target_exec_command_handlers[] = {
"and write the 8/16/32 bit values",
.usage = "arrayname bitwidth address count",
},
+ {
+ .name = "set_reg",
+ .mode = COMMAND_EXEC,
+ .jim_handler = target_jim_set_reg,
+ .help = "Set target register values",
+ .usage = "dict",
+ },
{
.name = "reset_nag",
.handler = handle_target_reset_nag,
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 30 +++++++++++++++++++++++++
src/target/target.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 95 insertions(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-03-01 08:37:51
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commit 8b740af10dd37b08c27588f34942154b817bf6fc
Author: Tarek BOCHKATI <tar...@gm...>
Date: Mon Feb 28 10:29:44 2022 +0100
flash/stm32l4x: fix maybe-uninitialized compiler error
using gcc (Ubuntu 9.3.0-17ubuntu1~20.04) 9.3.0 we get:
error: âretvalâ may be used uninitialized in this function
fixes: 13cd75b6ecfd (flash/nor/stm32xx: fix segfault accessing Cortex-M part number)
Change-Id: I897c40c5d2233f50a5385d251ebfa536023e5cf7
Signed-off-by: Tarek BOCHKATI <tar...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6861
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index fa8924ed3..fd0338899 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -1632,7 +1632,7 @@ err_lock:
static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
{
- int retval;
+ int retval = ERROR_OK;
struct target *target = bank->target;
/* try reading possible IDCODE registers, in the following order */
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32l4x.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-02-26 15:37:59
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commit 103b1d68db5038edd9e8878c798525715590f4e1
Author: Antonio Borneo <bor...@gm...>
Date: Sat Feb 19 16:56:42 2022 +0100
gdb_server: check target examined while combining reg list
Commit 6541233aa78d ("Combine register lists of smp targets.")
assumes that all the targets in the SMP cluster are already
examined and unconditionally call target_get_gdb_reg_list_noread()
that will in turn return error if the target is not examined yet.
Skip targets not examined yet.
Add an additional check in case the register list cannot be built,
e.g. because no target in the SMP cluster is examined. This should
never happen, but it's better to play safe.
Change-Id: I8609815c3d5144790fb05a870cb0c931540aef8a
Fixes: 6541233aa78d ("Combine register lists of smp targets.")
Reported-by: Michele Bisogno <mic...@re...>
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6853
Tested-by: jenkins
Reviewed-by: Michele Bisogno <mic...@re...>
Reviewed-by: Tim Newsome <ti...@si...>
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index f8a1aac83..4dee7e864 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -2281,6 +2281,9 @@ static int smp_reg_list_noread(struct target *target,
struct target_list *head;
foreach_smp_target(head, target->smp_targets) {
+ if (!target_was_examined(head->target))
+ continue;
+
struct reg **reg_list = NULL;
int reg_list_size;
int result = target_get_gdb_reg_list_noread(head->target, ®_list,
@@ -2329,8 +2332,17 @@ static int smp_reg_list_noread(struct target *target,
free(reg_list);
}
+ if (local_list_size == 0) {
+ LOG_ERROR("Unable to get register list");
+ free(local_list);
+ return ERROR_FAIL;
+ }
+
/* Now warn the user about any registers that weren't found in every target. */
foreach_smp_target(head, target->smp_targets) {
+ if (!target_was_examined(head->target))
+ continue;
+
struct reg **reg_list = NULL;
int reg_list_size;
int result = target_get_gdb_reg_list_noread(head->target, ®_list,
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-02-26 15:37:43
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- Log -----------------------------------------------------------------
commit bc50b8f1b299991851d4ff3eb30f583ed6aa530b
Author: Antonio Borneo <bor...@gm...>
Date: Sat Feb 19 16:16:31 2022 +0100
gdb_server: fix double free
Commit 6541233aa78d ("Combine register lists of smp targets.")
unconditionally assigns the output pointers of the function
smp_reg_list_noread(), even if the function fails and returns
error.
This causes a double free from the caller, that has assigned NULL
to the pointers to simplify the error handling.
Use local variables in smp_reg_list_noread() and assign the output
pointers only on success.
Change-Id: Ic0fd2f26520566cf322f0190780e15637c01cfae
Fixes: 6541233aa78d ("Combine register lists of smp targets.")
Reported-by: Michele Bisogno <mic...@re...>
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6852
Tested-by: jenkins
Reviewed-by: Michele Bisogno <mic...@re...>
Reviewed-by: Tim Newsome <ti...@si...>
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 95720e561..f8a1aac83 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -2272,12 +2272,12 @@ static int smp_reg_list_noread(struct target *target,
combined_list_size, REG_CLASS_ALL);
unsigned int combined_allocated = 256;
- *combined_list = malloc(combined_allocated * sizeof(struct reg *));
- if (*combined_list == NULL) {
+ struct reg **local_list = malloc(combined_allocated * sizeof(struct reg *));
+ if (!local_list) {
LOG_ERROR("malloc(%zu) failed", combined_allocated * sizeof(struct reg *));
return ERROR_FAIL;
}
- *combined_list_size = 0;
+ unsigned int local_list_size = 0;
struct target_list *head;
foreach_smp_target(head, target->smp_targets) {
@@ -2286,7 +2286,7 @@ static int smp_reg_list_noread(struct target *target,
int result = target_get_gdb_reg_list_noread(head->target, ®_list,
®_list_size, reg_class);
if (result != ERROR_OK) {
- free(*combined_list);
+ free(local_list);
return result;
}
for (int i = 0; i < reg_list_size; i++) {
@@ -2296,8 +2296,8 @@ static int smp_reg_list_noread(struct target *target,
/* Nested loop makes this O(n^2), but this entire function with
* 5 RISC-V targets takes just 2ms on my computer. Fast enough
* for me. */
- for (int j = 0; j < *combined_list_size; j++) {
- struct reg *b = (*combined_list)[j];
+ for (unsigned int j = 0; j < local_list_size; j++) {
+ struct reg *b = local_list[j];
if (!strcmp(a->name, b->name)) {
found = true;
if (a->size != b->size) {
@@ -2305,7 +2305,7 @@ static int smp_reg_list_noread(struct target *target,
"target, but %d bits on another target.",
a->name, a->size, b->size);
free(reg_list);
- free(*combined_list);
+ free(local_list);
return ERROR_FAIL;
}
break;
@@ -2313,16 +2313,16 @@ static int smp_reg_list_noread(struct target *target,
}
if (!found) {
LOG_DEBUG("[%s] %s not found in combined list", target_name(target), a->name);
- if (*combined_list_size >= (int) combined_allocated) {
+ if (local_list_size >= combined_allocated) {
combined_allocated *= 2;
- *combined_list = realloc(*combined_list, combined_allocated * sizeof(struct reg *));
- if (*combined_list == NULL) {
+ local_list = realloc(local_list, combined_allocated * sizeof(struct reg *));
+ if (!local_list) {
LOG_ERROR("realloc(%zu) failed", combined_allocated * sizeof(struct reg *));
return ERROR_FAIL;
}
}
- (*combined_list)[*combined_list_size] = a;
- (*combined_list_size)++;
+ local_list[local_list_size] = a;
+ local_list_size++;
}
}
}
@@ -2336,12 +2336,12 @@ static int smp_reg_list_noread(struct target *target,
int result = target_get_gdb_reg_list_noread(head->target, ®_list,
®_list_size, reg_class);
if (result != ERROR_OK) {
- free(*combined_list);
+ free(local_list);
return result;
}
- for (int i = 0; i < *combined_list_size; i++) {
+ for (unsigned int i = 0; i < local_list_size; i++) {
bool found = false;
- struct reg *a = (*combined_list)[i];
+ struct reg *a = local_list[i];
for (int j = 0; j < reg_list_size; j++) {
struct reg *b = reg_list[j];
if (b->exist && !strcmp(a->name, b->name)) {
@@ -2358,6 +2358,8 @@ static int smp_reg_list_noread(struct target *target,
free(reg_list);
}
+ *combined_list = local_list;
+ *combined_list_size = local_list_size;
return ERROR_OK;
}
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 32 +++++++++++++++++---------------
1 file changed, 17 insertions(+), 15 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-02-26 15:37:02
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commit e84be7088d5972ddd9bf502f8f66ac3b06ed3dda
Author: Sean Anderson <sea...@se...>
Date: Fri Feb 11 17:50:09 2022 -0500
board: Add NXP LS1088ARDB
This adds a board file for the NXP LS1088ARDB. This only covers the
"primary" JTAG header J55, and not the PCIe header (J91). The only
oddity is that the LS1088A and CPLD are muxed by adding/removing a
jumper from J48. Unfortunately, it doesn't look like OpenOCD supports
this CPLD beyond determining the irlen, so it's not very useful. Those
who are interested in experimenting can define CWTAP to access the CPLD,
but the default is to access the CPU.
Signed-off-by: Sean Anderson <sea...@se...>
Change-Id: Ia07436a534f86bd907aa5fe2a78a326a27855a24
Reviewed-on: https://review.openocd.org/c/openocd/+/6849
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/nxp_rdb-ls1088a.cfg b/tcl/board/nxp_rdb-ls1088a.cfg
new file mode 100644
index 000000000..40483f2d6
--- /dev/null
+++ b/tcl/board/nxp_rdb-ls1088a.cfg
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1088ARDB (Reference Design Board)
+# This is for the "main" JTAG connector J55
+
+transport select jtag
+reset_config srst_only
+
+# To access the CPLD, populate J48 and add `-c 'set CWTAP 1'` to your command
+# line. At the time of this writing, programming is unsupported.
+if { [info exists CWTAP] } {
+ source [find cpld/altera-epm240.cfg]
+} else {
+ source [find target/ls1088a.cfg]
+}
-----------------------------------------------------------------------
Summary of changes:
tcl/board/nxp_rdb-ls1088a.cfg | 14 ++++++++++++++
1 file changed, 14 insertions(+)
create mode 100644 tcl/board/nxp_rdb-ls1088a.cfg
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commit d1278660afcb3315fe74def3c2ca51cf28424963
Author: Sean Anderson <sea...@se...>
Date: Mon Feb 14 17:53:11 2022 -0500
target: ls1088a: Add service processor
Normally the service processor is not necessary for debugging. However,
if you are using the hard-coded RCW or your boot source is otherwise
corrupt, then the general purpose processors will never be released from
hold-off. This will cause GDB to become confused if it tries to attach,
since they will appear to be running arm32 processors. To deal with
this, we can release the CPUs manually with the BRRL register. This
register cannot be written to from the axi target, so we need to do it
from the service processor target. This involves halting the service
processor, modifying the register, and then resuming it again. We try
and determine what state the service processor was in to avoid resuming
it if it was already halted.
The reset vector for the general purpose processors is determined by the
boot logation pointer registers in the device configuration unit.
Normally these are set using pre-boot initialization commands, but if
they are not set then they default to 0. This will cause the CPU to
almost immediately hit an illegal instruction. This is fine because we
will almost certainly want to attach to the processor and load a program
anyway.
I considered adding this as an event handler for either gdb-attach or
reset-init. However, this command shouldn't be necessary most of the
time, and so I don't think we should run it automatically.
Signed-off-by: Sean Anderson <sea...@se...>
Change-Id: I1b725292d8a11274d03af5313dc83678e10e944c
Reviewed-on: https://review.openocd.org/c/openocd/+/6850
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ls1088a.cfg b/tcl/target/ls1088a.cfg
index 136ee77a3..f9ae9a134 100644
--- a/tcl/target/ls1088a.cfg
+++ b/tcl/target/ls1088a.cfg
@@ -36,6 +36,38 @@ for {set i 0} {$i < 8} {incr i} {
target smp {*}$_TARGETS
+# Service processor
+target create $_CHIPNAME.sp cortex_a -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80138000
+
+# Normally you will not need to call this, but if you are using the hard-coded
+# Reset Configuration Word (RCW) you will need to call this manually. The CPU's
+# reset vector is 0, and the boot ROM at that location contains ARMv7-A 32-bit
+# instructions. This will cause the CPU to almost immediately execute an
+# illegal instruction.
+#
+# This code is idempotent; releasing a released CPU has no effect, although it
+# will halt/resume the service processor.
+add_help_text release_cpu "Release a cpu which is held off"
+proc release_cpu {cpu} {
+ set RST_BRRL 0x1e60060
+
+ set old [target current]
+ targets $::_CHIPNAME.sp
+ set not_halted [string compare halted [$::_CHIPNAME.sp curstate]]
+ if {$not_halted} {
+ halt
+ }
+
+ # Release the cpu; it will start executing something bogus
+ mem2array regs 32 $RST_BRRL 1
+ mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]
+
+ if {$not_halted} {
+ resume
+ }
+ targets $old
+}
+
targets $_CHIPNAME.cpu0
# Seems to work OK in testing
-----------------------------------------------------------------------
Summary of changes:
tcl/target/ls1088a.cfg | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
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commit 3fcfe4f196f6c333ee0ba2078af9cfa3eb896761
Author: Sean Anderson <sea...@se...>
Date: Fri Feb 11 17:45:32 2022 -0500
target: Add support for ls1088a
The LS1088A is an octo-core aarch64 processor from NXP in the layerscape
family. The JTAG is undocumented, but I was able to figure things out
from the output of `dap info`. This is the first in-tree example of
using the hwthread rtos (as far as I know), so hopefully it can serve as
an example to other developers. There are some ETMs, but I was unable to
try them out because I got 'invalid command name "etm"' when trying to
test things out.
Signed-off-by: Sean Anderson <sea...@se...>
Change-Id: I9b0791d27d8c41170a413a8d86431107a85feba2
Reviewed-on: https://review.openocd.org/c/openocd/+/6848
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/ls1088a.cfg b/tcl/target/ls1088a.cfg
new file mode 100644
index 000000000..136ee77a3
--- /dev/null
+++ b/tcl/target/ls1088a.cfg
@@ -0,0 +1,42 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# NXP LS1088A
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME ls1088a
+}
+
+if { [info exists DAP_TAPID] } {
+ set _DAP_TAPID $DAP_TAPID
+} else {
+ set _DAP_TAPID 0x5ba00477
+}
+
+jtag newtap $_CHIPNAME dap -irlen 4 -expected-id $_DAP_TAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.dap
+
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 1
+
+set _CPU_BASE 0x81000000
+set _CPU_STRIDE 0x100000
+set _CPU_DBGOFF 0x10000
+set _CPU_CTIOFF 0x20000
+
+set _TARGETS {}
+for {set i 0} {$i < 8} {incr i} {
+ set _BASE [expr {$_CPU_BASE + $_CPU_STRIDE * $i}]
+ cti create $_CHIPNAME.cti$i -dap $_CHIPNAME.dap -ap-num 0 \
+ -baseaddr [expr {$_BASE + $_CPU_CTIOFF}]
+ target create $_CHIPNAME.cpu$i aarch64 -dap $_CHIPNAME.dap \
+ -cti $_CHIPNAME.cti$i -dbgbase [expr {$_BASE + $_CPU_DBGOFF}] \
+ {*}[expr {$i ? "-coreid $i" : "-rtos hwthread" }]
+ lappend _TARGETS $_CHIPNAME.cpu$i
+}
+
+target smp {*}$_TARGETS
+
+targets $_CHIPNAME.cpu0
+
+# Seems to work OK in testing
+adapter speed 10000
commit b61eae1962f008627f4593cfda9b3431e4c3c016
Author: Sean Anderson <sea...@se...>
Date: Fri Feb 11 17:43:30 2022 -0500
cpld: altera-epm240: Increase adapter speed
According to the datasheet, the minimum clock period with Vccio1 = 1.5V
(the lowest voltage supported) is 143ns, or around 6MHz. Set the default
adapter speed to 5 MHz.
Signed-off-by: Sean Anderson <sea...@se...>
Change-Id: I21cad33fa7f1e25e81f43b5d2214d1fa4ec924de
Reviewed-on: https://review.openocd.org/c/openocd/+/6847
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/cpld/altera-epm240.cfg b/tcl/cpld/altera-epm240.cfg
index 6e10188ca..ece02bbef 100644
--- a/tcl/cpld/altera-epm240.cfg
+++ b/tcl/cpld/altera-epm240.cfg
@@ -17,3 +17,7 @@ jtag newtap $_CHIPNAME tap -irlen 10 \
-expected-id 0x020a40dd \
-expected-id 0x020a50dd \
-expected-id 0x020a60dd
+
+# 200ns seems like a good speed
+# c.f. Table 5-34: MAX II JTAG Timing Parameters
+adapter speed 5000
-----------------------------------------------------------------------
Summary of changes:
tcl/cpld/altera-epm240.cfg | 4 ++++
tcl/target/ls1088a.cfg | 42 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 46 insertions(+)
create mode 100644 tcl/target/ls1088a.cfg
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From: OpenOCD-Gerrit <ope...@us...> - 2022-02-26 15:31:12
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commit d673521c39dcf82ce4c2e6d9d4dcdc7460c09fbe
Author: Sean Anderson <sea...@se...>
Date: Fri Feb 11 17:40:24 2022 -0500
cpld: altera-epm240: Add additional IDCODEs
This adds some additional IDCODEs from the datasheet. It also adds
support for customizing the tap name.
Signed-off-by: Sean Anderson <sea...@se...>
Change-Id: I7cda10b92c229b61836c12cd9ca410de358ede2e
Reviewed-on: https://review.openocd.org/c/openocd/+/6846
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/cpld/altera-epm240.cfg b/tcl/cpld/altera-epm240.cfg
index 62f2b73b7..6e10188ca 100644
--- a/tcl/cpld/altera-epm240.cfg
+++ b/tcl/cpld/altera-epm240.cfg
@@ -1,6 +1,19 @@
# Altera MAXII EPM240T100C CPLD
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME epm240
+}
+
# see MAX II Device Handbook
# Table 3-3: 32-Bit MAX II Device IDCODE
# Version Part Number Manuf. ID LSB
# 0000 0010 0000 1010 0001 000 0110 1110 1
-jtag newtap epm240 tap -expected-id 0x020a10dd -irlen 10
+jtag newtap $_CHIPNAME tap -irlen 10 \
+ -expected-id 0x020a10dd \
+ -expected-id 0x020a20dd \
+ -expected-id 0x020a30dd \
+ -expected-id 0x020a40dd \
+ -expected-id 0x020a50dd \
+ -expected-id 0x020a60dd
-----------------------------------------------------------------------
Summary of changes:
tcl/cpld/altera-epm240.cfg | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
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commit 13cd75b6ecfd8d9cf04e56b182b6a162ad50247c
Author: Tomas Vanek <va...@fb...>
Date: Thu Nov 25 06:24:52 2021 +0100
flash/nor/stm32xx: fix segfault accessing Cortex-M part number
Some of STM32 flash drivers read Cortex-M part number from
cortex_m->core_info.
In corner cases the core_info pointer was observed uninitialised
even if target_was_examined() returned true. See also [1]
Use the new and safe helper to get Cortex-M part number.
While on it switch also target_to_cm()/target_to_armv7m() to the safe
versions. This prevents a crash when the flash bank is misconfigured
with non-Cortex-M target.
Add missing checks for target_was_examined() to flash probes.
[1] 6545: fix crash in case cortex_m->core_info is not set
https://review.openocd.org/c/openocd/+/6545
Change-Id: If2471af74ebfe22f14442f48ae109b2e1bb5fa3b
Signed-off-by: Tomas Vanek <va...@fb...>
Fixes: f5898bd93ff8 (flash/stm32fxx.c: do not read CPUID as this info is stored in cortex_m_common)
Reviewed-on: https://review.openocd.org/c/openocd/+/6752
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index 90cee6412..29a3b7e06 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -622,15 +622,14 @@ cleanup:
static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
{
struct target *target = bank->target;
- struct cortex_m_common *cortex_m = target_to_cm(target);
uint32_t device_id_register = 0;
if (!target_was_examined(target)) {
LOG_ERROR("Target not examined yet");
- return ERROR_FAIL;
+ return ERROR_TARGET_NOT_EXAMINED;
}
- switch (cortex_m->core_info->partno) {
+ switch (cortex_m_get_partno_safe(target)) {
case CORTEX_M0_PARTNO: /* STM32F0x devices */
device_id_register = 0x40015800;
break;
@@ -659,15 +658,14 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
static int stm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_size_in_kb)
{
struct target *target = bank->target;
- struct cortex_m_common *cortex_m = target_to_cm(target);
uint32_t flash_size_reg;
if (!target_was_examined(target)) {
LOG_ERROR("Target not examined yet");
- return ERROR_FAIL;
+ return ERROR_TARGET_NOT_EXAMINED;
}
- switch (cortex_m->core_info->partno) {
+ switch (cortex_m_get_partno_safe(target)) {
case CORTEX_M0_PARTNO: /* STM32F0x devices */
flash_size_reg = 0x1FFFF7CC;
break;
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index aa0363232..58edca7e1 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -966,14 +966,14 @@ static int stm32x_get_device_id(struct flash_bank *bank, uint32_t *device_id)
* Only effects Rev A silicon */
struct target *target = bank->target;
- struct cortex_m_common *cortex_m = target_to_cm(target);
/* read stm32 device id register */
int retval = target_read_u32(target, 0xE0042000, device_id);
if (retval != ERROR_OK)
return retval;
- if ((*device_id & 0xfff) == 0x411 && cortex_m->core_info->partno == CORTEX_M4_PARTNO) {
+ if ((*device_id & 0xfff) == 0x411
+ && cortex_m_get_partno_safe(target) == CORTEX_M4_PARTNO) {
*device_id &= ~((0xFFFF << 16) | 0xfff);
*device_id |= (0x1000 << 16) | 0x413;
LOG_INFO("stm32f4x errata detected - fixing incorrect MCU_IDCODE");
@@ -1011,6 +1011,11 @@ static int stm32x_probe(struct flash_bank *bank)
bank->num_prot_blocks = 0;
bank->prot_blocks = NULL;
+ if (!target_was_examined(target)) {
+ LOG_ERROR("Target not examined yet");
+ return ERROR_TARGET_NOT_EXAMINED;
+ }
+
/* if explicitly called out as OTP bank, short circuit probe */
if (stm32x_is_otp(bank)) {
if (stm32x_otp_is_f7(bank)) {
diff --git a/src/flash/nor/stm32h7x.c b/src/flash/nor/stm32h7x.c
index d3f17b2b1..6d3149f94 100644
--- a/src/flash/nor/stm32h7x.c
+++ b/src/flash/nor/stm32h7x.c
@@ -759,7 +759,6 @@ static int stm32x_read_id_code(struct flash_bank *bank, uint32_t *id)
static int stm32x_probe(struct flash_bank *bank)
{
struct target *target = bank->target;
- struct cortex_m_common *cortex_m = target_to_cm(target);
struct stm32h7x_flash_bank *stm32x_info = bank->driver_priv;
uint16_t flash_size_in_kb;
uint32_t device_id;
@@ -767,6 +766,11 @@ static int stm32x_probe(struct flash_bank *bank)
stm32x_info->probed = false;
stm32x_info->part_info = NULL;
+ if (!target_was_examined(target)) {
+ LOG_ERROR("Target not examined yet");
+ return ERROR_TARGET_NOT_EXAMINED;
+ }
+
int retval = stm32x_read_id_code(bank, &stm32x_info->idcode);
if (retval != ERROR_OK)
return retval;
@@ -800,7 +804,8 @@ static int stm32x_probe(struct flash_bank *bank)
/* get flash size from target */
/* STM32H74x/H75x, the second core (Cortex-M4) cannot read the flash size */
retval = ERROR_FAIL;
- if (device_id == DEVID_STM32H74_H75XX && cortex_m->core_info->partno == CORTEX_M4_PARTNO)
+ if (device_id == DEVID_STM32H74_H75XX
+ && cortex_m_get_partno_safe(target) == CORTEX_M4_PARTNO)
LOG_WARNING("%s cannot read the flash size register", target_name(target));
else
retval = target_read_u16(target, stm32x_info->part_info->fsize_addr, &flash_size_in_kb);
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index e5100a015..fa8924ed3 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -1633,12 +1633,13 @@ err_lock:
static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
{
int retval;
+ struct target *target = bank->target;
/* try reading possible IDCODE registers, in the following order */
uint32_t dbgmcu_idcode[] = {DBGMCU_IDCODE_L4_G4, DBGMCU_IDCODE_G0, DBGMCU_IDCODE_L5};
for (unsigned int i = 0; i < ARRAY_SIZE(dbgmcu_idcode); i++) {
- retval = target_read_u32(bank->target, dbgmcu_idcode[i], id);
+ retval = target_read_u32(target, dbgmcu_idcode[i], id);
if ((retval == ERROR_OK) && ((*id & 0xfff) != 0) && ((*id & 0xfff) != 0xfff))
return ERROR_OK;
}
@@ -1647,12 +1648,16 @@ static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
* DBGMCU_IDCODE cannot be read using CPU1 (Cortex-M0+) at AP1,
* to solve this read the UID64 (IEEE 64-bit unique device ID register) */
- struct cortex_m_common *cortex_m = target_to_cm(bank->target);
+ struct armv7m_common *armv7m = target_to_armv7m_safe(target);
+ if (!armv7m) {
+ LOG_ERROR("Flash requires Cortex-M target");
+ return ERROR_TARGET_INVALID;
+ }
/* CPU2 (Cortex-M0+) is supported only with non-hla adapters because it is on AP1.
* Using HLA adapters armv7m.debug_ap is null, and checking ap_num triggers a segfault */
- if (cortex_m->core_info->partno == CORTEX_M0P_PARTNO &&
- cortex_m->armv7m.debug_ap && cortex_m->armv7m.debug_ap->ap_num == 1) {
+ if (cortex_m_get_partno_safe(target) == CORTEX_M0P_PARTNO &&
+ armv7m->debug_ap && armv7m->debug_ap->ap_num == 1) {
uint32_t uid64_ids;
/* UID64 is contains
@@ -1662,7 +1667,7 @@ static int stm32l4_read_idcode(struct flash_bank *bank, uint32_t *id)
*
* read only the fixed values {STID,DEVID} from UID64_IDS to identify the device as STM32WLx
*/
- retval = target_read_u32(bank->target, UID64_IDS, &uid64_ids);
+ retval = target_read_u32(target, UID64_IDS, &uid64_ids);
if (retval == ERROR_OK && uid64_ids == UID64_IDS_STM32WL) {
/* force the DEV_ID to DEVID_STM32WLE_WL5XX and the REV_ID to unknown */
*id = DEVID_STM32WLE_WL5XX;
@@ -1700,11 +1705,21 @@ static const char *get_stm32l4_bank_type_str(struct flash_bank *bank)
static int stm32l4_probe(struct flash_bank *bank)
{
struct target *target = bank->target;
- struct armv7m_common *armv7m = target_to_armv7m(target);
struct stm32l4_flash_bank *stm32l4_info = bank->driver_priv;
const struct stm32l4_part_info *part_info;
uint16_t flash_size_kb = 0xffff;
+ if (!target_was_examined(target)) {
+ LOG_ERROR("Target not examined yet");
+ return ERROR_TARGET_NOT_EXAMINED;
+ }
+
+ struct armv7m_common *armv7m = target_to_armv7m_safe(target);
+ if (!armv7m) {
+ LOG_ERROR("Flash requires Cortex-M target");
+ return ERROR_TARGET_INVALID;
+ }
+
stm32l4_info->probed = false;
/* read stm32 device id registers */
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32f1x.c | 10 ++++------
src/flash/nor/stm32f2x.c | 9 +++++++--
src/flash/nor/stm32h7x.c | 9 +++++++--
src/flash/nor/stm32l4x.c | 27 +++++++++++++++++++++------
4 files changed, 39 insertions(+), 16 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-02-25 20:27:22
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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commit b53f5c257185e5410622ed72790affb1bda88248
Author: Tomas Vanek <va...@fb...>
Date: Thu Nov 25 06:13:31 2021 +0100
target/cortex_m: add Cortex-M part number getter
The getter checks the magic numbers in arch_info to detect eventual
type mismatch.
Change-Id: I61134b05310a97ae9831517d0516c7b4240d35a5
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6751
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 8fb34f46c..555401416 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -46,6 +46,7 @@
#define ARM_CPUID_PARTNO_MASK (0xFFF << ARM_CPUID_PARTNO_POS)
enum cortex_m_partno {
+ CORTEX_M_PARTNO_INVALID,
CORTEX_M0_PARTNO = 0xC20,
CORTEX_M1_PARTNO = 0xC21,
CORTEX_M3_PARTNO = 0xC23,
@@ -294,6 +295,23 @@ target_to_cortex_m_safe(struct target *target)
return cortex_m;
}
+/**
+ * @returns cached value of Cortex-M part number
+ * or CORTEX_M_PARTNO_INVALID if the magic number does not match
+ * or core_info is not initialised.
+ */
+static inline enum cortex_m_partno cortex_m_get_partno_safe(struct target *target)
+{
+ struct cortex_m_common *cortex_m = target_to_cortex_m_safe(target);
+ if (!cortex_m)
+ return CORTEX_M_PARTNO_INVALID;
+
+ if (!cortex_m->core_info)
+ return CORTEX_M_PARTNO_INVALID;
+
+ return cortex_m->core_info->partno;
+}
+
int cortex_m_examine(struct target *target);
int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_m.h | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-02-25 19:57:06
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- Log -----------------------------------------------------------------
commit e4ba76a003ce4a2336eade806a04a278c376d0b6
Author: Tomas Vanek <va...@fb...>
Date: Wed Nov 24 22:11:13 2021 +0100
target/armv7m,cortex_m: introduce checked arch_info cast routines
target_to_armv7m() and target_to_cm() do not match the magic number
so they are not suitable for use outside of target driver code.
Add checked versions of pointer getters. Match the magic number
to ensure the returned value points to struct of the correct type.
Change-Id: If90ef7e969ef04f0f2103e0da29dcbe8e1ac1c0d
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6750
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/armv7m.h b/src/target/armv7m.h
index d33e57492..9ac121ac3 100644
--- a/src/target/armv7m.h
+++ b/src/target/armv7m.h
@@ -255,15 +255,48 @@ struct armv7m_common {
void (*pre_restore_context)(struct target *target);
};
+static inline bool is_armv7m(const struct armv7m_common *armv7m)
+{
+ return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
+}
+
+/**
+ * @returns the pointer to the target specific struct
+ * without matching a magic number.
+ * Use in target specific service routines, where the correct
+ * type of arch_info is certain.
+ */
static inline struct armv7m_common *
target_to_armv7m(struct target *target)
{
return container_of(target->arch_info, struct armv7m_common, arm);
}
-static inline bool is_armv7m(const struct armv7m_common *armv7m)
+/**
+ * @returns the pointer to the target specific struct
+ * or NULL if the magic number does not match.
+ * Use in a flash driver or any place where mismatch of the arch_info
+ * type can happen.
+ */
+static inline struct armv7m_common *
+target_to_armv7m_safe(struct target *target)
{
- return armv7m->common_magic == ARMV7M_COMMON_MAGIC;
+ if (!target)
+ return NULL;
+
+ if (!target->arch_info)
+ return NULL;
+
+ /* Check the parent type first to prevent peeking memory too far
+ * from arch_info pointer */
+ if (!is_arm(target_to_arm(target)))
+ return NULL;
+
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ if (!is_armv7m(armv7m))
+ return NULL;
+
+ return armv7m;
}
struct armv7m_algorithm {
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index cabe405ce..8fb34f46c 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -247,13 +247,6 @@ struct cortex_m_common {
bool maskints_erratum;
};
-static inline struct cortex_m_common *
-target_to_cm(struct target *target)
-{
- return container_of(target->arch_info,
- struct cortex_m_common, armv7m.arm);
-}
-
static inline bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
{
return cortex_m->common_magic == CORTEX_M_COMMON_MAGIC;
@@ -267,6 +260,40 @@ static inline bool is_cortex_m_with_dap_access(const struct cortex_m_common *cor
return !cortex_m->armv7m.is_hla_target;
}
+/**
+ * @returns the pointer to the target specific struct
+ * without matching a magic number.
+ * Use in target specific service routines, where the correct
+ * type of arch_info is certain.
+ */
+static inline struct cortex_m_common *
+target_to_cm(struct target *target)
+{
+ return container_of(target->arch_info,
+ struct cortex_m_common, armv7m.arm);
+}
+
+/**
+ * @returns the pointer to the target specific struct
+ * or NULL if the magic number does not match.
+ * Use in a flash driver or any place where mismatch of the arch_info
+ * type can happen.
+ */
+static inline struct cortex_m_common *
+target_to_cortex_m_safe(struct target *target)
+{
+ /* Check the parent types first to prevent peeking memory too far
+ * from arch_info pointer */
+ if (!target_to_armv7m_safe(target))
+ return NULL;
+
+ struct cortex_m_common *cortex_m = target_to_cm(target);
+ if (!is_cortex_m_or_hla(cortex_m))
+ return NULL;
+
+ return cortex_m;
+}
+
int cortex_m_examine(struct target *target);
int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint);
int cortex_m_unset_breakpoint(struct target *target, struct breakpoint *breakpoint);
-----------------------------------------------------------------------
Summary of changes:
src/target/armv7m.h | 37 +++++++++++++++++++++++++++++++++++--
src/target/cortex_m.h | 41 ++++++++++++++++++++++++++++++++++-------
2 files changed, 69 insertions(+), 9 deletions(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-02-25 19:54:22
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 10b5ac9ccb2b51b5aad01e4cb02be84fea3ebc62
Author: Tomas Vanek <va...@fb...>
Date: Wed Nov 24 19:05:21 2021 +0100
target/cortex_m: fix target_to_cm() helper
The third parameter of container_of() should point to the same member
as target->arch_info points to, struct arm.
It worked just because struct arm is the first member in
struct armv7m_common.
If you move arm member from the first place, OpenOCD fails heavily.
Change-Id: I0c0a5221490945563e17a0a34d99a603f1d6c2ff
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6749
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index c2f836a35..cabe405ce 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -251,7 +251,7 @@ static inline struct cortex_m_common *
target_to_cm(struct target *target)
{
return container_of(target->arch_info,
- struct cortex_m_common, armv7m);
+ struct cortex_m_common, armv7m.arm);
}
static inline bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_m.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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From: OpenOCD-Gerrit <ope...@us...> - 2022-02-25 11:00:21
|
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commit 29912328f07d562281e8a0db8855c8362afba546
Author: Simon Johansson <amp...@gm...>
Date: Mon Jan 17 13:30:59 2022 +0100
flash/nor/stm32f2x: Fix erase of bank 2 sectors
This commit corrects the erase function for stm32f2x when dealing with
sectors in bank 2, for STM32F42x/43x devices with 1MB flash.
On STM32F42x/43x with 1MB flash in dual bank configuration, the sector
numbering is not consecutive. The last sector in bank 1 is number 7, and
the first sector in bank 2 is number 12.
The sector indices used by openocd, however, _are_ consecutive (0 to 15
in this case). The arguments "first" and "last" to stm32x_erase() are of
this type, and so the logic surrounding sector numbers needed to be
corrected.
Since the two banks in dual bank mode have the same number of sectors, a
sector index in bank 2 is larger than or equal to half the total number
of sectors.
Change-Id: I15260f8a86d9002769a1ae1c40ebdf62142dae18
Signed-off-by: Simon Johansson <amp...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6810
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Tarek BOCHKATI <tar...@gm...>
diff --git a/src/flash/nor/stm32f2x.c b/src/flash/nor/stm32f2x.c
index d3e7d709c..aa0363232 100644
--- a/src/flash/nor/stm32f2x.c
+++ b/src/flash/nor/stm32f2x.c
@@ -636,8 +636,8 @@ static int stm32x_erase(struct flash_bank *bank, unsigned int first,
for (unsigned int i = first; i <= last; i++) {
unsigned int snb;
- if (stm32x_info->has_large_mem && i >= 12)
- snb = (i - 12) | 0x10;
+ if (stm32x_info->has_large_mem && i >= (bank->num_sectors / 2))
+ snb = (i - (bank->num_sectors / 2)) | 0x10;
else
snb = i;
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/stm32f2x.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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From: OpenOCD-Gerrit <ope...@us...> - 2022-02-19 14:34:09
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This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 94e7535be85a7bd5905dec68b6eae9a98aae0d7e (commit)
from 254883597f2487f6e75e10c36991149679e21870 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 94e7535be85a7bd5905dec68b6eae9a98aae0d7e
Author: Antonio Borneo <bor...@gm...>
Date: Wed Feb 2 13:46:46 2022 +0100
.gitmodules: switch away from repo.or.cz
The host repo.or.cz is often offline, creating issues for cloning
and building OpenOCD from scratch.
Already 'jimtcl' developer has dropped repo.or.cz, triggering the
OpenOCD commit 861e75f54efb ("jimtcl: switch to github").
Change also the link of the remaining submodules 'git2cl' and
'libjaylink' to their respective main repository.
Change-Id: Ib513237427635359ce36a480a8f2060e2fb12ba4
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/6834
Tested-by: jenkins
Reviewed-by: zapb <de...@za...>
diff --git a/.gitmodules b/.gitmodules
index 23ffa2543..f2da17ed7 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,9 +1,9 @@
[submodule "tools/git2cl"]
path = tools/git2cl
- url = https://repo.or.cz/git2cl.git
+ url = https://git.savannah.nongnu.org/git/git2cl.git
[submodule "jimtcl"]
path = jimtcl
url = https://github.com/msteveb/jimtcl.git
[submodule "src/jtag/drivers/libjaylink"]
path = src/jtag/drivers/libjaylink
- url = https://repo.or.cz/libjaylink.git
+ url = https://gitlab.zapb.de/libjaylink/libjaylink.git
-----------------------------------------------------------------------
Summary of changes:
.gitmodules | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
