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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-355-g2c8c2cb6b

[openocd-gerrit <ope...@us...>]

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- Log -----------------------------------------------------------------
commit 2c8c2cb6b1426afc73519a7445a71a0aed36cf0f
Author: Marek Vrbka <mar...@co...>
Date:   Mon Sep 18 14:32:44 2023 +0200

    command: Prepend logs during command capture
    
    Previously, if you ran a tcl command in capture like so:
    "capture { reg 0x1000 hw }"
    Such command did overwrite the tcl result if LOG_LVL_INFO or
    lower was logged during it.
    
    This patch changes it by prepending the log to the tcl result instead.
    As the tcl results should not be lost during capture.
    
    Change-Id: I37381b45e15c931ba2844d65c9d38f6ed2f6e4fd
    Signed-off-by: Marek Vrbka <mar...@co...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7902
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins
    Reviewed-by: Jan Matyas <jan...@co...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 2d59238b8..6ec280ad2 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -12475,7 +12475,7 @@ Return information about the flash banks
 @item @b{capture} <@var{command}>
 
 Run <@var{command}> and return full log output that was produced during
-its execution. Example:
+its execution together with the command output. Example:
 
 @example
 > capture "reset init"
diff --git a/src/helper/command.c b/src/helper/command.c
index 945b890b3..ef50ab5bd 100644
--- a/src/helper/command.c
+++ b/src/helper/command.c
@@ -99,8 +99,7 @@ static struct log_capture_state *command_log_capture_start(Jim_Interp *interp)
  * The tcl return value is empty for openocd commands that provide
  * progress output.
  *
- * Therefore we set the tcl return value only if we actually
- * captured output.
+ * For other commands, we prepend the logs to the tcl return value.
  */
 static void command_log_capture_finish(struct log_capture_state *state)
 {
@@ -109,15 +108,18 @@ static void command_log_capture_finish(struct log_capture_state *state)
 
 	log_remove_callback(tcl_output, state);
 
-	int length;
-	Jim_GetString(state->output, &length);
+	int loglen;
+	const char *log_result = Jim_GetString(state->output, &loglen);
+	int reslen;
+	const char *cmd_result = Jim_GetString(Jim_GetResult(state->interp), &reslen);
 
-	if (length > 0)
-		Jim_SetResult(state->interp, state->output);
-	else {
-		/* No output captured, use tcl return value (which could
-		 * be empty too). */
-	}
+	// Just in case the log doesn't end with a newline, we add it
+	if (loglen != 0 && reslen != 0 && log_result[loglen - 1] != '\n')
+		Jim_AppendString(state->interp, state->output, "\n", 1);
+
+	Jim_AppendString(state->interp, state->output, cmd_result, reslen);
+
+	Jim_SetResult(state->interp, state->output);
 	Jim_DecrRefCount(state->interp, state->output);
 
 	free(state);
@@ -691,8 +693,8 @@ COMMAND_HANDLER(handle_echo)
 	return ERROR_OK;
 }
 
-/* Capture progress output and return as tcl return value. If the
- * progress output was empty, return tcl return value.
+/* Return both the progress output (LOG_INFO and higher)
+ * and the tcl return value of a command.
  */
 static int jim_capture(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 {

commit bcaac692d0fce45189279a4c80cbd6852e4bbf4e
Author: Kirill Radkin <kir...@sy...>
Date:   Tue Sep 26 16:49:09 2023 +0300

    target: Fix an issue with rwp/rbp command in smp targets
    
    If wp/bp is missing at address rwp/rbp won't return zero code (on smp).
    Now it fixed.
    
    Fixes: 022e438292de ("target: Change policy of removing watchpoints/breakpoints.")
    
    Change-Id: I3a3c245f7088fc23227b286d2191fc7f3edba702
    Signed-off-by: Kirill Radkin <kir...@sy...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7910
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index 5ce0346bb..4a613cc28 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -367,8 +367,10 @@ int breakpoint_remove(struct target *target, target_addr_t address)
 		}
 	}
 
-	if (num_found_breakpoints == 0)
+	if (num_found_breakpoints == 0) {
 		LOG_TARGET_ERROR(target, "no breakpoint at address " TARGET_ADDR_FMT " found", address);
+		return ERROR_BREAKPOINT_NOT_FOUND;
+	}
 
 	return retval;
 }
@@ -591,7 +593,7 @@ int watchpoint_remove(struct target *target, target_addr_t address)
 				num_found_watchpoints++;
 
 				if (status != ERROR_OK) {
-					LOG_TARGET_ERROR(curr, "failed to remove watchpoint at address" TARGET_ADDR_FMT, address);
+					LOG_TARGET_ERROR(curr, "failed to remove watchpoint at address " TARGET_ADDR_FMT, address);
 					retval = status;
 				}
 			}
@@ -603,12 +605,14 @@ int watchpoint_remove(struct target *target, target_addr_t address)
 			num_found_watchpoints++;
 
 			if (retval != ERROR_OK)
-				LOG_TARGET_ERROR(target, "failed to remove watchpoint at address" TARGET_ADDR_FMT, address);
+				LOG_TARGET_ERROR(target, "failed to remove watchpoint at address " TARGET_ADDR_FMT, address);
 		}
 	}
 
-	if (num_found_watchpoints == 0)
+	if (num_found_watchpoints == 0) {
 		LOG_TARGET_ERROR(target, "no watchpoint at address " TARGET_ADDR_FMT " found", address);
+		return ERROR_WATCHPOINT_NOT_FOUND;
+	}
 
 	return retval;
 }

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi         |  2 +-
 src/helper/command.c     | 26 ++++++++++++++------------
 src/target/breakpoints.c | 12 ++++++++----
 3 files changed, 23 insertions(+), 17 deletions(-)


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[openocd-gerrit <ope...@us...>]

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- Log -----------------------------------------------------------------
commit d27a3a00b8582cf2750cbc86c6194f5796ccca06
Author: Florian Fainelli <f.f...@gm...>
Date:   Mon Mar 18 16:00:07 2019 -0700

    arm_opcode: Add support for ARM MCRR/MRRC
    
    Add support for the ARM MCRR/MRRC instructions which require the use of
    two registers to transfer a 64-bit co-processor registers. We are going
    to use this in a subsequent patch in order to properly dump 64-bit page
    table descriptors that exist on ARMv7A with VMSA extensions.
    
    We make use of r0 and r1 to transfer 64-bit quantities to/from DCC.
    
    Change-Id: Ic4975026c1ae4f2853795575ac7701d541248736
    Signed-off-by: Florian Fainelli <f.f...@gm...>
    Signed-off-by: Michael Chalfant <mic...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/5228
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/arm.h b/src/target/arm.h
index cc0f14cb6..d5053afb8 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -231,12 +231,22 @@ struct arm {
 			uint32_t crn, uint32_t crm,
 			uint32_t *value);
 
+	/** Read coprocessor to two registers. */
+	int (*mrrc)(struct target *target, int cpnum,
+			uint32_t op, uint32_t crm,
+			uint64_t *value);
+
 	/** Write coprocessor register.  */
 	int (*mcr)(struct target *target, int cpnum,
 			uint32_t op1, uint32_t op2,
 			uint32_t crn, uint32_t crm,
 			uint32_t value);
 
+	/** Write coprocessor from two registers. */
+	int (*mcrr)(struct target *target, int cpnum,
+			uint32_t op, uint32_t crm,
+			uint64_t value);
+
 	void *arch_info;
 
 	/** For targets conforming to ARM Debug Interface v5,
diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index ab9b50e23..9f3a444af 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -63,6 +63,29 @@ static int dpm_mrc(struct target *target, int cpnum,
 	return retval;
 }
 
+static int dpm_mrrc(struct target *target, int cpnum,
+	uint32_t op, uint32_t crm, uint64_t *value)
+{
+	struct arm *arm = target_to_arm(target);
+	struct arm_dpm *dpm = arm->dpm;
+	int retval;
+
+	retval = dpm->prepare(dpm);
+	if (retval != ERROR_OK)
+		return retval;
+
+	LOG_DEBUG("MRRC p%d, %d, r0, r1, c%d", cpnum,
+		 (int)op, (int)crm);
+
+	/* read coprocessor register into R0, R1; return via DCC */
+	retval = dpm->instr_read_data_r0_r1(dpm,
+			ARMV5_T_MRRC(cpnum, op, 0, 1, crm),
+			value);
+
+	/* (void) */ dpm->finish(dpm);
+	return retval;
+}
+
 static int dpm_mcr(struct target *target, int cpnum,
 	uint32_t op1, uint32_t op2, uint32_t crn, uint32_t crm,
 	uint32_t value)
@@ -88,6 +111,29 @@ static int dpm_mcr(struct target *target, int cpnum,
 	return retval;
 }
 
+static int dpm_mcrr(struct target *target, int cpnum,
+	uint32_t op, uint32_t crm, uint64_t value)
+{
+	struct arm *arm = target_to_arm(target);
+	struct arm_dpm *dpm = arm->dpm;
+	int retval;
+
+	retval = dpm->prepare(dpm);
+	if (retval != ERROR_OK)
+		return retval;
+
+	LOG_DEBUG("MCRR p%d, %d, r0, r1, c%d", cpnum,
+		(int)op, (int)crm);
+
+	/* read DCC into r0, r1; then write coprocessor register from R0, R1 */
+	retval = dpm->instr_write_data_r0_r1(dpm,
+			ARMV5_T_MCRR(cpnum, op, 0, 1, crm), value);
+
+	/* (void) */ dpm->finish(dpm);
+
+	return retval;
+}
+
 /*----------------------------------------------------------------------*/
 
 /*
@@ -1070,6 +1116,8 @@ int arm_dpm_setup(struct arm_dpm *dpm)
 	/* coprocessor access setup */
 	arm->mrc = dpm_mrc;
 	arm->mcr = dpm_mcr;
+	arm->mrrc = dpm_mrrc;
+	arm->mcrr = dpm_mcrr;
 
 	/* breakpoint setup -- optional until it works everywhere */
 	if (!target->type->add_breakpoint) {
diff --git a/src/target/arm_dpm.h b/src/target/arm_dpm.h
index d35e9f68d..2da463111 100644
--- a/src/target/arm_dpm.h
+++ b/src/target/arm_dpm.h
@@ -72,6 +72,12 @@ struct arm_dpm {
 	int (*instr_write_data_r0)(struct arm_dpm *dpm,
 			uint32_t opcode, uint32_t data);
 
+	/**
+	 * Runs two instructions, writing data to R0 and R1 before execution.
+	 */
+	int (*instr_write_data_r0_r1)(struct arm_dpm *dpm,
+			uint32_t opcode, uint64_t data);
+
 	/** Runs one instruction, writing data to R0 before execution. */
 	int (*instr_write_data_r0_64)(struct arm_dpm *dpm,
 			uint32_t opcode, uint64_t data);
@@ -92,6 +98,13 @@ struct arm_dpm {
 	int (*instr_read_data_r0)(struct arm_dpm *dpm,
 			uint32_t opcode, uint32_t *data);
 
+	/**
+	 * Runs two instructions, reading data from r0 and r1 after
+	 * execution.
+	 */
+	int (*instr_read_data_r0_r1)(struct arm_dpm *dpm,
+			uint32_t opcode, uint64_t *data);
+
 	int (*instr_read_data_r0_64)(struct arm_dpm *dpm,
 			uint32_t opcode, uint64_t *data);
 
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h
index c182f41c4..c8ce51f29 100644
--- a/src/target/arm_opcodes.h
+++ b/src/target/arm_opcodes.h
@@ -187,6 +187,17 @@
 	(0xee100010 | (crm) | ((op2) << 5) | ((cp) << 8) \
 	| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
 
+/* Move to two ARM registers from coprocessor
+ * cp: Coprocessor number
+ * op: Coprocessor opcode
+ * rt: destination register 1
+ * rt2: destination register 2
+ * crm: coprocessor source register
+ */
+#define ARMV5_T_MRRC(cp, op, rt, rt2, crm) \
+	(0xec500000 | (crm) | ((op) << 4) | ((cp) << 8) \
+	| ((rt) << 12) | ((rt2) << 16))
+
 /* Move to coprocessor from ARM register
  * cp: Coprocessor number
  * op1: Coprocessor opcode
@@ -199,6 +210,17 @@
 	(0xee000010 | (crm) | ((op2) << 5) | ((cp) << 8) \
 	| ((rd) << 12) | ((crn) << 16) | ((op1) << 21))
 
+/* Move to coprocessor from two ARM registers
+ * cp: Coprocessor number
+ * op: Coprocessor opcode
+ * rt: destination register 1
+ * rt2: destination register 2
+ * crm: coprocessor source register
+ */
+#define ARMV5_T_MCRR(cp, op, rt, rt2, crm) \
+	(0xec400000 | (crm) | ((op) << 4) | ((cp) << 8) \
+	 | ((rt) << 12) | ((rt2) << 16))
+
 /* Breakpoint instruction (ARMv5)
  * im: 16-bit immediate
  */
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 8e3f22417..7debb9498 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1093,6 +1093,94 @@ COMMAND_HANDLER(handle_armv4_5_mcrmrc)
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(handle_armv4_5_mcrrmrrc)
+{
+	bool is_mcrr = false;
+	unsigned int arg_cnt = 3;
+
+	if (!strcmp(CMD_NAME, "mcrr")) {
+		is_mcrr = true;
+		arg_cnt = 4;
+	}
+
+	if (arg_cnt != CMD_ARGC)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	struct target *target = get_current_target(CMD_CTX);
+	if (!target) {
+		command_print(CMD, "no current target");
+		return ERROR_FAIL;
+	}
+	if (!target_was_examined(target)) {
+		command_print(CMD, "%s: not yet examined", target_name(target));
+		return ERROR_TARGET_NOT_EXAMINED;
+	}
+
+	struct arm *arm = target_to_arm(target);
+	if (!is_arm(arm)) {
+		command_print(CMD, "%s: not an ARM", target_name(target));
+		return ERROR_FAIL;
+	}
+
+	if (target->state != TARGET_HALTED)
+		return ERROR_TARGET_NOT_HALTED;
+
+	int cpnum;
+	uint32_t op1;
+	uint32_t crm;
+	uint64_t value;
+
+	/* NOTE:  parameter sequence matches ARM instruction set usage:
+	 *	MCRR	pNUM, op1, rX1, rX2, CRm	; write CP from rX1 and rX2
+	 *	MREC	pNUM, op1, rX1, rX2, CRm	; read CP into rX1 and rX2
+	 * The "rXn" are necessarily omitted; they use Tcl mechanisms.
+	 */
+	COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cpnum);
+	if (cpnum & ~0xf) {
+		command_print(CMD, "coprocessor %d out of range", cpnum);
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[1], op1);
+	if (op1 & ~0xf) {
+		command_print(CMD, "op1 %d out of range", op1);
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+
+	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[2], crm);
+	if (crm & ~0xf) {
+		command_print(CMD, "CRm %d out of range", crm);
+		return ERROR_COMMAND_ARGUMENT_INVALID;
+	}
+
+	/*
+	 * FIXME change the call syntax here ... simplest to just pass
+	 * the MRC() or MCR() instruction to be executed.  That will also
+	 * let us support the "mrrc2" and "mcrr2" opcodes (toggling one bit)
+	 * if that's ever needed.
+	 */
+	if (is_mcrr) {
+		COMMAND_PARSE_NUMBER(u64, CMD_ARGV[3], value);
+
+		/* NOTE: parameters reordered! */
+		/* ARMV5_T_MCRR(cpnum, op1, crm) */
+		int retval = arm->mcrr(target, cpnum, op1, crm, value);
+		if (retval != ERROR_OK)
+			return retval;
+	} else {
+		value = 0;
+		/* NOTE: parameters reordered! */
+		/* ARMV5_T_MRRC(cpnum, op1, crm) */
+		int retval = arm->mrrc(target, cpnum, op1, crm, &value);
+		if (retval != ERROR_OK)
+			return retval;
+
+		command_print(CMD, "0x%" PRIx64, value);
+	}
+
+	return ERROR_OK;
+}
+
 static const struct command_registration arm_exec_command_handlers[] = {
 	{
 		.name = "reg",
@@ -1115,6 +1203,20 @@ static const struct command_registration arm_exec_command_handlers[] = {
 		.help = "read coprocessor register",
 		.usage = "cpnum op1 CRn CRm op2",
 	},
+	{
+		.name = "mcrr",
+		.mode = COMMAND_EXEC,
+		.handler = handle_armv4_5_mcrrmrrc,
+		.help = "write coprocessor 64-bit register",
+		.usage = "cpnum op1 CRm value",
+	},
+	{
+		.name = "mrrc",
+		.mode = COMMAND_EXEC,
+		.handler = handle_armv4_5_mcrrmrrc,
+		.help = "read coprocessor 64-bit register",
+		.usage = "cpnum op1 CRm",
+	},
 	{
 		.chain = arm_all_profiles_command_handlers,
 	},
@@ -1669,6 +1771,14 @@ static int arm_default_mrc(struct target *target, int cpnum,
 	return ERROR_FAIL;
 }
 
+static int arm_default_mrrc(struct target *target, int cpnum,
+	uint32_t op, uint32_t crm,
+	uint64_t *value)
+{
+	LOG_ERROR("%s doesn't implement MRRC", target_type_name(target));
+	return ERROR_FAIL;
+}
+
 static int arm_default_mcr(struct target *target, int cpnum,
 	uint32_t op1, uint32_t op2,
 	uint32_t crn, uint32_t crm,
@@ -1678,6 +1788,14 @@ static int arm_default_mcr(struct target *target, int cpnum,
 	return ERROR_FAIL;
 }
 
+static int arm_default_mcrr(struct target *target, int cpnum,
+	uint32_t op, uint32_t crm,
+	uint64_t value)
+{
+	LOG_ERROR("%s doesn't implement MCRR", target_type_name(target));
+	return ERROR_FAIL;
+}
+
 int arm_init_arch_info(struct target *target, struct arm *arm)
 {
 	target->arch_info = arm;
@@ -1697,8 +1815,12 @@ int arm_init_arch_info(struct target *target, struct arm *arm)
 
 	if (!arm->mrc)
 		arm->mrc = arm_default_mrc;
+	if (!arm->mrrc)
+		arm->mrrc = arm_default_mrrc;
 	if (!arm->mcr)
 		arm->mcr = arm_default_mcr;
+	if (!arm->mcrr)
+		arm->mcrr = arm_default_mcrr;
 
 	return ERROR_OK;
 }
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index abfd6ac5f..ba3349d09 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -471,6 +471,28 @@ static int cortex_a_instr_write_data_r0(struct arm_dpm *dpm,
 	return retval;
 }
 
+static int cortex_a_instr_write_data_r0_r1(struct arm_dpm *dpm,
+	uint32_t opcode, uint64_t data)
+{
+	struct cortex_a_common *a = dpm_to_a(dpm);
+	uint32_t dscr = DSCR_INSTR_COMP;
+	int retval;
+
+	retval = cortex_a_instr_write_data_rt_dcc(dpm, 0, data & 0xffffffffULL);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = cortex_a_instr_write_data_rt_dcc(dpm, 1, data >> 32);
+	if (retval != ERROR_OK)
+		return retval;
+
+	/* then the opcode, taking data from R0, R1 */
+	retval = cortex_a_exec_opcode(a->armv7a_common.arm.target,
+			opcode,
+			&dscr);
+	return retval;
+}
+
 static int cortex_a_instr_cpsr_sync(struct arm_dpm *dpm)
 {
 	struct target *target = dpm->arm->target;
@@ -539,6 +561,29 @@ static int cortex_a_instr_read_data_r0(struct arm_dpm *dpm,
 	return cortex_a_instr_read_data_rt_dcc(dpm, 0, data);
 }
 
+static int cortex_a_instr_read_data_r0_r1(struct arm_dpm *dpm,
+	uint32_t opcode, uint64_t *data)
+{
+	uint32_t lo, hi;
+	int retval;
+
+	/* the opcode, writing data to RO, R1 */
+	retval = cortex_a_instr_read_data_r0(dpm, opcode, &lo);
+	if (retval != ERROR_OK)
+		return retval;
+
+	*data = lo;
+
+	/* write R1 to DCC */
+	retval = cortex_a_instr_read_data_rt_dcc(dpm, 1, &hi);
+	if (retval != ERROR_OK)
+		return retval;
+
+	*data |= (uint64_t)hi << 32;
+
+	return retval;
+}
+
 static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
 	uint32_t addr, uint32_t control)
 {
@@ -612,10 +657,12 @@ static int cortex_a_dpm_setup(struct cortex_a_common *a, uint32_t didr)
 
 	dpm->instr_write_data_dcc = cortex_a_instr_write_data_dcc;
 	dpm->instr_write_data_r0 = cortex_a_instr_write_data_r0;
+	dpm->instr_write_data_r0_r1 = cortex_a_instr_write_data_r0_r1;
 	dpm->instr_cpsr_sync = cortex_a_instr_cpsr_sync;
 
 	dpm->instr_read_data_dcc = cortex_a_instr_read_data_dcc;
 	dpm->instr_read_data_r0 = cortex_a_instr_read_data_r0;
+	dpm->instr_read_data_r0_r1 = cortex_a_instr_read_data_r0_r1;
 
 	dpm->bpwp_enable = cortex_a_bpwp_enable;
 	dpm->bpwp_disable = cortex_a_bpwp_disable;

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm.h         |  10 ++++
 src/target/arm_dpm.c     |  48 +++++++++++++++++++
 src/target/arm_dpm.h     |  13 +++++
 src/target/arm_opcodes.h |  22 +++++++++
 src/target/armv4_5.c     | 122 +++++++++++++++++++++++++++++++++++++++++++++++
 src/target/cortex_a.c    |  47 ++++++++++++++++++
 6 files changed, 262 insertions(+)


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commit 1bc4182cebcbdf93d68d9759f4b4579ea4df7887
Author: Frank Plowman <po...@fr...>
Date:   Sun Sep 17 19:20:04 2023 +0100

    target/nrf52: Create and configure TPIU
    
    Firstly, create the TPIU nrf52.tpiu if using the nrf52 target. This is
    standard, using AP 0 and TPIU base address 0xE0040000.
    Secondly, add a pre_enable handler for this TPIU which configures the
    TRACEMUX field of the TRACECONFIG register. This register is reset
    every time the MCU resets, so the pre_enable handler creates a
    reset-end handler to ensure the register remains set.
    
    Change-Id: I408b20fc03dc2060c21bad0c21ed713eee55a113
    Signed-off-by: Frank Plowman <po...@fr...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7901
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/nrf52.cfg b/tcl/target/nrf52.cfg
index 2539be049..0c82c5758 100644
--- a/tcl/target/nrf52.cfg
+++ b/tcl/target/nrf52.cfg
@@ -5,6 +5,7 @@
 #
 
 source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
 
 if { [info exists CHIPNAME] } {
 	set _CHIPNAME $CHIPNAME
@@ -116,3 +117,51 @@ proc nrf52_recover {} {
 }
 
 add_help_text nrf52_recover "Mass erase and unlock nRF52 device"
+
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0xE0040000
+
+lappend _telnet_autocomplete_skip _proc_pre_enable_$_CHIPNAME.tpiu
+proc _proc_pre_enable_$_CHIPNAME.tpiu {_targetname _chipname} {
+	targets $_targetname
+
+	# Read FICR.INFO.PART
+	set PART [mrw 0x10000100]
+
+	switch $PART {
+		0x52840 -
+		0x52833 -
+		0x52832 {
+			if { [$_chipname.tpiu cget -protocol] eq "sync" } {
+				if { [$_chipname.tpiu cget -port-width] != 4 } {
+					echo "Error. Device only supports 4-bit sync traces."
+					return
+				}
+
+				# Set TRACECONFIG.TRACEMUX to enable synchronous trace
+				mmw 0x4000055C 0x00020000 0x00010000
+				$_targetname configure -event reset-end {
+					mmw 0x4000055C 0x00020000 0x00010000
+				}
+			} else {
+				# Set TRACECONFIG.TRACEMUX to enable SWO
+				mmw 0x4000055C 0x00010000 0x00020000
+				$_targetname configure -event reset-end {
+					mmw 0x4000055C 0x00010000 0x00020000
+				}
+			}
+		}
+		0x52820 -
+		0x52811 -
+		0x52810 -
+		0x52805 {
+			echo "Error: Device does not support TPIU"
+			return
+		}
+		default {
+			echo "Error: Unknown device"
+			return
+		}
+	}
+}
+
+$_CHIPNAME.tpiu configure -event pre-enable "_proc_pre_enable_$_CHIPNAME.tpiu $_TARGETNAME $_CHIPNAME"

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/nrf52.cfg | 49 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)


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commit 9c7c5ca4eb04b110f66b4e3c2494a1d55a962b33
Author: Nishanth Menon <nm...@ti...>
Date:   Thu Sep 14 07:49:02 2023 -0500

    tcl/target/ti_k3: Add AXI-AP port for direct SoC memory map access
    
    While we can read and write from memory from the view of various
    processors, all K3 debug systems have a AXI Access port that allows
    us to directly access memory from debug interface. This port is
    especially useful in the following scenarios:
    
    1. Debug cache related behavior on processors as this provides a
       direct bypass path.
    2. Processor has crashed or inaccessible for some reason (low power
       state etc.)
    3. Scenarios prior to the processor getting active.
    4. Debug MMU or address translation issues (example: TI's Region
       Address Table {RAT} translation table used to physically map
       SoC address space into R5/M4F processor address space)
    
    The AXI-AP port is the same for all processors in TI's K3 family.
    
    To prevent a circular-loop scenario for axi-ap accessing debug memory
    with dmem (direct memory access debug), enable this only when dmem is
    disabled.
    
    Change-Id: Ie4ca9222f034ffc2fa669fb5124a5f8e37b65e3b
    Reported-by: Dubravko Srsan <dub...@do...>
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7899
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 090f08209..1cd85eec3 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -417,4 +417,7 @@ if { 0 == [string compare [adapter name] dmem ] } {
 	} else {
 		puts "ERROR: ${SOC} data is missing to support dmem access!"
 	}
+} else {
+	# AXI AP access port for SoC address map
+	target create $_CHIPNAME.axi_ap mem_ap -dap $_CHIPNAME.dap -ap-num 2
 }

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/ti_k3.cfg | 3 +++
 1 file changed, 3 insertions(+)


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commit d14fef8495e6d0247ea2929053d27b5c561ac1d0
Author: Nishanth Menon <nm...@ti...>
Date:   Wed Sep 13 17:57:29 2023 -0500

    tcl/target/ti_k3: Introduce RTOS array variable to set various CPU RTOSes
    
    The Texas Instruments' K3 devices are a mix of AMP and SMP systems.
    The operating systems used on these processors can vary dramatically
    as well. Introduce a RTOS array variable, which is keyed off the cpu
    to identify which RTOS is used on that CPU. This can be "auto" or
    "hwthread" in case of SMP debug etc.
    
    For example:
    AM625 with an general purpose M4F running Zephyr and 4 A53s running SMP
    Linux could be invoked by:
    openocd -c 'set V8_SMP_DEBUG 1' -c 'set RTOS(am625.cpu.gp_mcu) Zephyr' \
            -c "set RTOS(am625.cpu.a53.0) hwthread" -f board/ti_am625evm.cfg
    
    Change-Id: Ib5e59fa2583b3115e5799658afcdd0ee91935e82
    Reported-by: Dubravko Srsan <dub...@do...>
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7898
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index bd7496e2c..090f08209 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -248,6 +248,13 @@ switch $_soc {
 	}
 }
 
+proc _get_rtos_type_for_cpu { target_name } {
+	if { [info exists ::RTOS($target_name)] } {
+		return $::RTOS($target_name)
+	}
+	return none
+}
+
 set _CHIPNAME $_soc
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_K3_DAP_TAPID -ignore-version
@@ -260,7 +267,10 @@ set _CTINAME $_CHIPNAME.cti
 
 # sysctrl is always present
 cti create $_CTINAME.sysctrl -dap $_CHIPNAME.dap -ap-num 7 -baseaddr [lindex $CM3_CTIBASE 0]
-target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine
+
+target create $_TARGETNAME.sysctrl cortex_m -dap $_CHIPNAME.dap -ap-num 7 -defer-examine \
+	-rtos [_get_rtos_type_for_cpu $_TARGETNAME.sysctrl]
+
 $_TARGETNAME.sysctrl configure -event reset-assert { }
 
 proc sysctrl_up {} {
@@ -304,7 +314,8 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
 		-baseaddr [lindex $ARMV8_CTIBASE $_core]
 
 	target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
-		-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
+		-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_armv8_cpu_name.$_core]
 
 	set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"
 
@@ -350,7 +361,8 @@ for { set _core 0 } { $_core < $_r5_cores } { incr _core } {
 
 	# inactive core examination will fail - wait till startup of additional core
 	target create $_TARGETNAME.$_r5_name cortex_r4 -dap $_CHIPNAME.dap \
-		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine
+		-dbgbase [lindex $R5_DBGBASE $_core] -ap-num 1 -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.$_r5_name]
 
 	$_TARGETNAME.$_r5_name configure -event gdb-attach {
 		_cpu_no_smp_up
@@ -368,7 +380,8 @@ proc r5_up { args } {
 
 if { $_gp_mcu_cores != 0 } {
 	cti create $_CTINAME.gp_mcu -dap $_CHIPNAME.dap -ap-num 8 -baseaddr [lindex $CM4_CTIBASE 0]
-	target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+	target create $_TARGETNAME.gp_mcu cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine \
+		-rtos [_get_rtos_type_for_cpu $_TARGETNAME.gp_mcu]
 	$_TARGETNAME.gp_mcu configure -event reset-assert { }
 
 	proc gp_mcu_up {} {

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/ti_k3.cfg | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)


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commit 7abb93aad4039f88427e1179660c0ee68146e6d4
Author: Dubravko Srsan <dub...@do...>
Date:   Wed Sep 13 16:23:03 2023 -0500

    tcl/target/ti_k3: Add coreid identification to SMP processors
    
    Describe the SMP Armv8 cores in SMP configuration with coreid
    explicitly called out. This allows for gdb session to call the smp
    behavior clearly.
    
    Change-Id: Ie43be22db64737bbb66181f09d3c83567044f3ac
    Signed-off-by: Dubravko Srsan <dub...@do...>
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7897
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 3c000ed59..bd7496e2c 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -303,7 +303,7 @@ for { set _core 0 } { $_core < $_armv8_cores } { incr _core } {
 	cti create $_CTINAME.$_armv8_cpu_name.$_core -dap $_CHIPNAME.dap -ap-num 1 \
 		-baseaddr [lindex $ARMV8_CTIBASE $_core]
 
-	target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap \
+	target create $_TARGETNAME.$_armv8_cpu_name.$_core aarch64 -dap $_CHIPNAME.dap -coreid $_core \
 		-dbgbase [lindex $ARMV8_DBGBASE $_core] -cti $_CTINAME.$_armv8_cpu_name.$_core -defer-examine
 
 	set _v8_smp_targets "$_v8_smp_targets $_TARGETNAME.$_armv8_cpu_name.$_core"

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/ti_k3.cfg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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commit 871276cfead7d1ebf11492a1c82691835e1f135a
Author: Dubravko Srsan <dub...@do...>
Date:   Wed Sep 13 14:02:09 2023 -0500

    tcl/target/ti_k3: Fix smp target description
    
    When _v8_smp_targets is used with V8_SMP_DEBUG=1, describe the targets
    as SMP targets. However, the variable expansion is not in the context of
    a proc, and a typo in referring to global $_v8_smp_targets causes this
    to fail. Just refer to $_v8_smp_targets directly.
    
    Change-Id: Iffe5fd2703bed6a9c840284285e70b8a8ce84e17
    Signed-off-by: Dubravko Srsan <dub...@do...>
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7896
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti_k3.cfg
index 01e11c69f..3c000ed59 100644
--- a/tcl/target/ti_k3.cfg
+++ b/tcl/target/ti_k3.cfg
@@ -340,7 +340,7 @@ if { $_v8_smp_debug == 0 } {
 		_armv8_smp_up
 	}
 	# Declare SMP
-	target smp $:::_v8_smp_targets
+	target smp {*}$_v8_smp_targets
 }
 
 for { set _core 0 } { $_core < $_r5_cores } { incr _core } {

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/ti_k3.cfg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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commit 2f17449dff3272e08f509e0f06aa08d3acf7e105
Author: Parshintsev Anatoly <ana...@sy...>
Date:   Tue Sep 5 21:08:02 2023 +0300

    target: return error if attempting to access non-existing registers
    
    Change-Id: Ic22edcab46d21dbc71f78275a78bdea9c2bcc394
    Signed-off-by: Parshintsev Anatoly <ana...@sy...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7886
    Reviewed-by: Tim Newsome <ti...@si...>
    Reviewed-by: Jan Matyas <jan...@co...>
    Reviewed-by: Marek Vrbka <mar...@co...>
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/target.c b/src/target/target.c
index 121974375..acd351a66 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -3116,7 +3116,7 @@ COMMAND_HANDLER(handle_reg_command)
 		if (!reg) {
 			command_print(CMD, "%i is out of bounds, the current target "
 					"has only %i registers (0 - %i)", num, count, count - 1);
-			return ERROR_OK;
+			return ERROR_FAIL;
 		}
 	} else {
 		/* access a single register by its name */
@@ -3175,7 +3175,7 @@ COMMAND_HANDLER(handle_reg_command)
 
 not_found:
 	command_print(CMD, "register %s not found in current target", CMD_ARGV[0]);
-	return ERROR_OK;
+	return ERROR_FAIL;
 }
 
 COMMAND_HANDLER(handle_poll_command)

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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commit d20304b3fb0f27f62844144837ee5b99ee040bcd
Author: Artemiy Volkov <ar...@sy...>
Date:   Thu Jul 6 13:25:00 2023 +0200

    target/arc: do not invalidate icache when (un)setting breakpoints
    
    Currently, instruction cache is being invalidated in
    arc_{un,}set_breakpoint() regardless of whether the breakpoint's type is
    HW or SW. For SW breakpoints, this has no net effect as the caches are
    flushed as a by-product of overwriting instructions in main memory and
    is thus merely unnecessary; but for HW breakpoints this invalidation is
    not preceded by a flush and might lead to loss of data. This patch
    removes the invalidate() call altogether to correct this undesired
    behavior for HW breakpoints.
    
    With this patch applied, all supported HW breakpoint tests from the gdb
    testsuite are now passing with the arc-openocd backend.
    
    Change-Id: I3d252b97f01f1a1e2bf0eb8fb257bdab0c544bc2
    Signed-off-by: Artemiy Volkov <ar...@sy...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7767
    Tested-by: jenkins
    Reviewed-by: Evgeniy Didin <di...@sy...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/arc.c b/src/target/arc.c
index 2ca6be16d..45005b29b 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -1573,9 +1573,6 @@ static int arc_set_breakpoint(struct target *target,
 		return ERROR_FAIL;
 	}
 
-	/* core instruction cache is now invalid. */
-	CHECK_RETVAL(arc_cache_invalidate(target));
-
 	return ERROR_OK;
 }
 
@@ -1658,9 +1655,6 @@ static int arc_unset_breakpoint(struct target *target,
 			return ERROR_FAIL;
 	}
 
-	/* core instruction cache is now invalid. */
-	CHECK_RETVAL(arc_cache_invalidate(target));
-
 	return retval;
 }
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/arc.c | 6 ------
 1 file changed, 6 deletions(-)


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commit bdf73617e774b0791f9efec6659c78c1f60c03b5
Author: Antonio Borneo <bor...@gm...>
Date:   Thu Sep 7 09:58:25 2023 +0200

    armv8_dpm: fix registers read at debug entry
    
    The comment above armv8_dpm_read_current_registers() doesn't match
    the implementation, as the function reads all the registers from
    ARMV8_PC and above.
    The registers currently read are not relevant to answer to the
    usual GDB initial request through the 'g' packet. Plus the lack of
    differentiation per core state (AArch32 vs AArch64) causes the
    read of not existing registers in AArch32 triggering errors, as
    tentatively fixed by https://review.openocd.org/5517/
    
    Fix the code to read the registers initially required by GDB.
    Modify the comment to report the register list in AArch32 and in
    AArch64.
    Keep the extra checks inside the read loop, even if they are
    mostly irrelevant; this could prevent errors if someone needs to
    extend the number of registers to read.
    
    The current implementation of the register's description in
    OpenOCD does not allow to discriminate among AArch32 and AArch64
    registers. Add a TODO comment to highlight it.
    
    Change-Id: Icd47d93c19a9e1694a7b51bbc5ca7e21a578df41
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7887
    Tested-by: jenkins

diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index 9ba6b5453..552bcfa02 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -725,7 +725,8 @@ static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
 }
 
 /**
- * Read basic registers of the current context:  R0 to R15, and CPSR;
+ * Read basic registers of the current context:  R0 to R15, and CPSR in AArch32
+ * state or R0 to R31, PC and CPSR in AArch64 state;
  * sets the core mode (such as USR or IRQ) and state (such as ARM or Thumb).
  * In normal operation this is called on entry to halting debug state,
  * possibly after some other operations supporting restore of debug state
@@ -772,9 +773,15 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
 	/* update core mode and state */
 	armv8_set_cpsr(arm, cpsr);
 
-	for (unsigned int i = ARMV8_PC; i < cache->num_regs ; i++) {
+	/* read the remaining registers that would be required by GDB 'g' packet */
+	for (unsigned int i = ARMV8_R2; i <= ARMV8_PC ; i++) {
 		struct arm_reg *arm_reg;
 
+		/* in AArch32 skip AArch64 registers */
+		/* TODO: this should be detected below through arm_reg->mode */
+		if (arm->core_state != ARM_STATE_AARCH64 && i > ARMV8_R14 && i < ARMV8_PC)
+			continue;
+
 		r = armv8_reg_current(arm, i);
 		if (!r->exist || r->valid)
 			continue;

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv8_dpm.c | 11 +++++++++--
 1 file changed, 9 insertions(+), 2 deletions(-)


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commit f76c8de910e1e12f4b180956d0189c9483e949a5
Author: Ahmed Boughanmi <bou...@in...>
Date:   Wed Aug 30 02:26:40 2023 +0200

    target/cortex_m: support Infineon Cortex-M33 from SLx2 MCU
    
    The secure microcontroller Infineon SLx2 uses a custom Cortex-M33.
    The register CPUID reports value 0x490FDB00.
    
    Reference link to the product:
    Link: https://www.infineon.com/cms/en/about-infineon/press/market-news/2022/INFCSS202211-034.html
    
    Change-Id: I8911712c55bd50e24ed53cf49958352f470027a5
    Signed-off-by: Ahmed Boughanmi <bou...@in...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7879
    Reviewed-by: Karl Palsson <ka...@tw...>
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/arm.h b/src/target/arm.h
index 28e533019..cc0f14cb6 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -61,6 +61,7 @@ enum arm_arch {
 /** Known ARM implementor IDs */
 enum arm_implementor {
 	ARM_IMPLEMENTOR_ARM = 0x41,
+	ARM_IMPLEMENTOR_INFINEON = 0x49,
 	ARM_IMPLEMENTOR_REALTEK = 0x72,
 };
 
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 854e8eb58..3eafee0a1 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -111,6 +111,11 @@ static const struct cortex_m_part_info cortex_m_parts[] = {
 		.arch = ARM_ARCH_V8M,
 		.flags = CORTEX_M_F_HAS_FPV5,
 	},
+	{
+		.impl_part = INFINEON_SLX2_PARTNO,
+		.name = "Infineon-SLx2",
+		.arch = ARM_ARCH_V8M,
+	},
 	{
 		.impl_part = REALTEK_M200_PARTNO,
 		.name = "Real-M200 (KM0)",
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 065e4d47b..0bc139911 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -45,19 +45,20 @@
  */
 enum cortex_m_impl_part {
 	CORTEX_M_PARTNO_INVALID,
-	STAR_MC1_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0x132), /* FIXME - confirm implementor! */
-	CORTEX_M0_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC20),
-	CORTEX_M1_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC21),
-	CORTEX_M3_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC23),
-	CORTEX_M4_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC24),
-	CORTEX_M7_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC27),
-	CORTEX_M0P_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC60),
-	CORTEX_M23_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD20),
-	CORTEX_M33_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD21),
-	CORTEX_M35P_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD31),
-	CORTEX_M55_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD22),
-	REALTEK_M200_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK, 0xd20),
-	REALTEK_M300_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK, 0xd22),
+	STAR_MC1_PARTNO      = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0x132), /* FIXME - confirm implementor! */
+	CORTEX_M0_PARTNO     = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC20),
+	CORTEX_M1_PARTNO     = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC21),
+	CORTEX_M3_PARTNO     = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC23),
+	CORTEX_M4_PARTNO     = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC24),
+	CORTEX_M7_PARTNO     = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC27),
+	CORTEX_M0P_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xC60),
+	CORTEX_M23_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD20),
+	CORTEX_M33_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD21),
+	CORTEX_M35P_PARTNO   = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD31),
+	CORTEX_M55_PARTNO    = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_ARM, 0xD22),
+	INFINEON_SLX2_PARTNO = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_INFINEON, 0xDB0),
+	REALTEK_M200_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK, 0xd20),
+	REALTEK_M300_PARTNO  = ARM_MAKE_CPUID(ARM_IMPLEMENTOR_REALTEK, 0xd22),
 };
 
 /* Relevant Cortex-M flags, used in struct cortex_m_part_info.flags */

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm.h      |  1 +
 src/target/cortex_m.c |  5 +++++
 src/target/cortex_m.h | 27 ++++++++++++++-------------
 3 files changed, 20 insertions(+), 13 deletions(-)


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commit c6ab3abeeecfad4d3f48f8012b531d4172944768
Author: Marek Vrbka <mar...@co...>
Date:   Tue Sep 5 15:25:50 2023 +0200

    image: log error when unknown image type is specified
    
    This patch adds error reporting when unknown image type is specified.
    Previously, OpenOCD replied with an empty string.
    
    Change-Id: I16220b1f5deb3b966a21731f0adf7911a78e8959
    Signed-off-by: Marek Vrbka <mar...@co...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7883
    Tested-by: jenkins
    Reviewed-by: Jan Matyas <jan...@co...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/image.c b/src/target/image.c
index ad2d856b5..e998a35f4 100644
--- a/src/target/image.c
+++ b/src/target/image.c
@@ -96,20 +96,22 @@ static int autodetect_image_type(struct image *image, const char *url)
 static int identify_image_type(struct image *image, const char *type_string, const char *url)
 {
 	if (type_string) {
-		if (!strcmp(type_string, "bin"))
+		if (!strcmp(type_string, "bin")) {
 			image->type = IMAGE_BINARY;
-		else if (!strcmp(type_string, "ihex"))
+		} else if (!strcmp(type_string, "ihex")) {
 			image->type = IMAGE_IHEX;
-		else if (!strcmp(type_string, "elf"))
+		} else if (!strcmp(type_string, "elf")) {
 			image->type = IMAGE_ELF;
-		else if (!strcmp(type_string, "mem"))
+		} else if (!strcmp(type_string, "mem")) {
 			image->type = IMAGE_MEMORY;
-		else if (!strcmp(type_string, "s19"))
+		} else if (!strcmp(type_string, "s19")) {
 			image->type = IMAGE_SRECORD;
-		else if (!strcmp(type_string, "build"))
+		} else if (!strcmp(type_string, "build")) {
 			image->type = IMAGE_BUILDER;
-		else
+		} else {
+			LOG_ERROR("Unknown image type: %s, use one of: bin, ihex, elf, mem, s19, build", type_string);
 			return ERROR_IMAGE_TYPE_UNKNOWN;
+		}
 	} else
 		return autodetect_image_type(image, url);
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/image.c | 16 +++++++++-------
 1 file changed, 9 insertions(+), 7 deletions(-)


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commit 21f17260d438704deb1591777222e542efb8383d
Author: Vincent Fazio <vf...@xe...>
Date:   Wed Sep 6 11:10:41 2023 -0500

    jtag/drivers/bcm2835gpio: fix bcm2835_peri_base output format
    
    Previously, the bcm2835_peri_base value would be printed as a decimal
    value despite having a "0x" prefix, implying it should be a hex value.
    
      BCM2835 GPIO: peripheral_base = 0x1056964608
    
    Now, the value is correctly converted to hexidecimal.
    
      BCM2835 GPIO: peripheral_base = 0x3F000000
    
    Change-Id: Id59185423917e6350f99ef68320e2102a3192291
    Fixes: b41b368255d5 ("jtag/drivers/bcm2835gpio: extend peripheral_base to off_t")
    Signed-off-by: Vincent Fazio <vf...@xe...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7888
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/bcm2835gpio.c b/src/jtag/drivers/bcm2835gpio.c
index f41f7b51e..7fd7f3894 100644
--- a/src/jtag/drivers/bcm2835gpio.c
+++ b/src/jtag/drivers/bcm2835gpio.c
@@ -331,7 +331,7 @@ COMMAND_HANDLER(bcm2835gpio_handle_peripheral_base)
 	}
 
 	tmp_base = bcm2835_peri_base;
-	command_print(CMD, "BCM2835 GPIO: peripheral_base = 0x%08" PRIu64,
+	command_print(CMD, "BCM2835 GPIO: peripheral_base = 0x%08" PRIx64,
 				  tmp_base);
 	return ERROR_OK;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/bcm2835gpio.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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commit 4b1ea8511a7da9d7201df40302e3341c6e97ffdd
Author: Peter Mamonov <pma...@gm...>
Date:   Wed Jun 26 18:43:16 2019 +0300

    tcl/target: add support for Cavium Octeon II CN61xx
    
    Change-Id: Ia14854bc64f5a31b6591be69be4edee9cd1310c3
    Signed-off-by: Peter Mamonov <pma...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/5249
    Reviewed-by: Oleksij Rempel <li...@re...>
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/cavium_cn61xx.cfg b/tcl/target/cavium_cn61xx.cfg
new file mode 100644
index 000000000..60b56a519
--- /dev/null
+++ b/tcl/target/cavium_cn61xx.cfg
@@ -0,0 +1,15 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Cavium Octeon II CN61xx (PrID 0x000D9301)
+
+jtag newtap cpu tap0 -irlen 5
+jtag newtap cpu tap1 -irlen 5
+
+target create cpu.core0 mips_mips64 -chain-position cpu.tap0 -endian big -rtos hwthread -coreid 0
+target create cpu.core1 mips_mips64 -chain-position cpu.tap1 -endian big -rtos hwthread -coreid 1
+target smp cpu.core0 cpu.core1
+
+cpu.core0 configure -work-area-phys 0xffffffffa2000000 -work-area-size 0x20000
+cpu.core1 configure -work-area-phys 0xffffffffa2000000 -work-area-size 0x20000
+
+targets cpu.core0

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/cavium_cn61xx.cfg | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 tcl/target/cavium_cn61xx.cfg


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commit eeee3f41daf2b4668a0c6f75bc621146caa84b77
Author: Peter Mamonov <pma...@gm...>
Date:   Fri Sep 26 14:04:51 2014 +0400

    tcl/target: Add XLP3xx configuration files
    
    The patch adds configuration files for the following XLP 300-series
    processors: XLP304, XLP308, XLP316.
    
    Change-Id: Iaf2b807abf9fc4d7b51222fd40bdb18c6aca7d9c
    Signed-off-by: Aleksey Kuleshov <rn...@ya...>
    Signed-off-by: Peter Mamonov <pma...@gm...>
    CC: Antony Pavlov <ant...@gm...>
    CC: Dongxue Zhang <elt...@gm...>
    CC: Oleksij Rempel <li...@re...>
    CC: Paul Fertser <fer...@gm...>
    CC: Salvador Arroyo <sar...@ya...>
    CC: Spencer Oliver <sp...@sp...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/2323
    Tested-by: jenkins
    Reviewed-by: Oleksij Rempel <li...@re...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/netl_xlp304.cfg b/tcl/target/netl_xlp304.cfg
new file mode 100644
index 000000000..27c30a0d2
--- /dev/null
+++ b/tcl/target/netl_xlp304.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP304 processor by NetLogic Microsystems
+#
+
+set XLP_NT 4
+source [find target/netl_xlp3xx.cfg]
diff --git a/tcl/target/netl_xlp308.cfg b/tcl/target/netl_xlp308.cfg
new file mode 100644
index 000000000..c3ba11e78
--- /dev/null
+++ b/tcl/target/netl_xlp308.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP308 processor by NetLogic Microsystems
+#
+
+set XLP_NT 8
+source [find target/netl_xlp3xx.cfg]
diff --git a/tcl/target/netl_xlp316.cfg b/tcl/target/netl_xlp316.cfg
new file mode 100644
index 000000000..961b67f18
--- /dev/null
+++ b/tcl/target/netl_xlp316.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP316 processor by NetLogic Microsystems
+#
+
+set XLP_NT 16
+source [find target/netl_xlp3xx.cfg]
diff --git a/tcl/target/netl_xlp3xx.cfg b/tcl/target/netl_xlp3xx.cfg
new file mode 100644
index 000000000..2366503cb
--- /dev/null
+++ b/tcl/target/netl_xlp3xx.cfg
@@ -0,0 +1,39 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: XLP 300-series processors by NetLogic Microsystems
+#
+# See http://www.broadcom.com/products/Processors/Enterprise/XLP300-Series
+#
+# Use xlp304.cfg, xlp308.cfg, xlp316.cfg for particular processor model.
+#
+
+transport select jtag
+
+global XLP_NT
+
+for {set i $XLP_NT} {$i > 0} {incr i -1} {
+	jtag newtap xlp cpu_$i -irlen 5 -disable
+	if {$i != 1} {
+		jtag configure xlp.cpu_$i -event tap-enable {}
+	}
+}
+jtag newtap xlp jrc -irlen 16 -expected-id 0x00011449
+
+jtag configure xlp.cpu_1 -event tap-enable {
+	global XLP_NT
+	irscan xlp.jrc 0xe0
+	drscan xlp.jrc 1 1
+	for {set i $XLP_NT} {$i > 1} {incr i -1} {
+		jtag tapenable xlp.cpu_$i
+	}
+}
+
+proc chipreset {} {
+	irscan xlp.jrc 0xab
+	drscan xlp.jrc 1 1
+	drscan xlp.jrc 1 0
+}
+
+jtag configure xlp.jrc -event setup "jtag tapenable xlp.cpu_1"
+
+target create xlp.cpu_1 mips_mips64 -endian big -chain-position xlp.cpu_1

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/netl_xlp304.cfg |  7 +++++++
 tcl/target/netl_xlp308.cfg |  7 +++++++
 tcl/target/netl_xlp316.cfg |  7 +++++++
 tcl/target/netl_xlp3xx.cfg | 39 +++++++++++++++++++++++++++++++++++++++
 4 files changed, 60 insertions(+)
 create mode 100644 tcl/target/netl_xlp304.cfg
 create mode 100644 tcl/target/netl_xlp308.cfg
 create mode 100644 tcl/target/netl_xlp316.cfg
 create mode 100644 tcl/target/netl_xlp3xx.cfg


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commit 5fd4f2954d6673e5b2fd740da681439425794abc
Author: Tomas Vanek <va...@fb...>
Date:   Tue Mar 14 14:31:30 2023 +0100

    target/adi_v5_xxx: use ADIV5_DP_SELECT_APBANK
    
    and DP_SELECT_DPBANK.
    Use the defined symbols instead of magic numbers.
    
    Change-Id: I19c86b183e57e42b96f76eed180c0492cd67bee1
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7539
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 9f66adc68..afdc0e577 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -350,7 +350,7 @@ static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
 {
 	uint8_t out_value_buf[4];
 	int retval;
-	uint64_t sel = (reg_addr >> 4) & 0xf;
+	uint64_t sel = (reg_addr >> 4) & DP_SELECT_DPBANK;
 
 	/* No need to change SELECT or RDBUFF as they are not banked */
 	if (instr == JTAG_DP_DPACC && reg_addr != DP_SELECT && reg_addr != DP_RDBUFF &&
@@ -775,7 +775,7 @@ static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg)
 	}
 
 	/* ADIv5 */
-	sel = (ap->ap_num << 24) | (reg & 0x000000F0);
+	sel = (ap->ap_num << 24) | (reg & ADIV5_DP_SELECT_APBANK);
 
 	if (sel == dap->select)
 		return ERROR_OK;
diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index 5f40588d2..1b743657c 100644
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -523,7 +523,7 @@ static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
 	}
 
 	/* ADIv5 */
-	sel = (ap->ap_num << 24) | (reg & 0x000000F0);
+	sel = (ap->ap_num << 24) | (reg & ADIV5_DP_SELECT_APBANK);
 	if (dap->select != DP_SELECT_INVALID)
 		sel |= dap->select & DP_SELECT_DPBANK;
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/adi_v5_jtag.c | 4 ++--
 src/target/adi_v5_swd.c  | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)


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- Log -----------------------------------------------------------------
commit f49bf1adb42e3ae1b63da5d6e615c6f28b49f42a
Author: Tomas Vanek <va...@fb...>
Date:   Tue Mar 14 13:30:49 2023 +0100

    target/arm_adi_v5,jtag/drivers: rename ADIv5 only defines
    
    DP_SELECT_APSEL and DP_SELECT_APBANK is no more used in ADIv6.
    
    Change-Id: I4176574d46c6dc8eb3fe3aef6daab6e33492c050
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7538
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/rshim.c b/src/jtag/drivers/rshim.c
index 174fa1275..6170e86bd 100644
--- a/src/jtag/drivers/rshim.c
+++ b/src/jtag/drivers/rshim.c
@@ -254,8 +254,8 @@ static int rshim_dp_q_write(struct adiv5_dap *dap, unsigned int reg,
 		dp_ctrl_stat = data;
 		break;
 	case DP_SELECT:
-		ap_sel = (data & DP_SELECT_APSEL) >> 24;
-		ap_bank = (data & DP_SELECT_APBANK) >> 4;
+		ap_sel = (data & ADIV5_DP_SELECT_APSEL) >> 24;
+		ap_bank = (data & ADIV5_DP_SELECT_APBANK) >> 4;
 		break;
 	default:
 		LOG_INFO("Unknown command");
diff --git a/src/jtag/drivers/vdebug.c b/src/jtag/drivers/vdebug.c
index f6d99c6c1..d2311b2ea 100644
--- a/src/jtag/drivers/vdebug.c
+++ b/src/jtag/drivers/vdebug.c
@@ -1098,9 +1098,9 @@ static int vdebug_dap_queue_dp_write(struct adiv5_dap *dap, unsigned int reg, ui
 
 static int vdebug_dap_queue_ap_read(struct adiv5_ap *ap, unsigned int reg, uint32_t *data)
 {
-	if ((reg & DP_SELECT_APBANK) != ap->dap->select) {
-		vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, reg & DP_SELECT_APBANK, VD_ASPACE_DP, 0);
-		ap->dap->select = reg & DP_SELECT_APBANK;
+	if ((reg & ADIV5_DP_SELECT_APBANK) != ap->dap->select) {
+		vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, reg & ADIV5_DP_SELECT_APBANK, VD_ASPACE_DP, 0);
+		ap->dap->select = reg & ADIV5_DP_SELECT_APBANK;
 	}
 
 	vdebug_reg_read(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, NULL, VD_ASPACE_AP, 0);
@@ -1110,9 +1110,9 @@ static int vdebug_dap_queue_ap_read(struct adiv5_ap *ap, unsigned int reg, uint3
 
 static int vdebug_dap_queue_ap_write(struct adiv5_ap *ap, unsigned int reg, uint32_t data)
 {
-	if ((reg & DP_SELECT_APBANK) != ap->dap->select) {
-		vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, reg & DP_SELECT_APBANK, VD_ASPACE_DP, 0);
-		ap->dap->select = reg & DP_SELECT_APBANK;
+	if ((reg & ADIV5_DP_SELECT_APBANK) != ap->dap->select) {
+		vdebug_reg_write(vdc.hsocket, pbuf, DP_SELECT >> 2, reg & ADIV5_DP_SELECT_APBANK, VD_ASPACE_DP, 0);
+		ap->dap->select = reg & ADIV5_DP_SELECT_APBANK;
 	}
 
 	return vdebug_reg_write(vdc.hsocket, pbuf, (reg & DP_SELECT_DPBANK) >> 2, data, VD_ASPACE_AP, 0);
diff --git a/src/target/adi_v5_swd.c b/src/target/adi_v5_swd.c
index 275a50128..5f40588d2 100644
--- a/src/target/adi_v5_swd.c
+++ b/src/target/adi_v5_swd.c
@@ -147,7 +147,7 @@ static int swd_queue_dp_write_inner(struct adiv5_dap *dap, unsigned int reg,
 	swd_finish_read(dap);
 
 	if (reg == DP_SELECT) {
-		dap->select = data & (DP_SELECT_APSEL | DP_SELECT_APBANK | DP_SELECT_DPBANK);
+		dap->select = data & (ADIV5_DP_SELECT_APSEL | ADIV5_DP_SELECT_APBANK | DP_SELECT_DPBANK);
 
 		swd->write_reg(swd_cmd(false, false, reg), data, 0);
 
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 90d28bcf2..e21589363 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -97,16 +97,16 @@
 
 #define DP_DLPIDR_PROTVSN	1u
 
-#define DP_SELECT_APSEL 0xFF000000
-#define DP_SELECT_APBANK 0x000000F0
-#define DP_SELECT_DPBANK 0x0000000F
-#define DP_SELECT_INVALID 0x00FFFF00 /* Reserved bits one */
+#define ADIV5_DP_SELECT_APSEL	0xFF000000
+#define ADIV5_DP_SELECT_APBANK	0x000000F0
+#define DP_SELECT_DPBANK		0x0000000F
+#define DP_SELECT_INVALID		0x00FFFF00 /* Reserved bits one */
 
-#define DP_APSEL_MAX        (255) /* for ADIv5 only */
-#define DP_APSEL_INVALID    0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */
+#define DP_APSEL_MAX			(255) /* Strict limit for ADIv5, number of AP buffers for ADIv6 */
+#define DP_APSEL_INVALID		0xF00 /* more than DP_APSEL_MAX and not ADIv6 aligned 4k */
 
-#define DP_TARGETSEL_INVALID 0xFFFFFFFFU
-#define DP_TARGETSEL_DPID_MASK 0x0FFFFFFFU
+#define DP_TARGETSEL_INVALID	0xFFFFFFFFU
+#define DP_TARGETSEL_DPID_MASK	0x0FFFFFFFU
 #define DP_TARGETSEL_INSTANCEID_MASK 0xF0000000U
 #define DP_TARGETSEL_INSTANCEID_SHIFT 28
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/rshim.c  |  4 ++--
 src/jtag/drivers/vdebug.c | 12 ++++++------
 src/target/adi_v5_swd.c   |  2 +-
 src/target/arm_adi_v5.h   | 16 ++++++++--------
 4 files changed, 17 insertions(+), 17 deletions(-)


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commit eb22a37b42a7944694243b690bfbd736e1ef52e8
Author: Daniel Anselmi <dan...@gm...>
Date:   Sat Dec 17 13:11:30 2022 +0100

    pld: harmonize refresh commands
    
    add refresh command for lattice devices
    rename gowin reprogram to refresh
    rename virtex2 program to refresh
    
    Change-Id: I9da83a614b96da3e947ac4608b0a291b1d126914
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7839
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 7ad48c862..2d59238b8 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8764,8 +8764,8 @@ Change values for boundary scan instructions selecting the registers USER1 to US
 Description of the arguments can be found at command @command{virtex2 set_instr_codes}.
 @end deffn
 
-@deffn {Command} {virtex2 program} pld_name
-Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a. refresh.
+@deffn {Command} {virtex2 refresh} pld_name
+Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a. program.
 @end deffn
 @end deffn
 
@@ -8796,6 +8796,10 @@ for FPGA @var{pld_name} with value @var{val}.
 Set the length of the register for the preload. This is needed when the JTAG ID of the device is not known by openocd (newer NX devices).
 The load command for the FPGA @var{pld_name} will use a length for the preload of @var{length}.
 @end deffn
+
+@deffn {Command} {lattice refresh} pld_name
+Load the bitstream from external memory for FPGA @var{pld_name}. A.k.a program.
+@end deffn
 @end deffn
 
 
@@ -8850,9 +8854,9 @@ Reads and displays the user register
 for FPGA @var{pld_name}.
 @end deffn
 
-@deffn {Command} {gowin reload} pld_name
+@deffn {Command} {gowin refresh} pld_name
 Load the bitstream from external memory for
-FPGA @var{pld_name}. A.k.a. refresh.
+FPGA @var{pld_name}. A.k.a. reload.
 @end deffn
 @end deffn
 
diff --git a/src/pld/certus.c b/src/pld/certus.c
index 8bfdff495..a49501f54 100644
--- a/src/pld/certus.c
+++ b/src/pld/certus.c
@@ -304,3 +304,27 @@ int lattice_certus_get_facing_read_bits(struct lattice_pld_device *pld_device_in
 
 	return ERROR_OK;
 }
+
+int lattice_certus_refresh(struct lattice_pld_device *lattice_device)
+{
+	struct jtag_tap *tap = lattice_device->tap;
+	if (!tap)
+		return ERROR_FAIL;
+
+	int retval = lattice_preload(lattice_device);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = lattice_set_instr(tap, LSC_REFRESH, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	jtag_add_runtest(2, TAP_IDLE);
+	jtag_add_sleep(200000);
+	retval = lattice_set_instr(tap, BYPASS, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	jtag_add_runtest(100, TAP_IDLE);
+	jtag_add_sleep(1000);
+
+	return jtag_execute_queue();
+}
diff --git a/src/pld/certus.h b/src/pld/certus.h
index d21ad61d2..0fbfdef45 100644
--- a/src/pld/certus.h
+++ b/src/pld/certus.h
@@ -17,5 +17,6 @@ int lattice_certus_load(struct lattice_pld_device *lattice_device, struct lattic
 int lattice_certus_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info);
 int lattice_certus_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info);
 int lattice_certus_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits);
+int lattice_certus_refresh(struct lattice_pld_device *lattice_device);
 
 #endif /* OPENOCD_PLD_CERTUS_H */
diff --git a/src/pld/ecp2_3.c b/src/pld/ecp2_3.c
index a7b7580c7..5dfea9a27 100644
--- a/src/pld/ecp2_3.c
+++ b/src/pld/ecp2_3.c
@@ -304,3 +304,14 @@ int lattice_ecp2_3_get_facing_read_bits(struct lattice_pld_device *pld_device_in
 
 	return ERROR_OK;
 }
+
+int lattice_ecp2_3_refresh(struct lattice_pld_device *lattice_device)
+{
+	if (!lattice_device || !lattice_device->tap)
+		return ERROR_FAIL;
+
+	int retval = lattice_set_instr(lattice_device->tap, LSCC_REFRESH, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	return jtag_execute_queue();
+}
diff --git a/src/pld/ecp2_3.h b/src/pld/ecp2_3.h
index c5dec5693..d3f7464e1 100644
--- a/src/pld/ecp2_3.h
+++ b/src/pld/ecp2_3.h
@@ -18,5 +18,6 @@ int lattice_ecp3_load(struct lattice_pld_device *lattice_device, struct lattice_
 int lattice_ecp2_3_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info);
 int lattice_ecp2_3_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info);
 int lattice_ecp2_3_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits);
+int lattice_ecp2_3_refresh(struct lattice_pld_device *lattice_device);
 
 #endif /* OPENOCD_PLD_ECP2_3_H */
diff --git a/src/pld/ecp5.c b/src/pld/ecp5.c
index 024fe2b4a..f8ba33eaf 100644
--- a/src/pld/ecp5.c
+++ b/src/pld/ecp5.c
@@ -276,3 +276,27 @@ int lattice_ecp5_get_facing_read_bits(struct lattice_pld_device *pld_device_info
 
 	return ERROR_OK;
 }
+
+int lattice_ecp5_refresh(struct lattice_pld_device *lattice_device)
+{
+	struct jtag_tap *tap = lattice_device->tap;
+	if (!tap)
+		return ERROR_FAIL;
+
+	int retval = lattice_preload(lattice_device);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = lattice_set_instr(tap, LSC_REFRESH, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	jtag_add_runtest(2, TAP_IDLE);
+	jtag_add_sleep(200000);
+	retval = lattice_set_instr(tap, BYPASS, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	jtag_add_runtest(100, TAP_IDLE);
+	jtag_add_sleep(1000);
+
+	return jtag_execute_queue();
+}
diff --git a/src/pld/ecp5.h b/src/pld/ecp5.h
index daf481fa6..975678ece 100644
--- a/src/pld/ecp5.h
+++ b/src/pld/ecp5.h
@@ -17,5 +17,6 @@ int lattice_ecp5_load(struct lattice_pld_device *lattice_device, struct lattice_
 int lattice_ecp5_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info);
 int lattice_ecp5_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info);
 int lattice_ecp5_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits);
+int lattice_ecp5_refresh(struct lattice_pld_device *lattice_device);
 
 #endif /* OPENOCD_PLD_ECP5_H */
diff --git a/src/pld/gowin.c b/src/pld/gowin.c
index c42b2f22c..bbc2fe15f 100644
--- a/src/pld/gowin.c
+++ b/src/pld/gowin.c
@@ -543,10 +543,10 @@ static const struct command_registration gowin_exec_command_handlers[] = {
 		.help = "reading user register from FPGA",
 		.usage = "pld_name",
 	}, {
-		.name = "reload",
+		.name = "refresh",
 		.mode = COMMAND_EXEC,
 		.handler = gowin_reload_command_handler,
-		.help = "reloading bitstream from flash to SRAM",
+		.help = "reload bitstream from flash to SRAM",
 		.usage = "pld_name",
 	},
 	COMMAND_REGISTRATION_DONE
diff --git a/src/pld/lattice.c b/src/pld/lattice.c
index 4858603a8..cd72d3cb5 100644
--- a/src/pld/lattice.c
+++ b/src/pld/lattice.c
@@ -575,6 +575,35 @@ COMMAND_HANDLER(lattice_read_status_command_handler)
 	return retval;
 }
 
+COMMAND_HANDLER(lattice_refresh_command_handler)
+{
+	if (CMD_ARGC != 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	struct pld_device *device = get_pld_device_by_name_or_numstr(CMD_ARGV[0]);
+	if (!device) {
+		command_print(CMD, "pld device '#%s' is out of bounds or unknown", CMD_ARGV[0]);
+		return ERROR_FAIL;
+	}
+
+	struct lattice_pld_device *lattice_device = device->driver_priv;
+	if (!lattice_device)
+		return ERROR_FAIL;
+
+	int retval = lattice_check_device_family(lattice_device);
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (lattice_device->family == LATTICE_ECP2 || lattice_device->family == LATTICE_ECP3)
+		return lattice_ecp2_3_refresh(lattice_device);
+	else if (lattice_device->family == LATTICE_ECP5)
+		return lattice_ecp5_refresh(lattice_device);
+	else if (lattice_device->family == LATTICE_CERTUS)
+		return lattice_certus_refresh(lattice_device);
+
+	return ERROR_FAIL;
+}
+
 static const struct command_registration lattice_exec_command_handlers[] = {
 	{
 		.name = "read_status",
@@ -600,6 +629,12 @@ static const struct command_registration lattice_exec_command_handlers[] = {
 		.handler = lattice_set_preload_command_handler,
 		.help = "set length for preload (device specific)",
 		.usage = "pld_name value",
+	}, {
+		.name = "refresh",
+		.mode = COMMAND_EXEC,
+		.handler = lattice_refresh_command_handler,
+		.help = "refresh from configuration memory",
+		.usage = "pld_name",
 	},
 	COMMAND_REGISTRATION_DONE
 };
diff --git a/src/pld/lattice_cmd.h b/src/pld/lattice_cmd.h
index 389b7afe4..0c1062583 100644
--- a/src/pld/lattice_cmd.h
+++ b/src/pld/lattice_cmd.h
@@ -13,6 +13,7 @@
 #define PROGRAM_SPI          0x3A
 #define LSC_READ_STATUS      0x3C
 #define LSC_INIT_ADDRESS     0x46
+#define LSC_REFRESH          0x79
 #define LSC_BITSTREAM_BURST  0x7A
 #define READ_USERCODE        0xC0
 #define ISC_ENABLE           0xC6
diff --git a/src/pld/virtex2.c b/src/pld/virtex2.c
index fce764c1a..3dff90621 100644
--- a/src/pld/virtex2.c
+++ b/src/pld/virtex2.c
@@ -265,7 +265,7 @@ static int virtex2_load(struct pld_device *pld_device, const char *filename)
 	return retval;
 }
 
-COMMAND_HANDLER(virtex2_handle_program_command)
+COMMAND_HANDLER(virtex2_handle_refresh_command)
 {
 	struct pld_device *device;
 
@@ -449,10 +449,10 @@ static const struct command_registration virtex2_exec_command_handlers[] = {
 		.help = "set instructions codes used for jtag-hub",
 		.usage = "pld_name user1 [user2 [user3 [user4]]]",
 	}, {
-		.name = "program",
+		.name = "refresh",
 		.mode = COMMAND_EXEC,
-		.handler = virtex2_handle_program_command,
-		.help = "start loading of configuration (refresh)",
+		.handler = virtex2_handle_refresh_command,
+		.help = "start loading of configuration (program)",
 		.usage = "pld_name",
 	},
 	COMMAND_REGISTRATION_DONE

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi      | 12 ++++++++----
 src/pld/certus.c      | 24 ++++++++++++++++++++++++
 src/pld/certus.h      |  1 +
 src/pld/ecp2_3.c      | 11 +++++++++++
 src/pld/ecp2_3.h      |  1 +
 src/pld/ecp5.c        | 24 ++++++++++++++++++++++++
 src/pld/ecp5.h        |  1 +
 src/pld/gowin.c       |  4 ++--
 src/pld/lattice.c     | 35 +++++++++++++++++++++++++++++++++++
 src/pld/lattice_cmd.h |  1 +
 src/pld/virtex2.c     |  8 ++++----
 11 files changed, 112 insertions(+), 10 deletions(-)


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- Log -----------------------------------------------------------------
commit 198a914cf99a8602a05227ac5327a805714e4b87
Author: Daniel Anselmi <dan...@gm...>
Date:   Sat Dec 17 13:11:30 2022 +0100

    jtagspi/pld: add support from gatemate driver
    
    Provide jtagspi with specific procedures to be able to
    use jtagspi for programming spi-flash devices on cologne
    chip gatemate devices.
    
    Change-Id: Ifa1c4ca6e215d7f49bd21620898991af213812e9
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7838
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/pld/gatemate.c b/src/pld/gatemate.c
index 4ad2665c6..f35b39ad2 100644
--- a/src/pld/gatemate.c
+++ b/src/pld/gatemate.c
@@ -15,6 +15,8 @@
 #include "raw_bit.h"
 
 #define JTAG_CONFIGURE  0x06
+#define JTAG_SPI_BYPASS 0x05
+#define BYPASS          0x3F
 
 struct gatemate_pld_device {
 	struct jtag_tap *tap;
@@ -209,6 +211,66 @@ static int gatemate_load(struct pld_device *pld_device, const char *filename)
 	return retval;
 }
 
+static int gatemate_has_jtagspi_instruction(struct pld_device *device, bool *has_instruction)
+{
+	*has_instruction = true;
+	return ERROR_OK;
+}
+
+static int gatemate_connect_spi_to_jtag(struct pld_device *pld_device)
+{
+	if (!pld_device)
+		return ERROR_FAIL;
+
+	struct gatemate_pld_device *pld_device_info = pld_device->driver_priv;
+	if (!pld_device_info)
+		return ERROR_FAIL;
+
+	struct jtag_tap *tap = pld_device_info->tap;
+	if (!tap)
+		return ERROR_FAIL;
+
+	if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) == JTAG_SPI_BYPASS)
+		return ERROR_OK;
+
+	gatemate_set_instr(tap, JTAG_SPI_BYPASS);
+
+	return jtag_execute_queue();
+}
+
+static int gatemate_disconnect_spi_from_jtag(struct pld_device *pld_device)
+{
+	if (!pld_device)
+		return ERROR_FAIL;
+
+	struct gatemate_pld_device *pld_device_info = pld_device->driver_priv;
+	if (!pld_device_info)
+		return ERROR_FAIL;
+
+	struct jtag_tap *tap = pld_device_info->tap;
+	if (!tap)
+		return ERROR_FAIL;
+
+	if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != JTAG_SPI_BYPASS)
+		return ERROR_OK;
+
+	gatemate_set_instr(tap, BYPASS);
+
+	return jtag_execute_queue();
+}
+
+static int gatemate_get_stuff_bits(struct pld_device *pld_device, unsigned int *facing_read_bits,
+									unsigned int *trailing_write_bits)
+{
+	if (!pld_device)
+		return ERROR_FAIL;
+
+	*facing_read_bits = 1;
+	*trailing_write_bits = 1;
+
+	return ERROR_OK;
+}
+
 PLD_CREATE_COMMAND_HANDLER(gatemate_pld_create_command)
 {
 	if (CMD_ARGC != 4)
@@ -239,4 +301,8 @@ struct pld_driver gatemate_pld = {
 	.name = "gatemate",
 	.pld_create_command = &gatemate_pld_create_command,
 	.load = &gatemate_load,
+	.has_jtagspi_instruction = gatemate_has_jtagspi_instruction,
+	.connect_spi_to_jtag = gatemate_connect_spi_to_jtag,
+	.disconnect_spi_from_jtag = gatemate_disconnect_spi_from_jtag,
+	.get_stuff_bits = gatemate_get_stuff_bits,
 };
diff --git a/tcl/board/gatemate_eval.cfg b/tcl/board/gatemate_eval.cfg
index cc078a0e3..c4d3f3dfd 100644
--- a/tcl/board/gatemate_eval.cfg
+++ b/tcl/board/gatemate_eval.cfg
@@ -14,3 +14,9 @@ transport select jtag
 adapter speed 6000
 
 source [find fpga/gatemate.cfg]
+
+set JTAGSPI_CHAIN_ID gatemate.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init gatemate.pld "" -1
+#jtagspi_program workspace/blink/blink_slow.cfg.bit 0

-----------------------------------------------------------------------

Summary of changes:
 src/pld/gatemate.c          | 66 +++++++++++++++++++++++++++++++++++++++++++++
 tcl/board/gatemate_eval.cfg |  6 +++++
 2 files changed, 72 insertions(+)


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- Log -----------------------------------------------------------------
commit b86726b5a5bb1d2689a786b3294e8617867d5ef4
Author: Daniel Anselmi <dan...@gm...>
Date:   Sat Dec 17 13:11:30 2022 +0100

    jtagspi/pld: add support from intel driver
    
    Provide jtagspi with information to use jtagspi for
    programming spi-flash devices on intel devices using
    a proxy bitstream.
    
    Change-Id: Ib947b8c0dd61e2c6fa8beeb30074606131b1480f
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7837
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/pld/intel.c b/src/pld/intel.c
index ee3097391..8422c94c4 100644
--- a/src/pld/intel.c
+++ b/src/pld/intel.c
@@ -362,6 +362,12 @@ static int intel_get_ipdbg_hub(int user_num, struct pld_device *pld_device, stru
 	return ERROR_OK;
 }
 
+static int intel_get_jtagspi_userircode(struct pld_device *pld_device, unsigned int *ir)
+{
+	*ir = USER1;
+	return ERROR_OK;
+}
+
 COMMAND_HANDLER(intel_set_bscan_command_handler)
 {
 	unsigned int boundary_scan_length;
@@ -412,7 +418,6 @@ COMMAND_HANDLER(intel_set_check_pos_command_handler)
 	return ERROR_OK;
 }
 
-
 PLD_CREATE_COMMAND_HANDLER(intel_pld_create_command)
 {
 	if (CMD_ARGC != 4 && CMD_ARGC != 6)
@@ -498,4 +503,5 @@ struct pld_driver intel_pld = {
 	.pld_create_command = &intel_pld_create_command,
 	.load = &intel_load,
 	.get_ipdbg_hub = intel_get_ipdbg_hub,
+	.get_jtagspi_userircode = intel_get_jtagspi_userircode,
 };
diff --git a/tcl/board/bemicro_cycloneiii.cfg b/tcl/board/bemicro_cycloneiii.cfg
index 95dd394fd..bd1459adc 100644
--- a/tcl/board/bemicro_cycloneiii.cfg
+++ b/tcl/board/bemicro_cycloneiii.cfg
@@ -16,5 +16,9 @@ source [find fpga/altera-cycloneiii.cfg]
 
 #quartus_cpf --option=bitstream_compression=off -c output_files\cycloneiii_blinker.sof cycloneiii_blinker.rbf
 
-#openocd -f board/bemicro_cycloneiii.cfg -c "init" -c "pld load 0 cycloneiii_blinker.rbf"
+#openocd -f board/bemicro_cycloneiii.cfg -c "init" -c "pld load cycloneiii.pld cycloneiii_blinker.rbf"
 # "ipdbg -start -tap cycloneiii.tap -hub 0x00e -tool 0 -port 5555"
+
+
+set JTAGSPI_CHAIN_ID cycloneiii.pld
+source [find cpld/jtagspi.cfg]

-----------------------------------------------------------------------

Summary of changes:
 src/pld/intel.c                  | 8 +++++++-
 tcl/board/bemicro_cycloneiii.cfg | 6 +++++-
 2 files changed, 12 insertions(+), 2 deletions(-)


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commit 2d4fd58fca2afe32138ea66afbc458471c67046a
Author: Daniel Anselmi <dan...@gm...>
Date:   Sat Dec 17 13:11:30 2022 +0100

    jtagspi/pld: add support from xilinx driver
    
    Provide jtagspi with information to use jtagspi for
    programming spi-flash devices on xilinx devices
    using a proxy bitstream.
    
    Change-Id: I68000d71de25118ed8a8603e544cff1dc69bd9ba
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7836
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/pld/virtex2.c b/src/pld/virtex2.c
index 9b4a0979f..fce764c1a 100644
--- a/src/pld/virtex2.c
+++ b/src/pld/virtex2.c
@@ -326,6 +326,21 @@ static int xilinx_get_ipdbg_hub(int user_num, struct pld_device *pld_device, str
 	return ERROR_OK;
 }
 
+static int xilinx_get_jtagspi_userircode(struct pld_device *pld_device, unsigned int *ir)
+{
+	if (!pld_device || !pld_device->driver_priv)
+		return ERROR_FAIL;
+	struct virtex2_pld_device *pld_device_info = pld_device->driver_priv;
+
+	if (pld_device_info->command_set.num_user < 1) {
+		LOG_ERROR("code for command 'select user1' is unknown");
+		return ERROR_FAIL;
+	}
+
+	*ir = pld_device_info->command_set.user[0];
+	return ERROR_OK;
+}
+
 COMMAND_HANDLER(virtex2_handle_set_instuction_codes_command)
 {
 	if (CMD_ARGC < 6 || CMD_ARGC > (6 + VIRTEX2_MAX_USER_INSTRUCTIONS))
@@ -460,4 +475,5 @@ struct pld_driver virtex2_pld = {
 	.pld_create_command = &virtex2_pld_create_command,
 	.load = &virtex2_load,
 	.get_ipdbg_hub = xilinx_get_ipdbg_hub,
+	.get_jtagspi_userircode = xilinx_get_jtagspi_userircode,
 };
diff --git a/tcl/board/digilent_cmod_s7.cfg b/tcl/board/digilent_cmod_s7.cfg
new file mode 100644
index 000000000..c52ee9505
--- /dev/null
+++ b/tcl/board/digilent_cmod_s7.cfg
@@ -0,0 +1,25 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# digilent CMOD S7
+# https://digilent.com/reference/programmable-logic/cmod-s7/reference-manual
+
+
+adapter driver ftdi
+ftdi channel 0
+ftdi layout_init 0x0008 0x008b
+ftdi vid_pid 0x0403 0x6010
+reset_config none
+transport select jtag
+
+adapter speed 10000
+
+source [find cpld/xilinx-xc7.cfg]
+
+# "ipdbg -start -tap xc7.tap -hub 0x02 -tool 0 -port 5555"
+#openocd -f board/digilent_cmod_s7.cfg -c "init" -c "pld load xc7.pld shared_folder/cmod_s7_fast.bit"
+
+set JTAGSPI_CHAIN_ID xc7.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init xc7.pld "shared_folder/bscan_spi_xc7s25.bit" 0xab
+#jtagspi_program shared_folder/cmod_s7_fast.bit 0

-----------------------------------------------------------------------

Summary of changes:
 src/pld/virtex2.c              | 16 ++++++++++++++++
 tcl/board/digilent_cmod_s7.cfg | 25 +++++++++++++++++++++++++
 2 files changed, 41 insertions(+)
 create mode 100644 tcl/board/digilent_cmod_s7.cfg


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- Log -----------------------------------------------------------------
commit b2a22943e1d76b549c5ff5e84b95658abbd89a69
Author: Daniel Anselmi <dan...@gm...>
Date:   Sat Dec 17 13:11:30 2022 +0100

    jtagspi/pld: add support from efinix driver
    
    Provide jtagspi with information to use jtagspi for
    programming spi-flash devices on efinix trion and
    titanium devices using a proxy bitstream.
    
    Change-Id: I4a851fcaafe832c35bd7b825d95a3d08e4d57a7b
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7826
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/pld/efinix.c b/src/pld/efinix.c
index 8350cb1a2..b6e5f9e47 100644
--- a/src/pld/efinix.c
+++ b/src/pld/efinix.c
@@ -249,6 +249,12 @@ static int efinix_get_ipdbg_hub(int user_num, struct pld_device *pld_device, str
 	return ERROR_OK;
 }
 
+static int efinix_get_jtagspi_userircode(struct pld_device *pld_device, unsigned int *ir)
+{
+	*ir = USER1;
+	return ERROR_OK;
+}
+
 PLD_CREATE_COMMAND_HANDLER(efinix_pld_create_command)
 {
 	if (CMD_ARGC != 4 && CMD_ARGC != 6)
@@ -296,4 +302,5 @@ struct pld_driver efinix_pld = {
 	.pld_create_command = &efinix_pld_create_command,
 	.load = &efinix_load,
 	.get_ipdbg_hub = efinix_get_ipdbg_hub,
+	.get_jtagspi_userircode = efinix_get_jtagspi_userircode,
 };
diff --git a/tcl/board/trion_t20_bga256.cfg b/tcl/board/trion_t20_bga256.cfg
index 045d63de3..dc76d3910 100644
--- a/tcl/board/trion_t20_bga256.cfg
+++ b/tcl/board/trion_t20_bga256.cfg
@@ -19,6 +19,11 @@ adapter speed 6000
 
 source [find fpga/efinix_trion.cfg]
 
-#openocd -f board/trion_t20_bga256.cfg -c "init" -c "pld load 0 outflow/trion_blinker.bit"
+#openocd -f board/trion_t20_bga256.cfg -c "init" -c "pld load trion.pld outflow/trion_blinker.bit"
 #ipdbg -start -tap trion.tap -hub 0x8 -port 5555 -tool 0
 
+set JTAGSPI_CHAIN_ID trion.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init trion.pld "trion_jtagspi/outflow/trion_jtagspi.bit" 0xAB
+#jtagspi_program trion_blinker/outflow/trion_blinker.bin 0

commit 302027094bfa9f331f5de2d25ecea01bac68a58a
Author: Daniel Anselmi <dan...@gm...>
Date:   Sat Dec 17 13:11:30 2022 +0100

    jtagspi/pld: add support from lattice certus driver
    
    Provide jtagspi with specific procedures to be able to
    use jtagspi for programming spi-flash devices on lattice
    certus and certus po devices.
    
    Change-Id: I6a8ec16be78f86073a4ef5302f6241185b08e1c6
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7825
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/pld/certus.c b/src/pld/certus.c
index 1309c1b27..8bfdff495 100644
--- a/src/pld/certus.c
+++ b/src/pld/certus.c
@@ -231,3 +231,76 @@ int lattice_certus_load(struct lattice_pld_device *lattice_device, struct lattic
 
 	return lattice_certus_exit_programming_mode(tap);
 }
+
+int lattice_certus_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info)
+{
+	if (!pld_device_info)
+		return ERROR_FAIL;
+
+	struct jtag_tap *tap = pld_device_info->tap;
+	if (!tap)
+		return ERROR_FAIL;
+
+	if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) == PROGRAM_SPI)
+		return ERROR_OK;
+
+	// erase configuration
+	int retval = lattice_preload(pld_device_info);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = lattice_certus_enable_programming(tap);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = lattice_certus_erase_device(pld_device_info);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("erasing device failed");
+		return retval;
+	}
+
+	retval = lattice_certus_exit_programming_mode(tap);
+	if (retval != ERROR_OK)
+		return retval;
+
+	// connect jtag to spi pins
+	retval = lattice_set_instr(tap, PROGRAM_SPI, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+
+	struct scan_field field;
+	uint8_t buffer[2] = {0xfe, 0x68};
+	field.num_bits = 16;
+	field.out_value = buffer;
+	field.in_value = NULL;
+	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
+
+	return jtag_execute_queue();
+}
+
+int lattice_certus_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info)
+{
+	if (!pld_device_info)
+		return ERROR_FAIL;
+
+	struct jtag_tap *tap = pld_device_info->tap;
+	if (!tap)
+		return ERROR_FAIL;
+
+	/* Connecting it again takes way too long to do it multiple times for writing
+	   a bitstream (ca. 0.4s each access).
+	   We just leave it connected since SCS will not be active when not in shift_dr state.
+	   So there is no need to change instruction, just make sure we are not in shift dr state. */
+	jtag_add_runtest(2, TAP_IDLE);
+	return jtag_execute_queue();
+}
+
+int lattice_certus_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits)
+{
+	if (!pld_device_info)
+		return ERROR_FAIL;
+
+	*facing_read_bits = 0;
+
+	return ERROR_OK;
+}
diff --git a/src/pld/certus.h b/src/pld/certus.h
index 51defc5ca..d21ad61d2 100644
--- a/src/pld/certus.h
+++ b/src/pld/certus.h
@@ -14,5 +14,8 @@ int lattice_certus_read_status(struct jtag_tap *tap, uint64_t *status, uint64_t
 int lattice_certus_read_usercode(struct jtag_tap *tap, uint32_t *usercode, uint32_t out);
 int lattice_certus_write_usercode(struct lattice_pld_device *lattice_device, uint32_t usercode);
 int lattice_certus_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file);
+int lattice_certus_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info);
+int lattice_certus_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info);
+int lattice_certus_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits);
 
 #endif /* OPENOCD_PLD_CERTUS_H */
diff --git a/src/pld/lattice.c b/src/pld/lattice.c
index 14dbf2ae7..4858603a8 100644
--- a/src/pld/lattice.c
+++ b/src/pld/lattice.c
@@ -357,6 +357,8 @@ static int lattice_connect_spi_to_jtag(struct pld_device *pld_device)
 		return lattice_ecp2_3_connect_spi_to_jtag(pld_device_info);
 	else if (pld_device_info->family == LATTICE_ECP5)
 		return lattice_ecp5_connect_spi_to_jtag(pld_device_info);
+	else if (pld_device_info->family == LATTICE_CERTUS)
+		return lattice_certus_connect_spi_to_jtag(pld_device_info);
 
 	return ERROR_FAIL;
 }
@@ -376,6 +378,8 @@ static int lattice_disconnect_spi_from_jtag(struct pld_device *pld_device)
 		return lattice_ecp2_3_disconnect_spi_from_jtag(pld_device_info);
 	else if (pld_device_info->family == LATTICE_ECP5)
 		return lattice_ecp5_disconnect_spi_from_jtag(pld_device_info);
+	else if (pld_device_info->family == LATTICE_CERTUS)
+		return lattice_certus_disconnect_spi_from_jtag(pld_device_info);
 
 	return ERROR_FAIL;
 }
@@ -396,6 +400,8 @@ static int lattice_get_stuff_bits(struct pld_device *pld_device, unsigned int *f
 		return lattice_ecp2_3_get_facing_read_bits(pld_device_info, facing_read_bits);
 	else if (pld_device_info->family == LATTICE_ECP5)
 		return lattice_ecp5_get_facing_read_bits(pld_device_info, facing_read_bits);
+	else if (pld_device_info->family == LATTICE_CERTUS)
+		return lattice_certus_get_facing_read_bits(pld_device_info, facing_read_bits);
 
 	return ERROR_FAIL;
 }
diff --git a/tcl/board/certuspro_evaluation.cfg b/tcl/board/certuspro_evaluation.cfg
index 5ff2a1e32..ba2f17c22 100644
--- a/tcl/board/certuspro_evaluation.cfg
+++ b/tcl/board/certuspro_evaluation.cfg
@@ -12,3 +12,11 @@ transport select jtag
 adapter speed 10000
 
 source [find fpga/lattice_certuspro.cfg]
+
+#openocd -f board/certuspro_evaluation.cfg -c "init" -c "pld load certuspro.pld shared_folder/certuspro_blinker_impl_1.bit"
+
+set JTAGSPI_CHAIN_ID certuspro.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init certuspro.pld "" -1
+#jtagspi_program shared_folder/certuspro_blinker_impl1.bit 0

-----------------------------------------------------------------------

Summary of changes:
 src/pld/certus.c                   | 73 ++++++++++++++++++++++++++++++++++++++
 src/pld/certus.h                   |  3 ++
 src/pld/efinix.c                   |  7 ++++
 src/pld/lattice.c                  |  6 ++++
 tcl/board/certuspro_evaluation.cfg |  8 +++++
 tcl/board/trion_t20_bga256.cfg     |  7 +++-
 6 files changed, 103 insertions(+), 1 deletion(-)


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- Log -----------------------------------------------------------------
commit 536f2a9f2a7754d7975e2618bc19fcbc03e44f54
Author: Daniel Anselmi <dan...@gm...>
Date:   Sat Dec 17 13:11:30 2022 +0100

    jtagspi/pld: add support from lattice ecp5 driver
    
    Provide jtagspi with specific procedures to be able to
    use jtagspi for programming spi-flash devices on lattice
    ecp5 devices.
    
    Change-Id: I4a4a60f21d7e8685a5b8320b9c6ebdc2693bbd21
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7824
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/pld/ecp5.c b/src/pld/ecp5.c
index 2e1009baa..024fe2b4a 100644
--- a/src/pld/ecp5.c
+++ b/src/pld/ecp5.c
@@ -205,3 +205,74 @@ int lattice_ecp5_load(struct lattice_pld_device *lattice_device, struct lattice_
 	const uint32_t mask3 = STATUS_DONE_BIT | STATUS_FAIL_FLAG;
 	return lattice_verify_status_register_u32(lattice_device, out, expected2, mask3, false);
 }
+
+int lattice_ecp5_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info)
+{
+	if (!pld_device_info)
+		return ERROR_FAIL;
+
+	struct jtag_tap *tap = pld_device_info->tap;
+	if (!tap)
+		return ERROR_FAIL;
+
+	if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) == PROGRAM_SPI)
+		return ERROR_OK;
+
+	// erase configuration
+	int retval = lattice_preload(pld_device_info);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = lattice_ecp5_enable_sram_programming(tap);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = lattice_ecp5_erase_sram(tap);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = lattice_ecp5_exit_programming_mode(tap);
+	if (retval != ERROR_OK)
+		return retval;
+
+	// connect jtag to spi pins
+	retval = lattice_set_instr(tap, PROGRAM_SPI, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+
+	struct scan_field field;
+	uint8_t buffer[2] = {0xfe, 0x68};
+	field.num_bits = 16;
+	field.out_value = buffer;
+	field.in_value = NULL;
+	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
+
+	return jtag_execute_queue();
+}
+
+int lattice_ecp5_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info)
+{
+	if (!pld_device_info)
+		return ERROR_FAIL;
+
+	struct jtag_tap *tap = pld_device_info->tap;
+	if (!tap)
+		return ERROR_FAIL;
+
+	/* Connecting it again takes way too long to do it multiple times for writing
+	   a bitstream (ca. 0.4s each access).
+	   We just leave it connected since SCS will not be active when not in shift_dr state.
+	   So there is no need to change instruction, just make sure we are not in shift dr state. */
+	jtag_add_runtest(2, TAP_IDLE);
+	return jtag_execute_queue();
+}
+
+int lattice_ecp5_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits)
+{
+	if (!pld_device_info)
+		return ERROR_FAIL;
+
+	*facing_read_bits = 0;
+
+	return ERROR_OK;
+}
diff --git a/src/pld/ecp5.h b/src/pld/ecp5.h
index 7b0c86b4a..daf481fa6 100644
--- a/src/pld/ecp5.h
+++ b/src/pld/ecp5.h
@@ -14,5 +14,8 @@ int lattice_ecp5_read_status(struct jtag_tap *tap, uint32_t *status, uint32_t ou
 int lattice_ecp5_read_usercode(struct jtag_tap *tap, uint32_t *usercode, uint32_t out);
 int lattice_ecp5_write_usercode(struct lattice_pld_device *lattice_device, uint32_t usercode);
 int lattice_ecp5_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file);
+int lattice_ecp5_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info);
+int lattice_ecp5_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info);
+int lattice_ecp5_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits);
 
 #endif /* OPENOCD_PLD_ECP5_H */
diff --git a/src/pld/lattice.c b/src/pld/lattice.c
index 4085ec194..14dbf2ae7 100644
--- a/src/pld/lattice.c
+++ b/src/pld/lattice.c
@@ -355,6 +355,8 @@ static int lattice_connect_spi_to_jtag(struct pld_device *pld_device)
 
 	if (pld_device_info->family == LATTICE_ECP2 || pld_device_info->family == LATTICE_ECP3)
 		return lattice_ecp2_3_connect_spi_to_jtag(pld_device_info);
+	else if (pld_device_info->family == LATTICE_ECP5)
+		return lattice_ecp5_connect_spi_to_jtag(pld_device_info);
 
 	return ERROR_FAIL;
 }
@@ -372,6 +374,8 @@ static int lattice_disconnect_spi_from_jtag(struct pld_device *pld_device)
 
 	if (pld_device_info->family == LATTICE_ECP2 || pld_device_info->family == LATTICE_ECP3)
 		return lattice_ecp2_3_disconnect_spi_from_jtag(pld_device_info);
+	else if (pld_device_info->family == LATTICE_ECP5)
+		return lattice_ecp5_disconnect_spi_from_jtag(pld_device_info);
 
 	return ERROR_FAIL;
 }
@@ -390,6 +394,8 @@ static int lattice_get_stuff_bits(struct pld_device *pld_device, unsigned int *f
 
 	if (pld_device_info->family == LATTICE_ECP2 || pld_device_info->family == LATTICE_ECP3)
 		return lattice_ecp2_3_get_facing_read_bits(pld_device_info, facing_read_bits);
+	else if (pld_device_info->family == LATTICE_ECP5)
+		return lattice_ecp5_get_facing_read_bits(pld_device_info, facing_read_bits);
 
 	return ERROR_FAIL;
 }
diff --git a/src/pld/lattice_cmd.h b/src/pld/lattice_cmd.h
index 8d66ac4c4..389b7afe4 100644
--- a/src/pld/lattice_cmd.h
+++ b/src/pld/lattice_cmd.h
@@ -10,6 +10,7 @@
 
 #define ISC_ERASE            0x0E
 #define ISC_DISABLE          0x26
+#define PROGRAM_SPI          0x3A
 #define LSC_READ_STATUS      0x3C
 #define LSC_INIT_ADDRESS     0x46
 #define LSC_BITSTREAM_BURST  0x7A
diff --git a/tcl/board/ecp5_evaluation.cfg b/tcl/board/ecp5_evaluation.cfg
index 427037b71..dd663f79d 100644
--- a/tcl/board/ecp5_evaluation.cfg
+++ b/tcl/board/ecp5_evaluation.cfg
@@ -15,5 +15,11 @@ adapter speed 6000
 
 source [find fpga/lattice_ecp5.cfg]
 
-#openocd -f board/ecp5_evaluation.cfg -c "init" -c "pld load 0 shared_folder/ecp5_blinker_impl1.bit"
+#openocd -f board/ecp5_evaluation.cfg -c "init" -c "pld load ecp5.pld shared_folder/ecp5_blinker_impl1.bit"
 #ipdbg -start -tap ecp5.tap -hub 0x32 -port 5555 -tool 0
+
+set JTAGSPI_CHAIN_ID ecp5.pld
+source [find cpld/jtagspi.cfg]
+
+#jtagspi_init ecp5.pld "" -1
+#jtagspi_program shared_folder/ecp5_blinker_impl1_slow.bit 0

-----------------------------------------------------------------------

Summary of changes:
 src/pld/ecp5.c                | 71 +++++++++++++++++++++++++++++++++++++++++++
 src/pld/ecp5.h                |  3 ++
 src/pld/lattice.c             |  6 ++++
 src/pld/lattice_cmd.h         |  1 +
 tcl/board/ecp5_evaluation.cfg |  8 ++++-
 5 files changed, 88 insertions(+), 1 deletion(-)


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[openocd-gerrit <ope...@us...>]

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- Log -----------------------------------------------------------------
commit 2b99846ab67dd53540a18ed43fc9394c94f940ff
Author: Daniel Anselmi <dan...@gm...>
Date:   Fri Feb 24 15:57:30 2023 +0100

    jtagspi/pld: add support from lattice ecp2/ecp3 driver
    
    Provide jtagspi with specific procedures to be able to
    use jtagspi for programming spi-flash devices on lattice
    ecp2 and ecp3 devices.
    
    Change-Id: I39028aba47a74a0479be16d52d318f4bff7f2ed4
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7823
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/pld/ecp2_3.c b/src/pld/ecp2_3.c
index b1c2833d5..a7b7580c7 100644
--- a/src/pld/ecp2_3.c
+++ b/src/pld/ecp2_3.c
@@ -21,6 +21,7 @@
 #define ISC_DISABLE          0x1E
 #define LSCC_READ_STATUS     0x53
 #define LSCC_BITSTREAM_BURST 0x02
+#define PROGRAM_SPI          0x3A
 
 #define STATUS_DONE_BIT        0x00020000
 #define STATUS_ERROR_BITS_ECP2 0x00040003
@@ -249,3 +250,57 @@ int lattice_ecp3_load(struct lattice_pld_device *lattice_device, struct lattice_
 	const uint32_t expected = STATUS_DONE_BIT;
 	return lattice_verify_status_register_u32(lattice_device, out, expected, mask, false);
 }
+
+int lattice_ecp2_3_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info)
+{
+	if (!pld_device_info)
+		return ERROR_FAIL;
+
+	struct jtag_tap *tap = pld_device_info->tap;
+	if (!tap)
+		return ERROR_FAIL;
+
+	// erase configuration
+	int retval = lattice_set_instr(tap, ISC_ENABLE, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = lattice_set_instr(tap, ISC_ERASE, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = lattice_set_instr(tap, ISC_DISABLE, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+
+	// connect jtag to spi pins
+	retval = lattice_set_instr(tap, PROGRAM_SPI, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+
+	return jtag_execute_queue();
+}
+
+int lattice_ecp2_3_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info)
+{
+	if (!pld_device_info)
+		return ERROR_FAIL;
+
+	struct jtag_tap *tap = pld_device_info->tap;
+	if (!tap)
+		return ERROR_FAIL;
+
+	int retval = lattice_set_instr(tap, BYPASS, TAP_IDLE);
+	if (retval != ERROR_OK)
+		return retval;
+
+	return jtag_execute_queue();
+}
+
+int lattice_ecp2_3_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits)
+{
+	if (!pld_device_info)
+		return ERROR_FAIL;
+
+	*facing_read_bits = 1;
+
+	return ERROR_OK;
+}
diff --git a/src/pld/ecp2_3.h b/src/pld/ecp2_3.h
index 5f3e9e97b..c5dec5693 100644
--- a/src/pld/ecp2_3.h
+++ b/src/pld/ecp2_3.h
@@ -15,5 +15,8 @@ int lattice_ecp2_3_read_usercode(struct jtag_tap *tap, uint32_t *usercode, uint3
 int lattice_ecp2_3_write_usercode(struct lattice_pld_device *lattice_device, uint32_t usercode);
 int lattice_ecp2_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file);
 int lattice_ecp3_load(struct lattice_pld_device *lattice_device, struct lattice_bit_file *bit_file);
+int lattice_ecp2_3_connect_spi_to_jtag(struct lattice_pld_device *pld_device_info);
+int lattice_ecp2_3_disconnect_spi_from_jtag(struct lattice_pld_device *pld_device_info);
+int lattice_ecp2_3_get_facing_read_bits(struct lattice_pld_device *pld_device_info, unsigned int *facing_read_bits);
 
 #endif /* OPENOCD_PLD_ECP2_3_H */
diff --git a/src/pld/lattice.c b/src/pld/lattice.c
index 0cd08dd33..4085ec194 100644
--- a/src/pld/lattice.c
+++ b/src/pld/lattice.c
@@ -342,6 +342,64 @@ static int lattice_get_ipdbg_hub(int user_num, struct pld_device *pld_device, st
 	return ERROR_OK;
 }
 
+static int lattice_connect_spi_to_jtag(struct pld_device *pld_device)
+{
+	if (!pld_device)
+		return ERROR_FAIL;
+
+	struct lattice_pld_device *pld_device_info = pld_device->driver_priv;
+
+	int retval = lattice_check_device_family(pld_device_info);
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (pld_device_info->family == LATTICE_ECP2 || pld_device_info->family == LATTICE_ECP3)
+		return lattice_ecp2_3_connect_spi_to_jtag(pld_device_info);
+
+	return ERROR_FAIL;
+}
+
+static int lattice_disconnect_spi_from_jtag(struct pld_device *pld_device)
+{
+	if (!pld_device)
+		return ERROR_FAIL;
+
+	struct lattice_pld_device *pld_device_info = pld_device->driver_priv;
+
+	int retval = lattice_check_device_family(pld_device_info);
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (pld_device_info->family == LATTICE_ECP2 || pld_device_info->family == LATTICE_ECP3)
+		return lattice_ecp2_3_disconnect_spi_from_jtag(pld_device_info);
+
+	return ERROR_FAIL;
+}
+
+static int lattice_get_stuff_bits(struct pld_device *pld_device, unsigned int *facing_read_bits,
+		unsigned int *trailing_write_bits)
+{
+	if (!pld_device)
+		return ERROR_FAIL;
+
+	struct lattice_pld_device *pld_device_info = pld_device->driver_priv;
+
+	int retval = lattice_check_device_family(pld_device_info);
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (pld_device_info->family == LATTICE_ECP2 || pld_device_info->family == LATTICE_ECP3)
+		return lattice_ecp2_3_get_facing_read_bits(pld_device_info, facing_read_bits);
+
+	return ERROR_FAIL;
+}
+
+static int lattice_has_jtagspi_instruction(struct pld_device *device, bool *has_instruction)
+{
+	*has_instruction = true;
+	return ERROR_OK;
+}
+
 PLD_CREATE_COMMAND_HANDLER(lattice_pld_create_command)
 {
 	if (CMD_ARGC != 4 && CMD_ARGC != 6)
@@ -551,4 +609,8 @@ struct pld_driver lattice_pld = {
 	.pld_create_command = &lattice_pld_create_command,
 	.load = &lattice_load_command,
 	.get_ipdbg_hub = lattice_get_ipdbg_hub,
+	.has_jtagspi_instruction = lattice_has_jtagspi_instruction,
+	.connect_spi_to_jtag = lattice_connect_spi_to_jtag,
+	.disconnect_spi_from_jtag = lattice_disconnect_spi_from_jtag,
+	.get_stuff_bits = lattice_get_stuff_bits,
 };

-----------------------------------------------------------------------

Summary of changes:
 src/pld/ecp2_3.c  | 55 ++++++++++++++++++++++++++++++++++++++++++++++++
 src/pld/ecp2_3.h  |  3 +++
 src/pld/lattice.c | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 120 insertions(+)


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- Log -----------------------------------------------------------------
commit fe5ed48f40e4f1b36d74900d0d9b410affea6bdb
Author: Daniel Anselmi <dan...@gm...>
Date:   Fri Feb 24 15:57:30 2023 +0100

    jtagspi/pld: add interface to get support from pld drivers
    
    Jtagspi is using a proxy bitstream to "connect" JTAG to the
    SPI pins. This is not possible with all FPGA vendors/families.
    In this cases a dedicated procedure is needed to establish such
    a connection.
    
    This patch adds a jtagspi-mode for these cases. It also adds the
    needed interfaces to jtagspi and the pld-driver so the driver
    can select the mode and provide the necessary procedures.
    
    For the cases where a proxy bitstream is needed, the pld driver
    will select the mode and provide instruction code needed in this
    case.
    
    Change-Id: I9563f26739589157b39a3664a73d91152cd13f77
    Signed-off-by: Daniel Anselmi <dan...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/7822
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index f6f7a0c29..7ad48c862 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -5900,24 +5900,42 @@ flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
 @c "cfi part_id" disabled
 @end deffn
 
+@anchor{jtagspi}
 @deffn {Flash Driver} {jtagspi}
 @cindex Generic JTAG2SPI driver
 @cindex SPI
 @cindex jtagspi
 @cindex bscan_spi
 Several FPGAs and CPLDs can retrieve their configuration (bitstream) from a
-SPI flash connected to them. To access this flash from the host, the device
-is first programmed with a special proxy bitstream that
-exposes the SPI flash on the device's JTAG interface. The flash can then be
-accessed through JTAG.
+SPI flash connected to them. To access this flash from the host, some FPGA
+device provides dedicated JTAG instructions, while other FPGA devices should
+be programmed with a special proxy bitstream that exposes the SPI flash on
+the device's JTAG interface. The flash can then be accessed through JTAG.
 
-Since signaling between JTAG and SPI is compatible, all that is required for
+Since signalling between JTAG and SPI is compatible, all that is required for
 a proxy bitstream is to connect TDI-MOSI, TDO-MISO, TCK-CLK and activate
-the flash chip select when the JTAG state machine is in SHIFT-DR. Such
-a bitstream for several Xilinx FPGAs can be found in
+the flash chip select when the JTAG state machine is in SHIFT-DR.
+
+Such a bitstream for several Xilinx FPGAs can be found in
 @file{contrib/loaders/flash/fpga/xilinx_bscan_spi.py}. It requires
 @uref{https://github.com/m-labs/migen, migen} and a Xilinx toolchain to build.
 
+This mechanism with a proxy bitstream can also be used for FPGAs from Intel and
+Efinix. FPGAs from Lattice and Cologne Chip have dedicated JTAG instructions
+and procedure to connect the JTAG to the SPI signals and don't need a proxy
+bitstream. Support for these devices with dedicated procedure is provided by
+the pld drivers. For convenience the PLD drivers will provide the USERx code
+for FPGAs with a proxy bitstream. Currently the following PLD drivers are able
+to support jtagspi:
+@itemize
+@item Efinix: proxy-bitstream
+@item Gatemate: dedicated procedure
+@item Intel/Altera: proxy-bitstream
+@item Lattice: dedicated procedure supporting ECP2, ECP3, ECP5, Certus and Certus Pro devices
+@item AMD/Xilinx: proxy-bitstream
+@end itemize
+
+
 This flash bank driver requires a target on a JTAG tap and will access that
 tap directly. Since no support from the target is needed, the target can be a
 "testee" dummy. Since the target does not expose the flash memory
@@ -5935,14 +5953,25 @@ command, see below.
 @item @var{ir} ... is loaded into the JTAG IR to map the flash as the JTAG DR.
 For the bitstreams generated from @file{xilinx_bscan_spi.py} this is the
 @var{USER1} instruction.
-@end itemize
+@example
+target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
+set _USER1_INSTR_CODE 0x02
+flash bank $_FLASHNAME jtagspi 0x0 0 0 0 \
+           $_TARGETNAME $_USER1_INSTR_CODE
+@end example
+
+@item The option @option{-pld} @var{name} is used to have support from the
+PLD driver of pld device @var{name}. The name is the name of the pld device
+given during creation of the pld device.
+Pld device names are shown by the @command{pld devices} command.
 
 @example
-target create $_TARGETNAME testee -chain-position $_CHIPNAME.fpga
-set _XILINX_USER1 0x02
-flash bank $_FLASHNAME spi 0x0 0 0 0 \
-           $_TARGETNAME $_XILINX_USER1
+target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
+set _JTAGSPI_CHAIN_ID $_CHIPNAME.pld
+flash bank $_FLASHNAME jtagspi 0x0 0 0 0 \
+           $_TARGETNAME -pld $_JTAGSPI_CHAIN_ID
 @end example
+@end itemize
 
 @deffn Command {jtagspi set} bank_id name total_size page_size read_cmd unused pprg_cmd mass_erase_cmd sector_size sector_erase_cmd
 Sets flash parameters: @var{name} human readable string, @var{total_size}
@@ -8668,7 +8697,8 @@ Accordingly, both are called PLDs here.
 
 As it does for JTAG TAPs, debug targets, and flash chips (both NOR and NAND),
 OpenOCD maintains a list of PLDs available for use in various commands.
-Also, each such PLD requires a driver.
+Also, each such PLD requires a driver. PLD drivers may also be needed to program
+SPI flash connected to the FPGA to store the bitstream (@xref{jtagspi} for details).
 
 They are referenced by the name which was given when the pld was created or
 the number shown by the @command{pld devices} command.
diff --git a/src/flash/nor/jtagspi.c b/src/flash/nor/jtagspi.c
index 6bb3af9b7..4b975390b 100644
--- a/src/flash/nor/jtagspi.c
+++ b/src/flash/nor/jtagspi.c
@@ -12,6 +12,7 @@
 #include <jtag/jtag.h>
 #include <flash/nor/spi.h>
 #include <helper/time_support.h>
+#include <pld/pld.h>
 
 #define JTAGSPI_MAX_TIMEOUT 3000
 
@@ -21,19 +22,44 @@ struct jtagspi_flash_bank {
 	struct flash_device dev;
 	char devname[32];
 	bool probed;
-	bool always_4byte;			/* use always 4-byte address except for basic read 0x03 */
-	uint32_t ir;
-	unsigned int addr_len;		/* address length in bytes */
+	bool always_4byte;             /* use always 4-byte address except for basic read 0x03 */
+	unsigned int addr_len;         /* address length in bytes */
+	struct pld_device *pld_device; /* if not NULL, the PLD has special instructions for JTAGSPI */
+	uint32_t ir;                   /* when !pld_device, this instruction code is used in
+									  jtagspi_set_user_ir to connect through a proxy bitstream */
 };
 
 FLASH_BANK_COMMAND_HANDLER(jtagspi_flash_bank_command)
 {
-	struct jtagspi_flash_bank *info;
-
 	if (CMD_ARGC < 7)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	info = malloc(sizeof(struct jtagspi_flash_bank));
+	unsigned int ir = 0;
+	struct pld_device *device = NULL;
+	if (strcmp(CMD_ARGV[6], "-pld") == 0) {
+		if (CMD_ARGC < 8)
+			return ERROR_COMMAND_SYNTAX_ERROR;
+		device = get_pld_device_by_name_or_numstr(CMD_ARGV[7]);
+		if (device) {
+			bool has_jtagspi_instruction = false;
+			int retval = pld_has_jtagspi_instruction(device, &has_jtagspi_instruction);
+			if (retval != ERROR_OK)
+				return retval;
+			if (!has_jtagspi_instruction) {
+				retval = pld_get_jtagspi_userircode(device, &ir);
+				if (retval != ERROR_OK)
+					return retval;
+				device = NULL;
+			}
+		} else {
+			LOG_ERROR("pld device '#%s' is out of bounds or unknown", CMD_ARGV[7]);
+			return ERROR_FAIL;
+		}
+	} else {
+		COMMAND_PARSE_NUMBER(uint, CMD_ARGV[6], ir);
+	}
+
+	struct jtagspi_flash_bank *info = calloc(1, sizeof(struct jtagspi_flash_bank));
 	if (!info) {
 		LOG_ERROR("no memory for flash bank info");
 		return ERROR_FAIL;
@@ -47,18 +73,19 @@ FLASH_BANK_COMMAND_HANDLER(jtagspi_flash_bank_command)
 	}
 	info->tap = bank->target->tap;
 	info->probed = false;
-	COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], info->ir);
+
+	info->ir = ir;
+	info->pld_device = device;
 
 	return ERROR_OK;
 }
 
-static void jtagspi_set_ir(struct flash_bank *bank)
+static void jtagspi_set_user_ir(struct jtagspi_flash_bank *info)
 {
-	struct jtagspi_flash_bank *info = bank->driver_priv;
 	struct scan_field field;
 	uint8_t buf[4] = { 0 };
 
-	LOG_DEBUG("loading jtagspi ir");
+	LOG_DEBUG("loading jtagspi ir(0x%" PRIx32 ")", info->ir);
 	buf_set_u32(buf, 0, info->tap->ir_length, info->ir);
 	field.num_bits = info->tap->ir_length;
 	field.out_value = buf;
@@ -79,6 +106,7 @@ static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd,
 	assert(data_buffer || data_len == 0);
 
 	struct scan_field fields[6];
+	struct jtagspi_flash_bank *info = bank->driver_priv;
 
 	LOG_DEBUG("cmd=0x%02x write_len=%d data_len=%d", cmd, write_len, data_len);
 
@@ -87,22 +115,34 @@ static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd,
 	if (is_read)
 		data_len = -data_len;
 
+	unsigned int facing_read_bits = 0;
+	unsigned int trailing_write_bits = 0;
+
+	if (info->pld_device) {
+		int retval = pld_get_jtagspi_stuff_bits(info->pld_device, &facing_read_bits, &trailing_write_bits);
+		if (retval != ERROR_OK)
+			return retval;
+	}
+
 	int n = 0;
 	const uint8_t marker = 1;
-	fields[n].num_bits = 1;
-	fields[n].out_value = &marker;
-	fields[n].in_value = NULL;
-	n++;
-
-	/* transfer length = cmd + address + read/write,
-	 * -1 due to the counter implementation */
 	uint8_t xfer_bits[4];
-	h_u32_to_be(xfer_bits, ((sizeof(cmd) + write_len + data_len) * CHAR_BIT) - 1);
-	flip_u8(xfer_bits, xfer_bits, sizeof(xfer_bits));
-	fields[n].num_bits = sizeof(xfer_bits) * CHAR_BIT;
-	fields[n].out_value = xfer_bits;
-	fields[n].in_value = NULL;
-	n++;
+	if (!info->pld_device) { /* mode == JTAGSPI_MODE_PROXY_BITSTREAM */
+		facing_read_bits = jtag_tap_count_enabled();
+		fields[n].num_bits = 1;
+		fields[n].out_value = &marker;
+		fields[n].in_value = NULL;
+		n++;
+
+		/* transfer length = cmd + address + read/write,
+		 * -1 due to the counter implementation */
+		h_u32_to_be(xfer_bits, ((sizeof(cmd) + write_len + data_len) * CHAR_BIT) - 1);
+		flip_u8(xfer_bits, xfer_bits, sizeof(xfer_bits));
+		fields[n].num_bits = sizeof(xfer_bits) * CHAR_BIT;
+		fields[n].out_value = xfer_bits;
+		fields[n].in_value = NULL;
+		n++;
+	}
 
 	flip_u8(&cmd, &cmd, sizeof(cmd));
 	fields[n].num_bits = sizeof(cmd) * CHAR_BIT;
@@ -120,10 +160,12 @@ static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd,
 
 	if (data_len > 0) {
 		if (is_read) {
-			fields[n].num_bits = jtag_tap_count_enabled();
-			fields[n].out_value = NULL;
-			fields[n].in_value = NULL;
-			n++;
+			if (facing_read_bits) {
+				fields[n].num_bits = facing_read_bits;
+				fields[n].out_value = NULL;
+				fields[n].in_value = NULL;
+				n++;
+			}
 
 			fields[n].out_value = NULL;
 			fields[n].in_value = data_buffer;
@@ -135,16 +177,33 @@ static int jtagspi_cmd(struct flash_bank *bank, uint8_t cmd,
 		fields[n].num_bits = data_len * CHAR_BIT;
 		n++;
 	}
+	if (!is_read && trailing_write_bits) {
+		fields[n].num_bits = trailing_write_bits;
+		fields[n].out_value = NULL;
+		fields[n].in_value = NULL;
+		n++;
+	}
+
+	if (info->pld_device) {
+		int retval = pld_connect_spi_to_jtag(info->pld_device);
+		if (retval != ERROR_OK)
+			return retval;
+	} else {
+		jtagspi_set_user_ir(info);
+	}
 
-	jtagspi_set_ir(bank);
 	/* passing from an IR scan to SHIFT-DR clears BYPASS registers */
-	struct jtagspi_flash_bank *info = bank->driver_priv;
 	jtag_add_dr_scan(info->tap, n, fields, TAP_IDLE);
 	int retval = jtag_execute_queue();
+	if (retval != ERROR_OK)
+		return retval;
 
 	if (is_read)
 		flip_u8(data_buffer, data_buffer, data_len);
-	return retval;
+
+	if (info->pld_device)
+		return pld_disconnect_spi_from_jtag(info->pld_device);
+	return ERROR_OK;
 }
 
 COMMAND_HANDLER(jtagspi_handle_set)
diff --git a/src/pld/pld.c b/src/pld/pld.c
index c375418a9..81fb0c463 100644
--- a/src/pld/pld.c
+++ b/src/pld/pld.c
@@ -69,8 +69,95 @@ struct pld_device *get_pld_device_by_name_or_numstr(const char *str)
 	return get_pld_device_by_num(dev_num);
 }
 
-/* @deffn {Config Command} {pld create} pld_name driver -chain-position tap_name [options]
-*/
+
+int pld_has_jtagspi_instruction(struct pld_device *pld_device, bool *has_instruction)
+{
+	*has_instruction = false; /* default is using a proxy bitstream */
+
+	if (!pld_device)
+		return ERROR_FAIL;
+
+	struct pld_driver *pld_driver = pld_device->driver;
+	if (!pld_driver) {
+		LOG_ERROR("pld device has no associated driver");
+		return ERROR_FAIL;
+	}
+
+	if (pld_driver->has_jtagspi_instruction)
+		return pld_driver->has_jtagspi_instruction(pld_device, has_instruction);
+    /* else, take the default (proxy bitstream) */
+	return ERROR_OK;
+}
+
+int pld_get_jtagspi_userircode(struct pld_device *pld_device, unsigned int *ir)
+{
+	if (!pld_device)
+		return ERROR_FAIL;
+
+	struct pld_driver *pld_driver = pld_device->driver;
+	if (!pld_driver) {
+		LOG_ERROR("pld device has no associated driver");
+		return ERROR_FAIL;
+	}
+
+	if (pld_driver->get_jtagspi_userircode)
+		return pld_driver->get_jtagspi_userircode(pld_device, ir);
+
+	return ERROR_FAIL;
+}
+
+int pld_get_jtagspi_stuff_bits(struct pld_device *pld_device, unsigned int *facing_read_bits,
+							unsigned int *trailing_write_bits)
+{
+	if (!pld_device)
+		return ERROR_FAIL;
+
+	struct pld_driver *pld_driver = pld_device->driver;
+	if (!pld_driver) {
+		LOG_ERROR("pld device has no associated driver");
+		return ERROR_FAIL;
+	}
+
+	if (pld_driver->get_stuff_bits)
+		return pld_driver->get_stuff_bits(pld_device, facing_read_bits, trailing_write_bits);
+
+	return ERROR_OK;
+}
+
+int pld_connect_spi_to_jtag(struct pld_device *pld_device)
+{
+	if (!pld_device)
+		return ERROR_FAIL;
+
+	struct pld_driver *pld_driver = pld_device->driver;
+	if (!pld_driver) {
+		LOG_ERROR("pld device has no associated driver");
+		return ERROR_FAIL;
+	}
+
+	if (pld_driver->connect_spi_to_jtag)
+		return pld_driver->connect_spi_to_jtag(pld_device);
+
+	return ERROR_FAIL;
+}
+
+int pld_disconnect_spi_from_jtag(struct pld_device *pld_device)
+{
+	if (!pld_device)
+		return ERROR_FAIL;
+
+	struct pld_driver *pld_driver = pld_device->driver;
+	if (!pld_driver) {
+		LOG_ERROR("pld device has no associated driver");
+		return ERROR_FAIL;
+	}
+
+	if (pld_driver->disconnect_spi_from_jtag)
+		return pld_driver->disconnect_spi_from_jtag(pld_device);
+
+	return ERROR_FAIL;
+}
+
 COMMAND_HANDLER(handle_pld_create_command)
 {
 	if (CMD_ARGC < 2)
diff --git a/src/pld/pld.h b/src/pld/pld.h
index b736e6ae2..5e2fcd20c 100644
--- a/src/pld/pld.h
+++ b/src/pld/pld.h
@@ -20,12 +20,26 @@ struct pld_ipdbg_hub {
 	unsigned int user_ir_code;
 };
 
+int pld_has_jtagspi_instruction(struct pld_device *device, bool *has_instruction);
+int pld_get_jtagspi_userircode(struct pld_device *pld_device, unsigned int *ir);
+
+int pld_get_jtagspi_stuff_bits(struct pld_device *pld_device, unsigned int *facing_read_bits,
+							unsigned int *trailing_write_bits);
+int pld_connect_spi_to_jtag(struct pld_device *pld_device);
+int pld_disconnect_spi_from_jtag(struct pld_device *pld_device);
+
 struct pld_driver {
 	const char *name;
 	__PLD_CREATE_COMMAND((*pld_create_command));
 	const struct command_registration *commands;
 	int (*load)(struct pld_device *pld_device, const char *filename);
 	int (*get_ipdbg_hub)(int user_num, struct pld_device *pld_device, struct pld_ipdbg_hub *hub);
+	int (*has_jtagspi_instruction)(struct pld_device *device, bool *has_instruction);
+	int (*get_jtagspi_userircode)(struct pld_device *pld_device, unsigned int *ir);
+	int (*connect_spi_to_jtag)(struct pld_device *pld_device);
+	int (*disconnect_spi_from_jtag)(struct pld_device *pld_device);
+	int (*get_stuff_bits)(struct pld_device *pld_device, unsigned int *facing_read_bits,
+		unsigned int *trailing_write_bits);
 };
 
 #define PLD_CREATE_COMMAND_HANDLER(name) \
diff --git a/tcl/cpld/jtagspi.cfg b/tcl/cpld/jtagspi.cfg
index 4c84792fe..a7f02b977 100644
--- a/tcl/cpld/jtagspi.cfg
+++ b/tcl/cpld/jtagspi.cfg
@@ -4,6 +4,8 @@ set _USER1 0x02
 
 if { [info exists JTAGSPI_IR] } {
 	set _JTAGSPI_IR $JTAGSPI_IR
+} elseif {[info exists JTAGSPI_CHAIN_ID]} {
+	set _JTAGSPI_CHAIN_ID $JTAGSPI_CHAIN_ID
 } else {
 	set _JTAGSPI_IR $_USER1
 }
@@ -21,7 +23,11 @@ if { [info exists FLASHNAME] } {
 }
 
 target create $_TARGETNAME testee -chain-position $_CHIPNAME.tap
-flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR
+if { [info exists _JTAGSPI_IR] } {
+	flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR
+} else {
+    flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME -pld $_JTAGSPI_CHAIN_ID
+}
 
 # initialize jtagspi flash
 # chain_id: identifier of pld (you can get a list with 'pld devices')
@@ -33,7 +39,9 @@ flash bank $_FLASHNAME jtagspi 0 0 0 0 $_TARGETNAME $_JTAGSPI_IR
 proc jtagspi_init {chain_id proxy_bit {release_from_pwr_down_cmd -1}} {
 	# load proxy bitstream $proxy_bit and probe spi flash
 	global _FLASHNAME
-	pld load $chain_id $proxy_bit
+	if { $proxy_bit ne "" } {
+		pld load $chain_id $proxy_bit
+	}
 	reset halt
 	if {$release_from_pwr_down_cmd != -1} {
 		jtagspi cmd $_FLASHNAME 0 $release_from_pwr_down_cmd

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi        |  56 +++++++++++++++++------
 src/flash/nor/jtagspi.c | 119 ++++++++++++++++++++++++++++++++++++------------
 src/pld/pld.c           |  91 +++++++++++++++++++++++++++++++++++-
 src/pld/pld.h           |  14 ++++++
 tcl/cpld/jtagspi.cfg    |  12 ++++-
 5 files changed, 245 insertions(+), 47 deletions(-)


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