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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1112-g6bc2c5859

From: openocd-gerrit <ope...@us...> - 2025-08-02 13:11:38

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
       via  6bc2c585960d57c40792d072b38da0834d1e72f9 (commit)
      from  374a1f99832cbeb5eb345ed6c497b7abe3850f68 (commit)

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- Log -----------------------------------------------------------------
commit 6bc2c585960d57c40792d072b38da0834d1e72f9
Author: R. Diez <rdi...@rd...>
Date:   Sun Jul 20 10:39:02 2025 +0200

    configure.ac: Remove useless --enable-verbose-usb-io
    
    _DEBUG_USB_IO_ was not actually used anywhere.
    Its last user was the old ft2232 driver removed in Nov 2016
    with commit cc2d4f015f72d7c30d613b50572eb9f31fac515a
    ("Remove since long deprecated ft2232 driver").
    
    Change-Id: I1a98db7c7b03a89cc9347c0a66ec2106d2168c3f
    Signed-off-by: R. Diez <rdi...@rd...>
    
    Reviewed-on: https://review.openocd.org/c/openocd/+/9002
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index e05aa6ac8..e7f797608 100644
--- a/configure.ac
+++ b/configure.ac
@@ -262,34 +262,21 @@ AS_IF([test "x$enable_gcov" = "xyes"], [
   AC_DEFINE([USE_GCOV], [0], [0 to leave coverage collection disabled.])
 ])
 
-# set default verbose options, overridden by following options
-debug_usb_io=no
+# set default for debug_usb_comms, overridden by following options
 debug_usb_comms=no
 
 AC_ARG_ENABLE([verbose],
   AS_HELP_STRING([--enable-verbose],
       [Enable verbose JTAG I/O messages (for debugging).]),
   [
-  debug_usb_io=$enableval
   debug_usb_comms=$enableval
   ], [])
 
-AC_ARG_ENABLE([verbose_usb_io],
-  AS_HELP_STRING([--enable-verbose-usb-io],
-      [Enable verbose USB I/O messages (for debugging)]),
-  [debug_usb_io=$enableval], [])
-
 AC_ARG_ENABLE([verbose_usb_comms],
   AS_HELP_STRING([--enable-verbose-usb-comms],
       [Enable verbose USB communication messages (for debugging)]),
   [debug_usb_comms=$enableval], [])
 
-AC_MSG_CHECKING([whether to enable verbose USB I/O messages]);
-AC_MSG_RESULT([$debug_usb_io])
-AS_IF([test "x$debug_usb_io" = "xyes"], [
-  AC_DEFINE([_DEBUG_USB_IO_],[1], [Print verbose USB I/O messages])
-])
-
 AC_MSG_CHECKING([whether to enable verbose USB communication messages]);
 AC_MSG_RESULT([$debug_usb_comms])
 AS_IF([test "x$debug_usb_comms" = "xyes"], [

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1111-g374a1f998

From: openocd-gerrit <ope...@us...> - 2025-08-02 13:01:43

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
       via  374a1f99832cbeb5eb345ed6c497b7abe3850f68 (commit)
      from  eea3c568f9bdede39ee7e1446aeeb07d073d0ba8 (commit)

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- Log -----------------------------------------------------------------
commit 374a1f99832cbeb5eb345ed6c497b7abe3850f68
Author: Marc Schink <de...@za...>
Date:   Sun Jul 13 09:05:40 2025 +0200

    helper/log: Rework 'debug_level' command
    
    The patch changes the following:
    
     - Use correct return value ERROR_COMMAND_ARGUMENT_INVALID is case an
       invalid debug level is provided.
     - Do not echo the selected debug level.
     - Remove the 'debug_level: ' prefix when the debug level is shown.
       This makes processing via Tcl easier.
     - Use command_print() in order to provide the error message to the
       caller.
    
    Change-Id: Ida84a58c61060497fc36a1926eec7dd30c66cd72
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8996
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 90ed9d3b6..b188f2175 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -810,8 +810,7 @@ itself), use the @option{-d} command line switch. This sets the
 @option{debug_level} to "3", outputting the most information,
 including debug messages. The default setting is "2", outputting only
 informational messages, warnings and errors. You can also change this
-setting from within a telnet or gdb session using @command{debug_level<n>}
-(@pxref{debuglevel,,debug_level}).
+setting from within a telnet or gdb session using @ref{debuglevel,,@command{debug_level}}.
 
 You can redirect all output from the server to a file using the
 @option{-l <logfile>} switch.
@@ -9329,10 +9328,10 @@ will proceed to quit.
 @end deffn
 
 @anchor{debuglevel}
-@deffn {Command} {debug_level} [n]
+@deffn {Command} {debug_level} [number]
 @cindex message level
-Display debug level.
-If @var{n} (from 0..4) is provided, then set it to that level.
+Without arguments it displays the current debug level.
+If @var{number} (from 0..4) is provided, then set it to that level.
 This affects the kind of messages sent to the server log.
 Level 0 is error messages only;
 level 1 adds warnings;
diff --git a/src/helper/log.c b/src/helper/log.c
index 8f7ab0039..d8c4e09ac 100644
--- a/src/helper/log.c
+++ b/src/helper/log.c
@@ -207,18 +207,19 @@ void log_printf_lf(enum log_levels level,
 
 COMMAND_HANDLER(handle_debug_level_command)
 {
-	if (CMD_ARGC == 1) {
+	if (!CMD_ARGC) {
+		command_print(CMD, "%i", debug_level);
+	} else if (CMD_ARGC == 1) {
 		int new_level;
 		COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], new_level);
 		if ((new_level > LOG_LVL_DEBUG_IO) || (new_level < LOG_LVL_SILENT)) {
-			LOG_ERROR("level must be between %d and %d", LOG_LVL_SILENT, LOG_LVL_DEBUG_IO);
-			return ERROR_COMMAND_SYNTAX_ERROR;
+			command_print(CMD, "level must be between %d and %d", LOG_LVL_SILENT, LOG_LVL_DEBUG_IO);
+			return ERROR_COMMAND_ARGUMENT_INVALID;
 		}
 		debug_level = new_level;
-	} else if (CMD_ARGC > 1)
+	} else {
 		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	command_print(CMD, "debug_level: %i", debug_level);
+	}
 
 	return ERROR_OK;
 }
@@ -261,11 +262,11 @@ static const struct command_registration log_command_handlers[] = {
 		.name = "debug_level",
 		.handler = handle_debug_level_command,
 		.mode = COMMAND_ANY,
-		.help = "Sets the verbosity level of debugging output. "
+		.help = "Sets or display the verbosity level of debugging output. "
 			"0 shows errors only; 1 adds warnings; "
 			"2 (default) adds other info; 3 adds debugging; "
 			"4 adds extra verbose debugging.",
-		.usage = "number",
+		.usage = "[number]",
 	},
 	COMMAND_REGISTRATION_DONE
 };

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi |  9 ++++-----
 src/helper/log.c | 17 +++++++++--------
 2 files changed, 13 insertions(+), 13 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1110-geea3c568f

From: openocd-gerrit <ope...@us...> - 2025-08-02 13:01:19

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  eea3c568f9bdede39ee7e1446aeeb07d073d0ba8 (commit)
      from  2248f1ef1275115862bdd97363c68259661adde6 (commit)

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- Log -----------------------------------------------------------------
commit eea3c568f9bdede39ee7e1446aeeb07d073d0ba8
Author: OndÅej HoÅ¡ek <ond...@gm...>
Date:   Mon Jul 14 00:12:19 2025 +0200

    tcl/board: add mikroe/clicker4-stm32f745vg
    
    Add a board configuration file for the MikroElektronika Clicker 4 for
    STM32F745VG (MIKROE-6331), which contains their CMSIS-DAP-compatible
    on-board CODEGRIP programmer.
    
    Place this into its own subdirectory, since MikroElektronika has quite a
    few boards in their portfolio.
    
    Change-Id: If24ca286d65e024f3c3a8522b67727e268ab0bc9
    Signed-off-by: OndÅej HoÅ¡ek <ond...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8997
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/board/mikroe/clicker4-stm32f745vg.cfg b/tcl/board/mikroe/clicker4-stm32f745vg.cfg
new file mode 100644
index 000000000..9ccd94880
--- /dev/null
+++ b/tcl/board/mikroe/clicker4-stm32f745vg.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a MikroElektronika Click 4 board with a single STM32F745VG chip
+# and an on-board CODEGRIP debugger.
+# https://www.mikroe.com/clicker-4-for-stm32f745vgt6
+
+source [find interface/cmsis-dap.cfg]
+transport select jtag
+adapter speed 4000
+
+source [find target/stm32f7x.cfg]

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/mikroe/clicker4-stm32f745vg.cfg | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 tcl/board/mikroe/clicker4-stm32f745vg.cfg


hooks/post-receive
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Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1109-g2248f1ef1

From: openocd-gerrit <ope...@us...> - 2025-08-02 13:00:47

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  2248f1ef1275115862bdd97363c68259661adde6 (commit)
      from  4d14ac57414ea15922398998e75589f8bea2442d (commit)

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- Log -----------------------------------------------------------------
commit 2248f1ef1275115862bdd97363c68259661adde6
Author: Marc Schink <de...@za...>
Date:   Fri Jul 11 10:36:16 2025 +0200

    adapter/stlink: Hide '(re)connect' message
    
    Print a debug message rather than an info message because this
    information is not of importance for normal users.
    
    While at it, fix the 'EMBEDDED_FUNCTION_NAME' checkpatch issue.
    
    Change-Id: I9d458a6dd6818fdedc488e39d2daa6d72a21b743
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8994
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/stlink_usb.c b/src/jtag/drivers/stlink_usb.c
index 5ee1f8526..70a73eeb9 100644
--- a/src/jtag/drivers/stlink_usb.c
+++ b/src/jtag/drivers/stlink_usb.c
@@ -4194,7 +4194,7 @@ static int stlink_dap_op_connect(struct adiv5_dap *dap)
 	uint32_t idcode;
 	int retval;
 
-	LOG_INFO("stlink_dap_op_connect(%sconnect)", dap->do_reconnect ? "re" : "");
+	LOG_DEBUG("%s(%sconnect)", __func__, dap->do_reconnect ? "re" : "");
 
 	/* Check if we should reset srst already when connecting, but not if reconnecting. */
 	if (!dap->do_reconnect) {

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/stlink_usb.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1108-g4d14ac574

From: openocd-gerrit <ope...@us...> - 2025-08-02 13:00:23

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  4d14ac57414ea15922398998e75589f8bea2442d (commit)
      from  c8e6746e9fb2e35ae94ffe0318015001b0539f64 (commit)

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- Log -----------------------------------------------------------------
commit 4d14ac57414ea15922398998e75589f8bea2442d
Author: Marc Schink <de...@za...>
Date:   Fri Jul 11 14:39:45 2025 +0200

    rtt: Fix check for available down-channels
    
    The number of up-channels is erroneously checked instead of the number
    of down-channels.
    
    Change-Id: Iff5348387b3466ed66f34df81e1039918608ac77
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8995
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/rtt/rtt.c b/src/rtt/rtt.c
index 15b9a373a..3c7a966a7 100644
--- a/src/rtt/rtt.c
+++ b/src/rtt/rtt.c
@@ -288,7 +288,7 @@ int rtt_set_polling_interval(unsigned int interval)
 int rtt_write_channel(unsigned int channel_index, const uint8_t *buffer,
 		size_t *length)
 {
-	if (channel_index >= rtt.ctrl.num_up_channels) {
+	if (channel_index >= rtt.ctrl.num_down_channels) {
 		LOG_WARNING("rtt: Down-channel %u is not available", channel_index);
 		return ERROR_OK;
 	}

-----------------------------------------------------------------------

Summary of changes:
 src/rtt/rtt.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1107-gc8e6746e9

From: openocd-gerrit <ope...@us...> - 2025-08-02 13:00:00

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
       via  c8e6746e9fb2e35ae94ffe0318015001b0539f64 (commit)
      from  0d42f6a1b4598e335d03718f94b26166d3c52a43 (commit)

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- Log -----------------------------------------------------------------
commit c8e6746e9fb2e35ae94ffe0318015001b0539f64
Author: Marc Schink <de...@za...>
Date:   Tue Jul 8 07:17:19 2025 +0000

    rtt: Consider target endianness
    
    Consider target endianness when reading control block and channel
    information. Current implementation fails on big-endian devices.
    
    Tested on TMS570 (big-endian) and on nRF52 (little-endian).
    
    Note that in its current implementation RTT does not work properly on
    TMS570 due to its missing support for background memory access.
    
    Change-Id: Iab58804c42c85a932a750201a69ded35cebedd5d
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8993
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/rtt.c b/src/target/rtt.c
index 5ce049ae1..a8ab24a60 100644
--- a/src/target/rtt.c
+++ b/src/target/rtt.c
@@ -37,12 +37,12 @@ static int read_rtt_channel(struct target *target,
 		return ret;
 
 	channel->address = address;
-	channel->name_addr = buf_get_u32(buf + 0, 0, 32);
-	channel->buffer_addr = buf_get_u32(buf + 4, 0, 32);
-	channel->size = buf_get_u32(buf + 8, 0, 32);
-	channel->write_pos = buf_get_u32(buf + 12, 0, 32);
-	channel->read_pos = buf_get_u32(buf + 16, 0, 32);
-	channel->flags = buf_get_u32(buf + 20, 0, 32);
+	channel->name_addr = target_buffer_get_u32(target, buf + 0);
+	channel->buffer_addr = target_buffer_get_u32(target, buf + 4);
+	channel->size = target_buffer_get_u32(target, buf + 8);
+	channel->write_pos = target_buffer_get_u32(target, buf + 12);
+	channel->read_pos = target_buffer_get_u32(target, buf + 16);
+	channel->flags = target_buffer_get_u32(target, buf + 20);
 
 	return ERROR_OK;
 }
@@ -230,10 +230,8 @@ int target_rtt_read_control_block(struct target *target,
 
 	memcpy(ctrl->id, buf, RTT_CB_MAX_ID_LENGTH);
 	ctrl->id[RTT_CB_MAX_ID_LENGTH - 1] = '\0';
-	ctrl->num_up_channels = buf_get_u32(buf + RTT_CB_MAX_ID_LENGTH + 0,
-		0, 32);
-	ctrl->num_down_channels = buf_get_u32(buf + RTT_CB_MAX_ID_LENGTH + 4,
-		0, 32);
+	ctrl->num_up_channels = target_buffer_get_u32(target, buf + RTT_CB_MAX_ID_LENGTH + 0);
+	ctrl->num_down_channels = target_buffer_get_u32(target, buf + RTT_CB_MAX_ID_LENGTH + 4);
 
 	return ERROR_OK;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/rtt.c | 18 ++++++++----------
 1 file changed, 8 insertions(+), 10 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1106-g0d42f6a1b

From: openocd-gerrit <ope...@us...> - 2025-08-02 12:59:42

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 0d42f6a1b4598e335d03718f94b26166d3c52a43
Author: R. Diez <rdi...@rd...>
Date:   Sun Jul 20 12:12:36 2025 +0200

    configure.ac: Turn parpoart-ppdev warning into an error.
    
    Otherwise, it is easy to miss that configuration error.
    
    Change-Id: I889d2c1cc0150f4d7f178daf4509f7943ebfd4de
    Signed-off-by: R. Diez <rdi...@rd...>
    
    Reviewed-on: https://review.openocd.org/c/openocd/+/9004
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index ece9ba4c3..e05aa6ac8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -410,9 +410,8 @@ AS_CASE(["${host_cpu}"],
   [i?86|x86*], [],
   [
     AS_IF([test "x$parport_use_ppdev" = "xno"], [
-      AC_MSG_WARN([--disable-parport-ppdev is not supported by the host CPU])
+      AC_MSG_ERROR([--disable-parport-ppdev is not supported by the host CPU])
     ])
-    parport_use_ppdev=yes
 ])
 
 can_build_buspirate=yes

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)


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From: openocd-gerrit <ope...@us...> - 2025-08-02 12:58:44

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- Log -----------------------------------------------------------------
commit bf8590ea65958aec986ac49451e44f73209d6668
Author: R. Diez <rdi...@rd...>
Date:   Sun Jul 27 13:20:43 2025 +0200

    configure.ac: show the parallel port adapter in the config summary
    
    Use the same processing logic as most other enable/disable options.
    
    Change-Id: I994963fdab32a09c191f2e29620c9540136f980c
    Signed-off-by: R. Diez <rdi...@rd...>
    
    Reviewed-on: https://review.openocd.org/c/openocd/+/9003
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index 1f63d07d5..ece9ba4c3 100644
--- a/configure.ac
+++ b/configure.ac
@@ -183,6 +183,9 @@ m4_define([XVC_ADAPTERS],
 m4_define([SERIAL_PORT_ADAPTERS],
 	[[[buspirate], [Bus Pirate], [BUS_PIRATE]]])
 
+m4_define([PARALLEL_PORT_ADAPTER],
+	[[[parport], [PC Parallel Port], [PARPORT]]])
+
 m4_define([LINUXSPIDEV_ADAPTER],
 	[[[linuxspidev], [Linux spidev driver], [LINUXSPIDEV]]])
 m4_define([VDEBUG_ADAPTER],
@@ -340,6 +343,7 @@ AC_ARG_ADAPTERS([
   ],[auto])
 
 AC_ARG_ADAPTERS([
+  PARALLEL_PORT_ADAPTER,
   AMTJTAGACCEL_ADAPTER
   ],[no])
 
@@ -353,10 +357,6 @@ AC_ARG_ADAPTERS([
 AC_ARG_ADAPTERS([HOST_ARM_BITBANG_ADAPTERS],[no])
 AC_ARG_ADAPTERS([HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS],[no])
 
-AC_ARG_ENABLE([parport],
-  AS_HELP_STRING([--enable-parport], [Enable building the pc parallel port driver]),
-  [build_parport=$enableval], [build_parport=no])
-
 AC_ARG_ENABLE([parport_ppdev],
   AS_HELP_STRING([--disable-parport-ppdev],
       [Disable use of ppdev (/dev/parportN) for parport (for x86 only)]),
@@ -433,7 +433,7 @@ AS_CASE([$host_os],
     ], [
       is_cygwin=yes
       # sys/io.h needed under cygwin for parport access
-      AS_IF([test "x$build_parport" = "xyes"], [
+      AS_IF([test "x$enable_parport" != "xno"], [
         AC_CHECK_HEADERS([sys/io.h],[],AC_MSG_ERROR([Please install the cygwin ioperm package]))
       ])
     ])
@@ -496,13 +496,6 @@ AS_IF([test "x$is_darwin" = "xyes"], [
     AC_DEFINE([IS_DARWIN], [0], [0 if not building for Darwin.])
 ])
 
-AS_IF([test "x$build_parport" = "xyes"], [
-  build_bitbang=yes
-  AC_DEFINE([BUILD_PARPORT], [1], [1 if you want parport.])
-], [
-  AC_DEFINE([BUILD_PARPORT], [0], [0 if you don't want parport.])
-])
-
 AS_IF([test "x$ADAPTER_VAR([dummy])" != "xno"], [
   build_bitbang=yes
 ])
@@ -647,6 +640,7 @@ PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o
 PROCESS_ADAPTERS([XVC_ADAPTERS], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_pci_h" = "xyes"], [Linux build])
 PROCESS_ADAPTERS([SERIAL_PORT_ADAPTERS], ["x$can_build_buspirate" = "xyes"],
                                          [internal error: validation should happen beforehand])
+PROCESS_ADAPTERS([PARALLEL_PORT_ADAPTER], [true], [unused])
 PROCESS_ADAPTERS([LINUXSPIDEV_ADAPTER], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_spi_spidev_h" = "xyes"],
                                         [Linux spidev])
 PROCESS_ADAPTERS([VDEBUG_ADAPTER], [true], [unused])
@@ -724,7 +718,6 @@ AS_IF([test "x$enable_esp_usb_jtag" != "xno"], [
 ])
 
 AM_CONDITIONAL([RELEASE], [test "x$build_release" = "xyes"])
-AM_CONDITIONAL([PARPORT], [test "x$build_parport" = "xyes"])
 AM_CONDITIONAL([GIVEIO], [test "x$parport_use_giveio" = "xyes"])
 AM_CONDITIONAL([BITBANG], [test "x$build_bitbang" = "xyes"])
 AM_CONDITIONAL([USB_BLASTER_DRIVER], [test "x$enable_usb_blaster" != "xno" -o "x$enable_usb_blaster_2" != "xno"])
@@ -842,6 +835,7 @@ m4_foreach([adapterTuple], [USB1_ADAPTERS,
 	REMOTE_BITBANG_ADAPTER,
 	LIBJAYLINK_ADAPTERS, XVC_ADAPTERS,
 	SERIAL_PORT_ADAPTERS,
+	PARALLEL_PORT_ADAPTER,
 	LINUXSPIDEV_ADAPTER,
 	VDEBUG_ADAPTER,
 	JTAG_DPI_ADAPTER,

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 20 +++++++-------------
 1 file changed, 7 insertions(+), 13 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1104-g7cbb3c385

From: openocd-gerrit <ope...@us...> - 2025-08-02 12:58:15

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The branch, master has been updated
       via  7cbb3c38545c1ec1f5389adcbff9aa537675668c (commit)
      from  1272796cc55d6f6bc03105dac6e8f4775fa9ccc9 (commit)

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- Log -----------------------------------------------------------------
commit 7cbb3c38545c1ec1f5389adcbff9aa537675668c
Author: R. Diez <rdi...@rd...>
Date:   Sun Jul 20 16:31:52 2025 +0200

    configure.ac: Replace $build_dmem with $enable_dmem
    
    dmem uses now the standard option-handling logic,
    which defines $enable_xxx instead of $build_xxx.
    
    Change-Id: I810cf09241089b1dfbec0e2183e64f20050868be
    Signed-off-by: R. Diez <rdi...@rd...>
    
    Reviewed-on: https://review.openocd.org/c/openocd/+/9005
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index df94e20b8..1f63d07d5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -388,7 +388,7 @@ AS_CASE([$host_os],
       ])
     ])
 
-    AS_IF([test "x$build_dmem" = "xyes"], [
+    AS_IF([test "x$enable_dmem" = "xyes"], [
       AC_MSG_ERROR([dmem is only available on linux])
     ])
 ])

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


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- Log -----------------------------------------------------------------
commit 1272796cc55d6f6bc03105dac6e8f4775fa9ccc9
Author: Marc Schink <de...@za...>
Date:   Mon Jul 28 07:34:39 2025 +0000

    target/armv8: Use 'bool' data type for cache validity flag
    
    The variable is already used as boolean value but has the wrong data
    type.
    
    Change-Id: Ia54cfbcdad00dc15e1181c05fb97fcbaa435bb21
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9059
    Tested-by: jenkins
    Reviewed-by: Richard Allen <rs...@gm...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index d1ff023d9..9539a6437 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1095,7 +1095,7 @@ static int aarch64_post_debug_entry(struct target *target)
 	LOG_DEBUG("System_register: %8.8" PRIx64, aarch64->system_control_reg);
 	aarch64->system_control_reg_curr = aarch64->system_control_reg;
 
-	if (armv8->armv8_mmu.armv8_cache.info == -1) {
+	if (!armv8->armv8_mmu.armv8_cache.info_valid) {
 		armv8_identify_cache(armv8);
 		armv8_read_mpidr(armv8);
 	}
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 478a72b8d..51337a5d8 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -1303,7 +1303,7 @@ COMMAND_HANDLER(armv8_pauth_command)
 int armv8_handle_cache_info_command(struct command_invocation *cmd,
 	struct armv8_cache_common *armv8_cache)
 {
-	if (armv8_cache->info == -1) {
+	if (!armv8_cache->info_valid) {
 		command_print(cmd, "cache not yet identified");
 		return ERROR_OK;
 	}
@@ -1330,7 +1330,7 @@ int armv8_init_arch_info(struct target *target, struct armv8_common *armv8)
 	armv8->common_magic = ARMV8_COMMON_MAGIC;
 
 	armv8->armv8_mmu.armv8_cache.l2_cache = NULL;
-	armv8->armv8_mmu.armv8_cache.info = -1;
+	armv8->armv8_mmu.armv8_cache.info_valid = false;
 	armv8->armv8_mmu.armv8_cache.flush_all_data_cache = NULL;
 	armv8->armv8_mmu.armv8_cache.display_cache_info = NULL;
 	return ERROR_OK;
diff --git a/src/target/armv8.h b/src/target/armv8.h
index 51b8b00cd..5bc1719df 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -151,7 +151,7 @@ struct armv8_arch_cache {
 };
 
 struct armv8_cache_common {
-	int info;
+	bool info_valid;
 	int loc;
 	uint32_t iminline;
 	uint32_t dminline;
diff --git a/src/target/armv8_cache.c b/src/target/armv8_cache.c
index 1c251beb9..7bf4dcd47 100644
--- a/src/target/armv8_cache.c
+++ b/src/target/armv8_cache.c
@@ -214,7 +214,7 @@ static int armv8_handle_inner_cache_info_command(struct command_invocation *cmd,
 {
 	int cl;
 
-	if (armv8_cache->info == -1) {
+	if (!armv8_cache->info_valid) {
 		command_print(cmd, "cache not yet identified");
 		return ERROR_OK;
 	}
@@ -262,7 +262,7 @@ static int  armv8_flush_all_data(struct target *target)
 	int retval = ERROR_FAIL;
 	/*  check that armv8_cache is correctly identify */
 	struct armv8_common *armv8 = target_to_armv8(target);
-	if (armv8->armv8_mmu.armv8_cache.info == -1) {
+	if (!armv8->armv8_mmu.armv8_cache.info_valid) {
 		LOG_ERROR("trying to flush un-identified cache");
 		return retval;
 	}
@@ -288,7 +288,7 @@ static int  armv8_flush_all_instruction(struct target *target)
 	int retval = ERROR_FAIL;
 	/*  check that armv8_cache is correctly identify */
 	struct armv8_common *armv8 = target_to_armv8(target);
-	if (armv8->armv8_mmu.armv8_cache.info == -1) {
+	if (!armv8->armv8_mmu.armv8_cache.info_valid) {
 		LOG_ERROR("trying to flush un-identified cache");
 		return retval;
 	}
@@ -459,7 +459,7 @@ int armv8_identify_cache(struct armv8_common *armv8)
 	if (retval != ERROR_OK)
 		goto done;
 
-	armv8->armv8_mmu.armv8_cache.info = 1;
+	armv8->armv8_mmu.armv8_cache.info_valid = true;
 
 	/*  if no l2 cache initialize l1 data cache flush function function */
 	if (!armv8->armv8_mmu.armv8_cache.flush_all_data_cache) {

commit b4d05b6e72f972cfbaa2924b89152b052710e9fc
Author: Marc Schink <de...@za...>
Date:   Mon Jul 21 06:52:24 2025 +0000

    target/arvm7a:  Use 'bool' data type where appropriate
    
    The variables are already used as boolean value but have the wrong
    data type.
    
    Change-Id: I0f169cac83f6c4094e8d1acb2cb8f1017a96a5d8
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9008
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index c5829095e..9cde67788 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -139,7 +139,7 @@ int armv7a_read_ttbcr(struct target *target)
 
 	ttbcr_n = ttbcr & 0x7;
 	armv7a->armv7a_mmu.ttbcr = ttbcr;
-	armv7a->armv7a_mmu.cached = 1;
+	armv7a->armv7a_mmu.cached = true;
 
 	for (ttbidx = 0; ttbidx < 2; ttbidx++) {
 		/*  MRC p15,0,<Rt>,c2,c0,ttbidx */
@@ -158,7 +158,7 @@ int armv7a_read_ttbcr(struct target *target)
 	armv7a->armv7a_mmu.ttbr_range[1] = 0xffffffff;
 	armv7a->armv7a_mmu.ttbr_mask[0] = 0xffffffff << (14 - ttbcr_n);
 	armv7a->armv7a_mmu.ttbr_mask[1] = 0xffffffff << 14;
-	armv7a->armv7a_mmu.cached = 1;
+	armv7a->armv7a_mmu.cached = true;
 
 	retval = armv7a_read_midr(target);
 	if (retval != ERROR_OK)
@@ -187,7 +187,7 @@ int armv7a_handle_cache_info_command(struct command_invocation *cmd,
 
 	int cl;
 
-	if (armv7a_cache->info == -1) {
+	if (!armv7a_cache->info_valid) {
 		command_print(cmd, "cache not yet identified");
 		return ERROR_OK;
 	}
@@ -427,7 +427,7 @@ int armv7a_identify_cache(struct target *target)
 			armv7a_cache_flush_all_data;
 	}
 
-	armv7a->armv7a_mmu.armv7a_cache.info = 1;
+	armv7a->armv7a_mmu.armv7a_cache.info_valid = true;
 done:
 	dpm->finish(dpm);
 	armv7a_read_mpidr(target);
@@ -473,7 +473,7 @@ int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
 	armv7a->arm.target = target;
 	armv7a->arm.common_magic = ARM_COMMON_MAGIC;
 	armv7a->common_magic = ARMV7_COMMON_MAGIC;
-	armv7a->armv7a_mmu.armv7a_cache.info = -1;
+	armv7a->armv7a_mmu.armv7a_cache.info_valid = false;
 	armv7a->armv7a_mmu.armv7a_cache.outer_cache = NULL;
 	armv7a->armv7a_mmu.armv7a_cache.flush_all_data_cache = NULL;
 	return ERROR_OK;
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 0c5e0f90f..ae2ccbe2a 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -58,7 +58,7 @@ struct armv7a_arch_cache {
 
 /* common cache information */
 struct armv7a_cache_common {
-	int info;				/* -1 invalid, else valid */
+	bool info_valid;
 	int loc;				/* level of coherency */
 	uint32_t dminline;			/* minimum d-cache linelen */
 	uint32_t iminline;			/* minimum i-cache linelen */
@@ -72,7 +72,7 @@ struct armv7a_cache_common {
 
 struct armv7a_mmu_common {
 	/* following field mmu working way */
-	int32_t cached;     /* 0: not initialized, 1: initialized */
+	bool cached;
 	uint32_t ttbcr;     /* cache for ttbcr register */
 	uint32_t ttbr[2];
 	uint32_t ttbr_mask[2];
diff --git a/src/target/armv7a_cache_l2x.c b/src/target/armv7a_cache_l2x.c
index bc60e6d19..bdcf8cbbe 100644
--- a/src/target/armv7a_cache_l2x.c
+++ b/src/target/armv7a_cache_l2x.c
@@ -168,7 +168,7 @@ static int arm7a_handle_l2x_cache_info_command(struct command_invocation *cmd,
 {
 	struct armv7a_l2x_cache *l2x_cache = armv7a_cache->outer_cache;
 
-	if (armv7a_cache->info == -1) {
+	if (!armv7a_cache->info_valid) {
 		command_print(cmd, "cache not yet identified");
 		return ERROR_OK;
 	}
diff --git a/src/target/armv7a_mmu.c b/src/target/armv7a_mmu.c
index 43b5dae8e..ee1592ae8 100644
--- a/src/target/armv7a_mmu.c
+++ b/src/target/armv7a_mmu.c
@@ -214,7 +214,7 @@ COMMAND_HANDLER(armv7a_mmu_dump_table)
 			max_pt_idx -= 1;
 		}
 	} else {
-		if (mmu->cached != 1) {
+		if (!mmu->cached) {
 			LOG_ERROR("TTB not cached!");
 			return ERROR_FAIL;
 		}
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 69bc0920b..9e1aa4416 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1118,7 +1118,7 @@ static int cortex_a_post_debug_entry(struct target *target)
 	if (!armv7a->is_armv7r)
 		armv7a_read_ttbcr(target);
 
-	if (armv7a->armv7a_mmu.armv7a_cache.info == -1)
+	if (!armv7a->armv7a_mmu.armv7a_cache.info_valid)
 		armv7a_identify_cache(target);
 
 	if (armv7a->is_armv7r) {

-----------------------------------------------------------------------

Summary of changes:
 src/target/aarch64.c          |  2 +-
 src/target/armv7a.c           | 10 +++++-----
 src/target/armv7a.h           |  4 ++--
 src/target/armv7a_cache_l2x.c |  2 +-
 src/target/armv7a_mmu.c       |  2 +-
 src/target/armv8.c            |  4 ++--
 src/target/armv8.h            |  2 +-
 src/target/armv8_cache.c      |  8 ++++----
 src/target/cortex_a.c         |  2 +-
 9 files changed, 18 insertions(+), 18 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1101-gc2b8f994b

From: openocd-gerrit <ope...@us...> - 2025-08-02 12:57:02

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  c2b8f994bfdbfc7a7a290536a88f63e7cdc2d394 (commit)
      from  bd32290864eb2eb80411d72b388de3d78818e845 (commit)

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- Log -----------------------------------------------------------------
commit c2b8f994bfdbfc7a7a290536a88f63e7cdc2d394
Author: Marc Schink <de...@za...>
Date:   Sun Jul 20 11:33:38 2025 +0000

    target: Make use of str_enabled_disabled()
    
    The data type changes introduced in [1,2] lead to implicit casts from a
    boolean to an integer value in the string selection between "enabled" and
    "disabled".
    
    Use str_enabled_disabled() to get rid of this implicit cast.
    
    [1] https://review.openocd.org/c/openocd/+/8988
    [2] https://review.openocd.org/c/openocd/+/8992
    
    Change-Id: Ia98abdd43b42f394f5bf0aa845017dfbb0e087fd
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9007
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 933b49beb..702d6cfb1 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -14,6 +14,7 @@
 
 #include "arm720t.h"
 #include <helper/time_support.h>
+#include <helper/string_choices.h>
 #include "target_type.h"
 #include "register.h"
 #include "arm_opcodes.h"
@@ -227,14 +228,10 @@ static int arm720t_arch_state(struct target *target)
 {
 	struct arm720t_common *arm720t = target_to_arm720(target);
 
-	static const char *state[] = {
-		"disabled", "enabled"
-	};
-
 	arm_arch_state(target);
 	LOG_USER("MMU: %s, Cache: %s",
-			 state[arm720t->armv4_5_mmu.mmu_enabled],
-			 state[arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled]);
+			 str_enabled_disabled(arm720t->armv4_5_mmu.mmu_enabled),
+			 str_enabled_disabled(arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled));
 
 	return ERROR_OK;
 }
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 4dd576353..67c212e0b 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -12,6 +12,7 @@
 
 #include "arm920t.h"
 #include <helper/time_support.h>
+#include <helper/string_choices.h>
 #include "target_type.h"
 #include "register.h"
 #include "arm_opcodes.h"
@@ -509,10 +510,6 @@ static int arm920t_verify_pointer(struct command_invocation *cmd,
 /** Logs summary of ARM920 state for a halted target. */
 int arm920t_arch_state(struct target *target)
 {
-	static const char *state[] = {
-		"disabled", "enabled"
-	};
-
 	struct arm920t_common *arm920t = target_to_arm920(target);
 
 	if (arm920t->common_magic != ARM920T_COMMON_MAGIC) {
@@ -522,9 +519,9 @@ int arm920t_arch_state(struct target *target)
 
 	arm_arch_state(target);
 	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
-		state[arm920t->armv4_5_mmu.mmu_enabled],
-		state[arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
-		state[arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
+		str_enabled_disabled(arm920t->armv4_5_mmu.mmu_enabled),
+		str_enabled_disabled(arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled),
+		str_enabled_disabled(arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled));
 
 	return ERROR_OK;
 }
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 587f25061..a3fff2ae5 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -14,6 +14,7 @@
 
 #include "arm926ejs.h"
 #include <helper/time_support.h>
+#include <helper/string_choices.h>
 #include "target_type.h"
 #include "register.h"
 #include "arm_opcodes.h"
@@ -505,10 +506,6 @@ static int arm926ejs_verify_pointer(struct command_invocation *cmd,
 /** Logs summary of ARM926 state for a halted target. */
 int arm926ejs_arch_state(struct target *target)
 {
-	static const char *state[] = {
-		"disabled", "enabled"
-	};
-
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 
 	if (arm926ejs->common_magic != ARM926EJS_COMMON_MAGIC) {
@@ -518,9 +515,9 @@ int arm926ejs_arch_state(struct target *target)
 
 	arm_arch_state(target);
 	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
-			 state[arm926ejs->armv4_5_mmu.mmu_enabled],
-			 state[arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
-			 state[arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled]);
+			 str_enabled_disabled(arm926ejs->armv4_5_mmu.mmu_enabled),
+			 str_enabled_disabled(arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled),
+			 str_enabled_disabled(arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled));
 
 	return ERROR_OK;
 }
diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 2bbafd420..c5829095e 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -18,6 +18,7 @@
 
 #include "register.h"
 #include <helper/binarybuffer.h>
+#include <helper/string_choices.h>
 #include <helper/command.h>
 
 #include <stdlib.h>
@@ -480,10 +481,6 @@ int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a)
 
 int armv7a_arch_state(struct target *target)
 {
-	static const char *state[] = {
-		"disabled", "enabled"
-	};
-
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct arm *arm = &armv7a->arm;
 
@@ -496,13 +493,13 @@ int armv7a_arch_state(struct target *target)
 
 	if (armv7a->is_armv7r) {
 		LOG_TARGET_USER(target, "D-Cache: %s, I-Cache: %s",
-			state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
-			state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
+			str_enabled_disabled(armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled),
+			str_enabled_disabled(armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled));
 	} else {
 		LOG_TARGET_USER(target, "MMU: %s, D-Cache: %s, I-Cache: %s",
-			state[armv7a->armv7a_mmu.mmu_enabled],
-			state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
-			state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
+			str_enabled_disabled(armv7a->armv7a_mmu.mmu_enabled),
+			str_enabled_disabled(armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled),
+			str_enabled_disabled(armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled));
 	}
 
 	if (arm->core_mode == ARM_MODE_ABT)
diff --git a/src/target/armv8.c b/src/target/armv8.c
index ece49c2a2..478a72b8d 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -18,6 +18,7 @@
 
 #include "register.h"
 #include <helper/binarybuffer.h>
+#include <helper/string_choices.h>
 #include <helper/command.h>
 #include <helper/nvp.h>
 
@@ -1359,10 +1360,6 @@ static int armv8_aarch64_state(struct target *target)
 
 int armv8_arch_state(struct target *target)
 {
-	static const char * const state[] = {
-		"disabled", "enabled"
-	};
-
 	struct armv8_common *armv8 = target_to_armv8(target);
 	struct arm *arm = &armv8->arm;
 
@@ -1377,9 +1374,9 @@ int armv8_arch_state(struct target *target)
 		arm_arch_state(target);
 
 	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
-		state[armv8->armv8_mmu.mmu_enabled],
-		state[armv8->armv8_mmu.armv8_cache.d_u_cache_enabled],
-		state[armv8->armv8_mmu.armv8_cache.i_cache_enabled]);
+		str_enabled_disabled(armv8->armv8_mmu.mmu_enabled),
+		str_enabled_disabled(armv8->armv8_mmu.armv8_cache.d_u_cache_enabled),
+		str_enabled_disabled(armv8->armv8_mmu.armv8_cache.i_cache_enabled));
 
 	if (arm->core_mode == ARM_MODE_ABT)
 		armv8_show_fault_registers(target);
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 783628b12..50e03f202 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -22,6 +22,7 @@
 #include "arm_simulator.h"
 #include "arm_disassembler.h"
 #include <helper/time_support.h>
+#include <helper/string_choices.h>
 #include "register.h"
 #include "image.h"
 #include "arm_opcodes.h"
@@ -774,10 +775,6 @@ static int xscale_arch_state(struct target *target)
 	struct xscale_common *xscale = target_to_xscale(target);
 	struct arm *arm = &xscale->arm;
 
-	static const char *state[] = {
-		"disabled", "enabled"
-	};
-
 	static const char *arch_dbg_reason[] = {
 		"", "\n(processor reset)", "\n(trace buffer full)"
 	};
@@ -789,9 +786,9 @@ static int xscale_arch_state(struct target *target)
 
 	arm_arch_state(target);
 	LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s%s",
-		state[xscale->armv4_5_mmu.mmu_enabled],
-		state[xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled],
-		state[xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled],
+		str_enabled_disabled(xscale->armv4_5_mmu.mmu_enabled),
+		str_enabled_disabled(xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled),
+		str_enabled_disabled(xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled),
 		arch_dbg_reason[xscale->arch_debug_reason]);
 
 	return ERROR_OK;

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm720t.c   |  9 +++------
 src/target/arm920t.c   | 11 ++++-------
 src/target/arm926ejs.c | 11 ++++-------
 src/target/armv7a.c    | 15 ++++++---------
 src/target/armv8.c     | 11 ++++-------
 src/target/xscale.c    | 11 ++++-------
 6 files changed, 25 insertions(+), 43 deletions(-)


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Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1100-gbd3229086

From: openocd-gerrit <ope...@us...> - 2025-08-02 12:56:29

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  bd32290864eb2eb80411d72b388de3d78818e845 (commit)
       via  218ea2658a110bdfc6a4382ed42133a912b10d5d (commit)
      from  d20878b776ddbf9f98d96afa2767093e42271312 (commit)

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not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit bd32290864eb2eb80411d72b388de3d78818e845
Author: Marc Schink <de...@za...>
Date:   Wed Jul 9 12:06:59 2025 +0000

    target: Use 'bool' data type for {i,d_u}_cache_enabled
    
    The variables are already used as boolean value but have the wrong
    data type.
    
    Change-Id: Ia4c63d04fdd61bfd48e353fde9984b0e6cefbd8b
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8992
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 51ef1a82a..d1ff023d9 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1105,9 +1105,9 @@ static int aarch64_post_debug_entry(struct target *target)
 		armv8->armv8_mmu.mmu_enabled = aarch64->system_control_reg & 0x1U;
 	}
 	armv8->armv8_mmu.armv8_cache.d_u_cache_enabled =
-		(aarch64->system_control_reg & 0x4U) ? 1 : 0;
+		aarch64->system_control_reg & 0x4U;
 	armv8->armv8_mmu.armv8_cache.i_cache_enabled =
-		(aarch64->system_control_reg & 0x1000U) ? 1 : 0;
+		aarch64->system_control_reg & 0x1000U;
 	return ERROR_OK;
 }
 
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index c708c1daa..933b49beb 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -199,8 +199,9 @@ static int arm720t_post_debug_entry(struct target *target)
 	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 
 	arm720t->armv4_5_mmu.mmu_enabled = arm720t->cp15_control_reg & 0x1U;
-	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
-	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
+	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
+		arm720t->cp15_control_reg & 0x4U;
+	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = false;
 
 	/* save i/d fault status and address register */
 	retval = arm720t_read_cp15(target, 0xee150f10, &arm720t->fsr_reg);
@@ -355,8 +356,8 @@ static int arm720t_soft_reset_halt(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 	arm720t->armv4_5_mmu.mmu_enabled = false;
-	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
-	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
+	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = false;
+	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = false;
 
 	retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 	if (retval != ERROR_OK)
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 4f19affac..4dd576353 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -427,9 +427,9 @@ int arm920t_post_debug_entry(struct target *target)
 
 	arm920t->armv4_5_mmu.mmu_enabled = arm920t->cp15_control_reg & 0x1U;
 	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
-		(arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
+		arm920t->cp15_control_reg & 0x4U;
 	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
-		(arm920t->cp15_control_reg & 0x1000U) ? 1 : 0;
+		arm920t->cp15_control_reg & 0x1000U;
 
 	/* save i/d fault status and address register
 	 * FIXME use opcode macros */
@@ -778,8 +778,8 @@ int arm920t_soft_reset_halt(struct target *target)
 
 	arm920t_disable_mmu_caches(target, 1, 1, 1);
 	arm920t->armv4_5_mmu.mmu_enabled = false;
-	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
-	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
+	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = false;
+	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = false;
 
 	return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 }
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 8c31765e1..587f25061 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -441,8 +441,10 @@ static int arm926ejs_post_debug_entry(struct target *target)
 	}
 
 	arm926ejs->armv4_5_mmu.mmu_enabled = arm926ejs->cp15_control_reg & 0x1U;
-	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
-	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
+	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
+		arm926ejs->cp15_control_reg & 0x4U;
+	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
+		arm926ejs->cp15_control_reg & 0x1000U;
 
 	/* save i/d fault status and address register */
 	retval = arm926ejs->read_cp15(target, 0, 0, 5, 0, &arm926ejs->d_fsr);
@@ -576,8 +578,8 @@ int arm926ejs_soft_reset_halt(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 	arm926ejs->armv4_5_mmu.mmu_enabled = false;
-	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
-	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
+	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = false;
+	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = false;
 
 	return target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 }
diff --git a/src/target/armv4_5_cache.h b/src/target/armv4_5_cache.h
index 3659941e5..63fbdff33 100644
--- a/src/target/armv4_5_cache.h
+++ b/src/target/armv4_5_cache.h
@@ -24,8 +24,8 @@ struct armv4_5_cache_common {
 	int separate;	/* separate caches or unified cache */
 	struct armv4_5_cachesize d_u_size;	/* data cache */
 	struct armv4_5_cachesize i_size; /* instruction cache */
-	int i_cache_enabled;
-	int d_u_cache_enabled;
+	bool i_cache_enabled;
+	bool d_u_cache_enabled;
 };
 
 int armv4_5_identify_cache(uint32_t cache_type_reg,
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 69e223ddb..0c5e0f90f 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -63,8 +63,8 @@ struct armv7a_cache_common {
 	uint32_t dminline;			/* minimum d-cache linelen */
 	uint32_t iminline;			/* minimum i-cache linelen */
 	struct armv7a_arch_cache arch[6];	/* cache info, L1 - L7 */
-	int i_cache_enabled;
-	int d_u_cache_enabled;
+	bool i_cache_enabled;
+	bool d_u_cache_enabled;
 	/* outer unified cache if some */
 	struct armv7a_l2x_cache *outer_cache;
 	int (*flush_all_data_cache)(struct target *target);
diff --git a/src/target/armv8.h b/src/target/armv8.h
index 32c0dc32b..51b8b00cd 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -156,8 +156,8 @@ struct armv8_cache_common {
 	uint32_t iminline;
 	uint32_t dminline;
 	struct armv8_arch_cache arch[6];	/* cache info, L1 - L7 */
-	int i_cache_enabled;
-	int d_u_cache_enabled;
+	bool i_cache_enabled;
+	bool d_u_cache_enabled;
 
 	/* l2 external unified cache if some */
 	void *l2_cache;
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index d694ec0f2..69bc0920b 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1127,9 +1127,9 @@ static int cortex_a_post_debug_entry(struct target *target)
 		armv7a->armv7a_mmu.mmu_enabled = cortex_a->cp15_control_reg & 0x1U;
 	}
 	armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled =
-		(cortex_a->cp15_control_reg & 0x4U) ? 1 : 0;
+		cortex_a->cp15_control_reg & 0x4U;
 	armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled =
-		(cortex_a->cp15_control_reg & 0x1000U) ? 1 : 0;
+		cortex_a->cp15_control_reg & 0x1000U;
 	cortex_a->curr_mode = armv7a->arm.core_mode;
 
 	/* switch to SVC mode to read DACR */
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 7eaef6b8c..783628b12 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -984,9 +984,9 @@ static int xscale_debug_entry(struct target *target)
 		buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
 	xscale->armv4_5_mmu.mmu_enabled = xscale->cp15_control_reg & 0x1U;
 	xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
-		(xscale->cp15_control_reg & 0x4U) ? 1 : 0;
+		xscale->cp15_control_reg & 0x4U;
 	xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
-		(xscale->cp15_control_reg & 0x1000U) ? 1 : 0;
+		xscale->cp15_control_reg & 0x1000U;
 
 	/* tracing enabled, read collected trace data */
 	if (xscale->trace.mode != XSCALE_TRACE_DISABLED) {

commit 218ea2658a110bdfc6a4382ed42133a912b10d5d
Author: Marc Schink <de...@za...>
Date:   Wed Jul 9 11:45:23 2025 +0000

    target/cortex_a: Use 'bool' data type in cortex_a_mmu_modify()
    
    The variables are already used as boolean value but have the wrong
    data type.
    
    Change-Id: Ia1660751063993fcf46c86246e93a75089629ab5
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8991
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 42d01c3ac..d694ec0f2 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -69,7 +69,7 @@ static int cortex_a_unset_breakpoint(struct target *target,
 static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
 	uint32_t value, uint32_t *dscr);
 static int cortex_a_mmu(struct target *target, bool *enabled);
-static int cortex_a_mmu_modify(struct target *target, int enable);
+static int cortex_a_mmu_modify(struct target *target, bool enable);
 static int cortex_a_virt2phys(struct target *target,
 	target_addr_t virt, target_addr_t *phys);
 static int cortex_a_read_cpu_memory(struct target *target,
@@ -119,7 +119,7 @@ static int cortex_a_prep_memaccess(struct target *target, bool phys_access)
 		arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
 		cortex_a_mmu(target, &mmu_enabled);
 		if (mmu_enabled)
-			cortex_a_mmu_modify(target, 1);
+			cortex_a_mmu_modify(target, true);
 		if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
 			/* overwrite DACR to all-manager */
 			armv7a->arm.mcr(target, 15,
@@ -129,7 +129,7 @@ static int cortex_a_prep_memaccess(struct target *target, bool phys_access)
 	} else {
 		cortex_a_mmu(target, &mmu_enabled);
 		if (mmu_enabled)
-			cortex_a_mmu_modify(target, 0);
+			cortex_a_mmu_modify(target, false);
 	}
 	return ERROR_OK;
 }
@@ -156,7 +156,7 @@ static int cortex_a_post_memaccess(struct target *target, bool phys_access)
 		bool mmu_enabled = false;
 		cortex_a_mmu(target, &mmu_enabled);
 		if (mmu_enabled)
-			cortex_a_mmu_modify(target, 1);
+			cortex_a_mmu_modify(target, true);
 	}
 	return ERROR_OK;
 }
@@ -165,12 +165,12 @@ static int cortex_a_post_memaccess(struct target *target, bool phys_access)
 /*  modify cp15_control_reg in order to enable or disable mmu for :
  *  - virt2phys address conversion
  *  - read or write memory in phys or virt address */
-static int cortex_a_mmu_modify(struct target *target, int enable)
+static int cortex_a_mmu_modify(struct target *target, bool enable)
 {
 	struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	int retval = ERROR_OK;
-	int need_write = 0;
+	bool need_write = false;
 
 	if (enable) {
 		/*  if mmu enabled at target stop and mmu not enable */
@@ -180,12 +180,12 @@ static int cortex_a_mmu_modify(struct target *target, int enable)
 		}
 		if ((cortex_a->cp15_control_reg_curr & 0x1U) == 0) {
 			cortex_a->cp15_control_reg_curr |= 0x1U;
-			need_write = 1;
+			need_write = true;
 		}
 	} else {
 		if ((cortex_a->cp15_control_reg_curr & 0x1U) == 0x1U) {
 			cortex_a->cp15_control_reg_curr &= ~0x1U;
-			need_write = 1;
+			need_write = true;
 		}
 	}
 
@@ -3285,7 +3285,7 @@ static int cortex_a_virt2phys(struct target *target,
 	}
 
 	/* mmu must be enable in order to get a correct translation */
-	retval = cortex_a_mmu_modify(target, 1);
+	retval = cortex_a_mmu_modify(target, true);
 	if (retval != ERROR_OK)
 		return retval;
 	return armv7a_mmu_translate_va_pa(target, (uint32_t)virt,

-----------------------------------------------------------------------

Summary of changes:
 src/target/aarch64.c       |  4 ++--
 src/target/arm720t.c       |  9 +++++----
 src/target/arm920t.c       |  8 ++++----
 src/target/arm926ejs.c     | 10 ++++++----
 src/target/armv4_5_cache.h |  4 ++--
 src/target/armv7a.h        |  4 ++--
 src/target/armv8.h         |  4 ++--
 src/target/cortex_a.c      | 22 +++++++++++-----------
 src/target/xscale.c        |  4 ++--
 9 files changed, 36 insertions(+), 33 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1098-gd20878b77

From: openocd-gerrit <ope...@us...> - 2025-08-02 12:56:12

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  d20878b776ddbf9f98d96afa2767093e42271312 (commit)
       via  325e6d38b5d3edb3563481b96c897c3dc6f84bd8 (commit)
      from  a66e6fb43f1ff976d1a38edeb83caeacd06c4b80 (commit)

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- Log -----------------------------------------------------------------
commit d20878b776ddbf9f98d96afa2767093e42271312
Author: Marc Schink <de...@za...>
Date:   Tue Jul 8 13:52:43 2025 +0000

    target/cortex_a: Use 'bool' data type for cortex_a_*_memaccess()
    
    Use 'bool' because it is the appropriate data type.
    
    Change-Id: I543b153fe5f6af4d20988b95eb17f2357e706a76
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8990
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index b2cb75b98..42d01c3ac 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -109,13 +109,13 @@ static int cortex_a_restore_cp15_control_reg(struct target *target)
  * If !phys_access, switch to SVC mode and make sure MMU is on
  * If phys_access, switch off mmu
  */
-static int cortex_a_prep_memaccess(struct target *target, int phys_access)
+static int cortex_a_prep_memaccess(struct target *target, bool phys_access)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 	bool mmu_enabled = false;
 
-	if (phys_access == 0) {
+	if (!phys_access) {
 		arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
 		cortex_a_mmu(target, &mmu_enabled);
 		if (mmu_enabled)
@@ -139,12 +139,12 @@ static int cortex_a_prep_memaccess(struct target *target, int phys_access)
  * If !phys_access, switch to previous mode
  * If phys_access, restore MMU setting
  */
-static int cortex_a_post_memaccess(struct target *target, int phys_access)
+static int cortex_a_post_memaccess(struct target *target, bool phys_access)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct cortex_a_common *cortex_a = target_to_cortex_a(target);
 
-	if (phys_access == 0) {
+	if (!phys_access) {
 		if (cortex_a->dacrfixup_mode == CORTEX_A_DACRFIXUP_ON) {
 			/* restore */
 			armv7a->arm.mcr(target, 15,
@@ -2770,9 +2770,9 @@ static int cortex_a_read_phys_memory(struct target *target,
 		address, size, count);
 
 	/* read memory through the CPU */
-	cortex_a_prep_memaccess(target, 1);
+	cortex_a_prep_memaccess(target, true);
 	retval = cortex_a_read_cpu_memory(target, address, size, count, buffer);
-	cortex_a_post_memaccess(target, 1);
+	cortex_a_post_memaccess(target, true);
 
 	return retval;
 }
@@ -2786,9 +2786,9 @@ static int cortex_a_read_memory(struct target *target, target_addr_t address,
 	LOG_DEBUG("Reading memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
 		address, size, count);
 
-	cortex_a_prep_memaccess(target, 0);
+	cortex_a_prep_memaccess(target, false);
 	retval = cortex_a_read_cpu_memory(target, address, size, count, buffer);
-	cortex_a_post_memaccess(target, 0);
+	cortex_a_post_memaccess(target, false);
 
 	return retval;
 }
@@ -2806,9 +2806,9 @@ static int cortex_a_write_phys_memory(struct target *target,
 		address, size, count);
 
 	/* write memory through the CPU */
-	cortex_a_prep_memaccess(target, 1);
+	cortex_a_prep_memaccess(target, true);
 	retval = cortex_a_write_cpu_memory(target, address, size, count, buffer);
-	cortex_a_post_memaccess(target, 1);
+	cortex_a_post_memaccess(target, true);
 
 	return retval;
 }
@@ -2822,9 +2822,9 @@ static int cortex_a_write_memory(struct target *target, target_addr_t address,
 	LOG_DEBUG("Writing memory at address " TARGET_ADDR_FMT "; size %" PRIu32 "; count %" PRIu32,
 		address, size, count);
 
-	cortex_a_prep_memaccess(target, 0);
+	cortex_a_prep_memaccess(target, false);
 	retval = cortex_a_write_cpu_memory(target, address, size, count, buffer);
-	cortex_a_post_memaccess(target, 0);
+	cortex_a_post_memaccess(target, false);
 	return retval;
 }
 

commit 325e6d38b5d3edb3563481b96c897c3dc6f84bd8
Author: Marc Schink <de...@za...>
Date:   Wed Jul 9 11:37:30 2025 +0000

    target: Use 'bool' data type in mmu()
    
    The variable is already used in some parts of the code as boolean value
    but have the wrong data type.
    
    Change-Id: I50ccbf84c6f33a3034de989789c6b17312458ea8
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8989
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index f6fc6db4e..51ef1a82a 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -50,7 +50,7 @@ static int aarch64_set_hybrid_breakpoint(struct target *target,
 	struct breakpoint *breakpoint);
 static int aarch64_unset_breakpoint(struct target *target,
 	struct breakpoint *breakpoint);
-static int aarch64_mmu(struct target *target, int *enabled);
+static int aarch64_mmu(struct target *target, bool *enabled);
 static int aarch64_virt2phys(struct target *target,
 	target_addr_t virt, target_addr_t *phys);
 static int aarch64_read_cpu_memory(struct target *target,
@@ -2528,7 +2528,7 @@ static int aarch64_read_phys_memory(struct target *target,
 static int aarch64_read_memory(struct target *target, target_addr_t address,
 	uint32_t size, uint32_t count, uint8_t *buffer)
 {
-	int mmu_enabled = 0;
+	bool mmu_enabled = false;
 	int retval;
 
 	/* determine if MMU was enabled on target stop */
@@ -2565,7 +2565,7 @@ static int aarch64_write_phys_memory(struct target *target,
 static int aarch64_write_memory(struct target *target, target_addr_t address,
 	uint32_t size, uint32_t count, const uint8_t *buffer)
 {
-	int mmu_enabled = 0;
+	bool mmu_enabled = false;
 	int retval;
 
 	/* determine if MMU was enabled on target stop */
@@ -2876,7 +2876,7 @@ static void aarch64_deinit_target(struct target *target)
 	free(aarch64);
 }
 
-static int aarch64_mmu(struct target *target, int *enabled)
+static int aarch64_mmu(struct target *target, bool *enabled)
 {
 	struct aarch64_common *aarch64 = target_to_aarch64(target);
 	struct armv8_common *armv8 = &aarch64->armv8_common;
@@ -2885,7 +2885,7 @@ static int aarch64_mmu(struct target *target, int *enabled)
 		return ERROR_TARGET_NOT_HALTED;
 	}
 	if (armv8->is_armv8r)
-		*enabled = 0;
+		*enabled = false;
 	else
 		*enabled = target_to_aarch64(target)->armv8_common.armv8_mmu.mmu_enabled;
 	return ERROR_OK;
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index c9ee62d3d..c708c1daa 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -238,7 +238,7 @@ static int arm720t_arch_state(struct target *target)
 	return ERROR_OK;
 }
 
-static int arm720_mmu(struct target *target, int *enabled)
+static int arm720_mmu(struct target *target, bool *enabled)
 {
 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target, "not halted");
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 9faae9a47..4f19affac 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -529,7 +529,7 @@ int arm920t_arch_state(struct target *target)
 	return ERROR_OK;
 }
 
-static int arm920_mmu(struct target *target, int *enabled)
+static int arm920_mmu(struct target *target, bool *enabled)
 {
 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target, "not halted");
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 922b02013..8c31765e1 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -749,7 +749,7 @@ static int arm926ejs_virt2phys(struct target *target, target_addr_t virtual, tar
 	return ERROR_OK;
 }
 
-static int arm926ejs_mmu(struct target *target, int *enabled)
+static int arm926ejs_mmu(struct target *target, bool *enabled)
 {
 	struct arm926ejs_common *arm926ejs = target_to_arm926(target);
 
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 3d979bbab..b2cb75b98 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -68,7 +68,7 @@ static int cortex_a_unset_breakpoint(struct target *target,
 	struct breakpoint *breakpoint);
 static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
 	uint32_t value, uint32_t *dscr);
-static int cortex_a_mmu(struct target *target, int *enabled);
+static int cortex_a_mmu(struct target *target, bool *enabled);
 static int cortex_a_mmu_modify(struct target *target, int enable);
 static int cortex_a_virt2phys(struct target *target,
 	target_addr_t virt, target_addr_t *phys);
@@ -113,7 +113,7 @@ static int cortex_a_prep_memaccess(struct target *target, int phys_access)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 	struct cortex_a_common *cortex_a = target_to_cortex_a(target);
-	int mmu_enabled = 0;
+	bool mmu_enabled = false;
 
 	if (phys_access == 0) {
 		arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_SVC);
@@ -153,7 +153,7 @@ static int cortex_a_post_memaccess(struct target *target, int phys_access)
 		}
 		arm_dpm_modeswitch(&armv7a->dpm, ARM_MODE_ANY);
 	} else {
-		int mmu_enabled = 0;
+		bool mmu_enabled = false;
 		cortex_a_mmu(target, &mmu_enabled);
 		if (mmu_enabled)
 			cortex_a_mmu_modify(target, 1);
@@ -3249,7 +3249,7 @@ static void cortex_a_deinit_target(struct target *target)
 	free(cortex_a);
 }
 
-static int cortex_a_mmu(struct target *target, int *enabled)
+static int cortex_a_mmu(struct target *target, bool *enabled)
 {
 	struct armv7a_common *armv7a = target_to_armv7a(target);
 
@@ -3259,7 +3259,7 @@ static int cortex_a_mmu(struct target *target, int *enabled)
 	}
 
 	if (armv7a->is_armv7r)
-		*enabled = 0;
+		*enabled = false;
 	else
 		*enabled = target_to_cortex_a(target)->armv7a_common.armv7a_mmu.mmu_enabled;
 
@@ -3270,7 +3270,7 @@ static int cortex_a_virt2phys(struct target *target,
 	target_addr_t virt, target_addr_t *phys)
 {
 	int retval;
-	int mmu_enabled = 0;
+	bool mmu_enabled = false;
 
 	/*
 	 * If the MMU was not enabled at debug entry, there is no
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 11ef8f9b9..4ba0122ab 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -1520,10 +1520,10 @@ static int riscv_target_resume(struct target *target, bool current,
 			debug_execution, false);
 }
 
-static int riscv_mmu(struct target *target, int *enabled)
+static int riscv_mmu(struct target *target, bool *enabled)
 {
 	if (!riscv_enable_virt2phys) {
-		*enabled = 0;
+		*enabled = false;
 		return ERROR_OK;
 	}
 
@@ -1542,7 +1542,7 @@ static int riscv_mmu(struct target *target, int *enabled)
 
 	if ((get_field(mstatus, MSTATUS_MPRV) ? get_field(mstatus, MSTATUS_MPP) : priv) == PRV_M) {
 		LOG_DEBUG("SATP/MMU ignored in Machine mode (mstatus=0x%" PRIx64 ").", mstatus);
-		*enabled = 0;
+		*enabled = false;
 		return ERROR_OK;
 	}
 
@@ -1550,16 +1550,16 @@ static int riscv_mmu(struct target *target, int *enabled)
 	if (riscv_get_register(target, &satp, GDB_REGNO_SATP) != ERROR_OK) {
 		LOG_DEBUG("Couldn't read SATP.");
 		/* If we can't read SATP, then there must not be an MMU. */
-		*enabled = 0;
+		*enabled = false;
 		return ERROR_OK;
 	}
 
 	if (get_field(satp, RISCV_SATP_MODE(riscv_xlen(target))) == SATP_MODE_OFF) {
 		LOG_DEBUG("MMU is disabled.");
-		*enabled = 0;
+		*enabled = false;
 	} else {
 		LOG_DEBUG("MMU is enabled.");
-		*enabled = 1;
+		*enabled = true;
 	}
 
 	return ERROR_OK;
@@ -1674,7 +1674,7 @@ static int riscv_address_translate(struct target *target,
 
 static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
 {
-	int enabled;
+	bool enabled;
 	if (riscv_mmu(target, &enabled) == ERROR_OK) {
 		if (!enabled)
 			return ERROR_FAIL;
diff --git a/src/target/target.c b/src/target/target.c
index 995adbc9d..1428fac91 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -650,9 +650,9 @@ static int identity_virt2phys(struct target *target,
 	return ERROR_OK;
 }
 
-static int no_mmu(struct target *target, int *enabled)
+static int no_mmu(struct target *target, bool *enabled)
 {
-	*enabled = 0;
+	*enabled = false;
 	return ERROR_OK;
 }
 
@@ -1978,7 +1978,7 @@ int target_alloc_working_area_try(struct target *target, uint32_t size, struct w
 	/* Reevaluate working area address based on MMU state*/
 	if (!target->working_areas) {
 		int retval;
-		int enabled;
+		bool enabled;
 
 		retval = target->type->mmu(target, &enabled);
 		if (retval != ERROR_OK)
diff --git a/src/target/target_type.h b/src/target/target_type.h
index a146fab76..ccbe03a47 100644
--- a/src/target/target_type.h
+++ b/src/target/target_type.h
@@ -264,7 +264,7 @@ struct target_type {
 	int (*write_phys_memory)(struct target *target, target_addr_t phys_address,
 			uint32_t size, uint32_t count, const uint8_t *buffer);
 
-	int (*mmu)(struct target *target, int *enabled);
+	int (*mmu)(struct target *target, bool *enabled);
 
 	/* after reset is complete, the target can check if things are properly set up.
 	 *
diff --git a/src/target/x86_32_common.c b/src/target/x86_32_common.c
index 8cca9a5e9..f6dc71bac 100644
--- a/src/target/x86_32_common.c
+++ b/src/target/x86_32_common.c
@@ -96,7 +96,7 @@ int x86_32_common_init_arch_info(struct target *t, struct x86_32_common *x86_32)
 	return ERROR_OK;
 }
 
-int x86_32_common_mmu(struct target *t, int *enabled)
+int x86_32_common_mmu(struct target *t, bool *enabled)
 {
 	*enabled = true;
 	return ERROR_OK;
diff --git a/src/target/x86_32_common.h b/src/target/x86_32_common.h
index e23274769..7e8672ea0 100644
--- a/src/target/x86_32_common.h
+++ b/src/target/x86_32_common.h
@@ -299,7 +299,7 @@ int x86_32_get_gdb_reg_list(struct target *t,
 			enum target_register_class reg_class);
 int x86_32_common_init_arch_info(struct target *target,
 			struct x86_32_common *x86_32);
-int x86_32_common_mmu(struct target *t, int *enabled);
+int x86_32_common_mmu(struct target *t, bool *enabled);
 int x86_32_common_virt2phys(struct target *t, target_addr_t address, target_addr_t *physical);
 int x86_32_common_read_phys_mem(struct target *t, target_addr_t phys_address,
 			uint32_t size, uint32_t count, uint8_t *buffer);
diff --git a/src/target/xscale.c b/src/target/xscale.c
index b3d43ec7e..7eaef6b8c 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -3126,7 +3126,7 @@ static int xscale_virt2phys(struct target *target,
 	return ERROR_OK;
 }
 
-static int xscale_mmu(struct target *target, int *enabled)
+static int xscale_mmu(struct target *target, bool *enabled)
 {
 	struct xscale_common *xscale = target_to_xscale(target);
 
diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index 3366623d6..1a402743f 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -1556,7 +1556,7 @@ int xtensa_get_gdb_reg_list(struct target *target,
 	return ERROR_OK;
 }
 
-int xtensa_mmu_is_enabled(struct target *target, int *enabled)
+int xtensa_mmu_is_enabled(struct target *target, bool *enabled)
 {
 	struct xtensa *xtensa = target_to_xtensa(target);
 	*enabled = xtensa->core_config->mmu.itlb_entries_count > 0 ||
diff --git a/src/target/xtensa/xtensa.h b/src/target/xtensa/xtensa.h
index a920f77cd..daa88b10d 100644
--- a/src/target/xtensa/xtensa.h
+++ b/src/target/xtensa/xtensa.h
@@ -392,7 +392,7 @@ int xtensa_step(struct target *target, bool current, target_addr_t address,
 		bool handle_breakpoints);
 int xtensa_do_step(struct target *target, bool current, target_addr_t address,
 		bool handle_breakpoints);
-int xtensa_mmu_is_enabled(struct target *target, int *enabled);
+int xtensa_mmu_is_enabled(struct target *target, bool *enabled);
 int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t size, uint32_t count, uint8_t *buffer);
 int xtensa_read_buffer(struct target *target, target_addr_t address, uint32_t count, uint8_t *buffer);
 int xtensa_write_memory(struct target *target,

-----------------------------------------------------------------------

Summary of changes:
 src/target/aarch64.c       | 10 +++++-----
 src/target/arm720t.c       |  2 +-
 src/target/arm920t.c       |  2 +-
 src/target/arm926ejs.c     |  2 +-
 src/target/cortex_a.c      | 36 ++++++++++++++++++------------------
 src/target/riscv/riscv.c   | 14 +++++++-------
 src/target/target.c        |  6 +++---
 src/target/target_type.h   |  2 +-
 src/target/x86_32_common.c |  2 +-
 src/target/x86_32_common.h |  2 +-
 src/target/xscale.c        |  2 +-
 src/target/xtensa/xtensa.c |  2 +-
 src/target/xtensa/xtensa.h |  2 +-
 13 files changed, 42 insertions(+), 42 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1096-ga66e6fb43

From: openocd-gerrit <ope...@us...> - 2025-08-02 12:55:46

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  a66e6fb43f1ff976d1a38edeb83caeacd06c4b80 (commit)
      from  caf7ffc7ebb257b589d88aec4c3958ab2e6897f7 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit a66e6fb43f1ff976d1a38edeb83caeacd06c4b80
Author: Marc Schink <de...@za...>
Date:   Wed Jul 9 11:31:37 2025 +0000

    target: Use 'bool' data type for 'mmu_enabled'
    
    The variables are already used in some parts of the code as boolean
    value but have the wrong data type.
    
    Change-Id: I2c4955a6ed463fabf63a1dbd79145cb63bc7a99c
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8988
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 101cb1440..f6fc6db4e 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1100,10 +1100,9 @@ static int aarch64_post_debug_entry(struct target *target)
 		armv8_read_mpidr(armv8);
 	}
 	if (armv8->is_armv8r) {
-		armv8->armv8_mmu.mmu_enabled = 0;
+		armv8->armv8_mmu.mmu_enabled = false;
 	} else {
-		armv8->armv8_mmu.mmu_enabled =
-			(aarch64->system_control_reg & 0x1U) ? 1 : 0;
+		armv8->armv8_mmu.mmu_enabled = aarch64->system_control_reg & 0x1U;
 	}
 	armv8->armv8_mmu.armv8_cache.d_u_cache_enabled =
 		(aarch64->system_control_reg & 0x4U) ? 1 : 0;
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index d1433dde7..c9ee62d3d 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -198,7 +198,7 @@ static int arm720t_post_debug_entry(struct target *target)
 		return retval;
 	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 
-	arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
+	arm720t->armv4_5_mmu.mmu_enabled = arm720t->cp15_control_reg & 0x1U;
 	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
 	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
@@ -354,7 +354,7 @@ static int arm720t_soft_reset_halt(struct target *target)
 	retval = arm720t_disable_mmu_caches(target, 1, 1, 1);
 	if (retval != ERROR_OK)
 		return retval;
-	arm720t->armv4_5_mmu.mmu_enabled = 0;
+	arm720t->armv4_5_mmu.mmu_enabled = false;
 	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm720t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
@@ -407,7 +407,7 @@ static int arm720t_init_arch_info(struct target *target,
 	arm720t->armv4_5_mmu.disable_mmu_caches = arm720t_disable_mmu_caches;
 	arm720t->armv4_5_mmu.enable_mmu_caches = arm720t_enable_mmu_caches;
 	arm720t->armv4_5_mmu.has_tiny_pages = 0;
-	arm720t->armv4_5_mmu.mmu_enabled = 0;
+	arm720t->armv4_5_mmu.mmu_enabled = false;
 
 	return ERROR_OK;
 }
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 95cfd7ceb..9faae9a47 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -425,8 +425,7 @@ int arm920t_post_debug_entry(struct target *target)
 			&arm920t->armv4_5_mmu.armv4_5_cache);
 	}
 
-	arm920t->armv4_5_mmu.mmu_enabled =
-		(arm920t->cp15_control_reg & 0x1U) ? 1 : 0;
+	arm920t->armv4_5_mmu.mmu_enabled = arm920t->cp15_control_reg & 0x1U;
 	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
 		(arm920t->cp15_control_reg & 0x4U) ? 1 : 0;
 	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
@@ -778,7 +777,7 @@ int arm920t_soft_reset_halt(struct target *target)
 	arm->pc->valid = true;
 
 	arm920t_disable_mmu_caches(target, 1, 1, 1);
-	arm920t->armv4_5_mmu.mmu_enabled = 0;
+	arm920t->armv4_5_mmu.mmu_enabled = false;
 	arm920t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
@@ -819,7 +818,7 @@ static int arm920t_init_arch_info(struct target *target,
 	arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
 	arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
 	arm920t->armv4_5_mmu.has_tiny_pages = 1;
-	arm920t->armv4_5_mmu.mmu_enabled = 0;
+	arm920t->armv4_5_mmu.mmu_enabled = false;
 
 	/* disabling linefills leads to lockups, so keep them enabled for now
 	 * this doesn't affect correctness, but might affect timing issues, if
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 053110656..922b02013 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -440,7 +440,7 @@ static int arm926ejs_post_debug_entry(struct target *target)
 		armv4_5_identify_cache(cache_type_reg, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 	}
 
-	arm926ejs->armv4_5_mmu.mmu_enabled = (arm926ejs->cp15_control_reg & 0x1U) ? 1 : 0;
+	arm926ejs->armv4_5_mmu.mmu_enabled = arm926ejs->cp15_control_reg & 0x1U;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm926ejs->cp15_control_reg & 0x4U) ? 1 : 0;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = (arm926ejs->cp15_control_reg & 0x1000U) ? 1 : 0;
 
@@ -575,7 +575,7 @@ int arm926ejs_soft_reset_halt(struct target *target)
 	retval = arm926ejs_disable_mmu_caches(target, 1, 1, 1);
 	if (retval != ERROR_OK)
 		return retval;
-	arm926ejs->armv4_5_mmu.mmu_enabled = 0;
+	arm926ejs->armv4_5_mmu.mmu_enabled = false;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = 0;
 	arm926ejs->armv4_5_mmu.armv4_5_cache.i_cache_enabled = 0;
 
@@ -689,7 +689,7 @@ int arm926ejs_init_arch_info(struct target *target, struct arm926ejs_common *arm
 	arm926ejs->armv4_5_mmu.disable_mmu_caches = arm926ejs_disable_mmu_caches;
 	arm926ejs->armv4_5_mmu.enable_mmu_caches = arm926ejs_enable_mmu_caches;
 	arm926ejs->armv4_5_mmu.has_tiny_pages = 1;
-	arm926ejs->armv4_5_mmu.mmu_enabled = 0;
+	arm926ejs->armv4_5_mmu.mmu_enabled = false;
 
 	arm7_9->examine_debug_reason = arm926ejs_examine_debug_reason;
 
diff --git a/src/target/armv4_5_mmu.h b/src/target/armv4_5_mmu.h
index 774f1056e..bb30e807f 100644
--- a/src/target/armv4_5_mmu.h
+++ b/src/target/armv4_5_mmu.h
@@ -21,7 +21,7 @@ struct armv4_5_mmu_common {
 	int (*enable_mmu_caches)(struct target *target, int mmu, int d_u_cache, int i_cache);
 	struct armv4_5_cache_common armv4_5_cache;
 	int has_tiny_pages;
-	int mmu_enabled;
+	bool mmu_enabled;
 };
 
 int armv4_5_mmu_translate_va(struct target *target,
diff --git a/src/target/armv7a.h b/src/target/armv7a.h
index 2706c4629..69e223ddb 100644
--- a/src/target/armv7a.h
+++ b/src/target/armv7a.h
@@ -81,7 +81,7 @@ struct armv7a_mmu_common {
 	int (*read_physical_memory)(struct target *target, target_addr_t address, uint32_t size,
 			uint32_t count, uint8_t *buffer);
 	struct armv7a_cache_common armv7a_cache;
-	uint32_t mmu_enabled;
+	bool mmu_enabled;
 };
 
 struct armv7a_common {
diff --git a/src/target/armv8.h b/src/target/armv8.h
index 64ca5ec9d..32c0dc32b 100644
--- a/src/target/armv8.h
+++ b/src/target/armv8.h
@@ -179,7 +179,7 @@ struct armv8_mmu_common {
 	int (*read_physical_memory)(struct target *target, target_addr_t address,
 			uint32_t size, uint32_t count, uint8_t *buffer);
 	struct armv8_cache_common armv8_cache;
-	uint32_t mmu_enabled;
+	bool mmu_enabled;
 };
 
 struct armv8_common {
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index 2ebbf6577..3d979bbab 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1122,10 +1122,9 @@ static int cortex_a_post_debug_entry(struct target *target)
 		armv7a_identify_cache(target);
 
 	if (armv7a->is_armv7r) {
-		armv7a->armv7a_mmu.mmu_enabled = 0;
+		armv7a->armv7a_mmu.mmu_enabled = false;
 	} else {
-		armv7a->armv7a_mmu.mmu_enabled =
-			(cortex_a->cp15_control_reg & 0x1U) ? 1 : 0;
+		armv7a->armv7a_mmu.mmu_enabled = cortex_a->cp15_control_reg & 0x1U;
 	}
 	armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled =
 		(cortex_a->cp15_control_reg & 0x4U) ? 1 : 0;
diff --git a/src/target/fa526.c b/src/target/fa526.c
index d832d3e7d..254e5be6e 100644
--- a/src/target/fa526.c
+++ b/src/target/fa526.c
@@ -315,7 +315,7 @@ static int fa526_init_arch_info(struct target *target,
 	arm920t->armv4_5_mmu.disable_mmu_caches = arm920t_disable_mmu_caches;
 	arm920t->armv4_5_mmu.enable_mmu_caches = arm920t_enable_mmu_caches;
 	arm920t->armv4_5_mmu.has_tiny_pages = 1;
-	arm920t->armv4_5_mmu.mmu_enabled = 0;
+	arm920t->armv4_5_mmu.mmu_enabled = false;
 
 	/* disabling linefills leads to lockups, so keep them enabled for now
 	 * this doesn't affect correctness, but might affect timing issues, if
diff --git a/src/target/xscale.c b/src/target/xscale.c
index 84318a905..b3d43ec7e 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -982,7 +982,7 @@ static int xscale_debug_entry(struct target *target)
 	xscale_get_reg(&xscale->reg_cache->reg_list[XSCALE_CTRL]);
 	xscale->cp15_control_reg =
 		buf_get_u32(xscale->reg_cache->reg_list[XSCALE_CTRL].value, 0, 32);
-	xscale->armv4_5_mmu.mmu_enabled = (xscale->cp15_control_reg & 0x1U) ? 1 : 0;
+	xscale->armv4_5_mmu.mmu_enabled = xscale->cp15_control_reg & 0x1U;
 	xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
 		(xscale->cp15_control_reg & 0x4U) ? 1 : 0;
 	xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled =
@@ -3007,7 +3007,7 @@ static int xscale_init_arch_info(struct target *target,
 	xscale->armv4_5_mmu.disable_mmu_caches = xscale_disable_mmu_caches;
 	xscale->armv4_5_mmu.enable_mmu_caches = xscale_enable_mmu_caches;
 	xscale->armv4_5_mmu.has_tiny_pages = 1;
-	xscale->armv4_5_mmu.mmu_enabled = 0;
+	xscale->armv4_5_mmu.mmu_enabled = false;
 
 	return ERROR_OK;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/aarch64.c     | 5 ++---
 src/target/arm720t.c     | 6 +++---
 src/target/arm920t.c     | 7 +++----
 src/target/arm926ejs.c   | 6 +++---
 src/target/armv4_5_mmu.h | 2 +-
 src/target/armv7a.h      | 2 +-
 src/target/armv8.h       | 2 +-
 src/target/cortex_a.c    | 5 ++---
 src/target/fa526.c       | 2 +-
 src/target/xscale.c      | 4 ++--
 10 files changed, 19 insertions(+), 22 deletions(-)


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From: openocd-gerrit <ope...@us...> - 2025-08-02 12:55:29

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- Log -----------------------------------------------------------------
commit caf7ffc7ebb257b589d88aec4c3958ab2e6897f7
Author: Marc Schink <de...@za...>
Date:   Sun Jul 20 11:12:57 2025 +0000

    helper: Add string_choices.h
    
    Add the helper function str_enabled_disabled() to select between the two
    strings 'enabled' and 'disabled' depending on a boolean value.
    
    Additional functions for frequently used strings can be added in the future
    if required.
    
    Change-Id: I2d8ae96b141f87966836e6e4c3a2ed6d12b71fa5
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9006
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/helper/Makefile.am b/src/helper/Makefile.am
index 807212478..1a61f7871 100644
--- a/src/helper/Makefile.am
+++ b/src/helper/Makefile.am
@@ -32,6 +32,7 @@ noinst_LTLIBRARIES += %D%/libhelper.la
 	%D%/crc32.h \
 	%D%/time_support.h \
 	%D%/replacements.h \
+	%D%/string_choices.h \
 	%D%/fileio.h \
 	%D%/system.h \
 	%D%/jep106.h \
diff --git a/src/helper/string_choices.h b/src/helper/string_choices.h
new file mode 100644
index 000000000..7e535845d
--- /dev/null
+++ b/src/helper/string_choices.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef OPENOCD_HELPER_STRING_CHOICES_H
+#define OPENOCD_HELPER_STRING_CHOICES_H
+
+#include <helper/types.h>
+
+/*
+ * This file contains helper functions that return one of two strings depending
+ * on a boolean value. The format of these functions is 'str_$true_$false' where
+ * $true and $false are the two corresponding strings.
+ *
+ * These helper functions are beneficial because they improve code consistency
+ * and reduce the number of hardcoded strings.
+ */
+
+static inline const char *str_enabled_disabled(bool value)
+{
+	return value ? "enabled" : "disabled";
+}
+
+#endif /* OPENOCD_HELPER_STRING_CHOICES_H */

-----------------------------------------------------------------------

Summary of changes:
 src/helper/Makefile.am      |  1 +
 src/helper/string_choices.h | 22 ++++++++++++++++++++++
 2 files changed, 23 insertions(+)
 create mode 100644 src/helper/string_choices.h


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The branch, master has been updated
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      from  7e83049c93d8ec008b54e9dfe3774b9fc1c5ddcf (commit)

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- Log -----------------------------------------------------------------
commit 6872f7e406ad74f366f55947d23becd5a5faca15
Author: Marc Schink <de...@za...>
Date:   Tue Jul 8 07:57:27 2025 +0000

    adapter/xds110: Hide '(dis)connected' message
    
    Print a debug message rather than an info message because this
    information is not of importance for normal users.
    
    Change-Id: Ie91565df455ffc0bfe976d1782dd4318bfd2d30b
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8986
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c
index d1bb70590..6b3ca5cfb 100644
--- a/src/jtag/drivers/xds110.c
+++ b/src/jtag/drivers/xds110.c
@@ -428,7 +428,7 @@ static bool usb_connect(void)
 
 	/* Log the results */
 	if (result == 0)
-		LOG_INFO("XDS110: connected");
+		LOG_DEBUG("XDS110: connected");
 	else
 		LOG_ERROR("XDS110: failed to connect");
 
@@ -448,7 +448,7 @@ static void usb_disconnect(void)
 		xds110.ctx = NULL;
 	}
 
-	LOG_INFO("XDS110: disconnected");
+	LOG_DEBUG("XDS110: disconnected");
 }
 
 static bool usb_read(unsigned char *buffer, int size, int *bytes_read,

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/xds110.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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- Log -----------------------------------------------------------------
commit 7e83049c93d8ec008b54e9dfe3774b9fc1c5ddcf
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jul 4 16:37:38 2025 +0200

    tcl: add support for stm32mp2xx targets and boards
    
    Add support for the targets stm32mp21x, stm32mp23x and stm32mp25x.
    Add support for the boards stm32mp235f-dk and stm32mp257f-dk.
    
    The board stm32mp215f-dk has no configuration file as it only
    provides a generic JTAG/SWD connector for the stm32mp21x SoC.
    
    Change-Id: I0256bebd8a5d5600066d8ae191d83344a35d3d37
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8985
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>

diff --git a/tcl/board/st/stm32mp235f-dk.cfg b/tcl/board/st/stm32mp235f-dk.cfg
new file mode 100644
index 000000000..1f660f19e
--- /dev/null
+++ b/tcl/board/st/stm32mp235f-dk.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MB1605 with stm32mp23x
+# https://www.st.com/en/evaluation-tools/stm32mp257f-dk.html
+
+source [find interface/stlink.cfg]
+
+transport select swd
+
+source [find target/st/stm32mp23x.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/st/stm32mp257f-dk.cfg b/tcl/board/st/stm32mp257f-dk.cfg
new file mode 100644
index 000000000..182f1d00c
--- /dev/null
+++ b/tcl/board/st/stm32mp257f-dk.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MB1605
+# https://www.st.com/en/evaluation-tools/stm32mp257f-dk.html
+
+source [find interface/stlink.cfg]
+
+transport select swd
+
+source [find target/st/stm32mp25x.cfg]
+
+reset_config srst_only
diff --git a/tcl/target/st/stm32mp21x.cfg b/tcl/target/st/stm32mp21x.cfg
new file mode 100644
index 000000000..f4073a9f5
--- /dev/null
+++ b/tcl/target/st/stm32mp21x.cfg
@@ -0,0 +1,222 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP21x
+# STM32MP21x devices support both JTAG and SWD transports.
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp21x
+}
+
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA35] } {
+	set EN_CA35 1
+}
+if { ! [info exists EN_CM33] } {
+	set EN_CM33 1
+}
+
+set _ENDIAN little
+
+# jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x16503041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f
+if { [using_jtag] } {
+	swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+# define AXI & APB Memory Access Ports
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 2
+target create $_CHIPNAME.ap3 mem_ap -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
+
+# define the Cortex-A35
+cti create $_CHIPNAME.cti.a35 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80220000
+target create $_CHIPNAME.a35 aarch64 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase 0x80210000 \
+	-cti $_CHIPNAME.cti.a35 -defer-examine
+
+# define the Cortex-M33
+target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
+cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xe0042000
+
+# define the system CTIs
+cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80080000
+cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80090000
+
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x800A0000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80040000
+
+targets $_CHIPNAME.a35
+
+reset_config srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# wait 1 seconds for bootrom
+adapter srst delay 1000
+
+# set CSW for AXI
+$_CHIPNAME.dap apsel 2
+$_CHIPNAME.dap apcsw 0x12800000
+
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP0 and AXI
+proc _enable_debug {} {
+	# Enable DBGMCU clock in RC
+	$::_CHIPNAME.axi mww 0x44200520 0x500
+
+	# set debug enable bits in DBGMCU_CR to get ap3/cm33 visible
+	$::_CHIPNAME.ap0 mww 0x80001004 0x7
+
+	# Freeze watchdogs on CPU halt
+	$::_CHIPNAME.axi mww 0x440a003c 0x00000026
+	$::_CHIPNAME.axi mww 0x440a0040 0x00000038
+}
+
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+# Uses AXI
+proc _rcc_enable_traceclk {} {
+	# set bit TRACEEN in RCC_DBGCFGR to clock TPIU
+	target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0
+}
+
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP0, AP1 and AP3
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80001004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return
+	}
+
+	if { $halt } {
+		if { $::EN_CA35 } {
+			$::_CHIPNAME.ap1 arp_examine
+			$::_CHIPNAME.ap1 arp_halt
+			$::_CHIPNAME.ap1 mww 0x80210300 0
+			target_mmw $::_CHIPNAME.ap1 0x80210088 0x00004000 0
+		}
+		if { $::EN_CM33 } {
+			$::_CHIPNAME.ap3 arp_examine
+			$::_CHIPNAME.ap3 arp_halt
+			$::_CHIPNAME.ap3 mww 0xe000edf0 0xa05f0001
+		}
+	}
+
+	# alert wrapper that debugger is ready
+	$::_CHIPNAME.ap0 mww 0x80001004 0x07
+}
+
+lappend _telnet_autocomplete_skip _enable_dbgmcu_on_devboot
+# In DEV BOOT the BootROM does not completes the sequence to enable the
+# visibility of DBGMCU on AP0.
+# Write a value in DBGMCU_DBG_AUTH_DEV from CID1.
+# Returns 1 if DEV BOOT is detected
+# Uses AP2 (AXI bus)
+proc _enable_dbgmcu_on_devboot {} {
+	$::_CHIPNAME.axi mww 0x44230004 0
+	set boot_pins [expr {[$::_CHIPNAME.axi read_memory 0x44230000 32 1] & 0xf}]
+	if {$boot_pins != 0x3 && $boot_pins != 0xc} {
+		return 0
+	}
+
+	set rifsc_rimc_cr [$::_CHIPNAME.axi read_memory 0x42080c00 32 1]
+	if {$rifsc_rimc_cr != 0x00008710} {
+		echo "RIFSC_RIMC_CR modified, skip activation of DBGMCU"
+		return 1
+	}
+
+	# Enable DBGMCU clock in RC
+	$::_CHIPNAME.axi mww 0x44200520 0x500
+
+	# Change DAP (AXI) CID, write in DBGMCU, set back DAP CID
+	$::_CHIPNAME.axi mww 0x42080c00 0x00008110
+	$::_CHIPNAME.axi mww 0x440A0104 1
+	$::_CHIPNAME.axi mww 0x42080c00 0x00008710
+	return 1
+}
+
+$_CHIPNAME.m33 configure -event reset-assert { }
+
+$_CHIPNAME.axi configure -event reset-assert-post {
+	adapter assert srst
+}
+
+$_CHIPNAME.axi configure -event reset-deassert-pre {
+	adapter deassert srst deassert trst
+	$::_CHIPNAME.axi arp_examine
+	set is_dev_boot [_enable_dbgmcu_on_devboot]
+	if { !$is_dev_boot } {
+		_handshake_with_wrapper $halt
+	}
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35 } {
+		$::_CHIPNAME.a35 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.a35 arp_halt
+		}
+	}
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap3 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.ap3 arp_halt
+			$::_CHIPNAME.m33 arp_halt
+		}
+	}
+}
+
+$_CHIPNAME.axi configure -event examine-end {
+	set is_dev_boot [_enable_dbgmcu_on_devboot]
+	if { $is_dev_boot } {
+		echo "Dev boot detected"
+	}
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35 } {
+		$::_CHIPNAME.a35 arp_examine
+	}
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap3 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+	}
+}
diff --git a/tcl/target/st/stm32mp23x.cfg b/tcl/target/st/stm32mp23x.cfg
new file mode 100644
index 000000000..015f816e4
--- /dev/null
+++ b/tcl/target/st/stm32mp23x.cfg
@@ -0,0 +1,215 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP23x
+# STM32MP23x devices support both JTAG and SWD transports.
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp23x
+}
+
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA35_0] } {
+	set EN_CA35_0 1
+}
+if { ! [info exists EN_CA35_1] } {
+	set EN_CA35_1 1
+}
+if { ! [info exists EN_CM33] } {
+	set EN_CM33   1
+}
+
+set _ENDIAN little
+
+# jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x16505041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f
+if { [using_jtag] } {
+	swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+# define AXI & APB Memory Access Ports
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 4
+target create $_CHIPNAME.ap8 mem_ap -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+
+# define the first Cortex-A35
+cti create $_CHIPNAME.cti.a35_0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80220000
+target create $_CHIPNAME.a35_0 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80210000 \
+	-cti $_CHIPNAME.cti.a35_0 -defer-examine
+
+# define the second Cortex-A35
+cti create $_CHIPNAME.cti.a35_1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80320000
+target create $_CHIPNAME.a35_1 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80310000 \
+	-cti $_CHIPNAME.cti.a35_1 -defer-examine
+
+# define the Cortex-M33
+target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr 0xe0042000
+
+# define the system CTIs
+cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80090000
+cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800a0000
+
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800b0000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80050000
+
+targets $_CHIPNAME.a35_0
+
+target smp $_CHIPNAME.a35_0 $_CHIPNAME.a35_1
+$_CHIPNAME.a35_0 configure -rtos hwthread
+$_CHIPNAME.a35_1 configure -rtos hwthread
+
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# wait 1 seconds for bootrom
+adapter srst delay 1000
+
+# set CSW for AXI
+$_CHIPNAME.dap apsel 4
+$_CHIPNAME.dap apcsw 0x12800000
+
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP0 and AXI
+proc _enable_debug {} {
+	# set debug enable bits in DBGMCU_CR to get ap8/cm33 visible
+	$::_CHIPNAME.ap0 mww 0x80010004 0x17
+
+	# Freeze watchdogs on CPU halt
+	$::_CHIPNAME.axi mww 0x4a010008 0x00000000
+	$::_CHIPNAME.axi mww 0x4a01003c 0x00000026
+	$::_CHIPNAME.axi mww 0x4a010040 0x00000038
+	$::_CHIPNAME.axi mww 0x4a010044 0x00000400
+	$::_CHIPNAME.axi mww 0x4a010048 0x00000400
+	$::_CHIPNAME.axi mww 0x4a01004c 0x00000600
+}
+
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+# Uses AXI
+proc _rcc_enable_traceclk {} {
+	# set bit TRACEEN in RCC_DBGCFGR to clock TPIU
+	target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0
+}
+
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP0
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80010004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return;
+	}
+
+	if { $halt } {
+		if { $::EN_CA35_0 || $::EN_CA35_1 } {
+			$::_CHIPNAME.ap0 arp_examine
+			$::_CHIPNAME.ap0 arp_halt
+		}
+		if { $::EN_CA35_0 } {
+			$::_CHIPNAME.ap0 mww 0x80210300 0
+			target_mmw $::_CHIPNAME.ap0 0x80210088 0x00004000 0
+		}
+		if { $::EN_CA35_1 } {
+			$::_CHIPNAME.ap0 mww 0x80310300 0
+			target_mmw $::_CHIPNAME.ap0 0x80310088 0x00004000 0
+		}
+		if { $::EN_CM33 } {
+			$::_CHIPNAME.ap8 arp_examine
+			$::_CHIPNAME.ap8 arp_halt
+			$::_CHIPNAME.ap8 mww 0xe000edf0 0xa05f0001
+		}
+	}
+
+	# alert wrapper that debugger is ready
+	$::_CHIPNAME.ap0 mww 0x80010004 0x17
+}
+
+$_CHIPNAME.m33 configure -event reset-assert { }
+
+$_CHIPNAME.axi configure -event reset-assert-post {
+	adapter assert srst
+}
+
+$_CHIPNAME.axi configure -event reset-deassert-pre {
+	adapter deassert srst deassert trst
+
+	$::_CHIPNAME.ap0 arp_examine
+	_handshake_with_wrapper $halt
+
+	$::_CHIPNAME.axi arp_examine
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35_0 } {
+		$::_CHIPNAME.a35_0 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.a35_0 arp_halt
+		}
+	}
+	if { $::EN_CA35_1 } {
+		$::_CHIPNAME.a35_1 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.a35_1 arp_halt
+		}
+	}
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap8 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.m33 arp_halt
+		}
+	}
+}
+
+$_CHIPNAME.axi configure -event examine-end {
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35_0 } {
+		$::_CHIPNAME.a35_0 arp_examine
+	}
+	if { $::EN_CA35_1 } {
+		$::_CHIPNAME.a35_1 arp_examine
+	}
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap8 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+	}
+}
diff --git a/tcl/target/st/stm32mp25x.cfg b/tcl/target/st/stm32mp25x.cfg
new file mode 100644
index 000000000..6807d64a1
--- /dev/null
+++ b/tcl/target/st/stm32mp25x.cfg
@@ -0,0 +1,247 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP25x
+# STM32MP25x devices support both JTAG and SWD transports.
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp25x
+}
+
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA35_0] } {
+	set EN_CA35_0 1
+}
+if { ! [info exists EN_CA35_1] } {
+	set EN_CA35_1 1
+}
+if { ! [info exists EN_CM33] } {
+	set EN_CM33   1
+}
+if { ! [info exists EN_CM0P] } {
+	set EN_CM0P   1
+}
+
+set _ENDIAN little
+
+# jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x16505041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f
+if { [using_jtag] } {
+	swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+# define AXI & APB Memory Access Ports
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 4
+target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+target create $_CHIPNAME.ap8 mem_ap -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+
+# define the first Cortex-A35
+cti create $_CHIPNAME.cti.a35_0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80220000
+target create $_CHIPNAME.a35_0 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80210000 \
+	-cti $_CHIPNAME.cti.a35_0 -defer-examine
+
+# define the second Cortex-A35
+cti create $_CHIPNAME.cti.a35_1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80320000
+target create $_CHIPNAME.a35_1 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80310000 \
+	-cti $_CHIPNAME.cti.a35_1 -defer-examine
+
+# define the Cortex-M33
+target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr 0xe0042000
+
+# define the Cortex-M0+
+target create $_CHIPNAME.m0p cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+cti create $_CHIPNAME.cti.m0p -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xf0000000
+
+# define the system CTIs
+cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80090000
+cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800a0000
+
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800b0000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80050000
+
+targets $_CHIPNAME.a35_0
+
+target smp $_CHIPNAME.a35_0 $_CHIPNAME.a35_1
+$_CHIPNAME.a35_0 configure -rtos hwthread
+$_CHIPNAME.a35_1 configure -rtos hwthread
+
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# wait 1 seconds for bootrom
+adapter srst delay 1000
+
+# set CSW for AXI
+$_CHIPNAME.dap apsel 4
+$_CHIPNAME.dap apcsw 0x12800000
+
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_ap2_cm0p
+proc _enable_ap2_cm0p {} {
+	# set bits C3LPEN and C3EN in RCC_C3CFGR to enable AP2 and CM0+ clock
+	target_mmw $::_CHIPNAME.axi 0x54200490 6 0
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP0 and AXI
+proc _enable_debug {} {
+	# set debug enable bits in DBGMCU_CR to get ap2/cm0+ and ap8/cm33 visible
+	# set DBG_SWD_SEL_N bit in DBGMCU_CR to get ap2/cm0+ on main debug interface
+	$::_CHIPNAME.ap0 mww 0x80010004 0x17
+
+	if { $::EN_CM0P } {
+		_enable_ap2_cm0p
+	}
+
+	# Freeze watchdogs on CPU halt
+	$::_CHIPNAME.axi mww 0x4a010008 0x00000000
+	$::_CHIPNAME.axi mww 0x4a01003c 0x00000026
+	$::_CHIPNAME.axi mww 0x4a010040 0x00000038
+	$::_CHIPNAME.axi mww 0x4a010044 0x00000400
+	$::_CHIPNAME.axi mww 0x4a010048 0x00000400
+	$::_CHIPNAME.axi mww 0x4a01004c 0x00000600
+}
+
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+# Uses AXI
+proc _rcc_enable_traceclk {} {
+	# set bit TRACEEN in RCC_DBGCFGR to clock TPIU
+	target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0
+}
+
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP0
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80010004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return;
+	}
+
+	if { $halt } {
+		if { $::EN_CA35_0 || $::EN_CA35_1 } {
+			$::_CHIPNAME.ap0 arp_examine
+			$::_CHIPNAME.ap0 arp_halt
+		}
+		if { $::EN_CA35_0 } {
+			$::_CHIPNAME.ap0 mww 0x80210300 0
+			target_mmw $::_CHIPNAME.ap0 0x80210088 0x00004000 0
+		}
+		if { $::EN_CA35_1 } {
+			$::_CHIPNAME.ap0 mww 0x80310300 0
+			target_mmw $::_CHIPNAME.ap0 0x80310088 0x00004000 0
+		}
+		if { $::EN_CM33 } {
+			$::_CHIPNAME.ap8 arp_examine
+			$::_CHIPNAME.ap8 arp_halt
+			$::_CHIPNAME.ap8 mww 0xe000edf0 0xa05f0001
+		}
+	}
+
+	# alert wrapper that debugger is ready
+	$::_CHIPNAME.ap0 mww 0x80010004 0x17
+}
+
+$_CHIPNAME.m33 configure -event reset-assert { }
+$_CHIPNAME.m0p configure -event reset-assert { }
+
+$_CHIPNAME.axi configure -event reset-assert-post {
+	adapter assert srst
+}
+
+$_CHIPNAME.axi configure -event reset-deassert-pre {
+	adapter deassert srst deassert trst
+
+	$::_CHIPNAME.ap0 arp_examine
+	_handshake_with_wrapper $halt
+
+	$::_CHIPNAME.axi arp_examine
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35_0 } {
+		$::_CHIPNAME.a35_0 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.a35_0 arp_halt
+		}
+	}
+	if { $::EN_CA35_1 } {
+		$::_CHIPNAME.a35_1 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.a35_1 arp_halt
+		}
+	}
+	if { $::EN_CM0P } {
+		$::_CHIPNAME.ap2 arp_examine
+		$::_CHIPNAME.m0p arp_examine
+	}
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap8 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.m33 arp_halt
+		}
+	}
+}
+
+$_CHIPNAME.m0p configure -event examine-start {
+	_enable_ap2_cm0p
+}
+
+$_CHIPNAME.axi configure -event examine-end {
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35_0 } {
+		$::_CHIPNAME.a35_0 arp_examine
+	}
+	if { $::EN_CA35_1 } {
+		$::_CHIPNAME.a35_1 arp_examine
+	}
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap8 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+	}
+	if { $::EN_CM0P } {
+		$::_CHIPNAME.ap2 arp_examine
+		$::_CHIPNAME.m0p arp_examine
+	}
+}

commit f11b677decdb78fa70c980640daef8757312c1e6
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jul 4 16:34:29 2025 +0200

    tcl: stm32mp15x: modify handshake to open debug port, add hwthread
    
    Align the target script to the handshake implemented in the latest
    version of stm32wrapper4dbg to get access to the debug port.
    
    Use hwthread with the SMP node.
    
    Allow ignoring/masking some CPU from the configuration with the
    variables EN_<cpu>.
    
    Change-Id: I7117dd7df20b4f6b6e28f911e3e91ee763bdd200
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8984
    Tested-by: jenkins

diff --git a/tcl/target/st/stm32mp15x.cfg b/tcl/target/st/stm32mp15x.cfg
index bcdda73e9..979a5a491 100644
--- a/tcl/target/st/stm32mp15x.cfg
+++ b/tcl/target/st/stm32mp15x.cfg
@@ -18,6 +18,17 @@ if { [info exists CHIPNAME] } {
 	set _CHIPNAME stm32mp15x
 }
 
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA7_0] } {
+	set EN_CA7_0 1
+}
+if { ! [info exists EN_CA7_1] } {
+	set EN_CA7_1 1
+}
+if { ! [info exists EN_CM4] } {
+	set EN_CM4   1
+}
+
 if { [info exists CPUTAPID] } {
 	set _CPUTAPID $CPUTAPID
 } else {
@@ -42,20 +53,21 @@ if { [using_jtag] } {
 
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
 
-# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
-# so defer-examine it until the reset framework get merged
 # NOTE: keep ap-num and dbgbase to speed-up examine after reset
 # NOTE: do not change the order of target create
 target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
 target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
 target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
-target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
-target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
+target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000 -defer-examine
+target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000 -defer-examine
 target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
 
 targets $_CHIPNAME.cpu0
 
 target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
+$_CHIPNAME.cpu0 configure -rtos hwthread
+$_CHIPNAME.cpu1 configure -rtos hwthread
+
 $_CHIPNAME.cpu0 cortex_a maskisr on
 $_CHIPNAME.cpu1 cortex_a maskisr on
 $_CHIPNAME.cpu0 cortex_a dacrfixup on
@@ -96,7 +108,16 @@ proc axi_nsecure {} {
 
 axi_secure
 
-proc dbgmcu_enable_debug {} {
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP1
+proc _enable_debug {} {
 	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
 	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
 	# freeze watchdog 1 and 2 on cores halted
@@ -104,30 +125,97 @@ proc dbgmcu_enable_debug {} {
 	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
 }
 
-proc toggle_cpu0_dbg_claim0 {} {
-	# toggle CPU0 DBG_CLAIM[0]
-	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
-	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP1
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap1 read_memory 0xe0081004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return
+	}
+
+	if { $halt }  {
+		$::_CHIPNAME.ap1 arp_halt
+		if { $::EN_CA7_0 } {
+			$::_CHIPNAME.ap1 arp_halt
+			$::_CHIPNAME.ap1 mww 0xe00d0300 0
+			target_mmw $::_CHIPNAME.ap1 0xe00d0088 0x00004000 0
+		}
+	}
+
+	$::_CHIPNAME.ap1 mww 0xe0081004 0x7
 }
 
-proc detect_cpu1 {} {
+lappend _telnet_autocomplete_skip _detect_cpu1
+# Uses AP1
+proc _detect_cpu1 {} {
+	if { !$::EN_CA7_1 } {
+		return
+	}
+
 	set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
 	set dual_core [expr {$cpu1_prsr & 1}]
-	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
+	if { !$dual_core } {
+		set ::EN_CA7_1 0
+	}
 }
 
-proc rcc_enable_traceclk {} {
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+proc _rcc_enable_traceclk {} {
 	$::_CHIPNAME.ap2 mww 0x5000080c 0x301
 }
 
 # FIXME: most of handler below will be removed once reset framework get merged
-$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
-$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
-$_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
-$_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
-$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
-$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
-$_CHIPNAME.ap1  configure -event examine-start       {dap init}
-$_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
-$_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
-$_CHIPNAME.ap2  configure -event examine-end         {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}
+$_CHIPNAME.cm4  configure -event reset-assert { }
+
+$_CHIPNAME.ap1  configure -event reset-assert-post {
+	adapter assert srst
+}
+
+$_CHIPNAME.ap1  configure -event reset-deassert-pre {
+	adapter deassert srst deassert trst
+	$::_CHIPNAME.ap1 arp_examine
+	_handshake_with_wrapper $halt
+	if { $::EN_CA7_0 } {
+		$::_CHIPNAME.cpu0 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.cpu0 arp_halt
+		}
+	}
+	if { $::EN_CA7_1 } {
+		$::_CHIPNAME.cpu1 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.cpu1 arp_halt
+		}
+	}
+	_enable_debug
+}
+
+$_CHIPNAME.ap2  configure -event reset-deassert-pre {
+	_rcc_enable_traceclk
+	if { $::EN_CM4 } {
+		$::_CHIPNAME.cm4 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.cm4 arp_halt
+		}
+	}
+}
+
+$_CHIPNAME.ap1 configure -event examine-end {
+	_enable_debug
+	_detect_cpu1
+	if { $::EN_CA7_0 } {
+		$::_CHIPNAME.cpu0 arp_examine
+	}
+	if { $::EN_CA7_1 } {
+		$::_CHIPNAME.cpu1 arp_examine
+	}
+}
+
+$_CHIPNAME.ap2  configure -event examine-end {
+	_rcc_enable_traceclk
+	if { $::EN_CM4 } {
+		$::_CHIPNAME.cm4 arp_examine
+	}
+}

-----------------------------------------------------------------------

Summary of changes:
 .../st/{nucleo-u083rc.cfg => stm32mp235f-dk.cfg}   |   6 +-
 .../{st_nucleo_wb55.cfg => st/stm32mp257f-dk.cfg}  |   7 +-
 tcl/target/st/stm32mp15x.cfg                       | 132 +++++++++--
 tcl/target/st/stm32mp21x.cfg                       | 222 ++++++++++++++++++
 tcl/target/st/stm32mp23x.cfg                       | 215 ++++++++++++++++++
 tcl/target/st/stm32mp25x.cfg                       | 247 +++++++++++++++++++++
 6 files changed, 800 insertions(+), 29 deletions(-)
 copy tcl/board/st/{nucleo-u083rc.cfg => stm32mp235f-dk.cfg} (50%)
 copy tcl/board/{st_nucleo_wb55.cfg => st/stm32mp257f-dk.cfg} (54%)
 create mode 100644 tcl/target/st/stm32mp21x.cfg
 create mode 100644 tcl/target/st/stm32mp23x.cfg
 create mode 100644 tcl/target/st/stm32mp25x.cfg


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1091-g5d3f53363

From: openocd-gerrit <ope...@us...> - 2025-07-25 16:52:13

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The branch, master has been updated
       via  5d3f53363bc461fbc88f4e690c08f85057e17f5d (commit)
       via  9bb6fa67ca6de6f725df78ac8a415b5b47fb9420 (commit)
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- Log -----------------------------------------------------------------
commit 5d3f53363bc461fbc88f4e690c08f85057e17f5d
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jul 4 16:29:47 2025 +0200

    tcl: stm32mp13x: modify handshake to open debug port
    
    Align the target script to the handshake implemented in the latest
    version of stm32wrapper4dbg to get access to the debug port.
    
    Change-Id: Ia1c7773330fda776abb4385331fddbf431d11c39
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8983
    Tested-by: jenkins

diff --git a/tcl/target/st/stm32mp13x.cfg b/tcl/target/st/stm32mp13x.cfg
index bcf25c904..164e0ff1f 100644
--- a/tcl/target/st/stm32mp13x.cfg
+++ b/tcl/target/st/stm32mp13x.cfg
@@ -46,7 +46,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
 # NOTE: do not change the order of target create
 target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
 target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
-target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
+target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000 -defer-examine
 
 $_CHIPNAME.cpu cortex_a maskisr on
 $_CHIPNAME.cpu cortex_a dacrfixup on
@@ -76,27 +76,59 @@ proc axi_nsecure {} {
 
 axi_secure
 
-proc dbgmcu_enable_debug {} {
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP1
+proc _enable_debug {} {
 	# keep clock enabled in low-power
-	## catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
+	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
 	# freeze watchdog 1 and 2 on core halted
 	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
 	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
 }
 
-proc toggle_cpu_dbg_claim0 {} {
-	# toggle CPU0 DBG_CLAIM[0]
-	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
-	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP1
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap1 read_memory 0xe0081004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return
+	}
+
+	if { $halt } {
+		$::_CHIPNAME.ap1 arp_halt
+		$::_CHIPNAME.ap1 mww 0xe00d0300 0
+		target_mmw $::_CHIPNAME.ap1 0xe00d0088 0x00004000 0
+	}
+
+	$::_CHIPNAME.ap1 mww 0xe0081004 0x7
 }
 
 # FIXME: most of handlers below will be removed once reset framework get merged
+$_CHIPNAME.ap1 configure -event reset-assert-post {
+	adapter assert srst
+}
+
 $_CHIPNAME.ap1 configure -event reset-deassert-pre {
 	adapter deassert srst deassert trst
-	catch {dap init}
-	catch {$::_CHIPNAME.dap apid 1}
+	$::_CHIPNAME.ap1 arp_examine
+	_handshake_with_wrapper $halt
+	_enable_debug
+	$::_CHIPNAME.cpu arp_examine
+	if { $halt } {
+		$::_CHIPNAME.cpu arp_halt
+	}
+}
+
+$_CHIPNAME.ap1 configure -event examine-end {
+	_enable_debug
+	$::_CHIPNAME.cpu arp_examine
 }
-$_CHIPNAME.cpu configure -event reset-deassert-pre  {$::_CHIPNAME.cpu arp_examine}
-$_CHIPNAME.cpu configure -event reset-deassert-post {toggle_cpu_dbg_claim0; dbgmcu_enable_debug}
-$_CHIPNAME.ap1 configure -event examine-start       {dap init}
-$_CHIPNAME.ap1 configure -event examine-end         {dbgmcu_enable_debug}

commit 9bb6fa67ca6de6f725df78ac8a415b5b47fb9420
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jul 4 16:50:46 2025 +0200

    tcl: move STM32 MPU files in vendor folder
    
    Move the existing files for STM32MP13x and STM32MP15x in the
    folder "st".
    Rename the board files using the correct names.
    While there, add the missing URL to one of the boards.
    
    Change-Id: If8b92f55e3390ebc75df6a2ea09fcf798ea0b8cf
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8982
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>

diff --git a/tcl/board/stm32mp13x_dk.cfg b/tcl/board/st/stm32mp135f-dk.cfg
similarity index 83%
rename from tcl/board/stm32mp13x_dk.cfg
rename to tcl/board/st/stm32mp135f-dk.cfg
index 8ece24844..2259e0425 100644
--- a/tcl/board/stm32mp13x_dk.cfg
+++ b/tcl/board/st/stm32mp135f-dk.cfg
@@ -7,6 +7,6 @@ source [find interface/stlink.cfg]
 
 transport select swd
 
-source [find target/stm32mp13x.cfg]
+source [find target/st/stm32mp13x.cfg]
 
 reset_config srst_only
diff --git a/tcl/board/stm32mp15x_dk2.cfg b/tcl/board/st/stm32mp157f-dk2.cfg
similarity index 72%
rename from tcl/board/stm32mp15x_dk2.cfg
rename to tcl/board/st/stm32mp157f-dk2.cfg
index ba1c7f78a..b193ae3a0 100644
--- a/tcl/board/stm32mp15x_dk2.cfg
+++ b/tcl/board/st/stm32mp157f-dk2.cfg
@@ -3,11 +3,12 @@
 # board MB1272B
 # http://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html
 # http://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html
+# http://www.st.com/en/evaluation-tools/stm32mp157f-dk2.html
 
 source [find interface/stlink.cfg]
 
 transport select swd
 
-source [find target/stm32mp15x.cfg]
+source [find target/st/stm32mp15x.cfg]
 
 reset_config srst_only
diff --git a/tcl/file_renaming.cfg b/tcl/file_renaming.cfg
index 0a3c7ba65..20679b6ab 100644
--- a/tcl/file_renaming.cfg
+++ b/tcl/file_renaming.cfg
@@ -17,6 +17,8 @@ set _file_renaming {
 	board/nordic_nrf51822_mkit.cfg	board/nordic/nrf51822-mkit.cfg
 	board/nordic_nrf51_dk.cfg		board/nordic/nrf51-dk.cfg
 	board/nordic_nrf52_dk.cfg		board/nordic/nrf52-dk.cfg
+	board/stm32mp13x_dk.cfg			board/st/stm32mp135f-dk.cfg
+	board/stm32mp15x_dk2.cfg		board/st/stm32mp157f-dk2.cfg
 	target/nrf51.cfg	target/nordic/nrf51.cfg
 	target/nrf52.cfg	target/nordic/nrf52.cfg
 	target/nrf53.cfg	target/nordic/nrf53.cfg
diff --git a/tcl/target/stm32mp13x.cfg b/tcl/target/st/stm32mp13x.cfg
similarity index 100%
rename from tcl/target/stm32mp13x.cfg
rename to tcl/target/st/stm32mp13x.cfg
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/st/stm32mp15x.cfg
similarity index 100%
rename from tcl/target/stm32mp15x.cfg
rename to tcl/target/st/stm32mp15x.cfg

-----------------------------------------------------------------------

Summary of changes:
 .../{stm32mp13x_dk.cfg => st/stm32mp135f-dk.cfg}   |  2 +-
 .../{stm32mp15x_dk2.cfg => st/stm32mp157f-dk2.cfg} |  3 +-
 tcl/file_renaming.cfg                              |  2 +
 tcl/target/{ => st}/stm32mp13x.cfg                 | 58 +++++++++++++++++-----
 tcl/target/{ => st}/stm32mp15x.cfg                 |  0
 5 files changed, 50 insertions(+), 15 deletions(-)
 rename tcl/board/{stm32mp13x_dk.cfg => st/stm32mp135f-dk.cfg} (83%)
 rename tcl/board/{stm32mp15x_dk2.cfg => st/stm32mp157f-dk2.cfg} (72%)
 rename tcl/target/{ => st}/stm32mp13x.cfg (67%)
 rename tcl/target/{ => st}/stm32mp15x.cfg (100%)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1089-g1f56ea647

From: openocd-gerrit <ope...@us...> - 2025-07-25 16:42:51

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The branch, master has been updated
       via  1f56ea647d63b7495d513227622413f1826d75f9 (commit)
       via  6e87864dfc35a1513ffa02972812954e97efdf86 (commit)
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- Log -----------------------------------------------------------------
commit 1f56ea647d63b7495d513227622413f1826d75f9
Author: Liam Fletcher <lia...@mi...>
Date:   Mon May 26 10:42:56 2025 +0100

    tcl: add microchip's pic64gx curiosity config
    
    Microchip's PIC64GX Curiosity Board has a RISC-V core complex with 4
    application processors and one monitor processor. The Curiosity kit also
    has an on-board debug interface based around an FTDI 4232H device.
    
    This patch adds basic target, interface and board support for PIC64GX
    Curiosity Kit.
    
    Change-Id: I2234d8725744fbae00b3909773b370e5c18debd8
    Signed-off-by: Liam Fletcher <lia...@mi...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8878
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/board/microchip/pic64gx-curiosity-kit.cfg b/tcl/board/microchip/pic64gx-curiosity-kit.cfg
new file mode 100644
index 000000000..e7e67ea4b
--- /dev/null
+++ b/tcl/board/microchip/pic64gx-curiosity-kit.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Microchip RISC-V board
+#
+# https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx
+#
+adapter speed 6000
+
+source [find interface/microchip/embedded_flashpro5.cfg]
+source [find target/microchip/pic64gx.cfg]
diff --git a/tcl/target/microchip/pic64gx.cfg b/tcl/target/microchip/pic64gx.cfg
new file mode 100644
index 000000000..25cef6b23
--- /dev/null
+++ b/tcl/target/microchip/pic64gx.cfg
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: Pic64gx processor by Microchip Technologies
+#
+# https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME pic64gx
+}
+
+# Process COREID variable
+if {![exists COREID]} {
+	set COREID -1
+}
+
+transport select jtag
+
+# PIC64GX hart id to name lookup table
+array set hart_names {
+	0	e51
+	1	u54_1
+	2	u54_2
+	3	u54_3
+	4	u54_4
+}
+
+# PIC64GX table
+set pic64gx_tap_info {
+	PIC64GX1000 0x0f8531cf
+}
+
+proc expected_ids {tap_list} {
+	set str ""
+	dict for {key value} $tap_list {
+		append str "-expected-id" " " $value " "
+	}
+
+	return $str
+}
+
+set irlen 8
+set expected_ids [expected_ids $pic64gx_tap_info]
+eval jtag newtap $_CHIPNAME cpu -irlen $irlen $expected_ids -ignore-version
+
+if {$COREID == -1} {
+	# Single debug connection to all harts
+	set _TARGETNAME_0 $_CHIPNAME.$hart_names(0)
+	set _TARGETNAME_1 $_CHIPNAME.$hart_names(1)
+	set _TARGETNAME_2 $_CHIPNAME.$hart_names(2)
+	set _TARGETNAME_3 $_CHIPNAME.$hart_names(3)
+	set _TARGETNAME_4 $_CHIPNAME.$hart_names(4)
+
+	target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -rtos hwthread
+	target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 -rtos hwthread
+	target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 2 -rtos hwthread
+	target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 3 -rtos hwthread
+	target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu -coreid 4 -rtos hwthread
+	target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4
+} else {
+	# Debug connection to a specific hart
+	set _TARGETNAME_0 $_CHIPNAME.$hart_names($COREID)
+	target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid $COREID
+}
+
+# Only TRSTn supported
+reset_config trst_only

commit 6e87864dfc35a1513ffa02972812954e97efdf86
Author: Liam Fletcher <lia...@mi...>
Date:   Mon May 26 10:54:40 2025 +0100

    tcl: add embedded flashpro5 config
    
    To support Microchips Embedded Flashpro5
    
    Change-Id: I7861e0772fd4cbf0539725d238c59ae15bbcca41
    Signed-off-by: Liam Fletcher <lia...@mi...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8879
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/contrib/60-openocd.rules b/contrib/60-openocd.rules
index 29f8d7a6d..6632841a4 100644
--- a/contrib/60-openocd.rules
+++ b/contrib/60-openocd.rules
@@ -190,6 +190,10 @@ ATTRS{idVendor}=="138e", ATTRS{idProduct}=="9000", MODE="660", GROUP="plugdev",
 # Debug Board for Neo1973
 ATTRS{idVendor}=="1457", ATTRS{idProduct}=="5118", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
+# Microchip RISC-V Debug
+ATTRS{idVendor}=="1514", ATTRS{idProduct}=="2008", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1514", ATTRS{idProduct}=="200a", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
 # OSBDM
 ATTRS{idVendor}=="15a2", ATTRS{idProduct}=="0042", MODE="660", GROUP="plugdev", TAG+="uaccess"
 ATTRS{idVendor}=="15a2", ATTRS{idProduct}=="0058", MODE="660", GROUP="plugdev", TAG+="uaccess"
diff --git a/tcl/interface/microchip/embedded_flashpro5.cfg b/tcl/interface/microchip/embedded_flashpro5.cfg
new file mode 100644
index 000000000..117a54458
--- /dev/null
+++ b/tcl/interface/microchip/embedded_flashpro5.cfg
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Embedded FlashPro5
+#
+# https://www.microchip.com/en-us/development-tool/flashpro5
+#
+
+adapter driver ftdi
+
+# vidpid 1514:2008 = embedded flashpro5
+# vidpid 1514:200a = pic64gx
+ftdi vid_pid 0x1514 0x2008 0x1514 0x200a
+
+# That FTDI has 4 channels (channel 0 and 1 are MPSSE-capable, 2 and 3 are bitbang
+ftdi channel 0
+
+# Initial Layout - data[0..15] direction[0..15]
+ftdi layout_init 0x0018 0xfdfb
+#     Signal        Data    Direction       Notes
+# AD0 TCK           0       1 (out)         Port A TCK
+# AD1 TDI           0       1 (out)         Port A TDI
+# AD2 TDO           0       0 (in)          PORT A TDO
+# AD3 TMS           1       1 (out)         Port A TMS
+# AD4 GPIOL0        1       1 (out)         Port A TRST
+# AD5 GPIOL1        0       1 (out)         (unused)
+# AD6 GPIOL2        0       1 (out)         (unused)
+# AD7 GPIOL3        0       1 (out)         (unused)
+
+# BD0 TCK           0       1 (out)         FTDI_UART_B_TXD
+# BD1 TDI           0       0 (in)          FTDI_UART_B_RXD
+# BD2 TDO           0       1 (out)         (unused)
+# BD3 TMS           0       1 (out)         (unused)
+# BD4 GPIOL0        0       1 (out)         (unused)
+# BD5 GPIOL1        0       1 (out)         (unused)
+# BD6 GPIOL2        0       1 (out)         (unused)
+# BD7 GPIOL2        0       1 (out)         (unused)
+
+# Signals definition
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010

-----------------------------------------------------------------------

Summary of changes:
 contrib/60-openocd.rules                       |  4 +++
 tcl/board/microchip/pic64gx-curiosity-kit.cfg  | 10 +++++++
 tcl/interface/microchip/embedded_flashpro5.cfg | 40 ++++++++++++++++++++++++++
 tcl/target/microchip/{mpfs.cfg => pic64gx.cfg} | 26 +++++++----------
 4 files changed, 64 insertions(+), 16 deletions(-)
 create mode 100644 tcl/board/microchip/pic64gx-curiosity-kit.cfg
 create mode 100644 tcl/interface/microchip/embedded_flashpro5.cfg
 copy tcl/target/microchip/{mpfs.cfg => pic64gx.cfg} (73%)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1087-gd06ecba2e

From: openocd-gerrit <ope...@us...> - 2025-07-25 16:42:19

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The branch, master has been updated
       via  d06ecba2e62f3e1de914dd9ef019b85ea422d483 (commit)
      from  a192949095b3fc10a3916ee1d52d92d3b019fbea (commit)

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- Log -----------------------------------------------------------------
commit d06ecba2e62f3e1de914dd9ef019b85ea422d483
Author: Liam Fletcher <lia...@mi...>
Date:   Mon May 26 10:30:07 2025 +0100

    target: add microchip polarfire soc config
    
    Microchip's PolarFire SoC has a RISC-V core complex with four
    application processors and one monitor processor. This basic
    configuration can be used to attach to all proccessor's or a single
    processor, specified by the run-time argument $COREID
    
    It can be used with most FTDI based debug interfaces and has been tested
    with interface/ftdi/olimex-arm-usb-tiny-h.cfg.
    
    Change-Id: I75dd965f1ce550807706d00fe17de887d36f0b02
    Signed-off-by: Liam Fletcher <lia...@mi...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8877
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/microchip/mpfs.cfg b/tcl/target/microchip/mpfs.cfg
new file mode 100644
index 000000000..3a63e3d3b
--- /dev/null
+++ b/tcl/target/microchip/mpfs.cfg
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: MPFS PolarFire SoC-series processors by Microchip Technologies
+#
+# https://www.microchip.com/en-us/products/fpgas-and-plds/system-on-chip-fpgas/polarfire-soc-fpgas
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME mpfs
+}
+
+# Process COREID variable
+if { ![exists COREID] } {
+	set COREID -1
+}
+
+transport select jtag
+
+# PolarFire SoC (MPFS) hart id to name lookup table
+array set hart_names {
+	0	e51
+	1	u54_1
+	2	u54_2
+	3	u54_3
+	4	u54_4
+}
+
+# MPFS devices table
+set mpfs_cpu_tap_info {
+	MPFS025  0x0f8531cf
+	MPFS095  0x0f8181cf
+	MPFS160  0x0f8191cf
+	MPFS250  0x0f81a1cf
+	MPFS460  0x0f81b1cf
+	RTPFS160 0x0f8991cf
+	RTPFS460 0x0f89b1cf
+}
+
+proc expected_ids {tap_list} {
+	set str ""
+	dict for {key value} $tap_list {
+		append str "-expected-id" " " $value " "
+	}
+
+	return $str
+}
+
+set irlen 8
+set expected_ids [expected_ids $mpfs_cpu_tap_info]
+eval jtag newtap $_CHIPNAME cpu -irlen $irlen $expected_ids -ignore-version
+
+if {$COREID == -1} {
+	# Single debug connection to all HART's
+	set _TARGETNAME_0 $_CHIPNAME.$hart_names(0)
+	set _TARGETNAME_1 $_CHIPNAME.$hart_names(1)
+	set _TARGETNAME_2 $_CHIPNAME.$hart_names(2)
+	set _TARGETNAME_3 $_CHIPNAME.$hart_names(3)
+	set _TARGETNAME_4 $_CHIPNAME.$hart_names(4)
+
+	target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -rtos hwthread
+	target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 -rtos hwthread
+	target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 2 -rtos hwthread
+	target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 3 -rtos hwthread
+	target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu -coreid 4 -rtos hwthread
+	target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4
+} else {
+	# Debug connection to a specific hart
+	set _TARGETNAME_0 $_CHIPNAME.$hart_names($COREID)
+	target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid $COREID
+}
+
+# Only TRSTn supported
+reset_config trst_only

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/microchip/mpfs.cfg | 75 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 tcl/target/microchip/mpfs.cfg


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1086-ga19294909

From: openocd-gerrit <ope...@us...> - 2025-07-25 16:39:12

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The branch, master has been updated
       via  a192949095b3fc10a3916ee1d52d92d3b019fbea (commit)
       via  8cdf8cb99567654ff2b33feb781680159c9fbd63 (commit)
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- Log -----------------------------------------------------------------
commit a192949095b3fc10a3916ee1d52d92d3b019fbea
Author: Nicolas Derumigny <nic...@in...>
Date:   Tue Nov 5 15:49:04 2024 +0000

    jtag: drivers: xlnx-axi-xvc: Add support for Xilinx XVC over direct bus interface (AXI)
    
    This change allow to use direct mapping of the JTAG interface using
    Xilinx Virtual Cable (XVC) over AXI. This merges the existing XVC PCIe
    code and the patch proposed by Jeremy Garff
    (https://review.openocd.org/c/openocd/+/6594).
    
    This is useful when using on a Zynq/ZynqMP/uBlaze host with direct
    access to the debug bridge over AXI.  You can then use the debug bridge
    Xilinx IP (AXIXVC) to debug a remote device.
    
    Signed-off-by: Nicolas Derumigny <nic...@in...>
    Change-Id: I934591b489e30b400b87772b1437e6030440904c
    Reviewed-on: https://review.openocd.org/c/openocd/+/8595
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index 9bbb2c36a..df94e20b8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -177,8 +177,8 @@ m4_define([REMOTE_BITBANG_ADAPTER],
 m4_define([LIBJAYLINK_ADAPTERS],
 	[[[jlink], [SEGGER J-Link Programmer], [JLINK]]])
 
-m4_define([PCIE_ADAPTERS],
-	[[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_XVC]]])
+m4_define([XVC_ADAPTERS],
+	[[[xlnx_xvc], [Xilinx XVC PCIe and AXI drives], [XLNX_XVC]]])
 
 m4_define([SERIAL_PORT_ADAPTERS],
 	[[[buspirate], [Bus Pirate], [BUS_PIRATE]]])
@@ -335,7 +335,7 @@ AC_ARG_ADAPTERS([
   JTAG_DPI_ADAPTER,
   JTAG_VPI_ADAPTER,
   RSHIM_ADAPTER,
-  PCIE_ADAPTERS,
+  XVC_ADAPTERS,
   LIBJAYLINK_ADAPTERS
   ],[auto])
 
@@ -644,7 +644,7 @@ PROCESS_ADAPTERS([DMEM_ADAPTER], ["x$is_linux" = "xyes"], [Linux /dev/mem])
 PROCESS_ADAPTERS([SYSFSGPIO_ADAPTER], ["x$is_linux" = "xyes"], [Linux sysfs])
 PROCESS_ADAPTERS([REMOTE_BITBANG_ADAPTER], [true], [unused])
 PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o "x$use_libjaylink" = "xyes"], [libjaylink-0.2])
-PROCESS_ADAPTERS([PCIE_ADAPTERS], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_pci_h" = "xyes"], [Linux build])
+PROCESS_ADAPTERS([XVC_ADAPTERS], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_pci_h" = "xyes"], [Linux build])
 PROCESS_ADAPTERS([SERIAL_PORT_ADAPTERS], ["x$can_build_buspirate" = "xyes"],
                                          [internal error: validation should happen beforehand])
 PROCESS_ADAPTERS([LINUXSPIDEV_ADAPTER], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_spi_spidev_h" = "xyes"],
@@ -840,7 +840,8 @@ m4_foreach([adapterTuple], [USB1_ADAPTERS,
 	DMEM_ADAPTER,
 	SYSFSGPIO_ADAPTER,
 	REMOTE_BITBANG_ADAPTER,
-	LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, SERIAL_PORT_ADAPTERS,
+	LIBJAYLINK_ADAPTERS, XVC_ADAPTERS,
+	SERIAL_PORT_ADAPTERS,
 	LINUXSPIDEV_ADAPTER,
 	VDEBUG_ADAPTER,
 	JTAG_DPI_ADAPTER,
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 6d607d697..90ed9d3b6 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -613,6 +613,12 @@ emulation model of target hardware.
 
 @item @b{xlnx_pcie_xvc}
 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
+@* Link: @url{https://www.xilinx.com/products/intellectual-property/debug-bridge.html}
+
+@item @b{xlnx_axi_xvc}
+@* A JTAG driver exposing JTAG to OpenOCD over AXI-mapped registers.
+@* Link: @url{https://docs.amd.com/r/en-US/pg437-axi-jtag/Introduction}
+@* Link: @url{https://china.xilinx.com/support/documentation/application_notes/xapp1251-xvc-zynq-petalinux.pdf}
 
 @item @b{linuxspidev}
 @* A SPI based SWD driver using Linux SPI devices.
@@ -3352,6 +3358,21 @@ The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
 @end deffn
 @end deffn
 
+@deffn {Interface Driver} {xlnx_axi_xvc}
+This driver supports the Xilinx JTAG mapping over AXI using the AXI to JTAG
+Converter or the AXI-to-JTAG mode of the debug bridge.
+It is commonly found in Xilinx MPSoC based designs. It allows debugging
+fabric based JTAG/SWD devices such as Cortex-M1/M3 or RISC-V softcores. Access to this
+is exposed via extended capability registers in the AXI-mapped configuration space.
+
+@deffn {Config Command} {xlnx_axi_xvc dev_addr} addr
+Specifies the address of the AXI-mapped registers via parameter @var{addr}.
+
+The correct value for @var{addr} is specified in the "Address Editor" tab
+in Vivado.
+@end deffn
+@end deffn
+
 @deffn {Interface Driver} {bcm2835gpio}
 This GPIO interface is present in Raspberry Pi 0-4 which is a cheap
 single-board computer exposing some GPIOs on its expansion header.
diff --git a/src/jtag/drivers/xlnx-xvc.c b/src/jtag/drivers/xlnx-xvc.c
index 5208e2b87..6b3359538 100644
--- a/src/jtag/drivers/xlnx-xvc.c
+++ b/src/jtag/drivers/xlnx-xvc.c
@@ -1,8 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
 /*
- * Copyright (c) 2019 Google, LLC.
- * Author: Moritz Fischer <mo...@go...>
+ *	 Copyright (C) 2019 Google, LLC.
+ *	 Moritz Fischer <mo...@go...>
+ *
+ *	 Copyright (C) 2021 Western Digital Corporation or its affiliates
+ *	 Jeremy Garff <jer...@wd...>
+ *
+ *	 Copyright (C) 2024 Inria
+ *	 Nicolas Derumigny <nic...@in...>
  */
 
 #ifdef HAVE_CONFIG_H
@@ -11,13 +17,14 @@
 
 #include <stdint.h>
 #include <stdlib.h>
-#include <math.h>
 #include <unistd.h>
 #include <linux/pci.h>
+#include <sys/mman.h>
 
 #include <jtag/interface.h>
-#include <jtag/swd.h>
 #include <jtag/commands.h>
+#include <jtag/interface.h>
+#include <jtag/swd.h>
 #include <helper/replacements.h>
 #include <helper/bits.h>
 
@@ -28,14 +35,24 @@
 
 #define PCIE_EXT_CAP_LST	0x100
 
-#define XLNX_XVC_EXT_CAP	0x00
-#define XLNX_XVC_VSEC_HDR	0x04
-#define XLNX_XVC_LEN_REG	0x0C
-#define XLNX_XVC_TMS_REG	0x10
-#define XLNX_XVC_TDX_REG	0x14
+#define XLNX_PCIE_XVC_EXT_CAP	0x00
+#define XLNX_PCIE_XVC_VSEC_HDR	0x04
+#define XLNX_PCIE_XVC_LEN_REG	0x0C
+#define XLNX_PCIE_XVC_TMS_REG	0x10
+#define XLNX_PCIE_XVC_TDX_REG	0x14
+
+#define XLNX_PCIE_XVC_CAP_SIZE	0x20
+#define XLNX_PCIE_XVC_VSEC_ID	0x8
+
+#define XLNX_AXI_XVC_LEN_REG	0x00
+#define XLNX_AXI_XVC_TMS_REG	0x04
+#define XLNX_AXI_XVC_TDI_REG	0x08
+#define XLNX_AXI_XVC_TDO_REG	0x0c
+#define XLNX_AXI_XVC_CTRL_REG	0x10
+#define XLNX_AXI_XVC_MAX_REG	0x18
+
+#define XLNX_AXI_XVC_CTRL_REG_ENABLE_MASK	0x01
 
-#define XLNX_XVC_CAP_SIZE	0x20
-#define XLNX_XVC_VSEC_ID	0x8
 #define XLNX_XVC_MAX_BITS	0x20
 
 #define MASK_ACK(x) (((x) >> 9) & 0x7)
@@ -47,8 +64,23 @@ struct xlnx_pcie_xvc {
 	char *device;
 };
 
+struct xlnx_axi_xvc {
+	int fd;
+	uint32_t *base;
+	char *device_addr;
+	// Defaults to `/dev/mem` if NULL
+	char *device_file;
+};
+
+enum xlnx_xvc_type_t {
+	PCIE,
+	AXI
+};
+
 static struct xlnx_pcie_xvc xlnx_pcie_xvc_state;
 static struct xlnx_pcie_xvc *xlnx_pcie_xvc = &xlnx_pcie_xvc_state;
+static struct xlnx_axi_xvc xlnx_axi_xvc_state;
+static struct xlnx_axi_xvc *xlnx_axi_xvc = &xlnx_axi_xvc_state;
 
 static int xlnx_pcie_xvc_read_reg(const int offset, uint32_t *val)
 {
@@ -60,9 +92,9 @@ static int xlnx_pcie_xvc_read_reg(const int offset, uint32_t *val)
 	 * space accessor functions
 	 */
 	err = pread(xlnx_pcie_xvc->fd, &res, sizeof(res),
-		    xlnx_pcie_xvc->offset + offset);
+			xlnx_pcie_xvc->offset + offset);
 	if (err != sizeof(res)) {
-		LOG_ERROR("Failed to read offset %x", offset);
+		LOG_ERROR("Failed to read offset 0x%x", offset);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
@@ -72,6 +104,19 @@ static int xlnx_pcie_xvc_read_reg(const int offset, uint32_t *val)
 	return ERROR_OK;
 }
 
+static int xlnx_axi_xvc_read_reg(const int offset, uint32_t *val)
+{
+	uintptr_t b = ((uintptr_t)xlnx_axi_xvc->base) + offset;
+	volatile uint32_t *w = (uint32_t *)b;
+
+	if (val) {
+		__atomic_thread_fence(__ATOMIC_SEQ_CST);
+		*val = *w;
+	}
+
+	return ERROR_OK;
+}
+
 static int xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)
 {
 	int err;
@@ -81,9 +126,9 @@ static int xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)
 	 * space accessor functions
 	 */
 	err = pwrite(xlnx_pcie_xvc->fd, &val, sizeof(val),
-		     xlnx_pcie_xvc->offset + offset);
+			 xlnx_pcie_xvc->offset + offset);
 	if (err != sizeof(val)) {
-		LOG_ERROR("Failed to write offset: %x with value: %" PRIx32,
+		LOG_ERROR("Failed to write offset: 0x%x with value: %" PRIx32,
 			  offset, val);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
@@ -91,37 +136,117 @@ static int xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)
 	return ERROR_OK;
 }
 
+static int xlnx_axi_xvc_write_reg(const int offset, const uint32_t val)
+{
+	uintptr_t b = ((uintptr_t)xlnx_axi_xvc->base) + offset;
+	volatile uint32_t *w = (uint32_t *)b;
+
+	*w = val;
+	__atomic_thread_fence(__ATOMIC_SEQ_CST);
+
+	return ERROR_OK;
+}
+
 static int xlnx_pcie_xvc_transact(size_t num_bits, uint32_t tms, uint32_t tdi,
 				  uint32_t *tdo)
 {
 	int err;
 
-	err = xlnx_pcie_xvc_write_reg(XLNX_XVC_LEN_REG, num_bits);
+	err = xlnx_pcie_xvc_write_reg(XLNX_PCIE_XVC_LEN_REG, num_bits);
 	if (err != ERROR_OK)
 		return err;
 
-	err = xlnx_pcie_xvc_write_reg(XLNX_XVC_TMS_REG, tms);
+	err = xlnx_pcie_xvc_write_reg(XLNX_PCIE_XVC_TMS_REG, tms);
 	if (err != ERROR_OK)
 		return err;
 
-	err = xlnx_pcie_xvc_write_reg(XLNX_XVC_TDX_REG, tdi);
+	err = xlnx_pcie_xvc_write_reg(XLNX_PCIE_XVC_TDX_REG, tdi);
 	if (err != ERROR_OK)
 		return err;
 
-	err = xlnx_pcie_xvc_read_reg(XLNX_XVC_TDX_REG, tdo);
+	err = xlnx_pcie_xvc_read_reg(XLNX_PCIE_XVC_TDX_REG, tdo);
 	if (err != ERROR_OK)
 		return err;
 
 	if (tdo)
 		LOG_DEBUG_IO("Transact num_bits: %zu, tms: %" PRIx32 ", tdi: %" PRIx32 ", tdo: %" PRIx32,
-			     num_bits, tms, tdi, *tdo);
+				 num_bits, tms, tdi, *tdo);
 	else
 		LOG_DEBUG_IO("Transact num_bits: %zu, tms: %" PRIx32 ", tdi: %" PRIx32 ", tdo: <null>",
-			     num_bits, tms, tdi);
+				 num_bits, tms, tdi);
+	return ERROR_OK;
+}
+
+static int xlnx_axi_xvc_transact(size_t num_bits, uint32_t tms, uint32_t tdi,
+				  uint32_t *tdo)
+{
+	uint32_t ctrl;
+	int done = 0;
+	int err;
+
+	err = xlnx_axi_xvc_write_reg(XLNX_AXI_XVC_LEN_REG, num_bits);
+	if (err != ERROR_OK)
+		return err;
+
+	err = xlnx_axi_xvc_write_reg(XLNX_AXI_XVC_TMS_REG, tms);
+	if (err != ERROR_OK)
+		return err;
+
+	err = xlnx_axi_xvc_write_reg(XLNX_AXI_XVC_TDI_REG, tdi);
+	if (err != ERROR_OK)
+		return err;
+
+	err = xlnx_axi_xvc_write_reg(XLNX_AXI_XVC_CTRL_REG, XLNX_AXI_XVC_CTRL_REG_ENABLE_MASK);
+	if (err != ERROR_OK)
+		return err;
+
+	while (!done) {
+		err = xlnx_axi_xvc_read_reg(XLNX_AXI_XVC_CTRL_REG, &ctrl);
+		if (err != ERROR_OK)
+			return err;
+
+		if (!(ctrl & XLNX_AXI_XVC_CTRL_REG_ENABLE_MASK))
+			done = 1;
+
+		/*
+		 There is no delay here intentionally.	The usleep()
+		 function doesn't block and burns CPU cycles anyway.
+		 The turnaround time is fast enough at high JTAG rates
+		 that adding the call can slow down the overall
+		 throughput.	So we'll just sacrifice the CPU to get
+		 best performance.
+
+		 Additionally there is no timeout.	The underlying
+		 hardware is guaranteed to unset the enable bit within
+		 32 JTAG clock cycles.	There is no hardware condition
+		 that will keep it set forever.  Essentially, the hardware
+		 is also our timeout mechanism.
+		*/
+	}
+
+	err = xlnx_axi_xvc_read_reg(XLNX_AXI_XVC_TDO_REG, tdo);
+	if (err != ERROR_OK)
+		return err;
+
+	if (tdo)
+		LOG_DEBUG_IO("Transact num_bits: %zu, tms: 0x%x, tdi: 0x%x, tdo: 0x%x",
+				 num_bits, tms, tdi, *tdo);
+	else
+		LOG_DEBUG_IO("Transact num_bits: %zu, tms: 0x%x, tdi: 0x%x, tdo: <null>",
+				 num_bits, tms, tdi);
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_execute_stableclocks(struct jtag_command *cmd)
+static int xlnx_xvc_transact(size_t num_bits, uint32_t tms, uint32_t tdi,
+		uint32_t *tdo, enum xlnx_xvc_type_t xvc_type)
+{
+	if (xvc_type == PCIE)
+		return xlnx_pcie_xvc_transact(num_bits, tms, tdi, tdo);
+	assert(xvc_type == AXI);
+	return xlnx_axi_xvc_transact(num_bits, tms, tdi, tdo);
+}
+
+static int xlnx_xvc_execute_stableclocks(struct jtag_command *cmd, enum xlnx_xvc_type_t xvc_type)
 {
 	int tms = tap_get_state() == TAP_RESET ? 1 : 0;
 	size_t left = cmd->cmd.stableclocks->num_cycles;
@@ -132,7 +257,7 @@ static int xlnx_pcie_xvc_execute_stableclocks(struct jtag_command *cmd)
 
 	while (left) {
 		write = MIN(XLNX_XVC_MAX_BITS, left);
-		err = xlnx_pcie_xvc_transact(write, tms, 0, NULL);
+		err = xlnx_xvc_transact(write, tms, 0, NULL, xvc_type);
 		if (err != ERROR_OK)
 			return err;
 		left -= write;
@@ -141,12 +266,12 @@ static int xlnx_pcie_xvc_execute_stableclocks(struct jtag_command *cmd)
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_execute_statemove(size_t skip)
+static int xlnx_xvc_execute_statemove(size_t skip, enum xlnx_xvc_type_t xvc_type)
 {
 	uint8_t tms_scan = tap_get_tms_path(tap_get_state(),
-					    tap_get_end_state());
+						tap_get_end_state());
 	int tms_count = tap_get_tms_path_len(tap_get_state(),
-					     tap_get_end_state());
+						 tap_get_end_state());
 	int err;
 
 	LOG_DEBUG("statemove starting at (skip: %zu) %s end in %s", skip,
@@ -154,7 +279,7 @@ static int xlnx_pcie_xvc_execute_statemove(size_t skip)
 		  tap_state_name(tap_get_end_state()));
 
 
-	err = xlnx_pcie_xvc_transact(tms_count - skip, tms_scan >> skip, 0, NULL);
+	err = xlnx_xvc_transact(tms_count - skip, tms_scan >> skip, 0, NULL, xvc_type);
 	if (err != ERROR_OK)
 		return err;
 
@@ -163,7 +288,8 @@ static int xlnx_pcie_xvc_execute_statemove(size_t skip)
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
+static int xlnx_xvc_execute_runtest(struct jtag_command *cmd,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	int err = ERROR_OK;
 
@@ -175,7 +301,7 @@ static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
 
 	if (tap_get_state() != TAP_IDLE) {
 		tap_set_end_state(TAP_IDLE);
-		err = xlnx_pcie_xvc_execute_statemove(0);
+		err = xlnx_xvc_execute_statemove(0, xvc_type);
 		if (err != ERROR_OK)
 			return err;
 	};
@@ -185,7 +311,7 @@ static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
 
 	while (left) {
 		write = MIN(XLNX_XVC_MAX_BITS, left);
-		err = xlnx_pcie_xvc_transact(write, 0, 0, NULL);
+		err = xlnx_xvc_transact(write, 0, 0, NULL, xvc_type);
 		if (err != ERROR_OK)
 			return err;
 		left -= write;
@@ -193,12 +319,13 @@ static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
 
 	tap_set_end_state(tmp_state);
 	if (tap_get_state() != tap_get_end_state())
-		err = xlnx_pcie_xvc_execute_statemove(0);
+		err = xlnx_xvc_execute_statemove(0, xvc_type);
 
 	return err;
 }
 
-static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd)
+static int xlnx_xvc_execute_pathmove(struct jtag_command *cmd,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	unsigned int num_states = cmd->cmd.pathmove->num_states;
 	enum tap_state *path = cmd->cmd.pathmove->path;
@@ -210,9 +337,9 @@ static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd)
 
 	for (unsigned int i = 0; i < num_states; i++) {
 		if (path[i] == tap_state_transition(tap_get_state(), false)) {
-			err = xlnx_pcie_xvc_transact(1, 0, 0, NULL);
+			err = xlnx_xvc_transact(1, 0, 0, NULL, xvc_type);
 		} else if (path[i] == tap_state_transition(tap_get_state(), true)) {
-			err = xlnx_pcie_xvc_transact(1, 1, 0, NULL);
+			err = xlnx_xvc_transact(1, 1, 0, NULL, xvc_type);
 		} else {
 			LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition.",
 				  tap_state_name(tap_get_state()),
@@ -229,7 +356,8 @@ static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd)
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
+static int xlnx_xvc_execute_scan(struct jtag_command *cmd,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	enum scan_type type = jtag_scan_type(cmd->cmd.scan);
 	enum tap_state saved_end_state = cmd->cmd.scan->end_state;
@@ -253,13 +381,13 @@ static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
 	 */
 	if (ir_scan && tap_get_state() != TAP_IRSHIFT) {
 		tap_set_end_state(TAP_IRSHIFT);
-		err = xlnx_pcie_xvc_execute_statemove(0);
+		err = xlnx_xvc_execute_statemove(0, xvc_type);
 		if (err != ERROR_OK)
 			goto out_err;
 		tap_set_end_state(saved_end_state);
 	} else if (!ir_scan && (tap_get_state() != TAP_DRSHIFT)) {
 		tap_set_end_state(TAP_DRSHIFT);
-		err = xlnx_pcie_xvc_execute_statemove(0);
+		err = xlnx_xvc_execute_statemove(0, xvc_type);
 		if (err != ERROR_OK)
 			goto out_err;
 		tap_set_end_state(saved_end_state);
@@ -271,8 +399,8 @@ static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
 		/* the last TMS should be a 1, to leave the state */
 		tms = left <= XLNX_XVC_MAX_BITS ? BIT(write - 1) : 0;
 		tdi = (type != SCAN_IN) ? buf_get_u32(rd_ptr, 0, write) : 0;
-		err = xlnx_pcie_xvc_transact(write, tms, tdi, type != SCAN_OUT ?
-					     &tdo : NULL);
+		err = xlnx_xvc_transact(write, tms, tdi, type != SCAN_OUT ?
+						 &tdo : NULL, xvc_type);
 		if (err != ERROR_OK)
 			goto out_err;
 		left -= write;
@@ -285,7 +413,7 @@ static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
 	free(buf);
 
 	if (tap_get_state() != tap_get_end_state())
-		err = xlnx_pcie_xvc_execute_statemove(1);
+		err = xlnx_xvc_execute_statemove(1, xvc_type);
 
 	return err;
 
@@ -294,19 +422,14 @@ out_err:
 	return err;
 }
 
-static void xlnx_pcie_xvc_execute_reset(struct jtag_command *cmd)
-{
-	LOG_DEBUG("reset trst: %i srst: %i", cmd->cmd.reset->trst,
-		  cmd->cmd.reset->srst);
-}
-
-static void xlnx_pcie_xvc_execute_sleep(struct jtag_command *cmd)
+static void xlnx_xvc_execute_sleep(struct jtag_command *cmd)
 {
 	LOG_DEBUG("sleep %" PRIu32 "", cmd->cmd.sleep->us);
 	usleep(cmd->cmd.sleep->us);
 }
 
-static int xlnx_pcie_xvc_execute_tms(struct jtag_command *cmd)
+static int xlnx_xvc_execute_tms(struct jtag_command *cmd,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	const size_t num_bits = cmd->cmd.tms->num_bits;
 	const uint8_t *bits = cmd->cmd.tms->bits;
@@ -320,7 +443,7 @@ static int xlnx_pcie_xvc_execute_tms(struct jtag_command *cmd)
 	while (left) {
 		write = MIN(XLNX_XVC_MAX_BITS, left);
 		tms = buf_get_u32(bits, 0, write);
-		err = xlnx_pcie_xvc_transact(write, tms, 0, NULL);
+		err = xlnx_xvc_transact(write, tms, 0, NULL, xvc_type);
 		if (err != ERROR_OK)
 			return err;
 		left -= write;
@@ -330,29 +453,30 @@ static int xlnx_pcie_xvc_execute_tms(struct jtag_command *cmd)
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_execute_command(struct jtag_command *cmd)
+static int xlnx_xvc_execute_command(struct jtag_command *cmd,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	LOG_DEBUG("%s: cmd->type: %u", __func__, cmd->type);
 	switch (cmd->type) {
 	case JTAG_STABLECLOCKS:
-		return xlnx_pcie_xvc_execute_stableclocks(cmd);
+		return xlnx_xvc_execute_stableclocks(cmd, xvc_type);
 	case JTAG_RUNTEST:
-		return xlnx_pcie_xvc_execute_runtest(cmd);
+		return xlnx_xvc_execute_runtest(cmd, xvc_type);
 	case JTAG_TLR_RESET:
 		tap_set_end_state(cmd->cmd.statemove->end_state);
-		return xlnx_pcie_xvc_execute_statemove(0);
+		return xlnx_xvc_execute_statemove(0, xvc_type);
 	case JTAG_PATHMOVE:
-		return xlnx_pcie_xvc_execute_pathmove(cmd);
+		return xlnx_xvc_execute_pathmove(cmd, xvc_type);
 	case JTAG_SCAN:
-		return xlnx_pcie_xvc_execute_scan(cmd);
+		return xlnx_xvc_execute_scan(cmd, xvc_type);
 	case JTAG_RESET:
-		xlnx_pcie_xvc_execute_reset(cmd);
+		LOG_INFO("WARN: XVC driver has no reset.");
 		break;
 	case JTAG_SLEEP:
-		xlnx_pcie_xvc_execute_sleep(cmd);
+		xlnx_xvc_execute_sleep(cmd);
 		break;
 	case JTAG_TMS:
-		return xlnx_pcie_xvc_execute_tms(cmd);
+		return xlnx_xvc_execute_tms(cmd, xvc_type);
 	default:
 		LOG_ERROR("BUG: Unknown JTAG command type encountered.");
 		return ERROR_JTAG_QUEUE_FAILED;
@@ -361,13 +485,14 @@ static int xlnx_pcie_xvc_execute_command(struct jtag_command *cmd)
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_execute_queue(struct jtag_command *cmd_queue)
+static int xlnx_xvc_execute_queue(struct jtag_command *cmd_queue,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	struct jtag_command *cmd = cmd_queue;
 	int ret;
 
 	while (cmd) {
-		ret = xlnx_pcie_xvc_execute_command(cmd);
+		ret = xlnx_xvc_execute_command(cmd, xvc_type);
 
 		if (ret != ERROR_OK)
 			return ret;
@@ -378,6 +503,15 @@ static int xlnx_pcie_xvc_execute_queue(struct jtag_command *cmd_queue)
 	return ERROR_OK;
 }
 
+static int xlnx_pcie_xvc_execute_queue(struct jtag_command *cmd_queue)
+{
+	return xlnx_xvc_execute_queue(cmd_queue, PCIE);
+}
+
+static int xlnx_axi_xvc_execute_queue(struct jtag_command *cmd_queue)
+{
+	return xlnx_xvc_execute_queue(cmd_queue, AXI);
+}
 
 static int xlnx_pcie_xvc_init(void)
 {
@@ -399,8 +533,8 @@ static int xlnx_pcie_xvc_init(void)
 	 * vendor specific header */
 	xlnx_pcie_xvc->offset = PCIE_EXT_CAP_LST;
 	while (xlnx_pcie_xvc->offset <= PCI_CFG_SPACE_EXP_SIZE - sizeof(cap) &&
-	       xlnx_pcie_xvc->offset >= PCIE_EXT_CAP_LST) {
-		err = xlnx_pcie_xvc_read_reg(XLNX_XVC_EXT_CAP, &cap);
+		   xlnx_pcie_xvc->offset >= PCIE_EXT_CAP_LST) {
+		err = xlnx_pcie_xvc_read_reg(XLNX_PCIE_XVC_EXT_CAP, &cap);
 		if (err != ERROR_OK)
 			return err;
 		LOG_DEBUG("Checking capability at 0x%x; id=0x%04" PRIx32 " version=0x%" PRIx32 " next=0x%" PRIx32,
@@ -409,7 +543,7 @@ static int xlnx_pcie_xvc_init(void)
 			 PCI_EXT_CAP_VER(cap),
 			 PCI_EXT_CAP_NEXT(cap));
 		if (PCI_EXT_CAP_ID(cap) == PCI_EXT_CAP_ID_VNDR) {
-			err = xlnx_pcie_xvc_read_reg(XLNX_XVC_VSEC_HDR, &vh);
+			err = xlnx_pcie_xvc_read_reg(XLNX_PCIE_XVC_VSEC_HDR, &vh);
 			if (err != ERROR_OK)
 				return err;
 			LOG_DEBUG("Checking possible match at 0x%x; id: 0x%" PRIx32 "; rev: 0x%" PRIx32 "; length: 0x%" PRIx32,
@@ -417,14 +551,14 @@ static int xlnx_pcie_xvc_init(void)
 				 PCI_VNDR_HEADER_ID(vh),
 				 PCI_VNDR_HEADER_REV(vh),
 				 PCI_VNDR_HEADER_LEN(vh));
-			if ((PCI_VNDR_HEADER_ID(vh) == XLNX_XVC_VSEC_ID) &&
-			    (PCI_VNDR_HEADER_LEN(vh) == XLNX_XVC_CAP_SIZE))
+			if ((PCI_VNDR_HEADER_ID(vh) == XLNX_PCIE_XVC_VSEC_ID) &&
+				(PCI_VNDR_HEADER_LEN(vh) == XLNX_PCIE_XVC_CAP_SIZE))
 				break;
 		}
 		xlnx_pcie_xvc->offset = PCI_EXT_CAP_NEXT(cap);
 	}
-	if ((xlnx_pcie_xvc->offset > PCI_CFG_SPACE_EXP_SIZE - XLNX_XVC_CAP_SIZE) ||
-	     xlnx_pcie_xvc->offset < PCIE_EXT_CAP_LST) {
+	if ((xlnx_pcie_xvc->offset > PCI_CFG_SPACE_EXP_SIZE - XLNX_PCIE_XVC_CAP_SIZE) ||
+		 xlnx_pcie_xvc->offset < PCIE_EXT_CAP_LST) {
 		close(xlnx_pcie_xvc->fd);
 		return ERROR_JTAG_INIT_FAILED;
 	}
@@ -434,6 +568,44 @@ static int xlnx_pcie_xvc_init(void)
 	return ERROR_OK;
 }
 
+static int xlnx_axi_xvc_init(void)
+{
+	uint64_t baseaddr;
+
+	if (xlnx_axi_xvc->device_addr) {
+		baseaddr = strtoul(xlnx_axi_xvc->device_addr, NULL, 0);
+	} else {
+		LOG_ERROR("Please set device addr.");
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
+	if (xlnx_axi_xvc->device_file) {
+		LOG_INFO("Opening %s for AXI communication", xlnx_axi_xvc->device_file);
+		xlnx_axi_xvc->fd = open(xlnx_axi_xvc->device_file, O_RDWR | O_SYNC);
+	} else {
+		LOG_INFO("Opening /dev/mem for AXI communication");
+		xlnx_axi_xvc->fd = open("/dev/mem", O_RDWR | O_SYNC);
+	}
+
+	if (xlnx_axi_xvc->fd < 0) {
+		LOG_ERROR("Failed to open device file, check permissions.");
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
+	xlnx_axi_xvc->base = mmap(0, XLNX_AXI_XVC_MAX_REG, PROT_READ | PROT_WRITE,
+								  MAP_SHARED, xlnx_axi_xvc->fd, baseaddr);
+	if (xlnx_axi_xvc->base == MAP_FAILED) {
+		LOG_ERROR("mmap() failed, check permissions.");
+		close(xlnx_axi_xvc->fd);
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
+	LOG_INFO("Mapped Xilinx XVC/AXI vaddr %p paddr 0x%" PRIx64,
+			 xlnx_axi_xvc->base, baseaddr);
+
+	return ERROR_OK;
+}
+
 static int xlnx_pcie_xvc_quit(void)
 {
 	int err;
@@ -445,21 +617,55 @@ static int xlnx_pcie_xvc_quit(void)
 	return ERROR_OK;
 }
 
+static int xlnx_axi_xvc_quit(void)
+{
+	int err;
+
+	munmap(xlnx_axi_xvc->base, XLNX_AXI_XVC_MAX_REG);
+	free(xlnx_pcie_xvc->device);
+	free(xlnx_axi_xvc->device_file);
+	free(xlnx_axi_xvc->device_addr);
+
+	err = close(xlnx_axi_xvc->fd);
+	if (err)
+		return err;
+
+	return ERROR_OK;
+}
+
 COMMAND_HANDLER(xlnx_pcie_xvc_handle_config_command)
 {
-	if (CMD_ARGC < 1)
+	if (CMD_ARGC != 1)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	/* we can't really free this in a safe manner, so at least
-	 * limit the memory we're leaking by freeing the old one first
-	 * before allocating a new one ...
-	 */
 	free(xlnx_pcie_xvc->device);
 
 	xlnx_pcie_xvc->device = strdup(CMD_ARGV[0]);
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(xlnx_axi_xvc_handle_dev_addr_command)
+{
+	if (CMD_ARGC != 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	free(xlnx_axi_xvc->device_addr);
+
+	xlnx_axi_xvc->device_addr = strdup(CMD_ARGV[0]);
+	return ERROR_OK;
+}
+
+COMMAND_HANDLER(xlnx_axi_xvc_handle_dev_file_command)
+{
+	if (CMD_ARGC != 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	free(xlnx_axi_xvc->device_file);
+
+	xlnx_axi_xvc->device_file = strdup(CMD_ARGV[0]);
+	return ERROR_OK;
+}
+
 static const struct command_registration xlnx_pcie_xvc_subcommand_handlers[] = {
 	{
 		.name = "config",
@@ -482,11 +688,45 @@ static const struct command_registration xlnx_pcie_xvc_command_handlers[] = {
 	COMMAND_REGISTRATION_DONE
 };
 
+static const struct command_registration xlnx_axi_xvc_subcommand_handlers[] = {
+	{
+		.name = "dev_addr",
+		.handler = xlnx_axi_xvc_handle_dev_addr_command,
+		.mode = COMMAND_CONFIG,
+		.help = "Configure XVC/AXI JTAG device memory address",
+		.usage = "addr",
+	},
+	{
+		.name = "dev_file",
+		.handler = xlnx_axi_xvc_handle_dev_file_command,
+		.mode = COMMAND_CONFIG,
+		.help = "Configure XVC/AXI JTAG device file location",
+		.usage = "addr",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration xlnx_axi_xvc_command_handlers[] = {
+	{
+		.name = "xlnx_axi_xvc",
+		.mode = COMMAND_ANY,
+		.help = "perform xlnx_axi_xvc management",
+		.chain = xlnx_axi_xvc_subcommand_handlers,
+		.usage = "",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
 static struct jtag_interface xlnx_pcie_xvc_jtag_ops = {
 	.execute_queue = &xlnx_pcie_xvc_execute_queue,
 };
 
-static int xlnx_pcie_xvc_swd_sequence(const uint8_t *seq, size_t length)
+static struct jtag_interface xlnx_axi_xvc_jtag_ops = {
+	.execute_queue = &xlnx_axi_xvc_execute_queue,
+};
+
+static int xlnx_xvc_swd_sequence(const uint8_t *seq, size_t length,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	size_t left, write;
 	uint32_t send;
@@ -496,7 +736,7 @@ static int xlnx_pcie_xvc_swd_sequence(const uint8_t *seq, size_t length)
 	while (left) {
 		write = MIN(XLNX_XVC_MAX_BITS, left);
 		send = buf_get_u32(seq, 0, write);
-		err = xlnx_pcie_xvc_transact(write, send, 0, NULL);
+		err = xlnx_xvc_transact(write, send, 0, NULL, xvc_type);
 		if (err != ERROR_OK)
 			return err;
 		left -= write;
@@ -506,21 +746,22 @@ static int xlnx_pcie_xvc_swd_sequence(const uint8_t *seq, size_t length)
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_swd_switch_seq(enum swd_special_seq seq)
+static int xlnx_xvc_swd_switch_seq(enum swd_special_seq seq,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	switch (seq) {
 	case LINE_RESET:
 		LOG_DEBUG("SWD line reset");
-		return xlnx_pcie_xvc_swd_sequence(swd_seq_line_reset,
-						  swd_seq_line_reset_len);
+		return xlnx_xvc_swd_sequence(swd_seq_line_reset,
+						  swd_seq_line_reset_len, xvc_type);
 	case JTAG_TO_SWD:
 		LOG_DEBUG("JTAG-to-SWD");
-		return xlnx_pcie_xvc_swd_sequence(swd_seq_jtag_to_swd,
-						  swd_seq_jtag_to_swd_len);
+		return xlnx_xvc_swd_sequence(swd_seq_jtag_to_swd,
+						  swd_seq_jtag_to_swd_len, xvc_type);
 	case SWD_TO_JTAG:
 		LOG_DEBUG("SWD-to-JTAG");
-		return xlnx_pcie_xvc_swd_sequence(swd_seq_swd_to_jtag,
-						  swd_seq_swd_to_jtag_len);
+		return xlnx_xvc_swd_sequence(swd_seq_swd_to_jtag,
+						  swd_seq_swd_to_jtag_len, xvc_type);
 	default:
 		LOG_ERROR("Sequence %d not supported", seq);
 		return ERROR_FAIL;
@@ -529,19 +770,31 @@ static int xlnx_pcie_xvc_swd_switch_seq(enum swd_special_seq seq)
 	return ERROR_OK;
 }
 
+static int xlnx_pcie_xvc_swd_switch_seq(enum swd_special_seq seq)
+{
+	return xlnx_xvc_swd_switch_seq(seq, PCIE);
+}
+
+static int xlnx_axi_xvc_swd_switch_seq(enum swd_special_seq seq)
+{
+	return xlnx_xvc_swd_switch_seq(seq, AXI);
+}
+
 static int queued_retval;
 
-static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
-					uint32_t ap_delay_clk);
+static void xlnx_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+					uint32_t ap_delay_clk,
+					enum xlnx_xvc_type_t xvc_type);
 
-static void swd_clear_sticky_errors(void)
+static void swd_clear_sticky_errors(enum xlnx_xvc_type_t xvc_type)
 {
-	xlnx_pcie_xvc_swd_write_reg(swd_cmd(false,  false, DP_ABORT),
-		STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
+	xlnx_xvc_swd_write_reg(swd_cmd(false,  false, DP_ABORT),
+		STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0, xvc_type);
 }
 
-static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
-				       uint32_t ap_delay_clk)
+static void xlnx_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
+					uint32_t ap_delay_clk,
+					enum xlnx_xvc_type_t xvc_type)
 {
 	uint32_t res, ack, rpar;
 	int err;
@@ -550,23 +803,23 @@ static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
 
 	cmd |= SWD_CMD_START | SWD_CMD_PARK;
 	/* cmd + ack */
-	err = xlnx_pcie_xvc_transact(12, cmd, 0, &res);
+	err = xlnx_xvc_transact(12, cmd, 0, &res, xvc_type);
 	if (err != ERROR_OK)
 		goto err_out;
 
 	ack = MASK_ACK(res);
 
 	/* read data */
-	err = xlnx_pcie_xvc_transact(32, 0, 0, &res);
+	err = xlnx_xvc_transact(32, 0, 0, &res, xvc_type);
 	if (err != ERROR_OK)
 		goto err_out;
 
 	/* parity + trn */
-	err = xlnx_pcie_xvc_transact(2, 0, 0, &rpar);
+	err = xlnx_xvc_transact(2, 0, 0, &rpar, xvc_type);
 	if (err != ERROR_OK)
 		goto err_out;
 
-	LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
+	LOG_DEBUG("%s %s %s reg %X = %08" PRIx32,
 		  ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
 		  "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
 		  cmd & SWD_CMD_APNDP ? "AP" : "DP",
@@ -583,19 +836,19 @@ static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
 		if (value)
 			*value = res;
 		if (cmd & SWD_CMD_APNDP)
-			err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
+			err = xlnx_xvc_transact(ap_delay_clk, 0, 0, NULL, xvc_type);
 		queued_retval = err;
 		return;
 	case SWD_ACK_WAIT:
 		LOG_DEBUG_IO("SWD_ACK_WAIT");
-		swd_clear_sticky_errors();
+		swd_clear_sticky_errors(xvc_type);
 		return;
 	case SWD_ACK_FAULT:
 		LOG_DEBUG_IO("SWD_ACK_FAULT");
 		queued_retval = ack;
 		return;
 	default:
-		LOG_DEBUG_IO("No valid acknowledge: ack=%02"PRIx32, ack);
+		LOG_DEBUG_IO("No valid acknowledge: ack=%02" PRIx32, ack);
 		queued_retval = ack;
 		return;
 	}
@@ -603,8 +856,21 @@ err_out:
 	queued_retval = err;
 }
 
-static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
 					uint32_t ap_delay_clk)
+{
+	xlnx_xvc_swd_read_reg(cmd, value, ap_delay_clk, PCIE);
+}
+
+static void xlnx_axi_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
+					uint32_t ap_delay_clk)
+{
+	xlnx_xvc_swd_read_reg(cmd, value, ap_delay_clk, AXI);
+}
+
+static void xlnx_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+					uint32_t ap_delay_clk,
+					enum xlnx_xvc_type_t xvc_type)
 {
 	uint32_t res, ack;
 	int err;
@@ -613,23 +879,23 @@ static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
 
 	cmd |= SWD_CMD_START | SWD_CMD_PARK;
 	/* cmd + trn + ack */
-	err = xlnx_pcie_xvc_transact(13, cmd, 0, &res);
+	err = xlnx_xvc_transact(13, cmd, 0, &res, xvc_type);
 	if (err != ERROR_OK)
 		goto err_out;
 
 	ack = MASK_ACK(res);
 
 	/* write data */
-	err = xlnx_pcie_xvc_transact(32, value, 0, NULL);
+	err = xlnx_xvc_transact(32, value, 0, NULL, xvc_type);
 	if (err != ERROR_OK)
 		goto err_out;
 
 	/* parity + trn */
-	err = xlnx_pcie_xvc_transact(2, parity_u32(value), 0, NULL);
+	err = xlnx_xvc_transact(2, parity_u32(value), 0, NULL, xvc_type);
 	if (err != ERROR_OK)
 		goto err_out;
 
-	LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
+	LOG_DEBUG("%s %s %s reg %X = %08" PRIx32,
 		  ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
 		  "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
 		  cmd & SWD_CMD_APNDP ? "AP" : "DP",
@@ -640,19 +906,19 @@ static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
 	switch (ack) {
 	case SWD_ACK_OK:
 		if (cmd & SWD_CMD_APNDP)
-			err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
+			err = xlnx_xvc_transact(ap_delay_clk, 0, 0, NULL, xvc_type);
 		queued_retval = err;
 		return;
 	case SWD_ACK_WAIT:
 		LOG_DEBUG_IO("SWD_ACK_WAIT");
-		swd_clear_sticky_errors();
+		swd_clear_sticky_errors(xvc_type);
 		return;
 	case SWD_ACK_FAULT:
 		LOG_DEBUG_IO("SWD_ACK_FAULT");
 		queued_retval = ack;
 		return;
 	default:
-		LOG_DEBUG_IO("No valid acknowledge: ack=%02"PRIx32, ack);
+		LOG_DEBUG_IO("No valid acknowledge: ack=%02" PRIx32, ack);
 		queued_retval = ack;
 		return;
 	}
@@ -661,12 +927,24 @@ err_out:
 	queued_retval = err;
 }
 
-static int xlnx_pcie_xvc_swd_run_queue(void)
+static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+					uint32_t ap_delay_clk)
+{
+	xlnx_xvc_swd_write_reg(cmd, value, ap_delay_clk, PCIE);
+}
+
+static void xlnx_axi_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+					uint32_t ap_delay_clk)
+{
+	xlnx_xvc_swd_write_reg(cmd, value, ap_delay_clk, AXI);
+}
+
+static int xlnx_xvc_swd_run_queue(enum xlnx_xvc_type_t xvc_type)
 {
 	int err;
 
 	/* we want at least 8 idle cycles between each transaction */
-	err = xlnx_pcie_xvc_transact(8, 0, 0, NULL);
+	err = xlnx_xvc_transact(8, 0, 0, NULL, xvc_type);
 	if (err != ERROR_OK)
 		return err;
 
@@ -677,19 +955,37 @@ static int xlnx_pcie_xvc_swd_run_queue(void)
 	return err;
 }
 
-static int xlnx_pcie_xvc_swd_init(void)
+static int xlnx_pcie_xvc_swd_run_queue(void)
+{
+	return xlnx_xvc_swd_run_queue(PCIE);
+}
+
+static int xlnx_axi_xvc_swd_run_queue(void)
+{
+	return xlnx_xvc_swd_run_queue(AXI);
+}
+
+static int xlnx_xvc_swd_init(void)
 {
 	return ERROR_OK;
 }
 
 static const struct swd_driver xlnx_pcie_xvc_swd_ops = {
-	.init = xlnx_pcie_xvc_swd_init,
+	.init = xlnx_xvc_swd_init,
 	.switch_seq = xlnx_pcie_xvc_swd_switch_seq,
 	.read_reg = xlnx_pcie_xvc_swd_read_reg,
 	.write_reg = xlnx_pcie_xvc_swd_write_reg,
 	.run = xlnx_pcie_xvc_swd_run_queue,
 };
 
+static const struct swd_driver xlnx_axi_xvc_swd_ops = {
+	.init = xlnx_xvc_swd_init,
+	.switch_seq = xlnx_axi_xvc_swd_switch_seq,
+	.read_reg = xlnx_axi_xvc_swd_read_reg,
+	.write_reg = xlnx_axi_xvc_swd_write_reg,
+	.run = xlnx_axi_xvc_swd_run_queue,
+};
+
 struct adapter_driver xlnx_pcie_xvc_adapter_driver = {
 	.name = "xlnx_pcie_xvc",
 	.transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD,
@@ -702,3 +998,16 @@ struct adapter_driver xlnx_pcie_xvc_adapter_driver = {
 	.jtag_ops = &xlnx_pcie_xvc_jtag_ops,
 	.swd_ops  = &xlnx_pcie_xvc_swd_ops,
 };
+
+struct adapter_driver xlnx_axi_xvc_adapter_driver = {
+	.name = "xlnx_axi_xvc",
+	.transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD,
+	.transport_preferred_id = TRANSPORT_JTAG,
+	.commands = xlnx_axi_xvc_command_handlers,
+
+	.init = &xlnx_axi_xvc_init,
+	.quit = &xlnx_axi_xvc_quit,
+
+	.jtag_ops = &xlnx_axi_xvc_jtag_ops,
+	.swd_ops  = &xlnx_axi_xvc_swd_ops,
+};
diff --git a/src/jtag/interface.h b/src/jtag/interface.h
index 834997361..fb26c94ad 100644
--- a/src/jtag/interface.h
+++ b/src/jtag/interface.h
@@ -411,6 +411,7 @@ extern struct adapter_driver usbprog_adapter_driver;
 extern struct adapter_driver vdebug_adapter_driver;
 extern struct adapter_driver vsllink_adapter_driver;
 extern struct adapter_driver xds110_adapter_driver;
+extern struct adapter_driver xlnx_axi_xvc_adapter_driver;
 extern struct adapter_driver xlnx_pcie_xvc_adapter_driver;
 
 #endif /* OPENOCD_JTAG_INTERFACE_H */
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index 4bb2822d1..099b84425 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -156,7 +156,8 @@ struct adapter_driver *adapter_drivers[] = {
 		&xds110_adapter_driver,
 #endif
 #if BUILD_XLNX_XVC == 1
-		&xlnx_pcie_xvc_adapter_driver,
+	&xlnx_pcie_xvc_adapter_driver,
+	&xlnx_axi_xvc_adapter_driver,
 #endif
 
 		NULL,
diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl
index 2d8ebf041..88d802fcb 100644
--- a/src/jtag/startup.tcl
+++ b/src/jtag/startup.tcl
@@ -413,6 +413,12 @@ proc xlnx_pcie_xvc_config args {
 	eval xlnx_pcie_xvc config $args
 }
 
+lappend _telnet_autocomplete_skip xlnx_axi_xvc_config
+proc xlnx_axi_xvc_config args {
+	echo "DEPRECATED! use 'xlnx_axi_xvc config' not 'xlnx_axi_xvc_config'"
+	eval xlnx_axi_xvc config $args
+}
+
 lappend _telnet_autocomplete_skip ulink_download_firmware
 proc ulink_download_firmware args {
 	echo "DEPRECATED! use 'ulink download_firmware' not 'ulink_download_firmware'"

commit 8cdf8cb99567654ff2b33feb781680159c9fbd63
Author: Nicolas Derumigny <nic...@in...>
Date:   Mon Jun 30 11:21:18 2025 +0200

    driver: jtag: rename xlnx-pcie-xvc to xlnx-xvc
    
    Rename xlnx-pcie-xvc.c to xlnx-xvc.c in provision for AXI support
    
    Signed-off-by: Nicolas Derumigny <nic...@in...>
    Change-Id: I287fdcb8edf97f48c6f8614ac4c456f8ba197011
    Reviewed-on: https://review.openocd.org/c/openocd/+/8980
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/configure.ac b/configure.ac
index 453cbcfb5..9bbb2c36a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -178,7 +178,7 @@ m4_define([LIBJAYLINK_ADAPTERS],
 	[[[jlink], [SEGGER J-Link Programmer], [JLINK]]])
 
 m4_define([PCIE_ADAPTERS],
-	[[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_PCIE_XVC]]])
+	[[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_XVC]]])
 
 m4_define([SERIAL_PORT_ADAPTERS],
 	[[[buspirate], [Bus Pirate], [BUS_PIRATE]]])
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index b0dd8e3ad..e55e0478c 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -179,8 +179,8 @@ endif
 if LINUXSPIDEV
 DRIVERFILES += %D%/linuxspidev.c
 endif
-if XLNX_PCIE_XVC
-DRIVERFILES += %D%/xlnx-pcie-xvc.c
+if XLNX_XVC
+DRIVERFILES += %D%/xlnx-xvc.c
 endif
 if BCM2835GPIO
 DRIVERFILES += %D%/bcm2835gpio.c
diff --git a/src/jtag/drivers/xlnx-pcie-xvc.c b/src/jtag/drivers/xlnx-xvc.c
similarity index 100%
rename from src/jtag/drivers/xlnx-pcie-xvc.c
rename to src/jtag/drivers/xlnx-xvc.c
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index 834247245..4bb2822d1 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -155,7 +155,7 @@ struct adapter_driver *adapter_drivers[] = {
 #if BUILD_XDS110 == 1
 		&xds110_adapter_driver,
 #endif
-#if BUILD_XLNX_PCIE_XVC == 1
+#if BUILD_XLNX_XVC == 1
 		&xlnx_pcie_xvc_adapter_driver,
 #endif
 

-----------------------------------------------------------------------

Summary of changes:
 configure.ac                                     |  11 +-
 doc/openocd.texi                                 |  21 +
 src/jtag/drivers/Makefile.am                     |   4 +-
 src/jtag/drivers/{xlnx-pcie-xvc.c => xlnx-xvc.c} | 523 ++++++++++++++++++-----
 src/jtag/interface.h                             |   1 +
 src/jtag/interfaces.c                            |   5 +-
 src/jtag/startup.tcl                             |   6 +
 7 files changed, 455 insertions(+), 116 deletions(-)
 rename src/jtag/drivers/{xlnx-pcie-xvc.c => xlnx-xvc.c} (50%)


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Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1084-gcbc32c383

From: openocd-gerrit <ope...@us...> - 2025-07-06 04:45:59

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  cbc32c3831e39fd07f5fe0dc1cfb9a7be77ffa86 (commit)
      from  09a54c3a89af563329adf757990e0c6dd83a1095 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit cbc32c3831e39fd07f5fe0dc1cfb9a7be77ffa86
Author: Tomas Vanek <va...@fb...>
Date:   Thu Jul 3 06:52:29 2025 +0200

    flash/nor/stm32l4x: fix permanent write protection on STM32U5
    
    Unlike other devices supported by this driver STM32U5 devices
    have a new UNLOCK bit in FLASH_WRP1AR, WRP1BR, WRP2AR, WRP2BR
    registers. Writing zero to this bit makes the write protection
    block permanent with no way to unprotect.
    
    Commit 6554d176e926 ("flash/stm32l4x: support STM32U59/U5Ax devices")
    and later commits with additional U5 devices lack support for
    the UNLOCK bit and therefore makes write protection permanent
    without warning.
    
    Introduce the new bit flag F_WRP_HAS_LOCK and mark U5 devices by it.
    Set UNLOCK bit in stm32l4_write_one_wrpxy() if F_WRP_HAS_LOCK is set.
    
    Change-Id: I26b97d855e094a21540e3377f367520683af2eac
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8981
    Tested-by: jenkins

diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index f16333201..8001aaf00 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -152,6 +152,9 @@
 /* this flag indicates that programming should be done in quad-word
  * the default programming word size is double-word */
 #define F_QUAD_WORD_PROG    BIT(4)
+/* the registers WRPxyR have UNLOCK bit - writing zero locks the write
+ * protection region permanently! */
+#define F_WRP_HAS_LOCK		BIT(5)
 /* end of STM32L4 flags ******************************************************/
 
 
@@ -500,7 +503,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .num_revs              = ARRAY_SIZE(stm32u53_u54xx_revs),
 	  .device_str            = "STM32U535/U545",
 	  .max_flash_size_kb     = 512,
-	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
+								| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0BFA07A0,
 	  .otp_base              = 0x0BFA0000,
@@ -692,7 +696,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .num_revs              = ARRAY_SIZE(stm32u59_u5axx_revs),
 	  .device_str            = "STM32U59/U5Axx",
 	  .max_flash_size_kb     = 4096,
-	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
+								| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0BFA07A0,
 	  .otp_base              = 0x0BFA0000,
@@ -704,7 +709,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .num_revs              = ARRAY_SIZE(stm32u57_u58xx_revs),
 	  .device_str            = "STM32U57/U58xx",
 	  .max_flash_size_kb     = 2048,
-	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
+								| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0BFA07A0,
 	  .otp_base              = 0x0BFA0000,
@@ -716,7 +722,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .num_revs              = ARRAY_SIZE(stm32u5f_u5gxx_revs),
 	  .device_str            = "STM32U5F/U5Gxx",
 	  .max_flash_size_kb     = 4096,
-	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
+								| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0BFA07A0,
 	  .otp_base              = 0x0BFA0000,
@@ -1287,6 +1294,8 @@ static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *
 	int wrp_end = wrpxy->last - wrpxy->offset;
 
 	uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
+	if (stm32l4_info->part_info->flags & F_WRP_HAS_LOCK)
+		wrp_value |= FLASH_WRPXYR_UNLOCK;
 
 	return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
 }
diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index 07b3615a2..1f4f2344f 100644
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -69,6 +69,9 @@
 #define FLASH_U5_DUALBANK		BIT(21)
 #define FLASH_TZEN				BIT(31)
 
+/* FLASH_WRPxyR register bits */
+#define FLASH_WRPXYR_UNLOCK		BIT(31)
+
 /* FLASH secure block based bank 1/2 register offsets */
 #define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
 #define FLASH_SECBB2(X) (0xA0 + 4 * (X - 1))

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/stm32l4x.c | 17 +++++++++++++----
 src/flash/nor/stm32l4x.h |  3 +++
 2 files changed, 16 insertions(+), 4 deletions(-)


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From: openocd-gerrit <ope...@us...> - 2025-07-02 12:21:04

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- Log -----------------------------------------------------------------
commit 09a54c3a89af563329adf757990e0c6dd83a1095
Author: Tomas Vanek <va...@fb...>
Date:   Fri Jan 3 18:23:07 2025 +0100

    target/arm_adi: add URLs of latest ARM ADI spec
    
    While on it warn about screwed SWD diagrams in ADI spec
    and add reference to a SWD timing diagram.
    
    Change-Id: I628d707ebf8ce7c22ba19bdcfd06028d4eaa60f8
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8690
    Tested-by: jenkins

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index df897b80e..67a3fcc57 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -50,8 +50,16 @@
 /*
  * Relevant specifications from ARM include:
  *
- * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031F
+ * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031G
+ * https://developer.arm.com/documentation/ihi0031/latest/
+ *
  * ARM(tm) Debug Interface v6 Architecture Specification    ARM IHI 0074C
+ * https://developer.arm.com/documentation/ihi0074/latest/
+ *
+ * Note that diagrams B4-1 to B4-7 in both ADI specifications show
+ * SWCLK signal mostly in wrong polarity. See detailed SWD timing
+ * https://developer.arm.com/documentation/dui0499/b/arm-dstream-target-interface-connections/swd-timing-requirements
+ *
  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  *
  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)


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      from  537d907555ddd5137a6fecfc6d0d74b404b3445a (commit)

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- Log -----------------------------------------------------------------
commit f71b0bbd7b31627dfdfb87741cf207d83335357c
Author: Tomas Vanek <va...@fb...>
Date:   Fri Jan 3 15:04:43 2025 +0100

    jtag/swd: extend ap_delay_hint parameter comments
    
    Assure that zero is passed in ap_delay_hint in case of DP r/w.
    
    Change-Id: I5cd53b99950a7f1398b88f7394b3e66530803479
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8689
    Tested-by: jenkins

diff --git a/src/jtag/swd.h b/src/jtag/swd.h
index 3fe1365b5..c4b6215ab 100644
--- a/src/jtag/swd.h
+++ b/src/jtag/swd.h
@@ -270,6 +270,7 @@ struct swd_driver {
 	 * @param Where to store value to read from register
 	 * @param ap_delay_hint Number of idle cycles that may be
 	 * needed after an AP access to avoid WAITs
+	 * or zero in case of DP read.
 	 */
 	void (*read_reg)(uint8_t cmd, uint32_t *value, uint32_t ap_delay_hint);
 
@@ -280,6 +281,7 @@ struct swd_driver {
 	 * @param Value to be written to the register
 	 * @param ap_delay_hint Number of idle cycles that may be
 	 * needed after an AP access to avoid WAITs
+	 * or zero in case of DP write.
 	 */
 	void (*write_reg)(uint8_t cmd, uint32_t value, uint32_t ap_delay_hint);
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/swd.h | 2 ++
 1 file changed, 2 insertions(+)


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- Log -----------------------------------------------------------------
commit 537d907555ddd5137a6fecfc6d0d74b404b3445a
Author: Nishanth Menon <nm...@ti...>
Date:   Mon Jun 23 12:41:04 2025 -0500

    tcl/board/ti_*_swd_native.cfg: Add explicit transport info
    
    We use swd emulation in direct memory operations. Instead of relying
    on deprecated autoselect of transport, explicitly state swd as
    transport scheme.
    
    Change-Id: Iec7e2ad18edd365992cd7ba88558494bccf49fd2
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8975
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/board/ti_am625_swd_native.cfg b/tcl/board/ti_am625_swd_native.cfg
index dc4b20579..65314fe5d 100644
--- a/tcl/board/ti_am625_swd_native.cfg
+++ b/tcl/board/ti_am625_swd_native.cfg
@@ -14,6 +14,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
 	set SOC am625
diff --git a/tcl/board/ti_am62a7_swd_native.cfg b/tcl/board/ti_am62a7_swd_native.cfg
index 99fc0b0b3..3d5e89228 100644
--- a/tcl/board/ti_am62a7_swd_native.cfg
+++ b/tcl/board/ti_am62a7_swd_native.cfg
@@ -14,6 +14,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
 	set SOC am62a7
diff --git a/tcl/board/ti_am62p_swd_native.cfg b/tcl/board/ti_am62p_swd_native.cfg
index fa549f358..a8c6bd120 100644
--- a/tcl/board/ti_am62p_swd_native.cfg
+++ b/tcl/board/ti_am62p_swd_native.cfg
@@ -14,6 +14,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
 	set SOC am62p
diff --git a/tcl/board/ti_j721e_swd_native.cfg b/tcl/board/ti_j721e_swd_native.cfg
index 3041c3c34..38316387a 100644
--- a/tcl/board/ti_j721e_swd_native.cfg
+++ b/tcl/board/ti_j721e_swd_native.cfg
@@ -14,6 +14,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
         set SOC j721e
diff --git a/tcl/board/ti_j722s_swd_native.cfg b/tcl/board/ti_j722s_swd_native.cfg
index bbe0d508c..a171ec358 100644
--- a/tcl/board/ti_j722s_swd_native.cfg
+++ b/tcl/board/ti_j722s_swd_native.cfg
@@ -15,6 +15,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
 	set SOC j722s

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/ti_am625_swd_native.cfg  | 1 +
 tcl/board/ti_am62a7_swd_native.cfg | 1 +
 tcl/board/ti_am62p_swd_native.cfg  | 1 +
 tcl/board/ti_j721e_swd_native.cfg  | 1 +
 tcl/board/ti_j722s_swd_native.cfg  | 1 +
 5 files changed, 5 insertions(+)


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