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|
|
From: <ml...@ma...> - 2009-04-28 19:40:05
|
Author: mlu
Date: 2009-04-28 19:40:02 +0200 (Tue, 28 Apr 2009)
New Revision: 1556
Modified:
trunk/src/jtag/jlink.c
Log:
Correctedout buffer size and missing jlink_tap_init() call.
Expanded JLink adapter info at startup.
Modified: trunk/src/jtag/jlink.c
===================================================================
--- trunk/src/jtag/jlink.c 2009-04-28 13:40:06 UTC (rev 1555)
+++ trunk/src/jtag/jlink.c 2009-04-28 17:40:02 UTC (rev 1556)
@@ -44,7 +44,7 @@
// See Section 1.3.2 of the Segger JLink USB protocol manual
#define JLINK_IN_BUFFER_SIZE 2048
-#define JLINK_OUT_BUFFER_SIZE 2048
+#define JLINK_OUT_BUFFER_SIZE 2*2048+4
#define JLINK_EMU_RESULT_BUFFER_SIZE 64
/* Global USB buffers */
@@ -53,14 +53,16 @@
static u8 usb_emu_result_buffer[JLINK_EMU_RESULT_BUFFER_SIZE];
/* Constants for JLink command */
-#define EMU_CMD_VERSION 0x01
-#define EMU_CMD_SET_SPEED 0x05
-#define EMU_CMD_GET_STATE 0x07
-#define EMU_CMD_HW_JTAG3 0xcf
-#define EMU_CMD_HW_RESET0 0xdc
-#define EMU_CMD_HW_RESET1 0xdd
-#define EMU_CMD_HW_TRST0 0xde
-#define EMU_CMD_HW_TRST1 0xdf
+#define EMU_CMD_VERSION 0x01
+#define EMU_CMD_SET_SPEED 0x05
+#define EMU_CMD_GET_STATE 0x07
+#define EMU_CMD_HW_JTAG3 0xcf
+#define EMU_CMD_GET_MAX_MEM_BLOCK 0xd4
+#define EMU_CMD_HW_RESET0 0xdc
+#define EMU_CMD_HW_RESET1 0xdd
+#define EMU_CMD_HW_TRST0 0xde
+#define EMU_CMD_HW_TRST1 0xdf
+#define EMU_CMD_GET_CAPS 0xe8
/* max speed 12MHz v5.0 jlink */
#define JLINK_MAX_SPEED 12000
@@ -530,6 +532,7 @@
{
int result;
int len;
+ u32 jlink_caps, jlink_max_size;
/* query hardware version */
jlink_simple_command(EMU_CMD_VERSION);
@@ -537,8 +540,7 @@
result = jlink_usb_read(jlink_jtag_handle, 2);
if (2 != result)
{
- LOG_ERROR("J-Link command EMU_CMD_VERSION failed (%d)\n",
- result);
+ LOG_ERROR("J-Link command EMU_CMD_VERSION failed (%d)\n", result);
return ERROR_JTAG_DEVICE_ERROR;
}
@@ -546,14 +548,41 @@
result = jlink_usb_read(jlink_jtag_handle, len);
if (result != len)
{
- LOG_ERROR("J-Link command EMU_CMD_VERSION failed (%d)\n",
- result);
+ LOG_ERROR("J-Link command EMU_CMD_VERSION failed (%d)\n", result);
return ERROR_JTAG_DEVICE_ERROR;
}
usb_in_buffer[result] = 0;
LOG_INFO("%s", (char *)usb_in_buffer);
+ /* query hardware capabilities */
+ jlink_simple_command(EMU_CMD_GET_CAPS);
+
+ result = jlink_usb_read(jlink_jtag_handle, 4);
+ if (4 != result)
+ {
+ LOG_ERROR("J-Link command EMU_CMD_GET_CAPS failed (%d)\n", result);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ jlink_caps = buf_get_u32(usb_in_buffer, 0, 32);
+ LOG_INFO("JLink caps 0x%x", jlink_caps);
+
+
+ /* query hardware maximum memory block */
+ jlink_simple_command(EMU_CMD_GET_MAX_MEM_BLOCK);
+
+ result = jlink_usb_read(jlink_jtag_handle, 4);
+ if (4 != result)
+ {
+ LOG_ERROR("J-Link command EMU_CMD_GET_MAX_MEM_BLOCK failed (%d)\n", result);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ jlink_max_size = buf_get_u32(usb_in_buffer, 0, 32);
+ LOG_INFO("JLink max mem block %i", jlink_max_size);
+
+
return ERROR_OK;
}
@@ -689,8 +718,8 @@
result = jlink_usb_message(jlink_jtag_handle, 4 + 2 * byte_length, byte_length);
if (result != byte_length)
{
- LOG_ERROR("jlink_tap_execute, wrong result %d (expected %d)",
- result, byte_length);
+ LOG_ERROR("jlink_tap_execute, wrong result %d (expected %d)", result, byte_length);
+ jlink_tap_init();
return ERROR_JTAG_QUEUE_FAILED;
}
@@ -726,7 +755,6 @@
}
jlink_tap_init();
-
return ERROR_OK;
}
@@ -800,7 +828,7 @@
}
result = jlink_usb_read(jlink_jtag, in_length);
- if ((result != in_length) && (result != in_length + 1))
+ if ((result != in_length) && (result != (in_length + 1)))
{
LOG_ERROR("usb_bulk_read failed (requested=%d, result=%d)",
in_length, result);
|
|
From: ntfreak at B. <nt...@ma...> - 2009-04-28 15:40:10
|
Author: ntfreak
Date: 2009-04-28 15:40:06 +0200 (Tue, 28 Apr 2009)
New Revision: 1555
Modified:
trunk/src/helper/replacements.c
Log:
- fix win32 build
Modified: trunk/src/helper/replacements.c
===================================================================
--- trunk/src/helper/replacements.c 2009-04-28 08:42:09 UTC (rev 1554)
+++ trunk/src/helper/replacements.c 2009-04-28 13:40:06 UTC (rev 1555)
@@ -172,7 +172,8 @@
/* build an array of handles for non-sockets */
for (i = 0; i < max_fd; i++) {
if (SAFE_FD_ISSET(i, rfds) || SAFE_FD_ISSET(i, wfds) || SAFE_FD_ISSET(i, efds)) {
- handles[n_handles] = (HANDLE)_get_osfhandle(i);
+ long handle = _get_osfhandle(i);
+ handles[n_handles] = (HANDLE)handle;
if (handles[n_handles] == INVALID_HANDLE_VALUE) {
/* socket */
if (SAFE_FD_ISSET(i, rfds)) {
@@ -246,8 +247,9 @@
if (WAIT_OBJECT_0 == WaitForSingleObject(handles[i], 0)) {
if (SAFE_FD_ISSET(handle_slot_to_fd[i], rfds)) {
DWORD dwBytes;
+ long handle = _get_osfhandle(handle_slot_to_fd[i]);
- if (PeekNamedPipe((HANDLE)_get_osfhandle(handle_slot_to_fd[i]), NULL, 0, NULL, &dwBytes, NULL))
+ if (PeekNamedPipe((HANDLE)handle, NULL, 0, NULL, &dwBytes, NULL))
{
/* check to see if gdb pipe has data available */
if (dwBytes)
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-28 10:42:10
|
Author: oharboe
Date: 2009-04-28 10:42:09 +0200 (Tue, 28 Apr 2009)
New Revision: 1554
Modified:
trunk/src/target/arm11.c
Log:
fix checksum memory. By failing the fallback code will handle checksum calculation
Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c 2009-04-28 07:34:43 UTC (rev 1553)
+++ trunk/src/target/arm11.c 2009-04-28 08:42:09 UTC (rev 1554)
@@ -1305,11 +1305,13 @@
return arm11_write_memory(target, address, 4, count, buffer);
}
+/* here we have nothing target specific to contribute, so we fail and then the
+ * fallback code will read data from the target and calculate the CRC on the
+ * host.
+ */
int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
{
- FNC_INFO_NOTIMPLEMENTED;
-
- return ERROR_OK;
+ return ERROR_FAIL;
}
/* target break-/watchpoint control
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-28 09:34:44
|
Author: oharboe
Date: 2009-04-28 09:34:43 +0200 (Tue, 28 Apr 2009)
New Revision: 1553
Modified:
trunk/src/jtag/gw16012.c
Log:
Zach Welch <zw...@su...> fix gw16012 with --enable-parport_ppdev
Modified: trunk/src/jtag/gw16012.c
===================================================================
--- trunk/src/jtag/gw16012.c 2009-04-28 07:33:50 UTC (rev 1552)
+++ trunk/src/jtag/gw16012.c 2009-04-28 07:34:43 UTC (rev 1553)
@@ -461,32 +461,65 @@
}
#endif
-static int gw16012_init(void)
+#if PARPORT_USE_PPDEV == 1
+
+#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
+
+#define GW16012_PPDEV_NAME "ppi"
+
+static int gw16012_init_ioctls(void)
{
-#if PARPORT_USE_PPDEV == 1
+ int temp = 0;
+ temp = ioctl(device_handle, PPCLAIM);
+ if (temp < 0)
+ {
+ LOG_ERROR("cannot claim device");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ temp = PARPORT_MODE_COMPAT;
+ temp = ioctl(device_handle, PPSETMODE, &temp);
+ if (temp < 0)
+ {
+ LOG_ERROR(" cannot set compatible mode to device");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ temp = IEEE1284_MODE_COMPAT;
+ temp = ioctl(device_handle, PPNEGOT, &temp);
+ if (temp < 0)
+ {
+ LOG_ERROR("cannot set compatible 1284 mode to device");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+ return ERROR_OK;
+}
+#else
+
+#define GW16012_PPDEV_NAME "parport"
+
+static int gw16012_init_ioctls(void)
+{
+ return ERROR_OK;
+}
+
+#endif // defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
+
+static int gw16012_init_device(void)
+{
+ const char *device_name = GW16012_PPDEV_NAME;
char buffer[256];
- int i = 0;
-#endif
- u8 status_port;
-#if PARPORT_USE_PPDEV == 1
- if (device_handle>0)
+ if (device_handle > 0)
{
LOG_ERROR("device is already opened");
return ERROR_JTAG_INIT_FAILED;
}
-#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
- LOG_DEBUG("opening /dev/ppi%d...", gw16012_port);
+ snprintf(buffer, 256, "/dev/%s%d", device_name, gw16012_port);
+ LOG_DEBUG("opening %s...", buffer);
- snprintf(buffer, 256, "/dev/ppi%d", gw16012_port);
device_handle = open(buffer, O_WRONLY);
-#else
- LOG_DEBUG("opening /dev/parport%d...", gw16012_port);
-
- snprintf(buffer, 256, "/dev/parport%d", gw16012_port);
- device_handle = open(buffer, O_WRONLY);
-#endif
if (device_handle<0)
{
LOG_ERROR("cannot open device. check it exists and that user read and write rights are set");
@@ -495,31 +528,16 @@
LOG_DEBUG("...open");
-#if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
- i=ioctl(device_handle, PPCLAIM);
- if (i<0)
- {
- LOG_ERROR("cannot claim device");
+ if (gw16012_init_ioctls() != ERROR_OK)
return ERROR_JTAG_INIT_FAILED;
- }
- i = PARPORT_MODE_COMPAT;
- i= ioctl(device_handle, PPSETMODE, & i);
- if (i<0)
- {
- LOG_ERROR(" cannot set compatible mode to device");
- return ERROR_JTAG_INIT_FAILED;
- }
+ return ERROR_OK;
+}
- i = IEEE1284_MODE_COMPAT;
- i = ioctl(device_handle, PPNEGOT, & i);
- if (i<0)
- {
- LOG_ERROR("cannot set compatible 1284 mode to device");
- return ERROR_JTAG_INIT_FAILED;
- }
-#endif
-#else
+#else // PARPORT_USE_PPDEV
+
+static int gw16012_init_device(void)
+{
if (gw16012_port == 0)
{
gw16012_port = 0x378;
@@ -544,8 +562,18 @@
#else
outb(0x0, gw16012_port + 2);
#endif
-#endif /* PARPORT_USE_PPDEV */
+ return ERROR_OK;
+}
+#endif // PARPORT_USE_PPDEV
+
+static int gw16012_init(void)
+{
+ u8 status_port;
+
+ if (gw16012_init_device() != ERROR_OK)
+ return ERROR_JTAG_INIT_FAILED;
+
gw16012_input(&status_port);
gw16012_msb = (status_port & 0x80) ^ 0x80;
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-28 09:33:51
|
Author: oharboe
Date: 2009-04-28 09:33:50 +0200 (Tue, 28 Apr 2009)
New Revision: 1552
Modified:
trunk/src/target/arm11.c
Log:
convert some LOG_INFO()'s during stepping into LOG_DEBUG()
Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c 2009-04-28 07:29:18 UTC (rev 1551)
+++ trunk/src/target/arm11.c 2009-04-28 07:33:50 UTC (rev 1552)
@@ -322,7 +322,7 @@
if (!dscr)
{
dscr = &dscr_local_tmp_copy;
-
+
CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
}
@@ -673,7 +673,7 @@
return ERROR_OK;
u32 dscr;
-
+
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
@@ -861,7 +861,7 @@
while (1)
{
u32 dscr;
-
+
CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
@@ -906,7 +906,7 @@
if (!current)
R(PC) = address;
- LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
+ LOG_DEBUG("STEP PC %08x%s", R(PC), !current ? "!" : "");
/** \todo TODO: Thumb not supported here */
@@ -920,7 +920,7 @@
R(PC) += 4;
arm11->reg_list[ARM11_RC_PC].valid = 1;
arm11->reg_list[ARM11_RC_PC].dirty = 0;
- LOG_INFO("Skipping BKPT");
+ LOG_DEBUG("Skipping BKPT");
}
/* skip over Wait for interrupt / Standby */
/* mcr 15, 0, r?, cr7, cr0, {4} */
@@ -929,12 +929,12 @@
R(PC) += 4;
arm11->reg_list[ARM11_RC_PC].valid = 1;
arm11->reg_list[ARM11_RC_PC].dirty = 0;
- LOG_INFO("Skipping WFI");
+ LOG_DEBUG("Skipping WFI");
}
/* ignore B to self */
else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
{
- LOG_INFO("Not stepping jump to self");
+ LOG_DEBUG("Not stepping jump to self");
}
else
{
@@ -1331,13 +1331,13 @@
if (!arm11->free_brps)
{
- LOG_INFO("no breakpoint unit available for hardware breakpoint");
+ LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (breakpoint->length != 4)
{
- LOG_INFO("only breakpoints of four bytes length supported");
+ LOG_DEBUG("only breakpoints of four bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-28 09:29:18
|
Author: oharboe
Date: 2009-04-28 09:29:18 +0200 (Tue, 28 Apr 2009)
New Revision: 1551
Modified:
trunk/src/target/arm11.c
trunk/src/target/arm11.h
trunk/src/target/arm11_dbgtap.c
Log:
Michael Bruck <mb...@di...> macros for error handling
Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c 2009-04-28 06:29:32 UTC (rev 1550)
+++ trunk/src/target/arm11.c 2009-04-28 07:29:18 UTC (rev 1551)
@@ -316,15 +316,14 @@
int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
{
FNC_INFO;
- int retval;
u32 dscr_local_tmp_copy;
if (!dscr)
{
dscr = &dscr_local_tmp_copy;
- if ((retval=arm11_read_DSCR(arm11, dscr))!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
}
if (!(*dscr & ARM11_DSCR_MODE_SELECT))
@@ -382,9 +381,7 @@
}}
/* Save DSCR */
- int retval;
- if ((retval=arm11_read_DSCR(arm11, &R(DSCR)))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
/* Save wDTR */
@@ -586,12 +583,9 @@
otherwise our programming would be sloppy */
{
u32 DSCR;
- int retval;
- if ((retval=arm11_read_DSCR(arm11, &DSCR))!=ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
+
if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
@@ -679,14 +673,12 @@
return ERROR_OK;
u32 dscr;
- int retval;
- if ((retval=arm11_read_DSCR(arm11, &dscr))!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
- if ((retval=arm11_check_init(arm11, &dscr))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_check_init(arm11, &dscr));
if (dscr & ARM11_DSCR_CORE_HALTED)
{
@@ -739,8 +731,6 @@
/* target execution control */
int arm11_halt(struct target_s *target)
{
- int retval = ERROR_OK;
-
FNC_INFO;
arm11_common_t * arm11 = target->arch_info;
@@ -767,19 +757,13 @@
arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
- if((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
u32 dscr;
while (1)
{
- int retval;
- retval = arm11_read_DSCR(arm11, &dscr);
- if (retval!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
if (dscr & ARM11_DSCR_CORE_HALTED)
break;
@@ -792,19 +776,15 @@
target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
- if((retval = target_call_event_callbacks(target,
- old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(
+ target_call_event_callbacks(target,
+ old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
return ERROR_OK;
}
int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
{
- int retval = ERROR_OK;
-
FNC_INFO;
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
@@ -876,17 +856,13 @@
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
- if((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
while (1)
{
u32 dscr;
- retval = arm11_read_DSCR(arm11, &dscr);
- if (retval!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
@@ -899,19 +875,14 @@
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
- if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
}
else
{
target->state = TARGET_DEBUG_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
- if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
- {
- return retval;
- }
+
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
}
return ERROR_OK;
@@ -919,8 +890,6 @@
int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
{
- int retval = ERROR_OK;
-
FNC_INFO;
LOG_DEBUG("target->state: %s",
@@ -943,8 +912,7 @@
u32 next_instruction;
- if ((arm11_read_memory_word(arm11, R(PC), &next_instruction))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070)
@@ -988,8 +956,7 @@
brp[1].address = ARM11_SC7_BCR0;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
- if ((retval=arm11_sc7_run(arm11, brp, asizeof(brp)))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
/* resume */
@@ -1000,15 +967,11 @@
R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
- if ((retval=arm11_leave_debug_state(arm11))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_leave_debug_state(arm11));
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
- if((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
/** \todo TODO: add a timeout */
@@ -1017,10 +980,9 @@
while (1)
{
u32 dscr;
- retval = arm11_read_DSCR(arm11, &dscr);
- if (retval!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
+
LOG_DEBUG("DSCR %08x", dscr);
if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
@@ -1032,8 +994,7 @@
arm11_sc7_clear_vbw(arm11);
/* save state */
- if((retval = arm11_on_enter_debug_state(arm11))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
/* restore default state */
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
@@ -1043,10 +1004,7 @@
// target->state = TARGET_HALTED;
target->debug_reason = DBG_REASON_SINGLESTEP;
- if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
return ERROR_OK;
}
@@ -1069,9 +1027,7 @@
if (target->reset_halt)
{
- int retval;
- if ((retval = target_halt(target))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(target_halt(target));
}
return ERROR_OK;
@@ -1511,25 +1467,18 @@
}
// no debug, otherwise breakpoint is not set
- if((retval = target_resume(target, 0, entry_point, 1, 0)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
- if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
if (target->state != TARGET_HALTED)
{
- if ((retval=target_halt(target))!=ERROR_OK)
- return retval;
- if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_halt(target));
+
+ CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
+
retval = ERROR_TARGET_TIMEOUT;
+
goto del_breakpoint;
}
@@ -1590,7 +1539,6 @@
int arm11_target_create(struct target_s *target, Jim_Interp *interp)
{
- int retval = ERROR_OK;
FNC_INFO;
NEW(arm11_common_t, arm11, 1);
@@ -1601,10 +1549,7 @@
arm11->jtag_info.tap = target->tap;
arm11->jtag_info.scann_size = 5;
- if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(arm_jtag_setup_connection(&arm11->jtag_info));
if (target->tap==NULL)
return ERROR_FAIL;
@@ -1630,7 +1575,6 @@
int arm11_examine(struct target_s *target)
{
FNC_INFO;
- int retval;
arm11_common_t * arm11 = target->arch_info;
@@ -1657,10 +1601,8 @@
arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(jtag_execute_queue());
-
switch (arm11->device_id & 0x0FFFF000)
{
case 0x07B36000: LOG_INFO("found ARM1136"); break;
Modified: trunk/src/target/arm11.h
===================================================================
--- trunk/src/target/arm11.h 2009-04-28 06:29:32 UTC (rev 1550)
+++ trunk/src/target/arm11.h 2009-04-28 07:29:18 UTC (rev 1551)
@@ -51,6 +51,16 @@
#define ARM11_TAP_DEFAULT TAP_INVALID
+#define CHECK_RETVAL(action) \
+do { \
+ int __retval = (action); \
+ \
+ if (__retval != ERROR_OK) \
+ return __retval; \
+ \
+} while (0)
+
+
typedef struct arm11_register_history_s
{
u32 value;
Modified: trunk/src/target/arm11_dbgtap.c
===================================================================
--- trunk/src/target/arm11_dbgtap.c 2009-04-28 06:29:32 UTC (rev 1550)
+++ trunk/src/target/arm11_dbgtap.c 2009-04-28 07:29:18 UTC (rev 1551)
@@ -229,11 +229,7 @@
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
if (arm11->last_dscr != dscr)
JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
@@ -242,7 +238,7 @@
*value=dscr;
- return retval;
+ return ERROR_OK;
}
/** Write the Debug Status and Control Register (DSCR)
@@ -266,9 +262,7 @@
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
@@ -383,9 +377,7 @@
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(jtag_execute_queue());
if (flag)
break;
@@ -447,10 +439,9 @@
Data = *data;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(jtag_execute_queue());
+
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
}
while (!Ready);
@@ -465,10 +456,9 @@
Data = 0;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(jtag_execute_queue());
+
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
while (!Ready);
@@ -550,9 +540,7 @@
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(jtag_execute_queue());
size_t error_count = 0;
@@ -625,9 +613,8 @@
do
{
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
@@ -728,9 +715,8 @@
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
- int retval;
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
+
+ CHECK_RETVAL(jtag_execute_queue());
JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
}
@@ -826,16 +812,13 @@
*/
int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
{
- int retval;
arm11_run_instr_data_prepare(arm11);
/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
- if ((retval=arm11_run_instr_data_to_core1(arm11, 0xee100e15, address))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_run_instr_data_to_core1(arm11, 0xee100e15, address));
/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
- if ((retval=arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1));
arm11_run_instr_data_finish(arm11);
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-28 08:29:32
|
Author: oharboe Date: 2009-04-28 08:29:32 +0200 (Tue, 28 Apr 2009) New Revision: 1550 Modified: trunk/PATCHES trunk/contrib/openocd.udev Log: eol-style native Modified: trunk/PATCHES =================================================================== --- trunk/PATCHES 2009-04-28 06:28:39 UTC (rev 1549) +++ trunk/PATCHES 2009-04-28 06:29:32 UTC (rev 1550) @@ -1,28 +1,28 @@ -Please mail patches to: - -ope...@li... - -The patch should be against svn trunk using an SVN -diff. - -Attach the patch to the email as a .txt file and -also write a short change log entry that maintainers -can copy and paste into the commit message - -Add yourself to the GPL copyright for non-trivial changes. - -To create a patch from the command line: - -svn diff >mypatch.txt - -http://svnbook.red-bean.com/en/1.0/re09.html - -NB! remember to use "svn add" on new files first! - -http://svnbook.red-bean.com/en/1.0/re01.html - - - -If you have a decent SVN GUI, then that should be -able to create and apply patches as well... +Please mail patches to: + +ope...@li... + +The patch should be against svn trunk using an SVN +diff. + +Attach the patch to the email as a .txt file and +also write a short change log entry that maintainers +can copy and paste into the commit message + +Add yourself to the GPL copyright for non-trivial changes. + +To create a patch from the command line: + +svn diff >mypatch.txt + +http://svnbook.red-bean.com/en/1.0/re09.html + +NB! remember to use "svn add" on new files first! + +http://svnbook.red-bean.com/en/1.0/re01.html + + + +If you have a decent SVN GUI, then that should be +able to create and apply patches as well... \ No newline at end of file Property changes on: trunk/PATCHES ___________________________________________________________________ Name: svn:eol-style + native Modified: trunk/contrib/openocd.udev =================================================================== --- trunk/contrib/openocd.udev 2009-04-28 06:28:39 UTC (rev 1549) +++ trunk/contrib/openocd.udev 2009-04-28 06:29:32 UTC (rev 1550) @@ -1,56 +1,56 @@ -BUS!="usb", ACTION!="add", SUBSYSTEM!=="usb_device", GOTO="openocd_rules_end" - -# Olimex ARM-USB-OCD -SYSFS{idVendor}=="15ba", SYSFS{idProduct}=="0003", MODE="664", GROUP="plugdev" - -# Olimex ARM-USB-OCD-TINY -SYSFS{idVendor}=="15ba", SYSFS{idProduct}=="0004", MODE="664", GROUP="plugdev" - -# Olimex ARM-JTAG-EW -SYSFS{idVendor}=="15ba", SYSFS{idProduct}=="001e", MODE="664", GROUP="plugdev" - -# USBprog with OpenOCD firmware -SYSFS{idVendor}=="1781", SYSFS{idProduct}=="0c63", MODE="664", GROUP="plugdev" - -# Amontec JTAGkey and JTAGkey-tiny -SYSFS{idVendor}=="0403", SYSFS{idProduct}=="cff8", MODE="664", GROUP="plugdev" - -# Amontec JTAGkey-HiSpeed -SYSFS{idVendor}=="0fbb", SYSFS{idProduct}=="1000", MODE="664", GROUP="plugdev" - -# Axiom AXM-0432 Link (Symphony SoundBite?) -# Calao Systems USB-A9260-C01 -# TinCanTools Flyswatter -# OOCD-Link -# Marvell Sheevaplug (early development versions) -SYSFS{idVendor}=="0403", SYSFS{idProduct}=="6010", MODE="664", GROUP="plugdev" - -# Calao Systems USB-A9260-C02 -SYSFS{idVendor}=="0403", SYSFS{idProduct}=="6001", MODE="664", GROUP="plugdev" - -# IAR J-Link USB -SYSFS{idVendor}=="1366", SYSFS{idProduct}=="0101", MODE="664", GROUP="plugdev" - -# Raisonance RLink -SYSFS{idVendor}=="138e", SYSFS{idProduct}=="9000", MODE="664", GROUP="plugdev" - -# Hitex STR9-comStick -SYSFS{idVendor}=="0640", SYSFS{idProduct}=="002c", MODE="664", GROUP="plugdev" - -# Hitex STM32-PerformanceStick -SYSFS{idVendor}=="0640", SYSFS{idProduct}=="002d", MODE="664", GROUP="plugdev" - -# Luminary Micro Stellaris/LM3S811 -SYSFS{idVendor}=="0403", SYSFS{idProduct}=="bcd9", MODE="664", GROUP="plugdev" - -# Xverve Signalyzer Tool (DT-USB-ST) -SYSFS{idVendor}=="0403", SYSFS{idProduct}=="bca0", MODE="664", GROUP="plugdev" - -# egnite Turtelizer 2 -SYSFS{idVendor}=="0403", SYSFS{idProduct}=="bdc8", MODE="664", GROUP="plugdev" - -# Marvell Sheevaplug -SYSFS{idVendor}=="9e88", SYSFS{idProduct}=="9e8f", MODE="664", GROUP="plugdev" - -LABEL="openocd_rules_end" - +BUS!="usb", ACTION!="add", SUBSYSTEM!=="usb_device", GOTO="openocd_rules_end" + +# Olimex ARM-USB-OCD +SYSFS{idVendor}=="15ba", SYSFS{idProduct}=="0003", MODE="664", GROUP="plugdev" + +# Olimex ARM-USB-OCD-TINY +SYSFS{idVendor}=="15ba", SYSFS{idProduct}=="0004", MODE="664", GROUP="plugdev" + +# Olimex ARM-JTAG-EW +SYSFS{idVendor}=="15ba", SYSFS{idProduct}=="001e", MODE="664", GROUP="plugdev" + +# USBprog with OpenOCD firmware +SYSFS{idVendor}=="1781", SYSFS{idProduct}=="0c63", MODE="664", GROUP="plugdev" + +# Amontec JTAGkey and JTAGkey-tiny +SYSFS{idVendor}=="0403", SYSFS{idProduct}=="cff8", MODE="664", GROUP="plugdev" + +# Amontec JTAGkey-HiSpeed +SYSFS{idVendor}=="0fbb", SYSFS{idProduct}=="1000", MODE="664", GROUP="plugdev" + +# Axiom AXM-0432 Link (Symphony SoundBite?) +# Calao Systems USB-A9260-C01 +# TinCanTools Flyswatter +# OOCD-Link +# Marvell Sheevaplug (early development versions) +SYSFS{idVendor}=="0403", SYSFS{idProduct}=="6010", MODE="664", GROUP="plugdev" + +# Calao Systems USB-A9260-C02 +SYSFS{idVendor}=="0403", SYSFS{idProduct}=="6001", MODE="664", GROUP="plugdev" + +# IAR J-Link USB +SYSFS{idVendor}=="1366", SYSFS{idProduct}=="0101", MODE="664", GROUP="plugdev" + +# Raisonance RLink +SYSFS{idVendor}=="138e", SYSFS{idProduct}=="9000", MODE="664", GROUP="plugdev" + +# Hitex STR9-comStick +SYSFS{idVendor}=="0640", SYSFS{idProduct}=="002c", MODE="664", GROUP="plugdev" + +# Hitex STM32-PerformanceStick +SYSFS{idVendor}=="0640", SYSFS{idProduct}=="002d", MODE="664", GROUP="plugdev" + +# Luminary Micro Stellaris/LM3S811 +SYSFS{idVendor}=="0403", SYSFS{idProduct}=="bcd9", MODE="664", GROUP="plugdev" + +# Xverve Signalyzer Tool (DT-USB-ST) +SYSFS{idVendor}=="0403", SYSFS{idProduct}=="bca0", MODE="664", GROUP="plugdev" + +# egnite Turtelizer 2 +SYSFS{idVendor}=="0403", SYSFS{idProduct}=="bdc8", MODE="664", GROUP="plugdev" + +# Marvell Sheevaplug +SYSFS{idVendor}=="9e88", SYSFS{idProduct}=="9e8f", MODE="664", GROUP="plugdev" + +LABEL="openocd_rules_end" + Property changes on: trunk/contrib/openocd.udev ___________________________________________________________________ Name: svn:eol-style + native |
|
From: oharboe at B. <oh...@ma...> - 2009-04-28 08:28:41
|
Author: oharboe
Date: 2009-04-28 08:28:39 +0200 (Tue, 28 Apr 2009)
New Revision: 1549
Modified:
trunk/src/jtag/dummy.c
trunk/src/server/httpd/Stylizer.java
trunk/src/target/arm_adi_v5.c
trunk/src/target/arm_adi_v5.h
trunk/src/target/target/at91sam9260_ext_RAM_ext_flash.cfg
trunk/src/target/target/mega128.cfg
trunk/testing/examples/SAM7X256Test/prj/eclipse_ram.gdb
trunk/testing/examples/SAM7X256Test/prj/eclipse_rom.gdb
trunk/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg
trunk/testing/examples/SAM7X256Test/prj/sam7x256_ram.ld
trunk/testing/examples/SAM7X256Test/prj/sam7x256_reset.script
trunk/testing/examples/SAM7X256Test/prj/sam7x256_rom.ld
trunk/testing/examples/STM32-103/readme.txt
Log:
eol-style native
Modified: trunk/src/jtag/dummy.c
===================================================================
--- trunk/src/jtag/dummy.c 2009-04-27 19:35:31 UTC (rev 1548)
+++ trunk/src/jtag/dummy.c 2009-04-28 06:28:39 UTC (rev 1549)
@@ -1,186 +1,186 @@
-/***************************************************************************
- * Copyright (C) 2008 by vind Harboe *
- * oyv...@zy... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- ***************************************************************************/
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "replacements.h"
-
-#include "jtag.h"
-#include "bitbang.h"
-
-
-/* my private tap controller state, which tracks state for calling code */
-static tap_state_t dummy_state = TAP_RESET;
-
-static int dummy_clock; /* edge detector */
-
-static int clock_count; /* count clocks in any stable state, only stable states */
-
-static u32 dummy_data;
-
-
-static int dummy_speed(int speed);
-static int dummy_register_commands(struct command_context_s *cmd_ctx);
-static int dummy_init(void);
-static int dummy_quit(void);
-static int dummy_khz(int khz, int *jtag_speed);
-static int dummy_speed_div(int speed, int *khz);
-
-
-/* The dummy driver is used to easily check the code path
- * where the target is unresponsive.
- */
-jtag_interface_t dummy_interface =
-{
- .name = "dummy",
-
- .execute_queue = bitbang_execute_queue,
-
- .speed = dummy_speed,
- .register_commands = dummy_register_commands,
- .khz = dummy_khz,
- .speed_div = dummy_speed_div,
-
- .init = dummy_init,
- .quit = dummy_quit,
-};
-
-static int dummy_read(void);
-static void dummy_write(int tck, int tms, int tdi);
-static void dummy_reset(int trst, int srst);
-static void dummy_led(int on);
-
-static bitbang_interface_t dummy_bitbang =
-{
- .read = dummy_read,
- .write = dummy_write,
- .reset = dummy_reset,
- .blink = dummy_led
-};
-
-static int dummy_read(void)
-{
- int data = 1 & dummy_data;
- dummy_data = (dummy_data >> 1) | (1<<31);
- return data;
-}
-
-
-static void dummy_write(int tck, int tms, int tdi)
-{
- /* TAP standard: "state transitions occur on rising edge of clock" */
- if( tck != dummy_clock )
- {
- if( tck )
- {
- tap_state_t old_state = dummy_state;
- dummy_state = tap_state_transition( old_state, tms );
-
- if( old_state != dummy_state )
- {
- if( clock_count )
- {
- LOG_DEBUG("dummy_tap: %d stable clocks", clock_count);
- clock_count = 0;
- }
-
- LOG_DEBUG("dummy_tap: %s", tap_state_name(dummy_state) );
-
-#if defined(DEBUG)
- if(dummy_state == TAP_DRCAPTURE)
- dummy_data = 0x01255043;
-#endif
- }
- else
- {
- /* this is a stable state clock edge, no change of state here,
- * simply increment clock_count for subsequent logging
- */
- ++clock_count;
- }
- }
- dummy_clock = tck;
- }
-}
-
-static void dummy_reset(int trst, int srst)
-{
- dummy_clock = 0;
-
- if (trst || (srst && (jtag_reset_config & RESET_SRST_PULLS_TRST)))
- dummy_state = TAP_RESET;
-
- LOG_DEBUG("reset to: %s", tap_state_name(dummy_state) );
-}
-
-static int dummy_khz(int khz, int *jtag_speed)
-{
- if (khz==0)
- {
- *jtag_speed=0;
- }
- else
- {
- *jtag_speed=64000/khz;
- }
- return ERROR_OK;
-}
-
-static int dummy_speed_div(int speed, int *khz)
-{
- if (speed==0)
- {
- *khz = 0;
- }
- else
- {
- *khz=64000/speed;
- }
-
- return ERROR_OK;
-}
-
-static int dummy_speed(int speed)
-{
- return ERROR_OK;
-}
-
-static int dummy_register_commands(struct command_context_s *cmd_ctx)
-{
- return ERROR_OK;
-}
-
-static int dummy_init(void)
-{
- bitbang_interface = &dummy_bitbang;
-
- return ERROR_OK;
-}
-
-static int dummy_quit(void)
-{
- return ERROR_OK;
-}
-
-static void dummy_led(int on)
-{
-}
-
+/***************************************************************************
+ * Copyright (C) 2008 by vind Harboe *
+ * oyv...@zy... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+
+#include "jtag.h"
+#include "bitbang.h"
+
+
+/* my private tap controller state, which tracks state for calling code */
+static tap_state_t dummy_state = TAP_RESET;
+
+static int dummy_clock; /* edge detector */
+
+static int clock_count; /* count clocks in any stable state, only stable states */
+
+static u32 dummy_data;
+
+
+static int dummy_speed(int speed);
+static int dummy_register_commands(struct command_context_s *cmd_ctx);
+static int dummy_init(void);
+static int dummy_quit(void);
+static int dummy_khz(int khz, int *jtag_speed);
+static int dummy_speed_div(int speed, int *khz);
+
+
+/* The dummy driver is used to easily check the code path
+ * where the target is unresponsive.
+ */
+jtag_interface_t dummy_interface =
+{
+ .name = "dummy",
+
+ .execute_queue = bitbang_execute_queue,
+
+ .speed = dummy_speed,
+ .register_commands = dummy_register_commands,
+ .khz = dummy_khz,
+ .speed_div = dummy_speed_div,
+
+ .init = dummy_init,
+ .quit = dummy_quit,
+};
+
+static int dummy_read(void);
+static void dummy_write(int tck, int tms, int tdi);
+static void dummy_reset(int trst, int srst);
+static void dummy_led(int on);
+
+static bitbang_interface_t dummy_bitbang =
+{
+ .read = dummy_read,
+ .write = dummy_write,
+ .reset = dummy_reset,
+ .blink = dummy_led
+};
+
+static int dummy_read(void)
+{
+ int data = 1 & dummy_data;
+ dummy_data = (dummy_data >> 1) | (1<<31);
+ return data;
+}
+
+
+static void dummy_write(int tck, int tms, int tdi)
+{
+ /* TAP standard: "state transitions occur on rising edge of clock" */
+ if( tck != dummy_clock )
+ {
+ if( tck )
+ {
+ tap_state_t old_state = dummy_state;
+ dummy_state = tap_state_transition( old_state, tms );
+
+ if( old_state != dummy_state )
+ {
+ if( clock_count )
+ {
+ LOG_DEBUG("dummy_tap: %d stable clocks", clock_count);
+ clock_count = 0;
+ }
+
+ LOG_DEBUG("dummy_tap: %s", tap_state_name(dummy_state) );
+
+#if defined(DEBUG)
+ if(dummy_state == TAP_DRCAPTURE)
+ dummy_data = 0x01255043;
+#endif
+ }
+ else
+ {
+ /* this is a stable state clock edge, no change of state here,
+ * simply increment clock_count for subsequent logging
+ */
+ ++clock_count;
+ }
+ }
+ dummy_clock = tck;
+ }
+}
+
+static void dummy_reset(int trst, int srst)
+{
+ dummy_clock = 0;
+
+ if (trst || (srst && (jtag_reset_config & RESET_SRST_PULLS_TRST)))
+ dummy_state = TAP_RESET;
+
+ LOG_DEBUG("reset to: %s", tap_state_name(dummy_state) );
+}
+
+static int dummy_khz(int khz, int *jtag_speed)
+{
+ if (khz==0)
+ {
+ *jtag_speed=0;
+ }
+ else
+ {
+ *jtag_speed=64000/khz;
+ }
+ return ERROR_OK;
+}
+
+static int dummy_speed_div(int speed, int *khz)
+{
+ if (speed==0)
+ {
+ *khz = 0;
+ }
+ else
+ {
+ *khz=64000/speed;
+ }
+
+ return ERROR_OK;
+}
+
+static int dummy_speed(int speed)
+{
+ return ERROR_OK;
+}
+
+static int dummy_register_commands(struct command_context_s *cmd_ctx)
+{
+ return ERROR_OK;
+}
+
+static int dummy_init(void)
+{
+ bitbang_interface = &dummy_bitbang;
+
+ return ERROR_OK;
+}
+
+static int dummy_quit(void)
+{
+ return ERROR_OK;
+}
+
+static void dummy_led(int on)
+{
+}
+
Property changes on: trunk/src/jtag/dummy.c
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/server/httpd/Stylizer.java
===================================================================
--- trunk/src/server/httpd/Stylizer.java 2009-04-27 19:35:31 UTC (rev 1548)
+++ trunk/src/server/httpd/Stylizer.java 2009-04-28 06:28:39 UTC (rev 1549)
@@ -1,114 +1,114 @@
-import java.io.File;
-import java.io.FileOutputStream;
-import java.io.IOException;
-import java.io.OutputStream;
-
-import javax.xml.parsers.DocumentBuilder;
-import javax.xml.parsers.DocumentBuilderFactory;
-import javax.xml.parsers.ParserConfigurationException;
-import javax.xml.transform.Transformer;
-import javax.xml.transform.TransformerConfigurationException;
-import javax.xml.transform.TransformerException;
-import javax.xml.transform.TransformerFactory;
-import javax.xml.transform.dom.DOMSource;
-import javax.xml.transform.stream.StreamResult;
-import javax.xml.transform.stream.StreamSource;
-
-import org.apache.xpath.XPathAPI;
-import org.w3c.dom.Document;
-import org.w3c.dom.Node;
-import org.w3c.dom.NodeList;
-import org.xml.sax.SAXException;
-
-/** used to generate .tcl files from */
-public class Stylizer
-{
- // Global value so it can be ref'd by the tree-adapter
- static Document document;
- public static void main(String argv[])
- {
- if (argv.length != 3)
- {
- System.err.println("Usage: java Stylizer stylesheet xmlfile outputdir");
- System.exit(1);
- }
- DocumentBuilderFactory factory = DocumentBuilderFactory.newInstance();
- try
- {
- System.err.println("Starting conversion...");
-
- File stylesheet = new File(argv[0]);
- File datafile = new File(argv[1]);
- DocumentBuilder builder = factory.newDocumentBuilder();
- document = builder.parse(datafile);
-
- NodeList list = XPathAPI.selectNodeList(document, "website/language/page");
-
- for (int i=0; i<list.getLength(); i++)
- {
- Node node=list.item(i);
-
- // Use a Transformer for output
- TransformerFactory tFactory = TransformerFactory.newInstance();
- StreamSource stylesource = new StreamSource(stylesheet);
- Transformer transformer = tFactory.newTransformer(stylesource);
-
- Node fileName = XPathAPI.selectSingleNode(node, "outfile/text()");
-
- System.err.println("Converting " + fileName.getNodeValue());
- DOMSource source = new DOMSource(document);
-
- OutputStream output=new FileOutputStream(new File(argv[2], fileName.getNodeValue()));
-
-
- try
- {
- StreamResult result = new StreamResult(output);
-
- transformer.setParameter("pagetogenerate", fileName.getNodeValue());
- transformer.transform(source, result);
- }
- finally
- {
- output.close();
- }
- }
- } catch (TransformerConfigurationException tce)
- {
- // Error generated by the parser
- System.out.println("\n** Transformer Factory error");
- System.out.println(" " + tce.getMessage());
- // Use the contained exception, if any
- Throwable x = tce;
- if (tce.getException() != null)
- x = tce.getException();
- x.printStackTrace();
- } catch (TransformerException te)
- {
- // Error generated by the parser
- System.out.println("\n** Transformation error");
- System.out.println(" " + te.getMessage());
- // Use the contained exception, if any
- Throwable x = te;
- if (te.getException() != null)
- x = te.getException();
- x.printStackTrace();
- } catch (SAXException sxe)
- {
- // Error generated by this application
- // (or a parser-initialization error)
- Exception x = sxe;
- if (sxe.getException() != null)
- x = sxe.getException();
- x.printStackTrace();
- } catch (ParserConfigurationException pce)
- {
- // Parser with specified options can't be built
- pce.printStackTrace();
- } catch (IOException ioe)
- {
- // I/O error
- ioe.printStackTrace();
- }
- } // main
-}
+import java.io.File;
+import java.io.FileOutputStream;
+import java.io.IOException;
+import java.io.OutputStream;
+
+import javax.xml.parsers.DocumentBuilder;
+import javax.xml.parsers.DocumentBuilderFactory;
+import javax.xml.parsers.ParserConfigurationException;
+import javax.xml.transform.Transformer;
+import javax.xml.transform.TransformerConfigurationException;
+import javax.xml.transform.TransformerException;
+import javax.xml.transform.TransformerFactory;
+import javax.xml.transform.dom.DOMSource;
+import javax.xml.transform.stream.StreamResult;
+import javax.xml.transform.stream.StreamSource;
+
+import org.apache.xpath.XPathAPI;
+import org.w3c.dom.Document;
+import org.w3c.dom.Node;
+import org.w3c.dom.NodeList;
+import org.xml.sax.SAXException;
+
+/** used to generate .tcl files from */
+public class Stylizer
+{
+ // Global value so it can be ref'd by the tree-adapter
+ static Document document;
+ public static void main(String argv[])
+ {
+ if (argv.length != 3)
+ {
+ System.err.println("Usage: java Stylizer stylesheet xmlfile outputdir");
+ System.exit(1);
+ }
+ DocumentBuilderFactory factory = DocumentBuilderFactory.newInstance();
+ try
+ {
+ System.err.println("Starting conversion...");
+
+ File stylesheet = new File(argv[0]);
+ File datafile = new File(argv[1]);
+ DocumentBuilder builder = factory.newDocumentBuilder();
+ document = builder.parse(datafile);
+
+ NodeList list = XPathAPI.selectNodeList(document, "website/language/page");
+
+ for (int i=0; i<list.getLength(); i++)
+ {
+ Node node=list.item(i);
+
+ // Use a Transformer for output
+ TransformerFactory tFactory = TransformerFactory.newInstance();
+ StreamSource stylesource = new StreamSource(stylesheet);
+ Transformer transformer = tFactory.newTransformer(stylesource);
+
+ Node fileName = XPathAPI.selectSingleNode(node, "outfile/text()");
+
+ System.err.println("Converting " + fileName.getNodeValue());
+ DOMSource source = new DOMSource(document);
+
+ OutputStream output=new FileOutputStream(new File(argv[2], fileName.getNodeValue()));
+
+
+ try
+ {
+ StreamResult result = new StreamResult(output);
+
+ transformer.setParameter("pagetogenerate", fileName.getNodeValue());
+ transformer.transform(source, result);
+ }
+ finally
+ {
+ output.close();
+ }
+ }
+ } catch (TransformerConfigurationException tce)
+ {
+ // Error generated by the parser
+ System.out.println("\n** Transformer Factory error");
+ System.out.println(" " + tce.getMessage());
+ // Use the contained exception, if any
+ Throwable x = tce;
+ if (tce.getException() != null)
+ x = tce.getException();
+ x.printStackTrace();
+ } catch (TransformerException te)
+ {
+ // Error generated by the parser
+ System.out.println("\n** Transformation error");
+ System.out.println(" " + te.getMessage());
+ // Use the contained exception, if any
+ Throwable x = te;
+ if (te.getException() != null)
+ x = te.getException();
+ x.printStackTrace();
+ } catch (SAXException sxe)
+ {
+ // Error generated by this application
+ // (or a parser-initialization error)
+ Exception x = sxe;
+ if (sxe.getException() != null)
+ x = sxe.getException();
+ x.printStackTrace();
+ } catch (ParserConfigurationException pce)
+ {
+ // Parser with specified options can't be built
+ pce.printStackTrace();
+ } catch (IOException ioe)
+ {
+ // I/O error
+ ioe.printStackTrace();
+ }
+ } // main
+}
Property changes on: trunk/src/server/httpd/Stylizer.java
___________________________________________________________________
Name: svn:eol-style
+ native
Property changes on: trunk/src/target/arm_adi_v5.c
___________________________________________________________________
Name: svn:eol-style
+ native
Property changes on: trunk/src/target/arm_adi_v5.h
___________________________________________________________________
Name: svn:eol-style
+ native
Property changes on: trunk/src/target/target/at91sam9260_ext_RAM_ext_flash.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/target/target/mega128.cfg
===================================================================
--- trunk/src/target/target/mega128.cfg 2009-04-27 19:35:31 UTC (rev 1548)
+++ trunk/src/target/target/mega128.cfg 2009-04-28 06:28:39 UTC (rev 1549)
@@ -1,42 +1,42 @@
-# for avr
-
- set _CHIPNAME avr
- set _ENDIAN little
-
-# jtag speed
-jtag_khz 4500
-
-reset_config srst_only
-jtag_nsrst_delay 100
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x8970203F
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
-
-#$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-
-flash bank avr 0 0 0 0 0
-
-#to use it, script will be like:
-#init
-#jtag_khz 4500
-#reset init
-#verify_ircapture disable
-#
-#halt
-#wait halt
-#poll
-#avr mass_erase 0
-#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex
-#reset run
-#shutdown
-#
-# For more information about the configuration files, take a look at:
-# openocd.texi
+# for avr
+
+ set _CHIPNAME avr
+ set _ENDIAN little
+
+# jtag speed
+jtag_khz 4500
+
+reset_config srst_only
+jtag_nsrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x8970203F
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
+
+#$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
+
+flash bank avr 0 0 0 0 0
+
+#to use it, script will be like:
+#init
+#jtag_khz 4500
+#reset init
+#verify_ircapture disable
+#
+#halt
+#wait halt
+#poll
+#avr mass_erase 0
+#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex
+#reset run
+#shutdown
+#
+# For more information about the configuration files, take a look at:
+# openocd.texi
Property changes on: trunk/src/target/target/mega128.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/testing/examples/SAM7X256Test/prj/eclipse_ram.gdb
===================================================================
--- trunk/testing/examples/SAM7X256Test/prj/eclipse_ram.gdb 2009-04-27 19:35:31 UTC (rev 1548)
+++ trunk/testing/examples/SAM7X256Test/prj/eclipse_ram.gdb 2009-04-28 06:28:39 UTC (rev 1549)
@@ -1,32 +1,32 @@
-target remote localhost:3333
-monitor reset
-monitor sleep 500
-monitor poll
-monitor soft_reset_halt
-monitor arm7_9 sw_bkpts enable
-
-# WDT_MR, disable watchdog
-monitor mww 0xFFFFFD44 0x00008000
-
-# RSTC_MR, enable user reset
-monitor mww 0xfffffd08 0xa5000001
-
-# CKGR_MOR
-monitor mww 0xFFFFFC20 0x00000601
-monitor sleep 10
-
-# CKGR_PLLR
-monitor mww 0xFFFFFC2C 0x00481c0e
-monitor sleep 10
-
-# PMC_MCKR
-monitor mww 0xFFFFFC30 0x00000007
-monitor sleep 10
-
-# PMC_IER
-monitor mww 0xFFFFFF60 0x00480100
-monitor sleep 100
-
-load
-break main
-continue
+target remote localhost:3333
+monitor reset
+monitor sleep 500
+monitor poll
+monitor soft_reset_halt
+monitor arm7_9 sw_bkpts enable
+
+# WDT_MR, disable watchdog
+monitor mww 0xFFFFFD44 0x00008000
+
+# RSTC_MR, enable user reset
+monitor mww 0xfffffd08 0xa5000001
+
+# CKGR_MOR
+monitor mww 0xFFFFFC20 0x00000601
+monitor sleep 10
+
+# CKGR_PLLR
+monitor mww 0xFFFFFC2C 0x00481c0e
+monitor sleep 10
+
+# PMC_MCKR
+monitor mww 0xFFFFFC30 0x00000007
+monitor sleep 10
+
+# PMC_IER
+monitor mww 0xFFFFFF60 0x00480100
+monitor sleep 100
+
+load
+break main
+continue
Property changes on: trunk/testing/examples/SAM7X256Test/prj/eclipse_ram.gdb
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/testing/examples/SAM7X256Test/prj/eclipse_rom.gdb
===================================================================
--- trunk/testing/examples/SAM7X256Test/prj/eclipse_rom.gdb 2009-04-27 19:35:31 UTC (rev 1548)
+++ trunk/testing/examples/SAM7X256Test/prj/eclipse_rom.gdb 2009-04-28 06:28:39 UTC (rev 1549)
@@ -1,32 +1,32 @@
-target remote localhost:3333
-monitor reset
-monitor sleep 500
-monitor poll
-monitor soft_reset_halt
-monitor arm7_9 force_hw_bkpts enable
-
-# WDT_MR, disable watchdog
-monitor mww 0xFFFFFD44 0x00008000
-
-# RSTC_MR, enable user reset
-monitor mww 0xfffffd08 0xa5000001
-
-# CKGR_MOR
-monitor mww 0xFFFFFC20 0x00000601
-monitor sleep 10
-
-# CKGR_PLLR
-monitor mww 0xFFFFFC2C 0x00481c0e
-monitor sleep 10
-
-# PMC_MCKR
-monitor mww 0xFFFFFC30 0x00000007
-monitor sleep 10
-
-# PMC_IER
-monitor mww 0xFFFFFF60 0x00480100
-monitor sleep 100
-
-load
-break main
-continue
+target remote localhost:3333
+monitor reset
+monitor sleep 500
+monitor poll
+monitor soft_reset_halt
+monitor arm7_9 force_hw_bkpts enable
+
+# WDT_MR, disable watchdog
+monitor mww 0xFFFFFD44 0x00008000
+
+# RSTC_MR, enable user reset
+monitor mww 0xfffffd08 0xa5000001
+
+# CKGR_MOR
+monitor mww 0xFFFFFC20 0x00000601
+monitor sleep 10
+
+# CKGR_PLLR
+monitor mww 0xFFFFFC2C 0x00481c0e
+monitor sleep 10
+
+# PMC_MCKR
+monitor mww 0xFFFFFC30 0x00000007
+monitor sleep 10
+
+# PMC_IER
+monitor mww 0xFFFFFF60 0x00480100
+monitor sleep 100
+
+load
+break main
+continue
Property changes on: trunk/testing/examples/SAM7X256Test/prj/eclipse_rom.gdb
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg
===================================================================
--- trunk/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg 2009-04-27 19:35:31 UTC (rev 1548)
+++ trunk/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg 2009-04-28 06:28:39 UTC (rev 1549)
@@ -1,40 +1,40 @@
-#daemon configuration
-telnet_port 4444
-gdb_port 3333
-
-# tell gdb our flash memory map
-# and enable flash programming
-gdb_memory_map enable
-gdb_flash_program enable
-
-#interface
-interface ft2232
-ft2232_device_desc "Amontec JTAGkey A"
-ft2232_layout jtagkey
-ft2232_vid_pid 0x0403 0xcff8
-jtag_speed 0
-jtag_nsrst_delay 200
-jtag_ntrst_delay 200
-
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config srst_only srst_pulls_trst
-
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-jtag_device 4 0x1 0xf 0xe
-
-#target configuration
-target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
-[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup false
-
-target_script 0 reset .\prj\sam7x256_reset.script
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank at91sam7 0 0 0 0 0
-
-# For more information about the configuration files, take a look at:
-# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
-
-init
-reset halt
+#daemon configuration
+telnet_port 4444
+gdb_port 3333
+
+# tell gdb our flash memory map
+# and enable flash programming
+gdb_memory_map enable
+gdb_flash_program enable
+
+#interface
+interface ft2232
+ft2232_device_desc "Amontec JTAGkey A"
+ft2232_layout jtagkey
+ft2232_vid_pid 0x0403 0xcff8
+jtag_speed 0
+jtag_nsrst_delay 200
+jtag_ntrst_delay 200
+
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config srst_only srst_pulls_trst
+
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+jtag_device 4 0x1 0xf 0xe
+
+#target configuration
+target create target0 arm7tdmi -endian little -chain-position 0 -variant arm7tdmi
+[new_target_name] configure -work-area-virt 0 -work-area-phys 0x00200000 -work-area-size 0x4000 -work-area-backup false
+
+target_script 0 reset .\prj\sam7x256_reset.script
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank at91sam7 0 0 0 0 0
+
+# For more information about the configuration files, take a look at:
+# http://openfacts.berlios.de/index-en.phtml?title=Open+On-Chip+Debugger
+
+init
+reset halt
Property changes on: trunk/testing/examples/SAM7X256Test/prj/sam7x256_jtagkey.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/testing/examples/SAM7X256Test/prj/sam7x256_ram.ld
===================================================================
--- trunk/testing/examples/SAM7X256Test/prj/sam7x256_ram.ld 2009-04-27 19:35:31 UTC (rev 1548)
+++ trunk/testing/examples/SAM7X256Test/prj/sam7x256_ram.ld 2009-04-28 06:28:39 UTC (rev 1549)
@@ -1,132 +1,132 @@
-/****************************************************************************
-* Copyright (c) 2006 by Michael Fischer. All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* 1. Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* 2. Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* 3. Neither the name of the author nor the names of its contributors may
-* be used to endorse or promote products derived from this software
-* without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
-* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-* SUCH DAMAGE.
-*
-****************************************************************************
-*
-* History:
-*
-* 30.03.06 mifi First Version
-****************************************************************************/
-
-
-ENTRY(ResetHandler)
-SEARCH_DIR(.)
-
-/*
- * Define stack size here
- */
-FIQ_STACK_SIZE = 0x0100;
-IRQ_STACK_SIZE = 0x0100;
-ABT_STACK_SIZE = 0x0100;
-UND_STACK_SIZE = 0x0100;
-SVC_STACK_SIZE = 0x0400;
-
-
-MEMORY
-{
- ram : org = 0x00200000, len = 64k
-}
-
-/*
- * Do not change the next code
- */
-SECTIONS
-{
- .text :
- {
- *(.vectors);
- . = ALIGN(4);
- *(.init);
- . = ALIGN(4);
- *(.text);
- . = ALIGN(4);
- *(.rodata);
- . = ALIGN(4);
- *(.rodata*);
- . = ALIGN(4);
- *(.glue_7t);
- . = ALIGN(4);
- *(.glue_7);
- . = ALIGN(4);
- etext = .;
- } > ram
-
- .data :
- {
- PROVIDE (__data_start = .);
- *(.data)
- . = ALIGN(4);
- edata = .;
- _edata = .;
- PROVIDE (__data_end = .);
- } > ram
-
- .bss :
- {
- PROVIDE (__bss_start = .);
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- PROVIDE (__bss_end = .);
-
- . = ALIGN(256);
-
- PROVIDE (__stack_start = .);
-
- PROVIDE (__stack_fiq_start = .);
- . += FIQ_STACK_SIZE;
- . = ALIGN(4);
- PROVIDE (__stack_fiq_end = .);
-
- PROVIDE (__stack_irq_start = .);
- . += IRQ_STACK_SIZE;
- . = ALIGN(4);
- PROVIDE (__stack_irq_end = .);
-
- PROVIDE (__stack_abt_start = .);
- . += ABT_STACK_SIZE;
- . = ALIGN(4);
- PROVIDE (__stack_abt_end = .);
-
- PROVIDE (__stack_und_start = .);
- . += UND_STACK_SIZE;
- . = ALIGN(4);
- PROVIDE (__stack_und_end = .);
-
- PROVIDE (__stack_svc_start = .);
- . += SVC_STACK_SIZE;
- . = ALIGN(4);
- PROVIDE (__stack_svc_end = .);
- PROVIDE (__stack_end = .);
- PROVIDE (__heap_start = .);
- } > ram
-
-}
-/*** EOF ***/
-
+/****************************************************************************
+* Copyright (c) 2006 by Michael Fischer. All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the author nor the names of its contributors may
+* be used to endorse or promote products derived from this software
+* without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+* SUCH DAMAGE.
+*
+****************************************************************************
+*
+* History:
+*
+* 30.03.06 mifi First Version
+****************************************************************************/
+
+
+ENTRY(ResetHandler)
+SEARCH_DIR(.)
+
+/*
+ * Define stack size here
+ */
+FIQ_STACK_SIZE = 0x0100;
+IRQ_STACK_SIZE = 0x0100;
+ABT_STACK_SIZE = 0x0100;
+UND_STACK_SIZE = 0x0100;
+SVC_STACK_SIZE = 0x0400;
+
+
+MEMORY
+{
+ ram : org = 0x00200000, len = 64k
+}
+
+/*
+ * Do not change the next code
+ */
+SECTIONS
+{
+ .text :
+ {
+ *(.vectors);
+ . = ALIGN(4);
+ *(.init);
+ . = ALIGN(4);
+ *(.text);
+ . = ALIGN(4);
+ *(.rodata);
+ . = ALIGN(4);
+ *(.rodata*);
+ . = ALIGN(4);
+ *(.glue_7t);
+ . = ALIGN(4);
+ *(.glue_7);
+ . = ALIGN(4);
+ etext = .;
+ } > ram
+
+ .data :
+ {
+ PROVIDE (__data_start = .);
+ *(.data)
+ . = ALIGN(4);
+ edata = .;
+ _edata = .;
+ PROVIDE (__data_end = .);
+ } > ram
+
+ .bss :
+ {
+ PROVIDE (__bss_start = .);
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ PROVIDE (__bss_end = .);
+
+ . = ALIGN(256);
+
+ PROVIDE (__stack_start = .);
+
+ PROVIDE (__stack_fiq_start = .);
+ . += FIQ_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_fiq_end = .);
+
+ PROVIDE (__stack_irq_start = .);
+ . += IRQ_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_irq_end = .);
+
+ PROVIDE (__stack_abt_start = .);
+ . += ABT_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_abt_end = .);
+
+ PROVIDE (__stack_und_start = .);
+ . += UND_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_und_end = .);
+
+ PROVIDE (__stack_svc_start = .);
+ . += SVC_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_svc_end = .);
+ PROVIDE (__stack_end = .);
+ PROVIDE (__heap_start = .);
+ } > ram
+
+}
+/*** EOF ***/
+
Property changes on: trunk/testing/examples/SAM7X256Test/prj/sam7x256_ram.ld
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/testing/examples/SAM7X256Test/prj/sam7x256_reset.script
===================================================================
--- trunk/testing/examples/SAM7X256Test/prj/sam7x256_reset.script 2009-04-27 19:35:31 UTC (rev 1548)
+++ trunk/testing/examples/SAM7X256Test/prj/sam7x256_reset.script 2009-04-28 06:28:39 UTC (rev 1549)
@@ -1,17 +1,17 @@
-#
-# Init - taken form the script openocd_at91sam7_ecr.script
-#
-# I take this script from the following page:
-#
-# http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html
-#
-mww 0xfffffd44 0x00008000 # disable watchdog
-mww 0xfffffd08 0xa5000001 # enable user reset
-mww 0xfffffc20 0x00000601 # CKGR_MOR : enable the main oscillator
-sleep 10
-mww 0xfffffc2c 0x00481c0e # CKGR_PLLR: 96.1097 MHz
-sleep 10
-mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
-sleep 10
-mww 0xffffff60 0x003c0100 # MC_FMR: flash mode (FWS=1,FMCN=60)
-sleep 100
+#
+# Init - taken form the script openocd_at91sam7_ecr.script
+#
+# I take this script from the following page:
+#
+# http://www.siwawi.arubi.uni-kl.de/avr_projects/arm_projects/openocd_intro/index.html
+#
+mww 0xfffffd44 0x00008000 # disable watchdog
+mww 0xfffffd08 0xa5000001 # enable user reset
+mww 0xfffffc20 0x00000601 # CKGR_MOR : enable the main oscillator
+sleep 10
+mww 0xfffffc2c 0x00481c0e # CKGR_PLLR: 96.1097 MHz
+sleep 10
+mww 0xfffffc30 0x00000007 # PMC_MCKR : MCK = PLL / 2 ~= 48 MHz
+sleep 10
+mww 0xffffff60 0x003c0100 # MC_FMR: flash mode (FWS=1,FMCN=60)
+sleep 100
Property changes on: trunk/testing/examples/SAM7X256Test/prj/sam7x256_reset.script
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/testing/examples/SAM7X256Test/prj/sam7x256_rom.ld
===================================================================
--- trunk/testing/examples/SAM7X256Test/prj/sam7x256_rom.ld 2009-04-27 19:35:31 UTC (rev 1548)
+++ trunk/testing/examples/SAM7X256Test/prj/sam7x256_rom.ld 2009-04-28 06:28:39 UTC (rev 1549)
@@ -1,133 +1,133 @@
-/****************************************************************************
-* Copyright (c) 2006 by Michael Fischer. All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without
-* modification, are permitted provided that the following conditions
-* are met:
-*
-* 1. Redistributions of source code must retain the above copyright
-* notice, this list of conditions and the following disclaimer.
-* 2. Redistributions in binary form must reproduce the above copyright
-* notice, this list of conditions and the following disclaimer in the
-* documentation and/or other materials provided with the distribution.
-* 3. Neither the name of the author nor the names of its contributors may
-* be used to endorse or promote products derived from this software
-* without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
-* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
-* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
-* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
-* SUCH DAMAGE.
-*
-****************************************************************************
-*
-* History:
-*
-* 26.01.08 mifi First Version
-****************************************************************************/
-
-
-ENTRY(ResetHandler)
-SEARCH_DIR(.)
-
-/*
- * Define stack size here
- */
-FIQ_STACK_SIZE = 0x0100;
-IRQ_STACK_SIZE = 0x0100;
-ABT_STACK_SIZE = 0x0100;
-UND_STACK_SIZE = 0x0100;
-SVC_STACK_SIZE = 0x0400;
-
-
-MEMORY
-{
- rom : org = 0x00100000, len = 256k
- ram : org = 0x00200000, len = 64k
-}
-
-/*
- * Do not change the next code
- */
-SECTIONS
-{
- .text :
- {
- *(.vectors);
- . = ALIGN(4);
- *(.init);
- . = ALIGN(4);
- *(.text);
- . = ALIGN(4);
- *(.rodata);
- . = ALIGN(4);
- *(.rodata*);
- . = ALIGN(4);
- *(.glue_7t);
- . = ALIGN(4);
- *(.glue_7);
- . = ALIGN(4);
- etext = .;
- } > rom
-
- .data :
- {
- PROVIDE (__data_start = .);
- *(.data)
- . = ALIGN(4);
- edata = .;
- _edata = .;
- PROVIDE (__data_end = .);
- } > ram
-
- .bss :
- {
- PROVIDE (__bss_start = .);
- *(.bss)
- *(COMMON)
- . = ALIGN(4);
- PROVIDE (__bss_end = .);
-
- . = ALIGN(256);
-
- PROVIDE (__stack_start = .);
-
- PROVIDE (__stack_fiq_start = .);
- . += FIQ_STACK_SIZE;
- . = ALIGN(4);
- PROVIDE (__stack_fiq_end = .);
-
- PROVIDE (__stack_irq_start = .);
- . += IRQ_STACK_SIZE;
- . = ALIGN(4);
- PROVIDE (__stack_irq_end = .);
-
- PROVIDE (__stack_abt_start = .);
- . += ABT_STACK_SIZE;
- . = ALIGN(4);
- PROVIDE (__stack_abt_end = .);
-
- PROVIDE (__stack_und_start = .);
- . += UND_STACK_SIZE;
- . = ALIGN(4);
- PROVIDE (__stack_und_end = .);
-
- PROVIDE (__stack_svc_start = .);
- . += SVC_STACK_SIZE;
- . = ALIGN(4);
- PROVIDE (__stack_svc_end = .);
- PROVIDE (__stack_end = .);
- PROVIDE (__heap_start = .);
- } > ram
-
-}
-/*** EOF ***/
-
+/****************************************************************************
+* Copyright (c) 2006 by Michael Fischer. All rights reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions
+* are met:
+*
+* 1. Redistributions of source code must retain the above copyright
+* notice, this list of conditions and the following disclaimer.
+* 2. Redistributions in binary form must reproduce the above copyright
+* notice, this list of conditions and the following disclaimer in the
+* documentation and/or other materials provided with the distribution.
+* 3. Neither the name of the author nor the names of its contributors may
+* be used to endorse or promote products derived from this software
+* without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
+* THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
+* THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+* SUCH DAMAGE.
+*
+****************************************************************************
+*
+* History:
+*
+* 26.01.08 mifi First Version
+****************************************************************************/
+
+
+ENTRY(ResetHandler)
+SEARCH_DIR(.)
+
+/*
+ * Define stack size here
+ */
+FIQ_STACK_SIZE = 0x0100;
+IRQ_STACK_SIZE = 0x0100;
+ABT_STACK_SIZE = 0x0100;
+UND_STACK_SIZE = 0x0100;
+SVC_STACK_SIZE = 0x0400;
+
+
+MEMORY
+{
+ rom : org = 0x00100000, len = 256k
+ ram : org = 0x00200000, len = 64k
+}
+
+/*
+ * Do not change the next code
+ */
+SECTIONS
+{
+ .text :
+ {
+ *(.vectors);
+ . = ALIGN(4);
+ *(.init);
+ . = ALIGN(4);
+ *(.text);
+ . = ALIGN(4);
+ *(.rodata);
+ . = ALIGN(4);
+ *(.rodata*);
+ . = ALIGN(4);
+ *(.glue_7t);
+ . = ALIGN(4);
+ *(.glue_7);
+ . = ALIGN(4);
+ etext = .;
+ } > rom
+
+ .data :
+ {
+ PROVIDE (__data_start = .);
+ *(.data)
+ . = ALIGN(4);
+ edata = .;
+ _edata = .;
+ PROVIDE (__data_end = .);
+ } > ram
+
+ .bss :
+ {
+ PROVIDE (__bss_start = .);
+ *(.bss)
+ *(COMMON)
+ . = ALIGN(4);
+ PROVIDE (__bss_end = .);
+
+ . = ALIGN(256);
+
+ PROVIDE (__stack_start = .);
+
+ PROVIDE (__stack_fiq_start = .);
+ . += FIQ_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_fiq_end = .);
+
+ PROVIDE (__stack_irq_start = .);
+ . += IRQ_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_irq_end = .);
+
+ PROVIDE (__stack_abt_start = .);
+ . += ABT_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_abt_end = .);
+
+ PROVIDE (__stack_und_start = .);
+ . += UND_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_und_end = .);
+
+ PROVIDE (__stack_svc_start = .);
+ . += SVC_STACK_SIZE;
+ . = ALIGN(4);
+ PROVIDE (__stack_svc_end = .);
+ PROVIDE (__stack_end = .);
+ PROVIDE (__heap_start = .);
+ } > ram
+
+}
+/*** EOF ***/
+
Property changes on: trunk/testing/examples/SAM7X256Test/prj/sam7x256_rom.ld
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/testing/examples/STM32-103/readme.txt
===================================================================
--- trunk/testing/examples/STM32-103/readme.txt 2009-04-27 19:35:31 UTC (rev 1548)
+++ trunk/testing/examples/STM32-103/readme.txt 2009-04-28 06:28:39 UTC (rev 1549)
@@ -1,6 +1,6 @@
-Olimex STM32-p103 board.
-
-main.elf is a file that can be programmed to flash for
-testing purposes(e.g. test GDB load performance).
-
+Olimex STM32-p103 board.
+
+main.elf is a file that can be programmed to flash for
+testing purposes(e.g. test GDB load performance).
+
http://www.olimex.com/dev/stm32-p103.html
\ No newline at end of file
Property changes on: trunk/testing/examples/STM32-103/readme.txt
___________________________________________________________________
Name: svn:eol-style
+ native
|
|
From: <oh...@ma...> - 2009-04-27 21:35:37
|
Author: oharboe
Date: 2009-04-27 21:35:31 +0200 (Mon, 27 Apr 2009)
New Revision: 1548
Modified:
trunk/src/flash/avrf.c
trunk/src/flash/avrf.h
trunk/src/target/avrt.c
trunk/src/target/avrt.h
Log:
SimonQian <sim...@si...> fix warnings(which stops compilation) and some bugs
Modified: trunk/src/flash/avrf.c
===================================================================
--- trunk/src/flash/avrf.c 2009-04-27 16:08:25 UTC (rev 1547)
+++ trunk/src/flash/avrf.c 2009-04-27 19:35:31 UTC (rev 1548)
@@ -1,500 +1,500 @@
-/***************************************************************************
- * Copyright (C) 2009 by Simon Qian *
- * Sim...@Si... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- ***************************************************************************/
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "replacements.h"
-
-#include "avrf.h"
-#include "avrt.h"
-#include "flash.h"
-#include "target.h"
-#include "log.h"
-#include "algorithm.h"
-#include "binarybuffer.h"
-
-#include <stdlib.h>
-#include <string.h>
-
-/* AVR_JTAG_Instructions */
-#define AVR_JTAG_INS_LEN 4
-// Public Instructions:
-#define AVR_JTAG_INS_EXTEST 0x00
-#define AVR_JTAG_INS_IDCODE 0x01
-#define AVR_JTAG_INS_SAMPLE_PRELOAD 0x02
-#define AVR_JTAG_INS_BYPASS 0x0F
-// AVR Specified Public Instructions:
-#define AVR_JTAG_INS_AVR_RESET 0x0C
-#define AVR_JTAG_INS_PROG_ENABLE 0x04
-#define AVR_JTAG_INS_PROG_COMMANDS 0x05
-#define AVR_JTAG_INS_PROG_PAGELOAD 0x06
-#define AVR_JTAG_INS_PROG_PAGEREAD 0x07
-
-// Data Registers:
-#define AVR_JTAG_REG_Bypass_Len 1
-#define AVR_JTAG_REG_DeviceID_Len 32
-
-#define AVR_JTAG_REG_Reset_Len 1
-#define AVR_JTAG_REG_JTAGID_Len 32
-#define AVR_JTAG_REG_ProgrammingEnable_Len 16
-#define AVR_JTAG_REG_ProgrammingCommand_Len 15
-#define AVR_JTAG_REG_FlashDataByte_Len 16
-
-avrf_type_t avft_chips_info[] =
-{
-// name, chip_id, flash_page_size, flash_page_num, eeprom_page_size, eeprom_page_num
- {"atmega128", 0x9702, 256, 512, 8, 512},
-};
-
-static int avrf_register_commands(struct command_context_s *cmd_ctx);
-static int avrf_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
-static int avrf_erase(struct flash_bank_s *bank, int first, int last);
-static int avrf_protect(struct flash_bank_s *bank, int set, int first, int last);
-static int avrf_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
-static int avrf_probe(struct flash_bank_s *bank);
-static int avrf_auto_probe(struct flash_bank_s *bank);
-//static int avrf_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-static int avrf_protect_check(struct flash_bank_s *bank);
-static int avrf_info(struct flash_bank_s *bank, char *buf, int buf_size);
-
-static int avrf_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-
-extern int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out);
-extern int avr_jtag_senddat(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int len);
-
-extern int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti);
-extern int mcu_write_dr(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int dr_len, int rti);
-extern int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti);
-extern int mcu_write_dr_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int dr_len, int rti);
-extern int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti);
-extern int mcu_write_dr_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int dr_len, int rti);
-extern int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti);
-extern int mcu_write_dr_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int dr_len, int rti);
-extern int mcu_execute_queue(void);
-
-flash_driver_t avr_flash =
-{
- .name = "avr",
- .register_commands = avrf_register_commands,
- .flash_bank_command = avrf_flash_bank_command,
- .erase = avrf_erase,
- .protect = avrf_protect,
- .write = avrf_write,
- .probe = avrf_probe,
- .auto_probe = avrf_auto_probe,
- .erase_check = default_flash_mem_blank_check,
- .protect_check = avrf_protect_check,
- .info = avrf_info
-};
-
-/* avr program functions */
-static int avr_jtag_reset(avr_common_t *avr, u32 reset)
-{
- avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_AVR_RESET);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, reset ,AVR_JTAG_REG_Reset_Len);
-
- return ERROR_OK;
-}
-
-static int avr_jtag_read_jtagid(avr_common_t *avr, u32 *id)
-{
- avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_IDCODE);
- avr_jtag_senddat(avr->jtag_info.tap, id, 0, AVR_JTAG_REG_JTAGID_Len);
-
- return ERROR_OK;
-}
-
-static int avr_jtagprg_enterprogmode(avr_common_t *avr)
-{
- avr_jtag_reset(avr, 1);
-
- avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xA370, AVR_JTAG_REG_ProgrammingEnable_Len);
-
- return ERROR_OK;
-}
-
-static int avr_jtagprg_leaveprogmode(avr_common_t *avr)
-{
- avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2300, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
-
- avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0, AVR_JTAG_REG_ProgrammingEnable_Len);
-
- avr_jtag_reset(avr, 0);
-
- return ERROR_OK;
-}
-
-static int avr_jtagprg_chiperase(avr_common_t *avr)
-{
- u32 poll_value;
-
- avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2380, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3180, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
-
- do{
- poll_value = 0;
- avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
- if (ERROR_OK != mcu_execute_queue())
- {
- return ERROR_FAIL;
- }
- LOG_DEBUG("poll_value = 0x%04X", poll_value);
- }while(!(poll_value & 0x0200));
-
- return ERROR_OK;
-}
-
-static int avr_jtagprg_writeflashpage(avr_common_t *avr, u8 *page_buf, u32 buf_size, u32 addr, u32 page_size)
-{
- u32 i, poll_value;
-
- avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2310, AVR_JTAG_REG_ProgrammingCommand_Len);
-
- // load addr high byte
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0700 | ((addr >> 9) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
-
- // load addr low byte
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0300 | ((addr >> 1) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
-
- avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_PAGELOAD);
-
- for (i = 0; i < page_size; i++)
- {
- if (i < buf_size)
- {
- avr_jtag_senddat(avr->jtag_info.tap, NULL, page_buf[i], 8);
- }
- else
- {
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xFF, 8);
- }
- }
-
- avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
-
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3500, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
- avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
-
- do{
- poll_value = 0;
- avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
- if (ERROR_OK != mcu_execute_queue())
- {
- return ERROR_FAIL;
- }
- LOG_DEBUG("poll_value = 0x%04X", poll_value);
- }while(!(poll_value & 0x0200));
-
- return ERROR_OK;
-}
-
-/* interface command */
-static int avrf_register_commands(struct command_context_s *cmd_ctx)
-{
- command_t *avr_cmd = register_command(cmd_ctx, NULL, "avr", NULL, COMMAND_ANY, "avr flash specific commands");
-
- register_command(cmd_ctx, avr_cmd, "mass_erase", avrf_handle_mass_erase_command, COMMAND_EXEC,
- "mass erase device");
-
- return ERROR_OK;
-}
-
-static int avrf_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
-{
- avrf_flash_bank_t *avrf_info;
-
- if (argc < 6)
- {
- LOG_WARNING("incomplete flash_bank avr configuration");
- return ERROR_FLASH_BANK_INVALID;
- }
-
- avrf_info = malloc(sizeof(avrf_flash_bank_t));
- bank->driver_priv = avrf_info;
-
- avrf_info->probed = 0;
-
- return ERROR_OK;
-}
-
-static int avrf_erase(struct flash_bank_s *bank, int first, int last)
-{
- LOG_INFO(__FUNCTION__);
- return ERROR_OK;
-}
-
-static int avrf_protect(struct flash_bank_s *bank, int set, int first, int last)
-{
- LOG_INFO(__FUNCTION__);
- return ERROR_OK;
-}
-
-static int avrf_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
-{
- target_t *target = bank->target;
- avr_common_t *avr = target->arch_info;
- u32 cur_size, cur_buffer_size, page_size;
-
- if (bank->target->state != TARGET_HALTED)
- {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
- page_size = bank->sectors[0].size;
- if ((offset % page_size) != 0)
- {
- LOG_WARNING("offset 0x%x breaks required %d-byte alignment", offset, page_size);
- return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
- }
-
- LOG_DEBUG("offset is 0x%08X", offset);
- LOG_DEBUG("count is %d", count);
-
- if (ERROR_OK != avr_jtagprg_enterprogmode(avr))
- {
- return ERROR_FAIL;
- }
-
- cur_size = 0;
- while(count > 0)
- {
- if (count > page_size)
- {
- cur_buffer_size = page_size;
- }
- else
- {
- cur_buffer_size = count;
- }
- avr_jtagprg_writeflashpage(avr, buffer + cur_size, cur_buffer_size, offset + cur_size, page_size);
- count -= cur_buffer_size;
- cur_size += cur_buffer_size;
-
- keep_alive();
- }
-
- return avr_jtagprg_leaveprogmode(avr);
-}
-
-#define EXTRACT_MFG(X) (((X) & 0xffe) >> 1)
-#define EXTRACT_PART(X) (((X) & 0xffff000) >> 12)
-#define EXTRACT_VER(X) (((X) & 0xf0000000) >> 28)
-static int avrf_probe(struct flash_bank_s *bank)
-{
- target_t *target = bank->target;
- avrf_flash_bank_t *avrf_info = bank->driver_priv;
- avr_common_t *avr = target->arch_info;
- avrf_type_t *avr_info;
- int i;
- u32 device_id;
-
- if (bank->target->state != TARGET_HALTED)
- {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
- avrf_info->probed = 0;
-
- avr_jtag_read_jtagid(avr, &device_id);
- if (ERROR_OK != mcu_execute_queue())
- {
- return ERROR_FAIL;
- }
-
- LOG_INFO( "device id = 0x%08x", device_id );
- if (EXTRACT_MFG(device_id) != 0x1F)
- {
- LOG_ERROR("0x%X is invalid Manufacturer for avr, 0x%X is expected", EXTRACT_MFG(device_id), 0x1F);
- }
-
- for (i = 0; i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])); i++)
- {
- if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id))
- {
- avr_info = &avft_chips_info[i];
- LOG_INFO("target device is %s", avr_info->name);
- break;
- }
- }
-
- if (i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])))
- {
- // chip found
- bank->base = 0x00000000;
- bank->size = (avr_info->flash_page_size * avr_info->flash_page_num);
- bank->num_sectors = avr_info->flash_page_num;
- bank->sectors = malloc(sizeof(flash_sector_t) * avr_info->flash_page_num);
-
- for (i = 0; i < avr_info->flash_page_num; i++)
- {
- bank->sectors[i].offset = i * avr_info->flash_page_size;
- bank->sectors[i].size = avr_info->flash_page_size;
- bank->sectors[i].is_erased = -1;
- bank->sectors[i].is_protected = 1;
- }
-
- avrf_info->probed = 1;
- return ERROR_OK;
- }
- else
- {
- // chip not supported
- LOG_ERROR("0x%X is not support for avr", EXTRACT_PART(device_id));
-
- avrf_info->probed = 1;
- return ERROR_FAIL;
- }
-}
-
-static int avrf_auto_probe(struct flash_bank_s *bank)
-{
- avrf_flash_bank_t *avrf_info = bank->driver_priv;
- if (avrf_info->probed)
- return ERROR_OK;
- return avrf_probe(bank);
-}
-
-static int avrf_protect_check(struct flash_bank_s *bank)
-{
- LOG_INFO(__FUNCTION__);
- return ERROR_OK;
-}
-
-static int avrf_info(struct flash_bank_s *bank, char *buf, int buf_size)
-{
- target_t *target = bank->target;
- avr_common_t *avr = target->arch_info;
- avrf_type_t *avr_info;
- int i;
- u32 device_id;
-
- if (bank->target->state != TARGET_HALTED)
- {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
- avr_jtag_read_jtagid(avr, &device_id);
- if (ERROR_OK != mcu_execute_queue())
- {
- return ERROR_FAIL;
- }
-
- LOG_INFO( "device id = 0x%08x", device_id );
- if (EXTRACT_MFG(device_id) != 0x1F)
- {
- LOG_ERROR("0x%X is invalid Manufacturer for avr, 0x%X is expected", EXTRACT_MFG(device_id), 0x1F);
- }
-
- for (i = 0; i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])); i++)
- {
- if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id))
- {
- avr_info = &avft_chips_info[i];
- LOG_INFO("target device is %s", avr_info->name);
-
- return ERROR_OK;
- }
- }
-
- if (i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])))
- {
- // chip found
- snprintf(buf, buf_size, "%s - Rev: 0x%X", avr_info->name, EXTRACT_VER(device_id));
- return ERROR_OK;
- }
- else
- {
- // chip not supported
- snprintf(buf, buf_size, "Cannot identify target as a avr\n");
- return ERROR_FLASH_OPERATION_FAILED;
- }
-}
-
-static int avrf_mass_erase(struct flash_bank_s *bank)
-{
- target_t *target = bank->target;
- avr_common_t *avr = target->arch_info;
-
- if (target->state != TARGET_HALTED)
- {
- LOG_ERROR("Target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
- if ((ERROR_OK != avr_jtagprg_enterprogmode(avr))
- || (ERROR_OK != avr_jtagprg_chiperase(avr))
- || (ERROR_OK != avr_jtagprg_leaveprogmode(avr)))
- {
- return ERROR_FAIL;
- }
-
- return ERROR_OK;
-}
-
-static int avrf_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
-{
- flash_bank_t *bank;
- int i;
-
- if (argc < 1)
- {
- command_print(cmd_ctx, "avr mass_erase <bank>");
- return ERROR_OK;
- }
-
- bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
- if (!bank)
- {
- command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
- return ERROR_OK;
- }
-
- if (avrf_mass_erase(bank) == ERROR_OK)
- {
- /* set all sectors as erased */
- for (i = 0; i < bank->num_sectors; i++)
- {
- bank->sectors[i].is_erased = 1;
- }
-
- command_print(cmd_ctx, "avr mass erase complete");
- }
- else
- {
- command_print(cmd_ctx, "avr mass erase failed");
- }
-
- LOG_DEBUG(__FUNCTION__);
- return ERROR_OK;
-}
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * Sim...@Si... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+
+#include "avrf.h"
+#include "avrt.h"
+#include "flash.h"
+#include "target.h"
+#include "log.h"
+#include "algorithm.h"
+#include "binarybuffer.h"
+
+#include <stdlib.h>
+#include <string.h>
+
+/* AVR_JTAG_Instructions */
+#define AVR_JTAG_INS_LEN 4
+// Public Instructions:
+#define AVR_JTAG_INS_EXTEST 0x00
+#define AVR_JTAG_INS_IDCODE 0x01
+#define AVR_JTAG_INS_SAMPLE_PRELOAD 0x02
+#define AVR_JTAG_INS_BYPASS 0x0F
+// AVR Specified Public Instructions:
+#define AVR_JTAG_INS_AVR_RESET 0x0C
+#define AVR_JTAG_INS_PROG_ENABLE 0x04
+#define AVR_JTAG_INS_PROG_COMMANDS 0x05
+#define AVR_JTAG_INS_PROG_PAGELOAD 0x06
+#define AVR_JTAG_INS_PROG_PAGEREAD 0x07
+
+// Data Registers:
+#define AVR_JTAG_REG_Bypass_Len 1
+#define AVR_JTAG_REG_DeviceID_Len 32
+
+#define AVR_JTAG_REG_Reset_Len 1
+#define AVR_JTAG_REG_JTAGID_Len 32
+#define AVR_JTAG_REG_ProgrammingEnable_Len 16
+#define AVR_JTAG_REG_ProgrammingCommand_Len 15
+#define AVR_JTAG_REG_FlashDataByte_Len 16
+
+avrf_type_t avft_chips_info[] =
+{
+// name, chip_id, flash_page_size, flash_page_num, eeprom_page_size, eeprom_page_num
+ {"atmega128", 0x9702, 256, 512, 8, 512},
+};
+
+static int avrf_register_commands(struct command_context_s *cmd_ctx);
+static int avrf_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
+static int avrf_erase(struct flash_bank_s *bank, int first, int last);
+static int avrf_protect(struct flash_bank_s *bank, int set, int first, int last);
+static int avrf_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int avrf_probe(struct flash_bank_s *bank);
+static int avrf_auto_probe(struct flash_bank_s *bank);
+//static int avrf_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+static int avrf_protect_check(struct flash_bank_s *bank);
+static int avrf_info(struct flash_bank_s *bank, char *buf, int buf_size);
+
+static int avrf_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+
+extern int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out);
+extern int avr_jtag_senddat(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int len);
+
+extern int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti);
+extern int mcu_write_dr(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int dr_len, int rti);
+extern int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti);
+extern int mcu_write_dr_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int dr_len, int rti);
+extern int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti);
+extern int mcu_write_dr_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int dr_len, int rti);
+extern int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti);
+extern int mcu_write_dr_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int dr_len, int rti);
+extern int mcu_execute_queue(void);
+
+flash_driver_t avr_flash =
+{
+ .name = "avr",
+ .register_commands = avrf_register_commands,
+ .flash_bank_command = avrf_flash_bank_command,
+ .erase = avrf_erase,
+ .protect = avrf_protect,
+ .write = avrf_write,
+ .probe = avrf_probe,
+ .auto_probe = avrf_auto_probe,
+ .erase_check = default_flash_mem_blank_check,
+ .protect_check = avrf_protect_check,
+ .info = avrf_info
+};
+
+/* avr program functions */
+static int avr_jtag_reset(avr_common_t *avr, u32 reset)
+{
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_AVR_RESET);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, reset ,AVR_JTAG_REG_Reset_Len);
+
+ return ERROR_OK;
+}
+
+static int avr_jtag_read_jtagid(avr_common_t *avr, u32 *id)
+{
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_IDCODE);
+ avr_jtag_senddat(avr->jtag_info.tap, id, 0, AVR_JTAG_REG_JTAGID_Len);
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_enterprogmode(avr_common_t *avr)
+{
+ avr_jtag_reset(avr, 1);
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xA370, AVR_JTAG_REG_ProgrammingEnable_Len);
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_leaveprogmode(avr_common_t *avr)
+{
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2300, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0, AVR_JTAG_REG_ProgrammingEnable_Len);
+
+ avr_jtag_reset(avr, 0);
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_chiperase(avr_common_t *avr)
+{
+ u32 poll_value;
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2380, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3180, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ do{
+ poll_value = 0;
+ avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
+ if (ERROR_OK != mcu_execute_queue())
+ {
+ return ERROR_FAIL;
+ }
+ LOG_DEBUG("poll_value = 0x%04X", poll_value);
+ }while(!(poll_value & 0x0200));
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_writeflashpage(avr_common_t *avr, u8 *page_buf, u32 buf_size, u32 addr, u32 page_size)
+{
+ u32 i, poll_value;
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2310, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ // load addr high byte
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0700 | ((addr >> 9) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ // load addr low byte
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0300 | ((addr >> 1) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_PAGELOAD);
+
+ for (i = 0; i < page_size; i++)
+ {
+ if (i < buf_size)
+ {
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, page_buf[i], 8);
+ }
+ else
+ {
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xFF, 8);
+ }
+ }
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3500, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ do{
+ poll_value = 0;
+ avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+ if (ERROR_OK != mcu_execute_queue())
+ {
+ return ERROR_FAIL;
+ }
+ LOG_DEBUG("poll_value = 0x%04X", poll_value);
+ }while(!(poll_value & 0x0200));
+
+ return ERROR_OK;
+}
+
+/* interface command */
+static int avrf_register_commands(struct command_context_s *cmd_ctx)
+{
+ command_t *avr_cmd = register_command(cmd_ctx, NULL, "avr", NULL, COMMAND_ANY, "avr flash specific commands");
+
+ register_command(cmd_ctx, avr_cmd, "mass_erase", avrf_handle_mass_erase_command, COMMAND_EXEC,
+ "mass erase device");
+
+ return ERROR_OK;
+}
+
+static int avrf_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
+{
+ avrf_flash_bank_t *avrf_info;
+
+ if (argc < 6)
+ {
+ LOG_WARNING("incomplete flash_bank avr configuration");
+ return ERROR_FLASH_BANK_INVALID;
+ }
+
+ avrf_info = malloc(sizeof(avrf_flash_bank_t));
+ bank->driver_priv = avrf_info;
+
+ avrf_info->probed = 0;
+
+ return ERROR_OK;
+}
+
+static int avrf_erase(struct flash_bank_s *bank, int first, int last)
+{
+ LOG_INFO(__FUNCTION__);
+ return ERROR_OK;
+}
+
+static int avrf_protect(struct flash_bank_s *bank, int set, int first, int last)
+{
+ LOG_INFO(__FUNCTION__);
+ return ERROR_OK;
+}
+
+static int avrf_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+{
+ target_t *target = bank->target;
+ avr_common_t *avr = target->arch_info;
+ u32 cur_size, cur_buffer_size, page_size;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ page_size = bank->sectors[0].size;
+ if ((offset % page_size) != 0)
+ {
+ LOG_WARNING("offset 0x%x breaks required %d-byte alignment", offset, page_size);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ LOG_DEBUG("offset is 0x%08X", offset);
+ LOG_DEBUG("count is %d", count);
+
+ if (ERROR_OK != avr_jtagprg_enterprogmode(avr))
+ {
+ return ERROR_FAIL;
+ }
+
+ cur_size = 0;
+ while(count > 0)
+ {
+ if (count > page_size)
+ {
+ cur_buffer_size = page_size;
+ }
+ else
+ {
+ cur_buffer_size = count;
+ }
+ avr_jtagprg_writeflashpage(avr, buffer + cur_size, cur_buffer_size, offset + cur_size, page_size);
+ count -= cur_buffer_size;
+ cur_size += cur_buffer_size;
+
+ keep_alive();
+ }
+
+ return avr_jtagprg_leaveprogmode(avr);
+}
+
+#define EXTRACT_MFG(X) (((X) & 0xffe) >> 1)
+#define EXTRACT_PART(X) (((X) & 0xffff000) >> 12)
+#define EXTRACT_VER(X) (((X) & 0xf0000000) >> 28)
+static int avrf_probe(struct flash_bank_s *bank)
+{
+ target_t *target = bank->target;
+ avrf_flash_bank_t *avrf_info = bank->driver_priv;
+ avr_common_t *avr = target->arch_info;
+ avrf_type_t *avr_info = NULL;
+ int i;
+ u32 device_id;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ avrf_info->probed = 0;
+
+ avr_jtag_read_jtagid(avr, &device_id);
+ if (ERROR_OK != mcu_execute_queue())
+ {
+ return ERROR_FAIL;
+ }
+
+ LOG_INFO( "device id = 0x%08x", device_id );
+ if (EXTRACT_MFG(device_id) != 0x1F)
+ {
+ LOG_ERROR("0x%X is invalid Manufacturer for avr, 0x%X is expected", EXTRACT_MFG(device_id), 0x1F);
+ }
+
+ for (i = 0; i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])); i++)
+ {
+ if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id))
+ {
+ avr_info = &avft_chips_info[i];
+ LOG_INFO("target device is %s", avr_info->name);
+ break;
+ }
+ }
+
+ if (avr_info != NULL)
+ {
+ // chip found
+ bank->base = 0x00000000;
+ bank->size = (avr_info->flash_page_size * avr_info->flash_page_num);
+ bank->num_sectors = avr_info->flash_page_num;
+ bank->sectors = malloc(sizeof(flash_sector_t) * avr_info->flash_page_num);
+
+ for (i = 0; i < avr_info->flash_page_num; i++)
+ {
+ bank->sectors[i].offset = i * avr_info->flash_page_size;
+ bank->sectors[i].size = avr_info->flash_page_size;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 1;
+ }
+
+ avrf_info->probed = 1;
+ return ERROR_OK;
+ }
+ else
+ {
+ // chip not supported
+ LOG_ERROR("0x%X is not support for avr", EXTRACT_PART(device_id));
+
+ avrf_info->probed = 1;
+ return ERROR_FAIL;
+ }
+}
+
+static int avrf_auto_probe(struct flash_bank_s *bank)
+{
+ avrf_flash_bank_t *avrf_info = bank->driver_priv;
+ if (avrf_info->probed)
+ return ERROR_OK;
+ return avrf_probe(bank);
+}
+
+static int avrf_protect_check(struct flash_bank_s *bank)
+{
+ LOG_INFO(__FUNCTION__);
+ return ERROR_OK;
+}
+
+static int avrf_info(struct flash_bank_s *bank, char *buf, int buf_size)
+{
+ target_t *target = bank->target;
+ avr_common_t *avr = target->arch_info;
+ avrf_type_t *avr_info = NULL;
+ int i;
+ u32 device_id;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ avr_jtag_read_jtagid(avr, &device_id);
+ if (ERROR_OK != mcu_execute_queue())
+ {
+ return ERROR_FAIL;
+ }
+
+ LOG_INFO( "device id = 0x%08x", device_id );
+ if (EXTRACT_MFG(device_id) != 0x1F)
+ {
+ LOG_ERROR("0x%X is invalid Manufacturer for avr, 0x%X is expected", EXTRACT_MFG(device_id), 0x1F);
+ }
+
+ for (i = 0; i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])); i++)
+ {
+ if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id))
+ {
+ avr_info = &avft_chips_info[i];
+ LOG_INFO("target device is %s", avr_info->name);
+
+ break;
+ }
+ }
+
+ if (avr_info != NULL)
+ {
+ // chip found
+ snprintf(buf, buf_size, "%s - Rev: 0x%X", avr_info->name, EXTRACT_VER(device_id));
+ return ERROR_OK;
+ }
+ else
+ {
+ // chip not supported
+ snprintf(buf, buf_size, "Cannot identify target as a avr\n");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+}
+
+static int avrf_mass_erase(struct flash_bank_s *bank)
+{
+ target_t *target = bank->target;
+ avr_common_t *avr = target->arch_info;
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if ((ERROR_OK != avr_jtagprg_enterprogmode(avr))
+ || (ERROR_OK != avr_jtagprg_chiperase(avr))
+ || (ERROR_OK != avr_jtagprg_leaveprogmode(avr)))
+ {
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static int avrf_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ flash_bank_t *bank;
+ int i;
+
+ if (argc < 1)
+ {
+ command_print(cmd_ctx, "avr mass_erase <bank>");
+ return ERROR_OK;
+ }
+
+ bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+ if (!bank)
+ {
+ command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
+ return ERROR_OK;
+ }
+
+ if (avrf_mass_erase(bank) == ERROR_OK)
+ {
+ /* set all sectors as erased */
+ for (i = 0; i < bank->num_sectors; i++)
+ {
+ bank->sectors[i].is_erased = 1;
+ }
+
+ command_print(cmd_ctx, "avr mass erase complete");
+ }
+ else
+ {
+ command_print(cmd_ctx, "avr mass erase failed");
+ }
+
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
Property changes on: trunk/src/flash/avrf.c
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/flash/avrf.h
===================================================================
--- trunk/src/flash/avrf.h 2009-04-27 16:08:25 UTC (rev 1547)
+++ trunk/src/flash/avrf.h 2009-04-27 19:35:31 UTC (rev 1548)
@@ -1,39 +1,39 @@
-/***************************************************************************
- * Copyright (C) 2009 by Simon Qian *
- * Sim...@Si... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- ***************************************************************************/
-#ifndef AVRF_H
-#define AVRF_H
-
-typedef struct avrf_type_s
-{
- char name[15];
- u16 chip_id;
- int flash_page_size;
- int flash_page_num;
- int eeprom_page_size;
- int eeprom_page_num;
-} avrf_type_t;
-
-typedef struct avrf_flash_bank_s
-{
- int ppage_size;
- int probed;
-} avrf_flash_bank_t;
-
-#endif /* AVRF_H */
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * Sim...@Si... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef AVRF_H
+#define AVRF_H
+
+typedef struct avrf_type_s
+{
+ char name[15];
+ u16 chip_id;
+ int flash_page_size;
+ int flash_page_num;
+ int eeprom_page_size;
+ int eeprom_page_num;
+} avrf_type_t;
+
+typedef struct avrf_flash_bank_s
+{
+ int ppage_size;
+ int probed;
+} avrf_flash_bank_t;
+
+#endif /* AVRF_H */
Property changes on: trunk/src/flash/avrf.h
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/target/avrt.c
===================================================================
--- trunk/src/target/avrt.c 2009-04-27 16:08:25 UTC (rev 1547)
+++ trunk/src/target/avrt.c 2009-04-27 19:35:31 UTC (rev 1548)
@@ -1,354 +1,354 @@
-/***************************************************************************
- * Copyright (C) 2009 by Simon Qian *
- * Sim...@Si... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- ***************************************************************************/
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "replacements.h"
-
-#include "avrt.h"
-
-#include "register.h"
-#include "target.h"
-#include "log.h"
-#include "jtag.h"
-#include "binarybuffer.h"
-#include "time_support.h"
-#include "breakpoints.h"
-#include "fileio.h"
-
-#include <stdlib.h>
-#include <string.h>
-
-#include <sys/types.h>
-#include <unistd.h>
-#include <errno.h>
-
-#define AVR_JTAG_INS_LEN 4
-
-/* cli handling */
-int avr_register_commands(struct command_context_s *cmd_ctx);
-
-/* forward declarations */
-int avr_target_create(struct target_s *target, Jim_Interp *interp);
-int avr_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
-int avr_quit(void);
-
-int avr_arch_state(struct target_s *target);
-int avr_poll(target_t *target);
-int avr_halt(target_t *target);
-int avr_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
-int avr_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
-
-int avr_assert_reset(target_t *target);
-int avr_deassert_reset(target_t *target);
-int avr_soft_reset_halt(struct target_s *target);
-
-/* IR and DR functions */
-int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out);
-int avr_jtag_senddat(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int len);
-
-int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti);
-int mcu_write_dr(jtag_tap_t *tap, u8 *dr_in, u8 *dr_out, int dr_len, int rti);
-int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti);
-int mcu_write_dr_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int dr_len, int rti);
-int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti);
-int mcu_write_dr_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int dr_len, int rti);
-int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti);
-int mcu_write_dr_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int dr_len, int rti);
-int mcu_execute_queue(void);
-
-target_type_t avr_target =
-{
- .name = "avr",
-
- .poll = avr_poll,
- .arch_state = avr_arch_state,
-
- .target_request_data = NULL,
-
- .halt = avr_halt,
- .resume = avr_resume,
- .step = avr_step,
-
- .assert_reset = avr_assert_reset,
- .deassert_reset = avr_deassert_reset,
- .soft_reset_halt = avr_soft_reset_halt,
-/*
- .get_gdb_reg_list = avr_get_gdb_reg_list,
-
- .read_memory = avr_read_memory,
- .write_memory = avr_write_memory,
- .bulk_write_memory = avr_bulk_write_memory,
- .checksum_memory = avr_checksum_memory,
- .blank_check_memory = avr_blank_check_memory,
-
- .run_algorithm = avr_run_algorithm,
-
- .add_breakpoint = avr_add_breakpoint,
- .remove_breakpoint = avr_remove_breakpoint,
- .add_watchpoint = avr_add_watchpoint,
- .remove_watchpoint = avr_remove_watchpoint,
-*/
- .register_commands = avr_register_commands,
- .target_create = avr_target_create,
- .init_target = avr_init_target,
- .quit = avr_quit,
-/*
- .virt2phys = avr_virt2phys,
- .mmu = avr_mmu
-*/
-};
-
-int avr_register_commands(struct command_context_s *cmd_ctx)
-{
- LOG_DEBUG(__FUNCTION__);
- return ERROR_OK;
-}
-
-int avr_target_create(struct target_s *target, Jim_Interp *interp)
-{
- avr_common_t *avr = calloc(1, sizeof(avr_common_t));
-
- avr->jtag_info.tap = target->tap;
- target->arch_info = avr;
-
- return ERROR_OK;
-}
-
-int avr_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
-{
- LOG_DEBUG(__FUNCTION__);
- return ERROR_OK;
-}
-
-int avr_quit(void)
-{
- LOG_DEBUG(__FUNCTION__);
- return ERROR_OK;
-}
-
-int avr_arch_state(struct target_s *target)
-{
- LOG_DEBUG(__FUNCTION__);
- return ERROR_OK;
-}
-
-int avr_poll(target_t *target)
-{
- if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
- {
- target->state = TARGET_HALTED;
- }
-
- LOG_DEBUG(__FUNCTION__);
- return ERROR_OK;
-}
-
-int avr_halt(target_t *target)
-{
- LOG_DEBUG(__FUNCTION__);
- return ERROR_OK;
-}
-
-int avr_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
-{
- LOG_DEBUG(__FUNCTION__);
- return ERROR_OK;
-}
-
-int avr_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
-{
- LOG_DEBUG(__FUNCTION__);
- return ERROR_OK;
-}
-
-int avr_assert_reset(target_t *target)
-{
- target->state = TARGET_RESET;
-
- LOG_DEBUG(__FUNCTION__);
- return ERROR_OK;
-}
-
-int avr_deassert_reset(target_t *target)
-{
- target->state = TARGET_RUNNING;
-
- LOG_DEBUG(__FUNCTION__);
- return ERROR_OK;
-}
-
-int avr_soft_reset_halt(struct target_s *target)
-{
- LOG_DEBUG(__FUNCTION__);
- return ERROR_OK;
-}
-
-int avr_jtag_senddat(jtag_tap_t *tap, u32* dr_in, u32 dr_out, int len)
-{
- return mcu_write_dr_u32(tap, dr_in, dr_out, len, 1);
-}
-
-int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out)
-{
- return mcu_write_ir_u8(tap, ir_in, ir_out, AVR_JTAG_INS_LEN, 1);
-}
-
-/* IR and DR functions */
-int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti)
-{
- if (NULL == tap)
- {
- LOG_ERROR("invalid tap");
- return ERROR_FAIL;
- }
- if (ir_len != tap->ir_length)
- {
- LOG_ERROR("invalid ir_len");
- return ERROR_FAIL;
- }
-
- {
- scan_field_t field[1];
-
- field[0].tap = tap;
- field[0].num_bits = tap->ir_length;
- field[0].out_value = ir_out;
- field[0].out_mask = NULL;
- field[0].in_value = ir_in;
- field[0].in_check_value = NULL;
- field[0].in_check_mask = NULL;
- field[0].in_handler = NULL;
- field[0].in_handler_priv = NULL;
- jtag_add_plain_ir_scan(sizeof(field) / sizeof(field[0]), field, TAP_IDLE);
- }
-
- return ERROR_OK;
-}
-
-int mcu_write_dr(jtag_tap_t *tap, u8 *dr_in, u8 *dr_out, int dr_len, int rti)
-{
- if (NULL == tap)
- {
- LOG_ERROR("invalid tap");
- return ERROR_FAIL;
- }
-
- {
- scan_field_t field[1];
-
- field[0].tap = tap;
- field[0].num_bits = dr_len;
- field[0].out_value = dr_out;
- field[0].out_mask = NULL;
- field[0].in_value = dr_in;
- field[0].in_check_value = NULL;
- field[0].in_check_mask = NULL;
- field[0].in_handler = NULL;
- field[0].in_handler_priv = NULL;
- jtag_add_plain_dr_scan(sizeof(field) / sizeof(field[0]), field, TAP_IDLE);
- }
-
- return ERROR_OK;
-}
-
-int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti)
-{
- if (ir_len > 8)
- {
- LOG_ERROR("ir_len overflow, maxium is 8");
- return ERROR_FAIL;
- }
-
- mcu_write_ir(tap, ir_in, &ir_out, ir_len, rti);
-
- return ERROR_OK;
-}
-
-int mcu_write_dr_u8(jtag_tap_t *tap, u8 *dr_in, u8 dr_out, int dr_len, int rti)
-{
- if (dr_len > 8)
- {
- LOG_ERROR("dr_len overflow, maxium is 8");
- return ERROR_FAIL;
- }
-
- mcu_write_dr(tap, dr_in, &dr_out, dr_len, rti);
-
- return ERROR_OK;
-}
-
-int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti)
-{
- if (ir_len > 16)
- {
- LOG_ERROR("ir_len overflow, maxium is 16");
- return ERROR_FAIL;
- }
-
- mcu_write_ir(tap, (u8*)ir_in, (u8*)&ir_out, ir_len, rti);
-
- return ERROR_OK;
-}
-
-int mcu_write_dr_u16(jtag_tap_t *tap, u16 *dr_in, u16 dr_out, int dr_len, int rti)
-{
- if (dr_len > 16)
- {
- LOG_ERROR("dr_len overflow, maxium is 16");
- return ERROR_FAIL;
- }
-
- mcu_write_dr(tap, (u8*)dr_in, (u8*)&dr_out, dr_len, rti);
-
- return ERROR_OK;
-}
-
-int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti)
-{
- if (ir_len > 32)
- {
- LOG_ERROR("ir_len overflow, maxium is 32");
- return ERROR_FAIL;
- }
-
- mcu_write_ir(tap, (u8*)ir_in, (u8*)&ir_out, ir_len, rti);
-
- return ERROR_OK;
-}
-
-int mcu_write_dr_u32(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int dr_len, int rti)
-{
- if (dr_len > 32)
- {
- LOG_ERROR("dr_len overflow, maxium is 32");
- return ERROR_FAIL;
- }
-
- mcu_write_dr(tap, (u8*)dr_in, (u8*)&dr_out, dr_len, rti);
-
- return ERROR_OK;
-}
-
-int mcu_execute_queue(void)
-{
- return jtag_execute_queue();
-}
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * Sim...@Si... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+
+#include "avrt.h"
+
+#include "register.h"
+#include "target.h"
+#include "log.h"
+#include "jtag.h"
+#include "binarybuffer.h"
+#include "time_support.h"
+#include "breakpoints.h"
+#include "fileio.h"
+
+#include <stdlib.h>
+#include <string.h>
+
+#include <sys/types.h>
+#include <unistd.h>
+#include <errno.h>
+
+#define AVR_JTAG_INS_LEN 4
+
+/* cli handling */
+int avr_register_commands(struct command_context_s *cmd_ctx);
+
+/* forward declarations */
+int avr_target_create(struct target_s *target, Jim_Interp *interp);
+int avr_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
+int avr_quit(void);
+
+int avr_arch_state(struct target_s *target);
+int avr_poll(target_t *target);
+int avr_halt(target_t *target);
+int avr_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
+int avr_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
+
+int avr_assert_reset(target_t *target);
+int avr_deassert_reset(target_t *target);
+int avr_soft_reset_halt(struct target_s *target);
+
+/* IR and DR functions */
+int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out);
+int avr_jtag_senddat(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int len);
+
+int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti);
+int mcu_write_dr(jtag_tap_t *tap, u8 *dr_in, u8 *dr_out, int dr_len, int rti);
+int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti);
+int mcu_write_dr_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int dr_len, int rti);
+int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti);
+int mcu_write_dr_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int dr_len, int rti);
+int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti);
+int mcu_write_dr_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int dr_len, int rti);
+int mcu_execute_queue(void);
+
+target_type_t avr_target =
+{
+ .name = "avr",
+
+ .poll = avr_poll,
+ .arch_state = avr_arch_state,
+
+ .target_request_data = NULL,
+
+ .halt = avr_halt,
+ .resume = avr_resume,
+ .step = avr_step,
+
+ .assert_reset = avr_assert_reset,
+ .deassert_reset = avr_deassert_reset,
+ .soft_reset_halt = avr_soft_reset_halt,
+/*
+ .get_gdb_reg_list = avr_get_gdb_reg_list,
+
+ .read_memory = avr_read_memory,
+ .write_memory = avr_write_memory,
+ .bulk_write_memory = avr_bulk_write_memory,
+ .checksum_memory = avr_checksum_memory,
+ .blank_check_memory = avr_blank_check_memory,
+
+ .run_algorithm = avr_run_algorithm,
+
+ .add_breakpoint = avr_add_breakpoint,
+ .remove_breakpoint = avr_remove_breakpoint,
+ .add_watchpoint = avr_add_watchpoint,
+ .remove_watchpoint = avr_remove_watchpoint,
+*/
+ .register_commands = avr_register_commands,
+ .target_create = avr_target_create,
+ .init_target = avr_init_target,
+ .quit = avr_quit,
+/*
+ .virt2phys = avr_virt2phys,
+ .mmu = avr_mmu
+*/
+};
+
+int avr_register_commands(struct command_context_s *cmd_ctx)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_target_create(struct target_s *target, Jim_Interp *interp)
+{
+ avr_common_t *avr = calloc(1, sizeof(avr_common_t));
+
+ avr->jtag_info.tap = target->tap;
+ target->arch_info = avr;
+
+ return ERROR_OK;
+}
+
+int avr_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_quit(void)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_arch_state(struct target_s *target)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_poll(target_t *target)
+{
+ if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
+ {
+ target->state = TARGET_HALTED;
+ }
+
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_halt(target_t *target)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_assert_reset(target_t *target)
+{
+ target->state = TARGET_RESET;
+
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_deassert_reset(target_t *target)
+{
+ target->state = TARGET_RUNNING;
+
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_soft_reset_halt(struct target_s *target)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_jtag_senddat(jtag_tap_t *tap, u32* dr_in, u32 dr_out, int len)
+{
+ return mcu_write_dr_u32(tap, dr_in, dr_out, len, 1);
+}
+
+int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out)
+{
+ return mcu_write_ir_u8(tap, ir_in, ir_out, AVR_JTAG_INS_LEN, 1);
+}
+
+/* IR and DR functions */
+int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti)
+{
+ if (NULL == tap)
+ {
+ LOG_ERROR("invalid tap");
+ return ERROR_FAIL;
+ }
+ if (ir_len != tap->ir_length)
+ {
+ LOG_ERROR("invalid ir_len");
+ return ERROR_FAIL;
+ }
+
+ {
+ scan_field_t field[1];
+
+ field[0].tap = tap;
+ field[0].num_bits = tap->ir_length;
+ field[0].out_value = ir_out;
+ field[0].out_mask = NULL;
+ field[0].in_value = ir_in;
+ field[0].in_check_value = NULL;
+ field[0].in_check_mask = NULL;
+ field[0].in_handler = NULL;
+ field[0].in_handler_priv = NULL;
+ jtag_add_plain_ir_scan(sizeof(field) / sizeof(field[0]), field, TAP_IDLE);
+ }
+
+ return ERROR_OK;
+}
+
+int mcu_write_dr(jtag_tap_t *tap, u8 *dr_in, u8 *dr_out, int dr_len, int rti)
+{
+ if (NULL == tap)
+ {
+ LOG_ERROR("invalid tap");
+ return ERROR_FAIL;
+ }
+
+ {
+ scan_field_t field[1];
+
+ field[0].tap = tap;
+ field[0].num_bits = dr_len;
+ field[0].out_value = dr_out;
+ field[0].out_mask = NULL;
+ field[0].in_value = dr_in;
+ field[0].in_check_value = NULL;
+ field[0].in_check_mask = NULL;
+ field[0].in_handler = NULL;
+ field[0].in_handler_priv = NULL;
+ jtag_add_plain_dr_scan(sizeof(field) / sizeof(field[0]), field, TAP_IDLE);
+ }
+
+ return ERROR_OK;
+}
+
+int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti)
+{
+ if (ir_len > 8)
+ {
+ LOG_ERROR("ir_len overflow, maxium is 8");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_ir(tap, ir_in, &ir_out, ir_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_dr_u8(jtag_tap_t *tap, u8 *dr_in, u8 dr_out, int dr_len, int rti)
+{
+ if (dr_len > 8)
+ {
+ LOG_ERROR("dr_len overflow, maxium is 8");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_dr(tap, dr_in, &dr_out, dr_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti)
+{
+ if (ir_len > 16)
+ {
+ LOG_ERROR("ir_len overflow, maxium is 16");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_ir(tap, (u8*)ir_in, (u8*)&ir_out, ir_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_dr_u16(jtag_tap_t *tap, u16 *dr_in, u16 dr_out, int dr_len, int rti)
+{
+ if (dr_len > 16)
+ {
+ LOG_ERROR("dr_len overflow, maxium is 16");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_dr(tap, (u8*)dr_in, (u8*)&dr_out, dr_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti)
+{
+ if (ir_len > 32)
+ {
+ LOG_ERROR("ir_len overflow, maxium is 32");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_ir(tap, (u8*)ir_in, (u8*)&ir_out, ir_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_dr_u32(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int dr_len, int rti)
+{
+ if (dr_len > 32)
+ {
+ LOG_ERROR("dr_len overflow, maxium is 32");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_dr(tap, (u8*)dr_in, (u8*)&dr_out, dr_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_execute_queue(void)
+{
+ return jtag_execute_queue();
+}
Property changes on: trunk/src/target/avrt.c
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/target/avrt.h
===================================================================
--- trunk/src/target/avrt.h 2009-04-27 16:08:25 UTC (rev 1547)
+++ trunk/src/target/avrt.h 2009-04-27 19:35:31 UTC (rev 1548)
@@ -1,33 +1,33 @@
-/***************************************************************************
- * Copyright (C) 2009 by Simon Qian *
- * Sim...@Si... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- ***************************************************************************/
-#ifndef AVRT_H
-#define AVRT_H
-
-typedef struct mcu_jtag_s
-{
- jtag_tap_t *tap;
-} mcu_jtag_t;
-
-typedef struct avr_common_s
-{
- mcu_jtag_t jtag_info;
-} avr_common_t;
-
-#endif /* AVRT_H */
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * Sim...@Si... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef AVRT_H
+#define AVRT_H
+
+typedef struct mcu_jtag_s
+{
+ jtag_tap_t *tap;
+} mcu_jtag_t;
+
+typedef struct avr_common_s
+{
+ mcu_jtag_t jtag_info;
+} avr_common_t;
+
+#endif /* AVRT_H */
Property changes on: trunk/src/target/avrt.h
___________________________________________________________________
Name: svn:eol-style
+ native
|
|
From: <ml...@ma...> - 2009-04-27 18:08:26
|
Author: mlu
Date: 2009-04-27 18:08:25 +0200 (Mon, 27 Apr 2009)
New Revision: 1547
Modified:
trunk/src/target/arm_adi_v5.h
trunk/src/target/armv7m.c
Log:
Added dap baseaddr and dap apid commands
Modified: trunk/src/target/arm_adi_v5.h
===================================================================
--- trunk/src/target/arm_adi_v5.h 2009-04-27 16:03:39 UTC (rev 1546)
+++ trunk/src/target/arm_adi_v5.h 2009-04-27 16:08:25 UTC (rev 1547)
@@ -136,7 +136,9 @@
extern int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel);
/* Commands for user dap access */
+/* Currently implemented in armv7m, needs armv7m target structure to find jtag and swjdp structures */
extern int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
extern int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
-
+extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+extern int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
#endif
Modified: trunk/src/target/armv7m.c
===================================================================
--- trunk/src/target/armv7m.c 2009-04-27 16:03:39 UTC (rev 1546)
+++ trunk/src/target/armv7m.c 2009-04-27 16:08:25 UTC (rev 1547)
@@ -372,7 +372,7 @@
for (i = 0; i < num_reg_params; i++)
{
reg_t *reg = register_get_by_name(armv7m->core_cache, reg_params[i].reg_name, 0);
- u32 regvalue;
+// u32 regvalue;
if (!reg)
{
@@ -386,7 +386,7 @@
exit(-1);
}
- regvalue = buf_get_u32(reg_params[i].value, 0, 32);
+// regvalue = buf_get_u32(reg_params[i].value, 0, 32);
armv7m_set_core_reg(reg, reg_params[i].value);
}
@@ -553,8 +553,10 @@
command_t *arm_adi_v5_dap_cmd;
arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands");
- register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "dap info for ap [num] (default 0)");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "dap info for ap [num], default currently selected AP");
register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "select a different AP [num] (default 0)");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apid", handle_dap_apid_command, COMMAND_EXEC, "return id reg from AP [num], default currently selected AP");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "baseaddr", handle_dap_baseaddr_command, COMMAND_EXEC, "return debug base address from AP [num], default currently selected AP");
return ERROR_OK;
}
@@ -702,6 +704,75 @@
return ERROR_OK;
}
+/********************************************************************************************************************
+* Return the debug ap baseaddress in hexadecimal, no extra output to simplify script processing
+*********************************************************************************************************************/
+int handle_dap_baseaddr_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ u32 apsel, apselsave, baseaddr;
+ int retval;
+
+ apsel = swjdp->apsel;
+ apselsave = swjdp->apsel;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apsel);
+ }
+
+ dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "0x%8.8x", baseaddr);
+
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apselsave);
+ }
+
+ return retval;
+}
+
+
+/********************************************************************************************************************
+* Return the debug ap id in hexadecimal, no extra output to simplify script processing
+*********************************************************************************************************************/
+extern int handle_dap_apid_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ u32 apsel, apselsave, apid;
+ int retval;
+
+ apsel = swjdp->apsel;
+ apselsave = swjdp->apsel;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apsel);
+ }
+
+ dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "0x%8.8x", apid);
+ if (apselsave != apsel)
+ {
+ dap_ap_select(swjdp, apselsave);
+ }
+
+ return retval;
+}
+
int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
@@ -732,7 +803,7 @@
int retval;
u32 apsel;
- apsel = 0;
+ apsel = swjdp->apsel;
if (argc > 0)
{
apsel = strtoul(args[0], NULL, 0);
|
|
From: <oh...@ma...> - 2009-04-27 18:03:41
|
Author: oharboe
Date: 2009-04-27 18:03:39 +0200 (Mon, 27 Apr 2009)
New Revision: 1546
Modified:
trunk/src/jtag/jtag.h
Log:
Dick Hollenbeck <di...@so...> Collect some macros, add DIM()
Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h 2009-04-27 13:00:29 UTC (rev 1545)
+++ trunk/src/jtag/jtag.h 2009-04-27 16:03:39 UTC (rev 1546)
@@ -40,7 +40,18 @@
#define DEBUG_JTAG_IOZ 64
#endif
+/*-----<Macros>--------------------------------------------------*/
+/** When given an array, compute its DIMension, i.e. number of elements in the array */
+#define DIM(x) (sizeof(x)/sizeof((x)[0]))
+
+/** Calculate the number of bytes required to hold @a n TAP scan bits */
+#define TAP_SCAN_BYTES(n) CEIL(n, 8)
+
+/*-----</Macros>-------------------------------------------------*/
+
+
+
/*
* Tap states from ARM7TDMI-S Technical reference manual.
* Also, validated against several other ARM core technical manuals.
@@ -236,9 +247,6 @@
struct scan_field_s;
typedef int (*in_handler_t)(u8* in_value, void* priv, struct scan_field_s* field);
-/// @brief calculates number of bytes required to hold @a n TAP scan bits
-#define TAP_SCAN_BYTES(n) CEIL(n, 8)
-
typedef struct scan_field_s
{
jtag_tap_t* tap; /* tap pointer this instruction refers to */
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 15:00:30
|
Author: oharboe
Date: 2009-04-27 15:00:29 +0200 (Mon, 27 Apr 2009)
New Revision: 1545
Modified:
trunk/src/jtag/vsllink.c
Log:
SimonQian <sim...@si...> patch for error compiling vsllink if --enable-verbose-jtag-io is set
Modified: trunk/src/jtag/vsllink.c
===================================================================
--- trunk/src/jtag/vsllink.c 2009-04-27 12:12:44 UTC (rev 1544)
+++ trunk/src/jtag/vsllink.c 2009-04-27 13:00:29 UTC (rev 1545)
@@ -242,7 +242,7 @@
static int vsllink_usb_write(vsllink_jtag_t *vsllink_jtag, int out_length);
static int vsllink_usb_read(vsllink_jtag_t *vsllink_jtag);
-#ifdef _DEBUG_USB_COMMS_
+#if defined _DEBUG_USB_COMMS_ || defined _DEBUG_JTAG_IO_
static void vsllink_debug_buffer(u8 *buffer, int length);
#endif
@@ -1243,7 +1243,7 @@
// which is merged from the last tms shift command
vsllink_usb_out_buffer[vsllink_usb_out_buffer_idx++] = VSLLINK_CMDJTAGSEQ_SCAN | 1;
vsllink_usb_out_buffer[vsllink_usb_out_buffer_idx++] = ((tdi_len + 1) >> 0) & 0xff;
- vsllink_usb_out_buffer[vsllink_usb_out_buffer_idx++] = ((tdi_len + 1)>> 8) & 0xff;
+ vsllink_usb_out_buffer[vsllink_usb_out_buffer_idx++] = ((tdi_len + 1) >> 8) & 0xff;
vsllink_usb_out_buffer[vsllink_usb_out_buffer_idx++] = tms_tmp;
vsllink_usb_out_buffer[vsllink_usb_out_buffer_idx++] = buffer[0] << (8 - vsllink_tms_data_len);
@@ -1917,7 +1917,7 @@
#define BYTES_PER_LINE 16
-#ifdef _DEBUG_USB_COMMS_
+#if defined _DEBUG_USB_COMMS_ || defined _DEBUG_JTAG_IO_
static void vsllink_debug_buffer(u8 *buffer, int length)
{
char line[81];
@@ -1936,4 +1936,4 @@
LOG_DEBUG("%s", line);
}
}
-#endif // _DEBUG_USB_COMMS_
+#endif // _DEBUG_USB_COMMS_ || _DEBUG_JTAG_IO_
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 14:12:45
|
Author: oharboe
Date: 2009-04-27 14:12:44 +0200 (Mon, 27 Apr 2009)
New Revision: 1544
Modified:
trunk/src/target/arm11.c
Log:
clean up debug/info output to be in line with other targets
Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c 2009-04-27 12:02:07 UTC (rev 1543)
+++ trunk/src/target/arm11.c 2009-04-27 12:12:44 UTC (rev 1544)
@@ -525,24 +525,30 @@
void arm11_dump_reg_changes(arm11_common_t * arm11)
{
+
+ if (!(debug_level >= LOG_LVL_DEBUG))
+ {
+ return;
+ }
+
{size_t i;
for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
if (!arm11->reg_list[i].valid)
{
if (arm11->reg_history[i].valid)
- LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
+ LOG_DEBUG("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
}
else
{
if (arm11->reg_history[i].valid)
{
if (arm11->reg_history[i].value != arm11->reg_values[i])
- LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
+ LOG_DEBUG("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
}
else
{
- LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
+ LOG_DEBUG("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
}
}
}}
@@ -712,8 +718,13 @@
/* architecture specific status reply */
int arm11_arch_state(struct target_s *target)
{
- FNC_INFO_NOTIMPLEMENTED;
+ arm11_common_t * arm11 = target->arch_info;
+ LOG_USER("target halted due to %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
+ Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
+ R(CPSR),
+ R(PC));
+
return ERROR_OK;
}
@@ -814,7 +825,7 @@
if (!current)
R(PC) = address;
- LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
+ LOG_DEBUG("RESUME PC %08x%s", R(PC), !current ? "!" : "");
/* clear breakpoints/watchpoints and VCR*/
arm11_sc7_clear_vbw(arm11);
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 14:02:08
|
Author: oharboe
Date: 2009-04-27 14:02:07 +0200 (Mon, 27 Apr 2009)
New Revision: 1543
Modified:
trunk/src/target/arm11.c
trunk/src/target/arm11.h
trunk/src/target/arm11_dbgtap.c
Log:
more error handling
Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c 2009-04-27 11:24:01 UTC (rev 1542)
+++ trunk/src/target/arm11.c 2009-04-27 12:02:07 UTC (rev 1543)
@@ -932,7 +932,8 @@
u32 next_instruction;
- arm11_read_memory_word(arm11, R(PC), &next_instruction);
+ if ((arm11_read_memory_word(arm11, R(PC), &next_instruction))!=ERROR_OK)
+ return retval;
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070)
@@ -976,7 +977,8 @@
brp[1].address = ARM11_SC7_BCR0;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
- arm11_sc7_run(arm11, brp, asizeof(brp));
+ if ((retval=arm11_sc7_run(arm11, brp, asizeof(brp)))!=ERROR_OK)
+ return retval;
/* resume */
@@ -987,7 +989,8 @@
R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
- arm11_leave_debug_state(arm11);
+ if ((retval=arm11_leave_debug_state(arm11))!=ERROR_OK)
+ return retval;
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
@@ -1018,7 +1021,8 @@
arm11_sc7_clear_vbw(arm11);
/* save state */
- arm11_on_enter_debug_state(arm11);
+ if((retval = arm11_on_enter_debug_state(arm11))!=ERROR_OK)
+ return retval;
/* restore default state */
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
Modified: trunk/src/target/arm11.h
===================================================================
--- trunk/src/target/arm11.h 2009-04-27 11:24:01 UTC (rev 1542)
+++ trunk/src/target/arm11.h 2009-04-27 12:02:07 UTC (rev 1543)
@@ -240,18 +240,18 @@
void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state);
void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr);
-void arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
+int arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
void arm11_run_instr_data_prepare (arm11_common_t * arm11);
void arm11_run_instr_data_finish (arm11_common_t * arm11);
-void arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
+int arm11_run_instr_no_data (arm11_common_t * arm11, u32 * opcode, size_t count);
void arm11_run_instr_no_data1 (arm11_common_t * arm11, u32 opcode);
-void arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
-void arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
-void arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
-void arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
+int arm11_run_instr_data_to_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
+int arm11_run_instr_data_to_core_noack (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
+int arm11_run_instr_data_to_core1 (arm11_common_t * arm11, u32 opcode, u32 data);
+int arm11_run_instr_data_from_core (arm11_common_t * arm11, u32 opcode, u32 * data, size_t count);
void arm11_run_instr_data_from_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 * data);
void arm11_run_instr_data_to_core_via_r0 (arm11_common_t * arm11, u32 opcode, u32 data);
@@ -271,12 +271,12 @@
function returns. */
} arm11_sc7_action_t;
-void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
+int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count);
/* Mid-level helper functions */
void arm11_sc7_clear_vbw(arm11_common_t * arm11);
void arm11_sc7_set_vcr(arm11_common_t * arm11, u32 value);
-void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
+int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result);
#endif /* ARM11_H */
Modified: trunk/src/target/arm11_dbgtap.c
===================================================================
--- trunk/src/target/arm11_dbgtap.c 2009-04-27 11:24:01 UTC (rev 1542)
+++ trunk/src/target/arm11_dbgtap.c 2009-04-27 12:02:07 UTC (rev 1543)
@@ -254,7 +254,7 @@
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-void arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
+int arm11_write_DSCR(arm11_common_t * arm11, u32 dscr)
{
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
@@ -266,11 +266,15 @@
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("DSCR <= %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
+
+ return ERROR_OK;
}
@@ -365,7 +369,7 @@
* \param count Number of opcodes to execute
*
*/
-void arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
+int arm11_run_instr_no_data(arm11_common_t * arm11, u32 * opcode, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -379,12 +383,16 @@
arm11_add_debug_INST(arm11, 0, &flag, count ? TAP_IDLE : TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
if (flag)
break;
}
}
+
+ return ERROR_OK;
}
/** Execute one instruction via ITR
@@ -414,7 +422,7 @@
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -439,7 +447,9 @@
Data = *data;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_IDLE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("DTR Ready %d nRetry %d", Ready, nRetry);
}
@@ -455,11 +465,15 @@
Data = 0;
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
while (!Ready);
+
+ return ERROR_OK;
}
/** JTAG path for arm11_run_instr_data_to_core_noack
@@ -495,7 +509,7 @@
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_to_core_noack(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -536,7 +550,9 @@
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
size_t error_count = 0;
@@ -551,6 +567,8 @@
if (error_count)
LOG_ERROR("Transfer errors " ZU, error_count);
+
+ return ERROR_OK;
}
@@ -565,9 +583,9 @@
* \param data Data word to be passed to the core via DTR
*
*/
-void arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
+int arm11_run_instr_data_to_core1(arm11_common_t * arm11, u32 opcode, u32 data)
{
- arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
+ return arm11_run_instr_data_to_core(arm11, opcode, &data, 1);
}
@@ -584,7 +602,7 @@
* \param count Number of data words and instruction repetitions
*
*/
-void arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
+int arm11_run_instr_data_from_core(arm11_common_t * arm11, u32 opcode, u32 * data, size_t count)
{
arm11_add_IR(arm11, ARM11_ITRSEL, ARM11_TAP_DEFAULT);
@@ -607,7 +625,9 @@
do
{
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, count ? TAP_IDLE : TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("DTR Data %08x Ready %d nRetry %d", Data, Ready, nRetry);
}
@@ -615,6 +635,8 @@
*data++ = Data;
}
+
+ return ERROR_OK;
}
/** Execute one instruction via ITR
@@ -666,7 +688,7 @@
* \param count Number of instructions in the list.
*
*/
-void arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
+int arm11_sc7_run(arm11_common_t * arm11, arm11_sc7_action_t * actions, size_t count)
{
arm11_add_debug_SCAN_N(arm11, 0x07, ARM11_TAP_DEFAULT);
@@ -706,7 +728,9 @@
JTAG_DEBUG("SC7 <= Address %02x Data %08x nRW %d", AddressOut, DataOut, nRW);
arm11_add_dr_scan_vc(asizeof(chain7_fields), chain7_fields, TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
JTAG_DEBUG("SC7 => Address %02x Data %08x Ready %d", AddressIn, DataIn, Ready);
}
@@ -738,6 +762,8 @@
{
JTAG_DEBUG("SC7 %02d: %02x %s %08x", i, actions[i].address, actions[i].write ? "<=" : "=>", actions[i].value);
}}
+
+ return ERROR_OK;
}
/** Clear VCR and all breakpoints and watchpoints via scan chain 7
@@ -798,17 +824,22 @@
* \param result Pointer where to store result
*
*/
-void arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
+int arm11_read_memory_word(arm11_common_t * arm11, u32 address, u32 * result)
{
+ int retval;
arm11_run_instr_data_prepare(arm11);
/* MRC p14,0,r0,c0,c5,0 (r0 = address) */
- arm11_run_instr_data_to_core1(arm11, 0xee100e15, address);
+ if ((retval=arm11_run_instr_data_to_core1(arm11, 0xee100e15, address))!=ERROR_OK)
+ return retval;
/* LDC p14,c5,[R0],#4 (DTR = [r0]) */
- arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1);
+ if ((retval=arm11_run_instr_data_from_core(arm11, 0xecb05e01, result, 1))!=ERROR_OK)
+ return retval;
arm11_run_instr_data_finish(arm11);
+
+ return ERROR_OK;
}
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 13:24:05
|
Author: oharboe
Date: 2009-04-27 13:24:01 +0200 (Mon, 27 Apr 2009)
New Revision: 1542
Modified:
trunk/src/target/arm11.c
trunk/src/target/arm11.h
trunk/src/target/arm11_dbgtap.c
Log:
a little bit more error handling in ARM11
Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c 2009-04-27 10:37:07 UTC (rev 1541)
+++ trunk/src/target/arm11.c 2009-04-27 11:24:01 UTC (rev 1542)
@@ -48,7 +48,7 @@
#define FNC_INFO_NOTIMPLEMENTED
#endif
-static void arm11_on_enter_debug_state(arm11_common_t * arm11);
+static int arm11_on_enter_debug_state(arm11_common_t * arm11);
bool arm11_config_memwrite_burst = true;
bool arm11_config_memwrite_error_fatal = true;
@@ -313,16 +313,18 @@
* available a pointer to a word holding the
* DSCR can be passed. Otherwise use NULL.
*/
-void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
+int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
{
FNC_INFO;
+ int retval;
u32 dscr_local_tmp_copy;
if (!dscr)
{
dscr = &dscr_local_tmp_copy;
- *dscr = arm11_read_DSCR(arm11);
+ if ((retval=arm11_read_DSCR(arm11, dscr))!=ERROR_OK)
+ return retval;
}
if (!(*dscr & ARM11_DSCR_MODE_SELECT))
@@ -353,6 +355,8 @@
arm11_sc7_clear_vbw(arm11);
}
+
+ return ERROR_OK;
}
@@ -366,7 +370,7 @@
* or on other occasions that stop the processor.
*
*/
-static void arm11_on_enter_debug_state(arm11_common_t * arm11)
+static int arm11_on_enter_debug_state(arm11_common_t * arm11)
{
FNC_INFO;
@@ -378,9 +382,10 @@
}}
/* Save DSCR */
+ int retval;
+ if ((retval=arm11_read_DSCR(arm11, &R(DSCR)))!=ERROR_OK)
+ return retval;
- R(DSCR) = arm11_read_DSCR(arm11);
-
/* Save wDTR */
if (R(DSCR) & ARM11_DSCR_WDTR_FULL)
@@ -514,6 +519,8 @@
arm11_run_instr_data_finish(arm11);
arm11_dump_reg_changes(arm11);
+
+ return ERROR_OK;
}
void arm11_dump_reg_changes(arm11_common_t * arm11)
@@ -546,7 +553,7 @@
* This is called in preparation for the RESTART function.
*
*/
-void arm11_leave_debug_state(arm11_common_t * arm11)
+int arm11_leave_debug_state(arm11_common_t * arm11)
{
FNC_INFO;
@@ -572,7 +579,12 @@
/* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */
{
- u32 DSCR = arm11_read_DSCR(arm11);
+ u32 DSCR;
+ int retval;
+ if ((retval=arm11_read_DSCR(arm11, &DSCR))!=ERROR_OK)
+ {
+ return retval;
+ }
if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
@@ -632,6 +644,8 @@
}
arm11_record_register_history(arm11);
+
+ return ERROR_OK;
}
void arm11_record_register_history(arm11_common_t * arm11)
@@ -658,11 +672,15 @@
if (arm11->trst_active)
return ERROR_OK;
- u32 dscr = arm11_read_DSCR(arm11);
+ u32 dscr;
+ int retval;
+ if ((retval=arm11_read_DSCR(arm11, &dscr))!=ERROR_OK)
+ return retval;
LOG_DEBUG("DSCR %08x", dscr);
- arm11_check_init(arm11, &dscr);
+ if ((retval=arm11_check_init(arm11, &dscr))!=ERROR_OK)
+ return retval;
if (dscr & ARM11_DSCR_CORE_HALTED)
{
@@ -747,7 +765,10 @@
while (1)
{
- dscr = arm11_read_DSCR(arm11);
+ int retval;
+ retval = arm11_read_DSCR(arm11, &dscr);
+ if (retval!=ERROR_OK)
+ return retval;
if (dscr & ARM11_DSCR_CORE_HALTED)
break;
@@ -774,7 +795,7 @@
int retval = ERROR_OK;
FNC_INFO;
-
+
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
@@ -851,7 +872,10 @@
while (1)
{
- u32 dscr = arm11_read_DSCR(arm11);
+ u32 dscr;
+ retval = arm11_read_DSCR(arm11, &dscr);
+ if (retval!=ERROR_OK)
+ return retval;
LOG_DEBUG("DSCR %08x", dscr);
@@ -961,8 +985,8 @@
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
else
R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
-
+
arm11_leave_debug_state(arm11);
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
@@ -978,7 +1002,10 @@
while (1)
{
- u32 dscr = arm11_read_DSCR(arm11);
+ u32 dscr;
+ retval = arm11_read_DSCR(arm11, &dscr);
+ if (retval!=ERROR_OK)
+ return retval;
LOG_DEBUG("DSCR %08x", dscr);
@@ -1987,7 +2014,7 @@
RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
memrw_no_increment)
-
+
RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
step_irq_enable)
Modified: trunk/src/target/arm11.h
===================================================================
--- trunk/src/target/arm11.h 2009-04-27 10:37:07 UTC (rev 1541)
+++ trunk/src/target/arm11.h 2009-04-27 11:24:01 UTC (rev 1542)
@@ -91,7 +91,7 @@
bool trst_active;
bool halt_requested; /**< Keep track if arm11_halt() calls occured
during reset. Otherwise do it ASAP. */
-
+
bool simulate_reset_on_next_halt; /**< Perform cleanups of the ARM state on next halt */
/** \name Shadow registers to save processor state */
@@ -239,7 +239,7 @@
void arm11_add_IR (arm11_common_t * arm11, u8 instr, tap_state_t state);
void arm11_add_debug_SCAN_N (arm11_common_t * arm11, u8 chain, tap_state_t state);
void arm11_add_debug_INST (arm11_common_t * arm11, u32 inst, u8 * flag, tap_state_t state);
-u32 arm11_read_DSCR (arm11_common_t * arm11);
+int arm11_read_DSCR (arm11_common_t * arm11, u32 *dscr);
void arm11_write_DSCR (arm11_common_t * arm11, u32 dscr);
enum target_debug_reason arm11_get_DSCR_debug_reason(u32 dscr);
Modified: trunk/src/target/arm11_dbgtap.c
===================================================================
--- trunk/src/target/arm11_dbgtap.c 2009-04-27 10:37:07 UTC (rev 1541)
+++ trunk/src/target/arm11_dbgtap.c 2009-04-27 11:24:01 UTC (rev 1542)
@@ -216,7 +216,7 @@
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
-u32 arm11_read_DSCR(arm11_common_t * arm11)
+int arm11_read_DSCR(arm11_common_t * arm11, u32 *value)
{
arm11_add_debug_SCAN_N(arm11, 0x01, ARM11_TAP_DEFAULT);
@@ -229,14 +229,20 @@
arm11_add_dr_scan_vc(1, &chain1_field, TAP_DRPAUSE);
- jtag_execute_queue();
+ int retval;
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ {
+ return retval;
+ }
if (arm11->last_dscr != dscr)
JTAG_DEBUG("DSCR = %08x (OLD %08x)", dscr, arm11->last_dscr);
arm11->last_dscr = dscr;
- return dscr;
+ *value=dscr;
+
+ return retval;
}
/** Write the Debug Status and Control Register (DSCR)
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 12:37:09
|
Author: oharboe Date: 2009-04-27 12:37:07 +0200 (Mon, 27 Apr 2009) New Revision: 1541 Modified: zy1000/trunk/ecoshal/hal/zylin/phi/current/include/pkgconf/mlt_zylin_phi_dram_fast.ldi Log: fix cortex build problems Modified: zy1000/trunk/ecoshal/hal/zylin/phi/current/include/pkgconf/mlt_zylin_phi_dram_fast.ldi =================================================================== --- zy1000/trunk/ecoshal/hal/zylin/phi/current/include/pkgconf/mlt_zylin_phi_dram_fast.ldi 2009-04-27 10:32:13 UTC (rev 1540) +++ zy1000/trunk/ecoshal/hal/zylin/phi/current/include/pkgconf/mlt_zylin_phi_dram_fast.ldi 2009-04-27 10:37:07 UTC (rev 1541) @@ -181,10 +181,16 @@ KEEP (*(.text.*swjdp_scan*)) ; KEEP (*(.text.*ahbap_write_buf_u32*)) ; KEEP (*(.text.*ahbap_write_system_atomic_u32*)) ; + + KEEP (*(.text.*mem_ap_write_atomic_u32*)) ; + KEEP (*(.text.*mem_ap_read_atomic_u32*)) ; + + KEEP (*(.text.*ahbap_read_system_atomic_u32*)) ; KEEP (*(.text.*swjdp_transaction_endcheck*)) ; KEEP (*(.text.*buf_cmp_mask*)) ; KEEP (*(.text.*buf_cpy*)) ; + KEEP (*(.text.*dap_info_command*)) ; . = ALIGN (4); |
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 12:32:17
|
Author: oharboe
Date: 2009-04-27 12:32:13 +0200 (Mon, 27 Apr 2009)
New Revision: 1540
Added:
trunk/src/flash/avrf.c
trunk/src/flash/avrf.h
trunk/src/target/avrt.c
trunk/src/target/avrt.h
Modified:
trunk/src/flash/Makefile.am
trunk/src/flash/flash.c
trunk/src/target/Makefile.am
trunk/src/target/target.c
Log:
SimonQian <sim...@si...> AVR wip
Modified: trunk/src/flash/Makefile.am
===================================================================
--- trunk/src/flash/Makefile.am 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/flash/Makefile.am 2009-04-27 10:32:13 UTC (rev 1540)
@@ -7,10 +7,10 @@
str7x.c str9x.c aduc702x.c nand.c nand_ecc.c \
lpc3180_nand_controller.c stellaris.c str9xpec.c stm32x.c tms470.c \
ecos.c orion_nand.c s3c24xx_nand.c s3c2410_nand.c s3c2412_nand.c \
- s3c2440_nand.c s3c2443_nand.c lpc288x.c ocl.c mflash.c pic32mx.c
+ s3c2440_nand.c s3c2443_nand.c lpc288x.c ocl.c mflash.c pic32mx.c avrf.c
noinst_HEADERS = \
flash.h lpc2000.h cfi.h non_cfi.h at91sam7.h at91sam7_old.h str7x.h \
str9x.h nand.h lpc3180_nand_controller.h stellaris.h str9xpec.h \
stm32x.h tms470.h s3c24xx_nand.h s3c24xx_regs_nand.h lpc288x.h \
- mflash.h ocl.h pic32mx.h
+ mflash.h ocl.h pic32mx.h avrf.h
MAINTAINERCLEANFILES = Makefile.in
Added: trunk/src/flash/avrf.c
===================================================================
--- trunk/src/flash/avrf.c 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/flash/avrf.c 2009-04-27 10:32:13 UTC (rev 1540)
@@ -0,0 +1,500 @@
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * Sim...@Si... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+
+#include "avrf.h"
+#include "avrt.h"
+#include "flash.h"
+#include "target.h"
+#include "log.h"
+#include "algorithm.h"
+#include "binarybuffer.h"
+
+#include <stdlib.h>
+#include <string.h>
+
+/* AVR_JTAG_Instructions */
+#define AVR_JTAG_INS_LEN 4
+// Public Instructions:
+#define AVR_JTAG_INS_EXTEST 0x00
+#define AVR_JTAG_INS_IDCODE 0x01
+#define AVR_JTAG_INS_SAMPLE_PRELOAD 0x02
+#define AVR_JTAG_INS_BYPASS 0x0F
+// AVR Specified Public Instructions:
+#define AVR_JTAG_INS_AVR_RESET 0x0C
+#define AVR_JTAG_INS_PROG_ENABLE 0x04
+#define AVR_JTAG_INS_PROG_COMMANDS 0x05
+#define AVR_JTAG_INS_PROG_PAGELOAD 0x06
+#define AVR_JTAG_INS_PROG_PAGEREAD 0x07
+
+// Data Registers:
+#define AVR_JTAG_REG_Bypass_Len 1
+#define AVR_JTAG_REG_DeviceID_Len 32
+
+#define AVR_JTAG_REG_Reset_Len 1
+#define AVR_JTAG_REG_JTAGID_Len 32
+#define AVR_JTAG_REG_ProgrammingEnable_Len 16
+#define AVR_JTAG_REG_ProgrammingCommand_Len 15
+#define AVR_JTAG_REG_FlashDataByte_Len 16
+
+avrf_type_t avft_chips_info[] =
+{
+// name, chip_id, flash_page_size, flash_page_num, eeprom_page_size, eeprom_page_num
+ {"atmega128", 0x9702, 256, 512, 8, 512},
+};
+
+static int avrf_register_commands(struct command_context_s *cmd_ctx);
+static int avrf_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank);
+static int avrf_erase(struct flash_bank_s *bank, int first, int last);
+static int avrf_protect(struct flash_bank_s *bank, int set, int first, int last);
+static int avrf_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count);
+static int avrf_probe(struct flash_bank_s *bank);
+static int avrf_auto_probe(struct flash_bank_s *bank);
+//static int avrf_handle_part_id_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+static int avrf_protect_check(struct flash_bank_s *bank);
+static int avrf_info(struct flash_bank_s *bank, char *buf, int buf_size);
+
+static int avrf_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+
+extern int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out);
+extern int avr_jtag_senddat(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int len);
+
+extern int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti);
+extern int mcu_write_dr(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int dr_len, int rti);
+extern int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti);
+extern int mcu_write_dr_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int dr_len, int rti);
+extern int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti);
+extern int mcu_write_dr_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int dr_len, int rti);
+extern int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti);
+extern int mcu_write_dr_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int dr_len, int rti);
+extern int mcu_execute_queue(void);
+
+flash_driver_t avr_flash =
+{
+ .name = "avr",
+ .register_commands = avrf_register_commands,
+ .flash_bank_command = avrf_flash_bank_command,
+ .erase = avrf_erase,
+ .protect = avrf_protect,
+ .write = avrf_write,
+ .probe = avrf_probe,
+ .auto_probe = avrf_auto_probe,
+ .erase_check = default_flash_mem_blank_check,
+ .protect_check = avrf_protect_check,
+ .info = avrf_info
+};
+
+/* avr program functions */
+static int avr_jtag_reset(avr_common_t *avr, u32 reset)
+{
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_AVR_RESET);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, reset ,AVR_JTAG_REG_Reset_Len);
+
+ return ERROR_OK;
+}
+
+static int avr_jtag_read_jtagid(avr_common_t *avr, u32 *id)
+{
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_IDCODE);
+ avr_jtag_senddat(avr->jtag_info.tap, id, 0, AVR_JTAG_REG_JTAGID_Len);
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_enterprogmode(avr_common_t *avr)
+{
+ avr_jtag_reset(avr, 1);
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xA370, AVR_JTAG_REG_ProgrammingEnable_Len);
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_leaveprogmode(avr_common_t *avr)
+{
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2300, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3300, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_ENABLE);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0, AVR_JTAG_REG_ProgrammingEnable_Len);
+
+ avr_jtag_reset(avr, 0);
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_chiperase(avr_common_t *avr)
+{
+ u32 poll_value;
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2380, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3180, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ do{
+ poll_value = 0;
+ avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3380, AVR_JTAG_REG_ProgrammingCommand_Len);
+ if (ERROR_OK != mcu_execute_queue())
+ {
+ return ERROR_FAIL;
+ }
+ LOG_DEBUG("poll_value = 0x%04X", poll_value);
+ }while(!(poll_value & 0x0200));
+
+ return ERROR_OK;
+}
+
+static int avr_jtagprg_writeflashpage(avr_common_t *avr, u8 *page_buf, u32 buf_size, u32 addr, u32 page_size)
+{
+ u32 i, poll_value;
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x2310, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ // load addr high byte
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0700 | ((addr >> 9) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ // load addr low byte
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x0300 | ((addr >> 1) & 0xFF), AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_PAGELOAD);
+
+ for (i = 0; i < page_size; i++)
+ {
+ if (i < buf_size)
+ {
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, page_buf[i], 8);
+ }
+ else
+ {
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0xFF, 8);
+ }
+ }
+
+ avr_jtag_sendinstr(avr->jtag_info.tap, NULL, AVR_JTAG_INS_PROG_COMMANDS);
+
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3500, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+ avr_jtag_senddat(avr->jtag_info.tap, NULL, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+
+ do{
+ poll_value = 0;
+ avr_jtag_senddat(avr->jtag_info.tap, &poll_value, 0x3700, AVR_JTAG_REG_ProgrammingCommand_Len);
+ if (ERROR_OK != mcu_execute_queue())
+ {
+ return ERROR_FAIL;
+ }
+ LOG_DEBUG("poll_value = 0x%04X", poll_value);
+ }while(!(poll_value & 0x0200));
+
+ return ERROR_OK;
+}
+
+/* interface command */
+static int avrf_register_commands(struct command_context_s *cmd_ctx)
+{
+ command_t *avr_cmd = register_command(cmd_ctx, NULL, "avr", NULL, COMMAND_ANY, "avr flash specific commands");
+
+ register_command(cmd_ctx, avr_cmd, "mass_erase", avrf_handle_mass_erase_command, COMMAND_EXEC,
+ "mass erase device");
+
+ return ERROR_OK;
+}
+
+static int avrf_flash_bank_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct flash_bank_s *bank)
+{
+ avrf_flash_bank_t *avrf_info;
+
+ if (argc < 6)
+ {
+ LOG_WARNING("incomplete flash_bank avr configuration");
+ return ERROR_FLASH_BANK_INVALID;
+ }
+
+ avrf_info = malloc(sizeof(avrf_flash_bank_t));
+ bank->driver_priv = avrf_info;
+
+ avrf_info->probed = 0;
+
+ return ERROR_OK;
+}
+
+static int avrf_erase(struct flash_bank_s *bank, int first, int last)
+{
+ LOG_INFO(__FUNCTION__);
+ return ERROR_OK;
+}
+
+static int avrf_protect(struct flash_bank_s *bank, int set, int first, int last)
+{
+ LOG_INFO(__FUNCTION__);
+ return ERROR_OK;
+}
+
+static int avrf_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)
+{
+ target_t *target = bank->target;
+ avr_common_t *avr = target->arch_info;
+ u32 cur_size, cur_buffer_size, page_size;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ page_size = bank->sectors[0].size;
+ if ((offset % page_size) != 0)
+ {
+ LOG_WARNING("offset 0x%x breaks required %d-byte alignment", offset, page_size);
+ return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
+ }
+
+ LOG_DEBUG("offset is 0x%08X", offset);
+ LOG_DEBUG("count is %d", count);
+
+ if (ERROR_OK != avr_jtagprg_enterprogmode(avr))
+ {
+ return ERROR_FAIL;
+ }
+
+ cur_size = 0;
+ while(count > 0)
+ {
+ if (count > page_size)
+ {
+ cur_buffer_size = page_size;
+ }
+ else
+ {
+ cur_buffer_size = count;
+ }
+ avr_jtagprg_writeflashpage(avr, buffer + cur_size, cur_buffer_size, offset + cur_size, page_size);
+ count -= cur_buffer_size;
+ cur_size += cur_buffer_size;
+
+ keep_alive();
+ }
+
+ return avr_jtagprg_leaveprogmode(avr);
+}
+
+#define EXTRACT_MFG(X) (((X) & 0xffe) >> 1)
+#define EXTRACT_PART(X) (((X) & 0xffff000) >> 12)
+#define EXTRACT_VER(X) (((X) & 0xf0000000) >> 28)
+static int avrf_probe(struct flash_bank_s *bank)
+{
+ target_t *target = bank->target;
+ avrf_flash_bank_t *avrf_info = bank->driver_priv;
+ avr_common_t *avr = target->arch_info;
+ avrf_type_t *avr_info;
+ int i;
+ u32 device_id;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ avrf_info->probed = 0;
+
+ avr_jtag_read_jtagid(avr, &device_id);
+ if (ERROR_OK != mcu_execute_queue())
+ {
+ return ERROR_FAIL;
+ }
+
+ LOG_INFO( "device id = 0x%08x", device_id );
+ if (EXTRACT_MFG(device_id) != 0x1F)
+ {
+ LOG_ERROR("0x%X is invalid Manufacturer for avr, 0x%X is expected", EXTRACT_MFG(device_id), 0x1F);
+ }
+
+ for (i = 0; i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])); i++)
+ {
+ if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id))
+ {
+ avr_info = &avft_chips_info[i];
+ LOG_INFO("target device is %s", avr_info->name);
+ break;
+ }
+ }
+
+ if (i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])))
+ {
+ // chip found
+ bank->base = 0x00000000;
+ bank->size = (avr_info->flash_page_size * avr_info->flash_page_num);
+ bank->num_sectors = avr_info->flash_page_num;
+ bank->sectors = malloc(sizeof(flash_sector_t) * avr_info->flash_page_num);
+
+ for (i = 0; i < avr_info->flash_page_num; i++)
+ {
+ bank->sectors[i].offset = i * avr_info->flash_page_size;
+ bank->sectors[i].size = avr_info->flash_page_size;
+ bank->sectors[i].is_erased = -1;
+ bank->sectors[i].is_protected = 1;
+ }
+
+ avrf_info->probed = 1;
+ return ERROR_OK;
+ }
+ else
+ {
+ // chip not supported
+ LOG_ERROR("0x%X is not support for avr", EXTRACT_PART(device_id));
+
+ avrf_info->probed = 1;
+ return ERROR_FAIL;
+ }
+}
+
+static int avrf_auto_probe(struct flash_bank_s *bank)
+{
+ avrf_flash_bank_t *avrf_info = bank->driver_priv;
+ if (avrf_info->probed)
+ return ERROR_OK;
+ return avrf_probe(bank);
+}
+
+static int avrf_protect_check(struct flash_bank_s *bank)
+{
+ LOG_INFO(__FUNCTION__);
+ return ERROR_OK;
+}
+
+static int avrf_info(struct flash_bank_s *bank, char *buf, int buf_size)
+{
+ target_t *target = bank->target;
+ avr_common_t *avr = target->arch_info;
+ avrf_type_t *avr_info;
+ int i;
+ u32 device_id;
+
+ if (bank->target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ avr_jtag_read_jtagid(avr, &device_id);
+ if (ERROR_OK != mcu_execute_queue())
+ {
+ return ERROR_FAIL;
+ }
+
+ LOG_INFO( "device id = 0x%08x", device_id );
+ if (EXTRACT_MFG(device_id) != 0x1F)
+ {
+ LOG_ERROR("0x%X is invalid Manufacturer for avr, 0x%X is expected", EXTRACT_MFG(device_id), 0x1F);
+ }
+
+ for (i = 0; i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])); i++)
+ {
+ if (avft_chips_info[i].chip_id == EXTRACT_PART(device_id))
+ {
+ avr_info = &avft_chips_info[i];
+ LOG_INFO("target device is %s", avr_info->name);
+
+ return ERROR_OK;
+ }
+ }
+
+ if (i < (int)(sizeof(avft_chips_info) / sizeof(avft_chips_info[0])))
+ {
+ // chip found
+ snprintf(buf, buf_size, "%s - Rev: 0x%X", avr_info->name, EXTRACT_VER(device_id));
+ return ERROR_OK;
+ }
+ else
+ {
+ // chip not supported
+ snprintf(buf, buf_size, "Cannot identify target as a avr\n");
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+}
+
+static int avrf_mass_erase(struct flash_bank_s *bank)
+{
+ target_t *target = bank->target;
+ avr_common_t *avr = target->arch_info;
+
+ if (target->state != TARGET_HALTED)
+ {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if ((ERROR_OK != avr_jtagprg_enterprogmode(avr))
+ || (ERROR_OK != avr_jtagprg_chiperase(avr))
+ || (ERROR_OK != avr_jtagprg_leaveprogmode(avr)))
+ {
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static int avrf_handle_mass_erase_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ flash_bank_t *bank;
+ int i;
+
+ if (argc < 1)
+ {
+ command_print(cmd_ctx, "avr mass_erase <bank>");
+ return ERROR_OK;
+ }
+
+ bank = get_flash_bank_by_num(strtoul(args[0], NULL, 0));
+ if (!bank)
+ {
+ command_print(cmd_ctx, "flash bank '#%s' is out of bounds", args[0]);
+ return ERROR_OK;
+ }
+
+ if (avrf_mass_erase(bank) == ERROR_OK)
+ {
+ /* set all sectors as erased */
+ for (i = 0; i < bank->num_sectors; i++)
+ {
+ bank->sectors[i].is_erased = 1;
+ }
+
+ command_print(cmd_ctx, "avr mass erase complete");
+ }
+ else
+ {
+ command_print(cmd_ctx, "avr mass erase failed");
+ }
+
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
Added: trunk/src/flash/avrf.h
===================================================================
--- trunk/src/flash/avrf.h 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/flash/avrf.h 2009-04-27 10:32:13 UTC (rev 1540)
@@ -0,0 +1,39 @@
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * Sim...@Si... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef AVRF_H
+#define AVRF_H
+
+typedef struct avrf_type_s
+{
+ char name[15];
+ u16 chip_id;
+ int flash_page_size;
+ int flash_page_num;
+ int eeprom_page_size;
+ int eeprom_page_num;
+} avrf_type_t;
+
+typedef struct avrf_flash_bank_s
+{
+ int ppage_size;
+ int probed;
+} avrf_flash_bank_t;
+
+#endif /* AVRF_H */
Modified: trunk/src/flash/flash.c
===================================================================
--- trunk/src/flash/flash.c 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/flash/flash.c 2009-04-27 10:32:13 UTC (rev 1540)
@@ -77,6 +77,7 @@
extern flash_driver_t lpc288x_flash;
extern flash_driver_t ocl_flash;
extern flash_driver_t pic32mx_flash;
+extern flash_driver_t avr_flash;
flash_driver_t *flash_drivers[] = {
&lpc2000_flash,
@@ -94,6 +95,7 @@
&lpc288x_flash,
&ocl_flash,
&pic32mx_flash,
+ &avr_flash,
NULL,
};
Modified: trunk/src/target/Makefile.am
===================================================================
--- trunk/src/target/Makefile.am 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/target/Makefile.am 2009-04-27 10:32:13 UTC (rev 1540)
@@ -13,11 +13,11 @@
arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c arm_adi_v5.c \
etm_dummy.c $(OOCD_TRACE_FILES) target_request.c trace.c arm11.c arm11_dbgtap.c mips32.c mips_m4k.c \
- mips32_pracc.c mips32_dmaacc.c mips_ejtag.c
+ mips32_pracc.c mips32_dmaacc.c mips_ejtag.c avrt.c
noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h arm_adi_v5.h \
- etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
+ etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h avrt.h
nobase_dist_pkglib_DATA =
nobase_dist_pkglib_DATA += xscale/debug_handler.bin
Added: trunk/src/target/avrt.c
===================================================================
--- trunk/src/target/avrt.c 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/target/avrt.c 2009-04-27 10:32:13 UTC (rev 1540)
@@ -0,0 +1,354 @@
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * Sim...@Si... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+
+#include "avrt.h"
+
+#include "register.h"
+#include "target.h"
+#include "log.h"
+#include "jtag.h"
+#include "binarybuffer.h"
+#include "time_support.h"
+#include "breakpoints.h"
+#include "fileio.h"
+
+#include <stdlib.h>
+#include <string.h>
+
+#include <sys/types.h>
+#include <unistd.h>
+#include <errno.h>
+
+#define AVR_JTAG_INS_LEN 4
+
+/* cli handling */
+int avr_register_commands(struct command_context_s *cmd_ctx);
+
+/* forward declarations */
+int avr_target_create(struct target_s *target, Jim_Interp *interp);
+int avr_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
+int avr_quit(void);
+
+int avr_arch_state(struct target_s *target);
+int avr_poll(target_t *target);
+int avr_halt(target_t *target);
+int avr_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
+int avr_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
+
+int avr_assert_reset(target_t *target);
+int avr_deassert_reset(target_t *target);
+int avr_soft_reset_halt(struct target_s *target);
+
+/* IR and DR functions */
+int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out);
+int avr_jtag_senddat(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int len);
+
+int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti);
+int mcu_write_dr(jtag_tap_t *tap, u8 *dr_in, u8 *dr_out, int dr_len, int rti);
+int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti);
+int mcu_write_dr_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int dr_len, int rti);
+int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti);
+int mcu_write_dr_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int dr_len, int rti);
+int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti);
+int mcu_write_dr_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int dr_len, int rti);
+int mcu_execute_queue(void);
+
+target_type_t avr_target =
+{
+ .name = "avr",
+
+ .poll = avr_poll,
+ .arch_state = avr_arch_state,
+
+ .target_request_data = NULL,
+
+ .halt = avr_halt,
+ .resume = avr_resume,
+ .step = avr_step,
+
+ .assert_reset = avr_assert_reset,
+ .deassert_reset = avr_deassert_reset,
+ .soft_reset_halt = avr_soft_reset_halt,
+/*
+ .get_gdb_reg_list = avr_get_gdb_reg_list,
+
+ .read_memory = avr_read_memory,
+ .write_memory = avr_write_memory,
+ .bulk_write_memory = avr_bulk_write_memory,
+ .checksum_memory = avr_checksum_memory,
+ .blank_check_memory = avr_blank_check_memory,
+
+ .run_algorithm = avr_run_algorithm,
+
+ .add_breakpoint = avr_add_breakpoint,
+ .remove_breakpoint = avr_remove_breakpoint,
+ .add_watchpoint = avr_add_watchpoint,
+ .remove_watchpoint = avr_remove_watchpoint,
+*/
+ .register_commands = avr_register_commands,
+ .target_create = avr_target_create,
+ .init_target = avr_init_target,
+ .quit = avr_quit,
+/*
+ .virt2phys = avr_virt2phys,
+ .mmu = avr_mmu
+*/
+};
+
+int avr_register_commands(struct command_context_s *cmd_ctx)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_target_create(struct target_s *target, Jim_Interp *interp)
+{
+ avr_common_t *avr = calloc(1, sizeof(avr_common_t));
+
+ avr->jtag_info.tap = target->tap;
+ target->arch_info = avr;
+
+ return ERROR_OK;
+}
+
+int avr_init_target(struct command_context_s *cmd_ctx, struct target_s *target)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_quit(void)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_arch_state(struct target_s *target)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_poll(target_t *target)
+{
+ if ((target->state == TARGET_RUNNING) || (target->state == TARGET_DEBUG_RUNNING))
+ {
+ target->state = TARGET_HALTED;
+ }
+
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_halt(target_t *target)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_assert_reset(target_t *target)
+{
+ target->state = TARGET_RESET;
+
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_deassert_reset(target_t *target)
+{
+ target->state = TARGET_RUNNING;
+
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_soft_reset_halt(struct target_s *target)
+{
+ LOG_DEBUG(__FUNCTION__);
+ return ERROR_OK;
+}
+
+int avr_jtag_senddat(jtag_tap_t *tap, u32* dr_in, u32 dr_out, int len)
+{
+ return mcu_write_dr_u32(tap, dr_in, dr_out, len, 1);
+}
+
+int avr_jtag_sendinstr(jtag_tap_t *tap, u8 *ir_in, u8 ir_out)
+{
+ return mcu_write_ir_u8(tap, ir_in, ir_out, AVR_JTAG_INS_LEN, 1);
+}
+
+/* IR and DR functions */
+int mcu_write_ir(jtag_tap_t *tap, u8 *ir_in, u8 *ir_out, int ir_len, int rti)
+{
+ if (NULL == tap)
+ {
+ LOG_ERROR("invalid tap");
+ return ERROR_FAIL;
+ }
+ if (ir_len != tap->ir_length)
+ {
+ LOG_ERROR("invalid ir_len");
+ return ERROR_FAIL;
+ }
+
+ {
+ scan_field_t field[1];
+
+ field[0].tap = tap;
+ field[0].num_bits = tap->ir_length;
+ field[0].out_value = ir_out;
+ field[0].out_mask = NULL;
+ field[0].in_value = ir_in;
+ field[0].in_check_value = NULL;
+ field[0].in_check_mask = NULL;
+ field[0].in_handler = NULL;
+ field[0].in_handler_priv = NULL;
+ jtag_add_plain_ir_scan(sizeof(field) / sizeof(field[0]), field, TAP_IDLE);
+ }
+
+ return ERROR_OK;
+}
+
+int mcu_write_dr(jtag_tap_t *tap, u8 *dr_in, u8 *dr_out, int dr_len, int rti)
+{
+ if (NULL == tap)
+ {
+ LOG_ERROR("invalid tap");
+ return ERROR_FAIL;
+ }
+
+ {
+ scan_field_t field[1];
+
+ field[0].tap = tap;
+ field[0].num_bits = dr_len;
+ field[0].out_value = dr_out;
+ field[0].out_mask = NULL;
+ field[0].in_value = dr_in;
+ field[0].in_check_value = NULL;
+ field[0].in_check_mask = NULL;
+ field[0].in_handler = NULL;
+ field[0].in_handler_priv = NULL;
+ jtag_add_plain_dr_scan(sizeof(field) / sizeof(field[0]), field, TAP_IDLE);
+ }
+
+ return ERROR_OK;
+}
+
+int mcu_write_ir_u8(jtag_tap_t *tap, u8 *ir_in, u8 ir_out, int ir_len, int rti)
+{
+ if (ir_len > 8)
+ {
+ LOG_ERROR("ir_len overflow, maxium is 8");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_ir(tap, ir_in, &ir_out, ir_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_dr_u8(jtag_tap_t *tap, u8 *dr_in, u8 dr_out, int dr_len, int rti)
+{
+ if (dr_len > 8)
+ {
+ LOG_ERROR("dr_len overflow, maxium is 8");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_dr(tap, dr_in, &dr_out, dr_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_ir_u16(jtag_tap_t *tap, u16 *ir_in, u16 ir_out, int ir_len, int rti)
+{
+ if (ir_len > 16)
+ {
+ LOG_ERROR("ir_len overflow, maxium is 16");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_ir(tap, (u8*)ir_in, (u8*)&ir_out, ir_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_dr_u16(jtag_tap_t *tap, u16 *dr_in, u16 dr_out, int dr_len, int rti)
+{
+ if (dr_len > 16)
+ {
+ LOG_ERROR("dr_len overflow, maxium is 16");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_dr(tap, (u8*)dr_in, (u8*)&dr_out, dr_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_ir_u32(jtag_tap_t *tap, u32 *ir_in, u32 ir_out, int ir_len, int rti)
+{
+ if (ir_len > 32)
+ {
+ LOG_ERROR("ir_len overflow, maxium is 32");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_ir(tap, (u8*)ir_in, (u8*)&ir_out, ir_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_write_dr_u32(jtag_tap_t *tap, u32 *dr_in, u32 dr_out, int dr_len, int rti)
+{
+ if (dr_len > 32)
+ {
+ LOG_ERROR("dr_len overflow, maxium is 32");
+ return ERROR_FAIL;
+ }
+
+ mcu_write_dr(tap, (u8*)dr_in, (u8*)&dr_out, dr_len, rti);
+
+ return ERROR_OK;
+}
+
+int mcu_execute_queue(void)
+{
+ return jtag_execute_queue();
+}
Added: trunk/src/target/avrt.h
===================================================================
--- trunk/src/target/avrt.h 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/target/avrt.h 2009-04-27 10:32:13 UTC (rev 1540)
@@ -0,0 +1,33 @@
+/***************************************************************************
+ * Copyright (C) 2009 by Simon Qian *
+ * Sim...@Si... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef AVRT_H
+#define AVRT_H
+
+typedef struct mcu_jtag_s
+{
+ jtag_tap_t *tap;
+} mcu_jtag_t;
+
+typedef struct avr_common_s
+{
+ mcu_jtag_t jtag_info;
+} avr_common_t;
+
+#endif /* AVRT_H */
Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c 2009-04-27 10:16:16 UTC (rev 1539)
+++ trunk/src/target/target.c 2009-04-27 10:32:13 UTC (rev 1540)
@@ -105,6 +105,7 @@
extern target_type_t cortexm3_target;
extern target_type_t arm11_target;
extern target_type_t mips_m4k_target;
+extern target_type_t avr_target;
target_type_t *target_types[] =
{
@@ -119,6 +120,7 @@
&cortexm3_target,
&arm11_target,
&mips_m4k_target,
+ &avr_target,
NULL,
};
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 12:16:17
|
Author: oharboe
Date: 2009-04-27 12:16:16 +0200 (Mon, 27 Apr 2009)
New Revision: 1539
Added:
trunk/src/target/target/mega128.cfg
Log:
SimonQian <sim...@si...> AVR support
Added: trunk/src/target/target/mega128.cfg
===================================================================
--- trunk/src/target/target/mega128.cfg 2009-04-27 10:05:15 UTC (rev 1538)
+++ trunk/src/target/target/mega128.cfg 2009-04-27 10:16:16 UTC (rev 1539)
@@ -0,0 +1,42 @@
+# for avr
+
+ set _CHIPNAME avr
+ set _ENDIAN little
+
+# jtag speed
+jtag_khz 4500
+
+reset_config srst_only
+jtag_nsrst_delay 100
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x8970203F
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME avr -endian $_ENDIAN -chain-position $_TARGETNAME
+
+#$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
+
+flash bank avr 0 0 0 0 0
+
+#to use it, script will be like:
+#init
+#jtag_khz 4500
+#reset init
+#verify_ircapture disable
+#
+#halt
+#wait halt
+#poll
+#avr mass_erase 0
+#flash write_image E:/Versaloon/Software/CAMERAPROTOCOLAGENT.hex
+#reset run
+#shutdown
+#
+# For more information about the configuration files, take a look at:
+# openocd.texi
|
|
From: <ml...@ma...> - 2009-04-27 12:05:17
|
Author: mlu
Date: 2009-04-27 12:05:15 +0200 (Mon, 27 Apr 2009)
New Revision: 1538
Removed:
trunk/src/target/cortex_swjdp.c
trunk/src/target/cortex_swjdp.h
Log:
Deleted depreciated files ( new versions are arm_adi_v5.c/h )
Deleted: trunk/src/target/cortex_swjdp.c
===================================================================
--- trunk/src/target/cortex_swjdp.c 2009-04-27 09:12:18 UTC (rev 1537)
+++ trunk/src/target/cortex_swjdp.c 2009-04-27 10:05:15 UTC (rev 1538)
@@ -1,1029 +0,0 @@
-/***************************************************************************
- * Copyright (C) 2006 by Magnus Lundin *
- * lu...@ml... *
- * *
- * Copyright (C) 2008 by Spencer Oliver *
- * sp...@sp... *
- * *
- * Copyright (C) 2009 by Oyvind Harboe *
- * oyv...@zy... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- ***************************************************************************/
-/***************************************************************************
- * *
- * CoreSight (Light?) SerialWireJtagDebugPort *
- * *
- * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
- * Cortex-M3(tm) TRM, ARM DDI 0337C *
- * *
-***************************************************************************/
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "replacements.h"
-
-#include "cortex_m3.h"
-#include "cortex_swjdp.h"
-#include "jtag.h"
-#include "log.h"
-#include "time_support.h"
-#include <stdlib.h>
-
-/*
- * Transaction Mode:
- * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
- * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
- * result checking until swjdp_end_transaction()
- * This must be done before using or deallocating any return variables.
- * swjdp->trans_mode == TRANS_MODE_ATOMIC
- * All reads and writes to the AHB bus are checked for valid completion, and return values
- * are immediatley available.
-*/
-
-/***************************************************************************
- * *
- * DPACC and APACC scanchain access through JTAG-DR *
- * *
-***************************************************************************/
-
-/* Scan out and in from target ordered u8 buffers */
-int swjdp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
-{
- scan_field_t fields[2];
- u8 out_addr_buf;
-
- jtag_add_end_state(TAP_IDLE);
- arm_jtag_set_instr(jtag_info, instr, NULL);
-
- fields[0].tap = jtag_info->tap;
- fields[0].num_bits = 3;
- buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
- fields[0].out_value = &out_addr_buf;
- fields[0].out_mask = NULL;
- fields[0].in_value = ack;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].tap = jtag_info->tap;
- fields[1].num_bits = 32;
- fields[1].out_value = outvalue;
- fields[1].out_mask = NULL;
- fields[1].in_value = invalue;
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
-
- jtag_add_dr_scan(2, fields, TAP_INVALID);
-
- return ERROR_OK;
-}
-
-/* Scan out and in from host ordered u32 variables */
-int swjdp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
-{
- scan_field_t fields[2];
- u8 out_value_buf[4];
- u8 out_addr_buf;
-
- jtag_add_end_state(TAP_IDLE);
- arm_jtag_set_instr(jtag_info, instr, NULL);
-
- fields[0].tap = jtag_info->tap;
- fields[0].num_bits = 3;
- buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
- fields[0].out_value = &out_addr_buf;
- fields[0].out_mask = NULL;
- fields[0].in_value = ack;
- fields[0].in_check_value = NULL;
- fields[0].in_check_mask = NULL;
- fields[0].in_handler = NULL;
- fields[0].in_handler_priv = NULL;
-
- fields[1].tap = jtag_info->tap;
- fields[1].num_bits = 32;
- buf_set_u32(out_value_buf, 0, 32, outvalue);
- fields[1].out_value = out_value_buf;
- fields[1].out_mask = NULL;
- fields[1].in_value = NULL;
- if (invalue)
- {
- fields[1].in_handler = arm_jtag_buf_to_u32;
- fields[1].in_handler_priv = invalue;
- }
- else
- {
- fields[1].in_handler = NULL;
- fields[1].in_handler_priv = NULL;
- }
- fields[1].in_check_value = NULL;
- fields[1].in_check_mask = NULL;
-
- jtag_add_dr_scan(2, fields, TAP_INVALID);
-
- return ERROR_OK;
-}
-
-/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
-int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
-{
- swjdp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
- if ((RnW == DPAP_READ) && (invalue != NULL))
- {
- swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
- }
-
- /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
- if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
- {
- return swjdp_transaction_endcheck(swjdp);
- }
-
- return ERROR_OK;
-}
-
-int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
-{
- swjdp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
- if ((RnW==DPAP_READ) && (invalue != NULL))
- {
- swjdp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
- }
-
- /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
- if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
- {
- return swjdp_transaction_endcheck(swjdp);
- }
-
- return ERROR_OK;
-}
-
-int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
-{
- int retval;
- u32 ctrlstat;
-
- /* too expensive to call keep_alive() here */
-
-#if 0
- /* Danger!!!! BROKEN!!!! */
- scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
- R956 introduced the check on return value here and now Michael Schwingen reports
- that this code no longer works....
-
- https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
- */
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- {
- LOG_ERROR("BUG: Why does this fail the first time????");
- }
- /* Why??? second time it works??? */
-#endif
-
- scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
-
- swjdp->ack = swjdp->ack & 0x7;
-
- if (swjdp->ack != 2)
- {
- long long then=timeval_ms();
- while (swjdp->ack != 2)
- {
- if (swjdp->ack == 1)
- {
- if ((timeval_ms()-then) > 1000)
- {
- LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
- return ERROR_JTAG_DEVICE_ERROR;
- }
- }
- else
- {
- LOG_WARNING("Invalid ACK in SWJDP transaction");
- return ERROR_JTAG_DEVICE_ERROR;
- }
-
- scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
- swjdp->ack = swjdp->ack & 0x7;
- }
- } else
- {
- /* common code path avoids fn to timeval_ms() */
- }
-
- /* Check for STICKYERR and STICKYORUN */
- if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
- {
- LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
- /* Check power to debug regions */
- if ((ctrlstat & 0xf0000000) != 0xf0000000)
- {
- ahbap_debugport_init(swjdp);
- }
- else
- {
- u32 dcb_dhcsr,nvic_shcsr, nvic_bfar, nvic_cfsr;
-
- /* Print information about last AHBAP access */
- LOG_ERROR("AHBAP: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
- if (ctrlstat & SSTICKYORUN)
- LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
-
- if (ctrlstat & SSTICKYERR)
- LOG_ERROR("SWJ-DP STICKY ERROR");
-
- /* Clear Sticky Error Bits */
- scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
- scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
-
- LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
-
- /* Can we find out the reason for the error ?? */
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
- ahbap_read_system_atomic_u32(swjdp, NVIC_SHCSR, &nvic_shcsr);
- ahbap_read_system_atomic_u32(swjdp, NVIC_CFSR, &nvic_cfsr);
- ahbap_read_system_atomic_u32(swjdp, NVIC_BFAR, &nvic_bfar);
- LOG_ERROR("dcb_dhcsr 0x%x, nvic_shcsr 0x%x, nvic_cfsr 0x%x, nvic_bfar 0x%x", dcb_dhcsr, nvic_shcsr, nvic_cfsr, nvic_bfar);
- }
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
- return ERROR_JTAG_DEVICE_ERROR;
- }
-
- return ERROR_OK;
-}
-
-/***************************************************************************
- * *
- * DP and AHB-AP register access through APACC and DPACC *
- * *
-***************************************************************************/
-
-int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
-{
- return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
-}
-
-int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
-{
- return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
-}
-
-int swjdp_bankselect_apacc(swjdp_common_t *swjdp,u32 reg_addr)
-{
- u32 select;
- select = (reg_addr & 0xFF0000F0);
-
- if (select != swjdp->dp_select_value)
- {
- swjdp_write_dpacc(swjdp, select, DP_SELECT);
- swjdp->dp_select_value = select;
- }
-
- return ERROR_OK;
-}
-
-int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
-{
- swjdp_bankselect_apacc(swjdp, reg_addr);
- scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
-
- return ERROR_OK;
-}
-
-int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
-{
- swjdp_bankselect_apacc(swjdp, reg_addr);
- scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
-
- return ERROR_OK;
-}
-int ahbap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
-{
- u8 out_value_buf[4];
-
- buf_set_u32(out_value_buf, 0, 32, value);
- swjdp_bankselect_apacc(swjdp, reg_addr);
- scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
-
- return ERROR_OK;
-}
-
-int ahbap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
-{
- swjdp_bankselect_apacc(swjdp, reg_addr);
- scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
-
- return ERROR_OK;
-}
-
-/***************************************************************************
- * *
- * AHB-AP access to memory and system registers on AHB bus *
- * *
-***************************************************************************/
-
-int ahbap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
-{
- csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
- if (csw != swjdp->ap_csw_value)
- {
- /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
- ahbap_write_reg_u32(swjdp, AHBAP_CSW, csw );
- swjdp->ap_csw_value = csw;
- }
- if (tar != swjdp->ap_tar_value)
- {
- /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
- ahbap_write_reg_u32(swjdp, AHBAP_TAR, tar );
- swjdp->ap_tar_value = tar;
- }
- if (csw & CSW_ADDRINC_MASK)
- {
- /* Do not cache TAR value when autoincrementing */
- swjdp->ap_tar_value = -1;
- }
- return ERROR_OK;
-}
-
-/*****************************************************************************
-* *
-* ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
-* *
-* Read a u32 value from memory or system register *
-* Functionally equivalent to target_read_u32(target, address, u32 *value), *
-* but with less overhead *
-*****************************************************************************/
-int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
-{
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
- ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
-
- return ERROR_OK;
-}
-
-int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
-{
- ahbap_read_system_u32(swjdp, address, value);
-
- return swjdp_transaction_endcheck(swjdp);
-}
-
-/*****************************************************************************
-* *
-* ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
-* *
-* Write a u32 value to memory or system register *
-* *
-*****************************************************************************/
-int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value)
-{
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
- ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (address & 0xC), value );
-
- return ERROR_OK;
-}
-
-int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
-{
- ahbap_write_system_u32(swjdp, address, value);
-
- return swjdp_transaction_endcheck(swjdp);
-}
-
-/*****************************************************************************
-* *
-* ahbap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
-* *
-* Write a buffer in target order (little endian) *
-* *
-*****************************************************************************/
-int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 outvalue;
- int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
- u32 adr = address;
- u8* pBuffer = buffer;
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- count >>= 2;
- wcount = count;
-
- /* if we have an unaligned access - reorder data */
- if (adr & 0x3u)
- {
- for (writecount = 0; writecount < count; writecount++)
- {
- int i;
- outvalue = *((u32*)pBuffer);
-
- for (i = 0; i < 4; i++ )
- {
- *((u8*)pBuffer + (adr & 0x3)) = outvalue;
- outvalue >>= 8;
- adr++;
- }
- pBuffer += 4;
- }
- }
-
- while (wcount > 0)
- {
- /* Adjust to write blocks within 4K aligned boundaries */
- blocksize = (0x1000 - (0xFFF & address)) >> 2;
- if (wcount < blocksize)
- blocksize = wcount;
-
- /* handle unaligned data at 4k boundary */
- if (blocksize == 0)
- blocksize = 1;
-
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
-
- for (writecount = 0; writecount < blocksize; writecount++)
- {
- ahbap_write_reg(swjdp, AHBAP_DRW, buffer + 4 * writecount );
- }
-
- if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
- {
- wcount = wcount - blocksize;
- address = address + 4 * blocksize;
- buffer = buffer + 4 * blocksize;
- }
- else
- {
- errorcount++;
- }
-
- if (errorcount > 1)
- {
- LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
- return ERROR_JTAG_DEVICE_ERROR;
- }
- }
-
- return retval;
-}
-
-int ahbap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 outvalue;
- int retval = ERROR_OK;
- int wcount, blocksize, writecount, i;
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- wcount = count >> 1;
-
- while (wcount > 0)
- {
- int nbytes;
-
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address)) >> 1;
-
- if (wcount < blocksize)
- blocksize = wcount;
-
- /* handle unaligned data at 4k boundary */
- if (blocksize == 0)
- blocksize = 1;
-
- ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
- writecount = blocksize;
-
- do
- {
- nbytes = MIN((writecount << 1), 4);
-
- if (nbytes < 4 )
- {
- if (ahbap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
-
- address += nbytes >> 1;
- }
- else
- {
- outvalue = *((u32*)buffer);
-
- for (i = 0; i < nbytes; i++ )
- {
- *((u8*)buffer + (address & 0x3)) = outvalue;
- outvalue >>= 8;
- address++;
- }
-
- outvalue = *((u32*)buffer);
- ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
- }
-
- buffer += nbytes >> 1;
- writecount -= nbytes >> 1;
-
- } while (writecount);
- wcount -= blocksize;
- }
-
- return retval;
-}
-
-int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 outvalue;
- int retval = ERROR_OK;
-
- if (count >= 4)
- return ahbap_write_buf_packed_u16(swjdp, buffer, count, address);
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- while (count > 0)
- {
- ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
- outvalue = *((u16*)buffer) << 8 * (address & 0x3);
- ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
- retval = swjdp_transaction_endcheck(swjdp);
- count -= 2;
- address += 2;
- buffer += 2;
- }
-
- return retval;
-}
-
-int ahbap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 outvalue;
- int retval = ERROR_OK;
- int wcount, blocksize, writecount, i;
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- wcount = count;
-
- while (wcount > 0)
- {
- int nbytes;
-
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address));
-
- if (wcount < blocksize)
- blocksize = wcount;
-
- ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
- writecount = blocksize;
-
- do
- {
- nbytes = MIN(writecount, 4);
-
- if (nbytes < 4 )
- {
- if (ahbap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
-
- address += nbytes;
- }
- else
- {
- outvalue = *((u32*)buffer);
-
- for (i = 0; i < nbytes; i++ )
- {
- *((u8*)buffer + (address & 0x3)) = outvalue;
- outvalue >>= 8;
- address++;
- }
-
- outvalue = *((u32*)buffer);
- ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue);
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
- }
-
- buffer += nbytes;
- writecount -= nbytes;
-
- } while (writecount);
- wcount -= blocksize;
- }
-
- return retval;
-}
-
-int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 outvalue;
- int retval = ERROR_OK;
-
- if (count >= 4)
- return ahbap_write_buf_packed_u8(swjdp, buffer, count, address);
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- while (count > 0)
- {
- ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
- outvalue = *((u8*)buffer) << 8 * (address & 0x3);
- ahbap_write_reg_u32(swjdp, AHBAP_DRW, outvalue );
- retval = swjdp_transaction_endcheck(swjdp);
- count--;
- address++;
- buffer++;
- }
-
- return retval;
-}
-
-/*********************************************************************************
-* *
-* ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
-* *
-* Read block fast in target order (little endian) into a buffer *
-* *
-**********************************************************************************/
-int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
- u32 adr = address;
- u8* pBuffer = buffer;
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- count >>= 2;
- wcount = count;
-
- while (wcount > 0)
- {
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address)) >> 2;
- if (wcount < blocksize)
- blocksize = wcount;
-
- /* handle unaligned data at 4k boundary */
- if (blocksize == 0)
- blocksize = 1;
-
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
-
- /* Scan out first read */
- swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, NULL, NULL);
- for (readcount = 0; readcount < blocksize - 1; readcount++)
- {
- /* Scan out read instruction and scan in previous value */
- swjdp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AHBAP_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
- }
-
- /* Scan in last value */
- swjdp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
- if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
- {
- wcount = wcount - blocksize;
- address += 4 * blocksize;
- buffer += 4 * blocksize;
- }
- else
- {
- errorcount++;
- }
-
- if (errorcount > 1)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
- }
-
- /* if we have an unaligned access - reorder data */
- if (adr & 0x3u)
- {
- for (readcount = 0; readcount < count; readcount++)
- {
- int i;
- u32 data = *((u32*)pBuffer);
-
- for (i = 0; i < 4; i++ )
- {
- *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
- pBuffer++;
- adr++;
- }
- }
- }
-
- return retval;
-}
-
-int ahbap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 invalue;
- int retval = ERROR_OK;
- int wcount, blocksize, readcount, i;
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- wcount = count >> 1;
-
- while (wcount > 0)
- {
- int nbytes;
-
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address)) >> 1;
- if (wcount < blocksize)
- blocksize = wcount;
-
- ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
-
- /* handle unaligned data at 4k boundary */
- if (blocksize == 0)
- blocksize = 1;
- readcount = blocksize;
-
- do
- {
- ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
-
- nbytes = MIN((readcount << 1), 4);
-
- for (i = 0; i < nbytes; i++ )
- {
- *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
- buffer++;
- address++;
- }
-
- readcount -= (nbytes >> 1);
- } while (readcount);
- wcount -= blocksize;
- }
-
- return retval;
-}
-
-int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 invalue, i;
- int retval = ERROR_OK;
-
- if (count >= 4)
- return ahbap_read_buf_packed_u16(swjdp, buffer, count, address);
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- while (count > 0)
- {
- ahbap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
- ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
- retval = swjdp_transaction_endcheck(swjdp);
- if (address & 0x1)
- {
- for (i = 0; i < 2; i++ )
- {
- *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
- buffer++;
- address++;
- }
- }
- else
- {
- *((u16*)buffer) = (invalue >> 8 * (address & 0x3));
- address += 2;
- buffer += 2;
- }
- count -= 2;
- }
-
- return retval;
-}
-
-int ahbap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 invalue;
- int retval = ERROR_OK;
- int wcount, blocksize, readcount, i;
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- wcount = count;
-
- while (wcount > 0)
- {
- int nbytes;
-
- /* Adjust to read within 4K block boundaries */
- blocksize = (0x1000 - (0xFFF & address));
-
- if (wcount < blocksize)
- blocksize = wcount;
-
- ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
- readcount = blocksize;
-
- do
- {
- ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
- if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
- {
- LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
- return ERROR_JTAG_DEVICE_ERROR;
- }
-
- nbytes = MIN(readcount, 4);
-
- for (i = 0; i < nbytes; i++ )
- {
- *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
- buffer++;
- address++;
- }
-
- readcount -= nbytes;
- } while (readcount);
- wcount -= blocksize;
- }
-
- return retval;
-}
-
-int ahbap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
-{
- u32 invalue;
- int retval = ERROR_OK;
-
- if (count >= 4)
- return ahbap_read_buf_packed_u8(swjdp, buffer, count, address);
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- while (count > 0)
- {
- ahbap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
- ahbap_read_reg_u32(swjdp, AHBAP_DRW, &invalue );
- retval = swjdp_transaction_endcheck(swjdp);
- *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
- count--;
- address++;
- buffer++;
- }
-
- return retval;
-}
-
-int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
-{
- int retval;
- u32 dcrdr;
-
- /* because the DCB_DCRDR is used for the emulated dcc channel
- * we gave to save/restore the DCB_DCRDR when used */
-
- ahbap_read_system_u32(swjdp, DCB_DCRDR, &dcrdr);
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- /* ahbap_write_system_u32(swjdp, DCB_DCRSR, regnum); */
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
- ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum );
-
- /* ahbap_read_system_u32(swjdp, DCB_DCRDR, value); */
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
- ahbap_read_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
-
- ahbap_write_system_u32(swjdp, DCB_DCRDR, dcrdr);
- retval = swjdp_transaction_endcheck(swjdp);
- return retval;
-}
-
-int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
-{
- int retval;
- u32 dcrdr;
-
- /* because the DCB_DCRDR is used for the emulated dcc channel
- * we gave to save/restore the DCB_DCRDR when used */
-
- ahbap_read_system_u32(swjdp, DCB_DCRDR, &dcrdr);
-
- swjdp->trans_mode = TRANS_MODE_COMPOSITE;
-
- /* ahbap_write_system_u32(swjdp, DCB_DCRDR, core_regs[i]); */
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
- ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRDR & 0xC), value );
-
- /* ahbap_write_system_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
- ahbap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
- ahbap_write_reg_u32(swjdp, AHBAP_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
-
- ahbap_write_system_u32(swjdp, DCB_DCRDR, dcrdr);
- retval = swjdp_transaction_endcheck(swjdp);
- return retval;
-}
-
-int ahbap_debugport_init(swjdp_common_t *swjdp)
-{
- u32 idreg, romaddr, dummy;
- u32 ctrlstat;
- int cnt = 0;
- int retval;
-
- LOG_DEBUG(" ");
-
- swjdp->ap_csw_value = -1;
- swjdp->ap_tar_value = -1;
- swjdp->trans_mode = TRANS_MODE_ATOMIC;
- swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
- swjdp_write_dpacc(swjdp, SSTICKYERR, DP_CTRL_STAT);
- swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
-
- swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
-
- swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
- swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
-
- /* Check that we have debug power domains activated */
- while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
- {
- LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
- swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
- alive_sleep(10);
- }
-
- while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
- {
- LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
- swjdp_read_dpacc(swjdp, &ctrlstat, DP_CTRL_STAT);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
- alive_sleep(10);
- }
-
- swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
- /* With debug power on we can activate OVERRUN checking */
- swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
- swjdp_write_dpacc(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
- swjdp_read_dpacc(swjdp, &dummy, DP_CTRL_STAT);
-
- ahbap_read_reg_u32(swjdp, 0xFC, &idreg);
- ahbap_read_reg_u32(swjdp, 0xF8, &romaddr);
-
- LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
-
- return ERROR_OK;
-}
Deleted: trunk/src/target/cortex_swjdp.h
===================================================================
--- trunk/src/target/cortex_swjdp.h 2009-04-27 09:12:18 UTC (rev 1537)
+++ trunk/src/target/cortex_swjdp.h 2009-04-27 10:05:15 UTC (rev 1538)
@@ -1,133 +0,0 @@
-/***************************************************************************
- * Copyright (C) 2006 by Magnus Lundin *
- * lu...@ml... *
- * *
- * Copyright (C) 2008 by Spencer Oliver *
- * sp...@sp... *
- * *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- ***************************************************************************/
-#ifndef CORTEX_SWJDP_H
-#define CORTEX_SWJDP_H
-
-#include "target.h"
-#include "register.h"
-#include "arm_jtag.h"
-
-#define SWJDP_IR_DPACC 0xA
-#define SWJDP_IR_APACC 0xB
-
-#define DPAP_WRITE 0
-#define DPAP_READ 1
-#define DP_ZERO 0
-#define DP_CTRL_STAT 0x4
-#define DP_SELECT 0x8
-#define DP_RDBUFF 0xC
-
-#define CORUNDETECT (1<<0)
-#define SSTICKYORUN (1<<1)
-#define SSTICKYERR (1<<5)
-#define CDBGRSTREQ (1<<26)
-#define CDBGRSTACK (1<<27)
-#define CDBGPWRUPREQ (1<<28)
-#define CDBGPWRUPACK (1<<29)
-#define CSYSPWRUPREQ (1<<30)
-#define CSYSPWRUPACK (1<<31)
-
-#define AHBAP_CSW 0x00
-#define AHBAP_TAR 0x04
-#define AHBAP_DRW 0x0C
-#define AHBAP_BD0 0x10
-#define AHBAP_BD1 0x14
-#define AHBAP_BD2 0x18
-#define AHBAP_BD3 0x1C
-#define AHBAP_DBGROMA 0xF8
-#define AHBAP_IDR 0xFC
-
-#define CSW_8BIT 0
-#define CSW_16BIT 1
-#define CSW_32BIT 2
-
-#define CSW_ADDRINC_MASK (3<<4)
-#define CSW_ADDRINC_OFF 0
-#define CSW_ADDRINC_SINGLE (1<<4)
-#define CSW_ADDRINC_PACKED (2<<4)
-#define CSW_HPROT (1<<25)
-#define CSW_MASTER_DEBUG (1<<29)
-#define CSW_DBGSWENABLE (1<<31)
-
-/* transaction mode */
-#define TRANS_MODE_NONE 0
-/* Transaction waits for previous to complete */
-#define TRANS_MODE_ATOMIC 1
-/* Freerunning transactions with delays and overrun checking */
-#define TRANS_MODE_COMPOSITE 2
-
-typedef struct swjdp_reg_s
-{
- int addr;
- arm_jtag_t *jtag_info;
-} swjdp_reg_t;
-
-typedef struct swjdp_common_s
-{
- arm_jtag_t *jtag_info;
- /* Control config */
- u32 dp_ctrl_stat;
- /* Register select cache */
- u32 dp_select_value;
- u32 ap_csw_value;
- u32 ap_tar_value;
- /* information about current pending SWjDP-AHBAP transaction */
- u8 trans_mode;
- u8 trans_rw;
- u8 ack;
-} swjdp_common_t;
-
-/* Internal functions used in the module, partial transactions, use with caution */
-extern int swjdp_write_dpacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
-/* extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr); */
-extern int swjdp_read_dpacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
-/* extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr); */
-extern int ahbap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf);
-extern int ahbap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf);
-
-/* External interface, partial operations must be completed with swjdp_transaction_endcheck() */
-extern int ahbap_read_system_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
-extern int ahbap_write_system_u32(swjdp_common_t *swjdp, u32 address, u32 value);
-extern int swjdp_transaction_endcheck(swjdp_common_t *swjdp);
-
-/* External interface, complete atomic operations */
-/* Host endian word transfer of single memory and system registers */
-extern int ahbap_read_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
-extern int ahbap_write_system_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value);
-
-/* Host endian word transfers of processor core registers */
-extern int ahbap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum);
-extern int ahbap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum);
-
-extern int ahbap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int ahbap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int ahbap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-
-extern int ahbap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int ahbap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-extern int ahbap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
-
-/* Initialisation of the debug system, power domains and registers */
-extern int ahbap_debugport_init(swjdp_common_t *swjdp);
-
-#endif
|
|
From: oharboe at B. <oh...@ma...> - 2009-04-27 11:12:21
|
Author: oharboe
Date: 2009-04-27 11:12:18 +0200 (Mon, 27 Apr 2009)
New Revision: 1537
Modified:
trunk/src/jtag/jtag.c
Log:
Some devices such as AVR will return 0xffffffff instead of the TDI
data at the end of the chain. Added kludge to handle this.
Modified: trunk/src/jtag/jtag.c
===================================================================
--- trunk/src/jtag/jtag.c 2009-04-27 08:29:28 UTC (rev 1536)
+++ trunk/src/jtag/jtag.c 2009-04-27 09:12:18 UTC (rev 1537)
@@ -1531,7 +1531,9 @@
u32 part;
u32 version;
- if (idcode == 0x000000FF)
+ /* some devices, such as AVR will output all 1's instead of TDI
+ input value at end of chain. */
+ if ((idcode == 0x000000FF)||(idcode == 0xFFFFFFFF))
{
int unexpected=0;
/* End of chain (invalid manufacturer ID)
@@ -1548,7 +1550,7 @@
for (bit_count += 32; bit_count < (JTAG_MAX_CHAIN_SIZE * 32) - 31;bit_count += 32)
{
idcode = buf_get_u32(idcode_buffer, bit_count, 32);
- if (unexpected||(idcode != 0x000000FF))
+ if (unexpected||((idcode != 0x000000FF)&&(idcode != 0xFFFFFFFF)))
{
LOG_WARNING("Unexpected idcode after end of chain! %d 0x%08x", bit_count, idcode);
unexpected = 1;
@@ -3306,7 +3308,7 @@
tap_state_t last_state;
- // set startstate (and possibly last, if tap_bits == 0)
+ // set startstate (and possibly last, if tap_bits == 0)
last_state = next_state;
DEBUG_JTAG_IO("TAP/SM: START state: %s", tap_state_name(next_state));
|
|
From: <ml...@ma...> - 2009-04-27 10:29:30
|
Author: mlu
Date: 2009-04-27 10:29:28 +0200 (Mon, 27 Apr 2009)
New Revision: 1536
Modified:
trunk/src/target/Makefile.am
trunk/src/target/armv7m.c
trunk/src/target/armv7m.h
trunk/src/target/cortex_m3.c
trunk/src/target/cortex_m3.h
Log:
Changed armv7m and cortexm3 to use nev arm_adi_v5 instead of cortex_swjdp.
Added support for accessport ROM table identification, dap command.
Modified: trunk/src/target/Makefile.am
===================================================================
--- trunk/src/target/Makefile.am 2009-04-27 08:21:35 UTC (rev 1535)
+++ trunk/src/target/Makefile.am 2009-04-27 08:29:28 UTC (rev 1536)
@@ -11,12 +11,12 @@
noinst_LIBRARIES = libtarget.a
libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c etm.c arm7tdmi.c arm9tdmi.c \
arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
- arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c cortex_swjdp.c \
+ arm966e.c arm926ejs.c feroceon.c etb.c xscale.c arm_simulator.c image.c armv7m.c cortex_m3.c arm_adi_v5.c \
etm_dummy.c $(OOCD_TRACE_FILES) target_request.c trace.c arm11.c arm11_dbgtap.c mips32.c mips_m4k.c \
mips32_pracc.c mips32_dmaacc.c mips_ejtag.c
noinst_HEADERS = target.h trace.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
- arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h cortex_swjdp.h \
+ arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h image.h armv7m.h cortex_m3.h arm_adi_v5.h \
etm_dummy.h oocd_trace.h target_request.h trace.h arm11.h mips32.h mips_m4k.h mips_ejtag.h mips32_pracc.h mips32_dmaacc.h
nobase_dist_pkglib_DATA =
Modified: trunk/src/target/armv7m.c
===================================================================
--- trunk/src/target/armv7m.c 2009-04-27 08:21:35 UTC (rev 1535)
+++ trunk/src/target/armv7m.c 2009-04-27 08:29:28 UTC (rev 1536)
@@ -550,6 +550,12 @@
int armv7m_register_commands(struct command_context_s *cmd_ctx)
{
+ command_t *arm_adi_v5_dap_cmd;
+
+ arm_adi_v5_dap_cmd = register_command(cmd_ctx, NULL, "dap", NULL, COMMAND_ANY, "cortex dap specific commands");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "info", handle_dap_info_command, COMMAND_EXEC, "dap info for ap [num] (default 0)");
+ register_command(cmd_ctx, arm_adi_v5_dap_cmd, "apsel", handle_dap_apsel_command, COMMAND_EXEC, "select a different AP [num] (default 0)");
+
return ERROR_OK;
}
@@ -695,3 +701,45 @@
return ERROR_OK;
}
+
+int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ u32 apsel, apid;
+ int retval;
+
+ apsel = 0;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+
+ dap_ap_select(swjdp, apsel);
+ dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
+ retval = swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8x", apsel, apid);
+
+ return retval;
+}
+
+int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
+{
+ target_t *target = get_current_target(cmd_ctx);
+ armv7m_common_t *armv7m = target->arch_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
+ int retval;
+ u32 apsel;
+
+ apsel = 0;
+ if (argc > 0)
+ {
+ apsel = strtoul(args[0], NULL, 0);
+ }
+
+ retval = dap_info_command(cmd_ctx, swjdp, apsel);
+
+ return retval;
+}
+
Modified: trunk/src/target/armv7m.h
===================================================================
--- trunk/src/target/armv7m.h 2009-04-27 08:21:35 UTC (rev 1535)
+++ trunk/src/target/armv7m.h 2009-04-27 08:29:28 UTC (rev 1536)
@@ -29,6 +29,7 @@
#include "register.h"
#include "target.h"
#include "arm_jtag.h"
+#include "arm_adi_v5.h"
/* define for enabling armv7 gdb workarounds */
#if 1
@@ -78,6 +79,8 @@
reg_cache_t *core_cache;
enum armv7m_mode core_mode;
int exception_number;
+ swjdp_common_t swjdp_info;
+
/* Direct processor core register read and writes */
int (*load_core_reg_u32)(struct target_s *target, enum armv7m_regtype type, u32 num, u32 *value);
Modified: trunk/src/target/cortex_m3.c
===================================================================
--- trunk/src/target/cortex_m3.c 2009-04-27 08:21:35 UTC (rev 1535)
+++ trunk/src/target/cortex_m3.c 2009-04-27 08:29:28 UTC (rev 1536)
@@ -22,6 +22,10 @@
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * *
+ * *
+ * Cortex-M3(tm) TRM, ARM DDI 0337C *
+ * *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
@@ -101,19 +105,70 @@
.quit = cortex_m3_quit
};
+int cortexm3_dap_read_coreregister_u32(swjdp_common_t *swjdp, u32 *value, int regnum)
+{
+ int retval;
+ u32 dcrdr;
+
+ /* because the DCB_DCRDR is used for the emulated dcc channel
+ * we gave to save/restore the DCB_DCRDR when used */
+
+ mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ /* mem_ap_write_u32(swjdp, DCB_DCRSR, regnum); */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum );
+
+ /* mem_ap_read_u32(swjdp, DCB_DCRDR, value); */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
+
+ mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
+ retval = swjdp_transaction_endcheck(swjdp);
+ return retval;
+}
+
+int cortexm3_dap_write_coreregister_u32(swjdp_common_t *swjdp, u32 value, int regnum)
+{
+ int retval;
+ u32 dcrdr;
+
+ /* because the DCB_DCRDR is used for the emulated dcc channel
+ * we gave to save/restore the DCB_DCRDR when used */
+
+ mem_ap_read_u32(swjdp, DCB_DCRDR, &dcrdr);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ /* mem_ap_write_u32(swjdp, DCB_DCRDR, core_regs[i]); */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRDR & 0xFFFFFFF0);
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRDR & 0xC), value );
+
+ /* mem_ap_write_u32(swjdp, DCB_DCRSR, i | DCRSR_WnR ); */
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, DCB_DCRSR & 0xFFFFFFF0);
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (DCB_DCRSR & 0xC), regnum | DCRSR_WnR );
+
+ mem_ap_write_u32(swjdp, DCB_DCRDR, dcrdr);
+ retval = swjdp_transaction_endcheck(swjdp);
+ return retval;
+}
+
+
int cortex_m3_write_debug_halt_mask(target_t *target, u32 mask_on, u32 mask_off)
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
/* mask off status bits */
cortex_m3->dcb_dhcsr &= ~((0xFFFF << 16) | mask_off);
/* create new register mask */
cortex_m3->dcb_dhcsr |= DBGKEY | C_DEBUGEN | mask_on;
- return ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
+ return mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, cortex_m3->dcb_dhcsr);
}
int cortex_m3_clear_halt(target_t *target)
@@ -121,15 +176,15 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
/* clear step if any */
cortex_m3_write_debug_halt_mask(target, C_HALT, C_STEP);
/* Read Debug Fault Status Register */
- ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+ mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
/* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
- ahbap_write_system_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
+ mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr);
return ERROR_OK;
@@ -140,7 +195,7 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
u32 dhcsr_save;
/* backup dhcsr reg */
@@ -148,8 +203,8 @@
/* mask interrupts if not done already */
if (!(cortex_m3->dcb_dhcsr & C_MASKINTS))
- ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
- ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
+ mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_HALT | C_DEBUGEN);
+ mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_MASKINTS | C_STEP | C_DEBUGEN);
LOG_DEBUG(" ");
/* restore dhcsr reg */
@@ -163,17 +218,16 @@
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
u32 savedram;
int retvalue;
- ahbap_read_system_u32(swjdp, 0x20000000, &savedram);
- ahbap_write_system_u32(swjdp, 0x20000000, opcode);
- ahbap_write_coreregister_u32(swjdp, 0x20000000, 15);
+ mem_ap_read_u32(swjdp, 0x20000000, &savedram);
+ mem_ap_write_u32(swjdp, 0x20000000, opcode);
+ cortexm3_dap_write_coreregister_u32(swjdp, 0x20000000, 15);
cortex_m3_single_step_core(target);
armv7m->core_cache->reg_list[15].dirty = armv7m->core_cache->reg_list[15].valid;
- retvalue = ahbap_write_system_atomic_u32(swjdp, 0x20000000, savedram);
+ retvalue = mem_ap_write_atomic_u32(swjdp, 0x20000000, savedram);
return retvalue;
}
@@ -200,28 +254,28 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
cortex_m3_fp_comparator_t *fp_list = cortex_m3->fp_comparator_list;
cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
- ahbap_read_system_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
LOG_DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr);
/* this regsiter is used for emulated dcc channel */
- ahbap_write_system_u32(swjdp, DCB_DCRDR, 0);
+ mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
/* Enable debug requests */
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
- ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
/* clear any interrupt masking */
cortex_m3_write_debug_halt_mask(target, 0, C_MASKINTS);
/* Enable trace and dwt */
- ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
+ mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
/* Monitor bus faults */
- ahbap_write_system_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
+ mem_ap_write_u32(swjdp, NVIC_SHCSR, SHCSR_BUSFAULTENA);
/* Enable FPB */
target_write_u32(target, FP_CTRL, 3);
@@ -245,7 +299,7 @@
armv7m_invalidate_core_regs(target);
/* make sure we have latest dhcsr flags */
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
return ERROR_OK;
}
@@ -283,36 +337,35 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
- ahbap_read_system_u32(swjdp, NVIC_SHCSR, &shcsr);
+ mem_ap_read_u32(swjdp, NVIC_SHCSR, &shcsr);
switch (armv7m->exception_number)
{
case 2: /* NMI */
break;
case 3: /* Hard Fault */
- ahbap_read_system_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
+ mem_ap_read_atomic_u32(swjdp, NVIC_HFSR, &except_sr);
if (except_sr & 0x40000000)
{
- ahbap_read_system_u32(swjdp, NVIC_CFSR, &cfsr);
+ mem_ap_read_u32(swjdp, NVIC_CFSR, &cfsr);
}
break;
case 4: /* Memory Management */
- ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr);
- ahbap_read_system_u32(swjdp, NVIC_MMFAR, &except_ar);
+ mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ mem_ap_read_u32(swjdp, NVIC_MMFAR, &except_ar);
break;
case 5: /* Bus Fault */
- ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr);
- ahbap_read_system_u32(swjdp, NVIC_BFAR, &except_ar);
+ mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
+ mem_ap_read_u32(swjdp, NVIC_BFAR, &except_ar);
break;
case 6: /* Usage Fault */
- ahbap_read_system_u32(swjdp, NVIC_CFSR, &except_sr);
+ mem_ap_read_u32(swjdp, NVIC_CFSR, &except_sr);
break;
case 11: /* SVCall */
break;
case 12: /* Debug Monitor */
- ahbap_read_system_u32(swjdp, NVIC_DFSR, &except_sr);
+ mem_ap_read_u32(swjdp, NVIC_DFSR, &except_sr);
break;
case 14: /* PendSV */
break;
@@ -337,14 +390,14 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
LOG_DEBUG(" ");
if (armv7m->pre_debug_entry)
armv7m->pre_debug_entry(target);
cortex_m3_clear_halt(target);
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if ((retval = armv7m->examine_debug_reason(target)) != ERROR_OK)
return retval;
@@ -417,10 +470,10 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
/* Read from Debug Halting Control and Status Register */
- retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (retval != ERROR_OK)
{
target->state = TARGET_UNKNOWN;
@@ -430,7 +483,7 @@
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
{
/* check if still in reset */
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (cortex_m3->dcb_dhcsr & S_RESET_ST)
{
@@ -476,7 +529,7 @@
#if 0
/* Read Debug Fault Status Register, added to figure out the lockup when running flashtest.script */
- ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+ mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
LOG_DEBUG("dcb_dhcsr 0x%x, nvic_dfsr 0x%x, target->state: %s", cortex_m3->dcb_dhcsr, cortex_m3->nvic_dfsr, Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name );
#endif
@@ -530,15 +583,15 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
u32 dcb_dhcsr = 0;
int retval, timeout = 0;
/* Enter debug state on reset, cf. end_reset_event() */
- ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
/* Request a reset */
- ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
+ mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_VECTRESET);
target->state = TARGET_RESET;
/* registers are now invalid */
@@ -546,10 +599,10 @@
while (timeout < 100)
{
- retval = ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
+ retval = mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &dcb_dhcsr);
if (retval == ERROR_OK)
{
- ahbap_read_system_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
+ mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
{
LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr);
@@ -657,7 +710,7 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
breakpoint_t *breakpoint = NULL;
if (target->state != TARGET_HALTED)
@@ -683,7 +736,7 @@
/* set step and clear halt */
cortex_m3_write_debug_halt_mask(target, C_STEP, C_HALT);
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
/* registers are now invalid */
armv7m_invalidate_core_regs(target);
@@ -704,7 +757,7 @@
{
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
int assert_srst = 1;
LOG_DEBUG("target->state: %s",
@@ -717,17 +770,17 @@
}
/* Enable debug requests */
- ahbap_read_system_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
+ mem_ap_read_atomic_u32(swjdp, DCB_DHCSR, &cortex_m3->dcb_dhcsr);
if (!(cortex_m3->dcb_dhcsr & C_DEBUGEN))
- ahbap_write_system_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
+ mem_ap_write_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN);
- ahbap_write_system_u32(swjdp, DCB_DCRDR, 0 );
+ mem_ap_write_u32(swjdp, DCB_DCRDR, 0 );
if (!target->reset_halt)
{
/* Set/Clear C_MASKINTS in a separate operation */
if (cortex_m3->dcb_dhcsr & C_MASKINTS)
- ahbap_write_system_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
+ mem_ap_write_atomic_u32(swjdp, DCB_DHCSR, DBGKEY | C_DEBUGEN | C_HALT);
/* clear any debug flags before resuming */
cortex_m3_clear_halt(target);
@@ -736,12 +789,12 @@
cortex_m3_write_debug_halt_mask(target, 0, C_HALT);
/* Enter debug state on reset, cf. end_reset_event() */
- ahbap_write_system_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
+ mem_ap_write_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR);
}
else
{
/* Enter debug state on reset, cf. end_reset_event() */
- ahbap_write_system_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
+ mem_ap_write_atomic_u32(swjdp, DCB_DEMCR, TRCENA | VC_HARDERR | VC_BUSERR | VC_CORERESET);
}
/* following hack is to handle luminary reset
@@ -789,14 +842,14 @@
else
{
/* this causes the luminary device to reset using the watchdog */
- ahbap_write_system_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
+ mem_ap_write_atomic_u32(swjdp, NVIC_AIRCR, AIRCR_VECTKEY | AIRCR_SYSRESETREQ);
LOG_DEBUG("Using Luminary Reset: SYSRESETREQ");
{
/* I do not know why this is necessary, but it fixes strange effects
* (step/resume cause a NMI after reset) on LM3S6918 -- Michael Schwingen */
u32 tmp;
- ahbap_read_system_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
+ mem_ap_read_atomic_u32(swjdp, NVIC_AIRCR, &tmp);
}
}
@@ -1179,13 +1232,12 @@
int retval;
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
{
/* read a normal core register */
- retval = ahbap_read_coreregister_u32(swjdp, value, num);
+ retval = cortexm3_dap_read_coreregister_u32(swjdp, value, num);
if (retval != ERROR_OK)
{
@@ -1197,7 +1249,7 @@
else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
{
/* read other registers */
- ahbap_read_coreregister_u32(swjdp, value, 20);
+ cortexm3_dap_read_coreregister_u32(swjdp, value, 20);
switch (num)
{
@@ -1235,8 +1287,7 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
#ifdef ARMV7_GDB_HACKS
/* If the LR register is being modified, make sure it will put us
@@ -1251,7 +1302,7 @@
if ((type == ARMV7M_REGISTER_CORE_GP) && (num <= ARMV7M_PSP))
{
- retval = ahbap_write_coreregister_u32(swjdp, value, num);
+ retval = cortexm3_dap_write_coreregister_u32(swjdp, value, num);
if (retval != ERROR_OK)
{
LOG_ERROR("JTAG failure %i", retval);
@@ -1264,7 +1315,7 @@
{
/* write other registers */
- ahbap_read_coreregister_u32(swjdp, ®, 20);
+ cortexm3_dap_read_coreregister_u32(swjdp, ®, 20);
switch (num)
{
@@ -1285,7 +1336,7 @@
break;
}
- ahbap_write_coreregister_u32(swjdp, reg, 20);
+ cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
LOG_DEBUG("write special reg %i value 0x%x ", num, value);
}
@@ -1301,8 +1352,7 @@
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
int retval;
/* sanitize arguments */
@@ -1314,13 +1364,13 @@
switch (size)
{
case 4:
- retval = ahbap_read_buf_u32(swjdp, buffer, 4 * count, address);
+ retval = mem_ap_read_buf_u32(swjdp, buffer, 4 * count, address);
break;
case 2:
- retval = ahbap_read_buf_u16(swjdp, buffer, 2 * count, address);
+ retval = mem_ap_read_buf_u16(swjdp, buffer, 2 * count, address);
break;
case 1:
- retval = ahbap_read_buf_u8(swjdp, buffer, count, address);
+ retval = mem_ap_read_buf_u8(swjdp, buffer, count, address);
break;
default:
LOG_ERROR("BUG: we shouldn't get here");
@@ -1334,8 +1384,7 @@
{
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
int retval;
/* sanitize arguments */
@@ -1345,13 +1394,13 @@
switch (size)
{
case 4:
- retval = ahbap_write_buf_u32(swjdp, buffer, 4 * count, address);
+ retval = mem_ap_write_buf_u32(swjdp, buffer, 4 * count, address);
break;
case 2:
- retval = ahbap_write_buf_u16(swjdp, buffer, 2 * count, address);
+ retval = mem_ap_write_buf_u16(swjdp, buffer, 2 * count, address);
break;
case 1:
- retval = ahbap_write_buf_u8(swjdp, buffer, count, address);
+ retval = mem_ap_write_buf_u8(swjdp, buffer, count, address);
break;
default:
LOG_ERROR("BUG: we shouldn't get here");
@@ -1386,7 +1435,7 @@
/* get pointers to arch-specific information */
armv7m_common_t *armv7m = target->arch_info;
cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
if ((retval = ahbap_debugport_init(swjdp)) != ERROR_OK)
return retval;
@@ -1451,7 +1500,7 @@
{
u16 dcrdr;
- ahbap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+ mem_ap_read_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
*ctrl = (u8)dcrdr;
*value = (u8)(dcrdr >> 8);
@@ -1462,7 +1511,7 @@
if (dcrdr & (1 << 0))
{
dcrdr = 0;
- ahbap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
+ mem_ap_write_buf_u16( swjdp, (u8*)&dcrdr, 1, DCB_DCRDR);
}
return ERROR_OK;
@@ -1471,8 +1520,7 @@
int cortex_m3_target_request_data(target_t *target, u32 size, u8 *buffer)
{
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
u8 data;
u8 ctrl;
u32 i;
@@ -1492,8 +1540,7 @@
if (!target->type->examined)
return ERROR_OK;
armv7m_common_t *armv7m = target->arch_info;
- cortex_m3_common_t *cortex_m3 = armv7m->arch_info;
- swjdp_common_t *swjdp = &cortex_m3->swjdp_info;
+ swjdp_common_t *swjdp = &armv7m->swjdp_info;
if (!target->dbg_msg_enabled)
return ERROR_OK;
@@ -1534,10 +1581,10 @@
cortex_m3->jtag_info.tap = tap;
cortex_m3->jtag_info.scann_size = 4;
- cortex_m3->swjdp_info.dp_select_value = -1;
- cortex_m3->swjdp_info.ap_csw_value = -1;
- cortex_m3->swjdp_info.ap_tar_value = -1;
- cortex_m3->swjdp_info.jtag_info = &cortex_m3->jtag_info;
+ armv7m->swjdp_info.dp_select_value = -1;
+ armv7m->swjdp_info.ap_csw_value = -1;
+ armv7m->swjdp_info.ap_tar_value = -1;
+ armv7m->swjdp_info.jtag_info = &cortex_m3->jtag_info;
/* initialize arch-specific breakpoint handling */
Modified: trunk/src/target/cortex_m3.h
===================================================================
--- trunk/src/target/cortex_m3.h 2009-04-27 08:21:35 UTC (rev 1535)
+++ trunk/src/target/cortex_m3.h 2009-04-27 08:29:28 UTC (rev 1536)
@@ -29,7 +29,7 @@
#include "register.h"
#include "target.h"
#include "armv7m.h"
-#include "cortex_swjdp.h"
+//#include "arm_adi_v5.h"
extern char* cortex_m3_state_strings[];
@@ -162,7 +162,7 @@
u32 *intsetenable;
armv7m_common_t armv7m;
- swjdp_common_t swjdp_info;
+// swjdp_common_t swjdp_info;
void *arch_info;
} cortex_m3_common_t;
@@ -188,7 +188,7 @@
int cortex_m3_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
int cortex_m3_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint);
-extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
+//extern int cortex_m3_register_commands(struct command_context_s *cmd_ctx);
extern int cortex_m3_init_arch_info(target_t *target, cortex_m3_common_t *cortex_m3, jtag_tap_t *tap);
#endif /* CORTEX_M3_H */
|
|
From: <ml...@ma...> - 2009-04-27 10:21:38
|
Author: mlu
Date: 2009-04-27 10:21:35 +0200 (Mon, 27 Apr 2009)
New Revision: 1535
Added:
trunk/src/target/arm_adi_v5.c
trunk/src/target/arm_adi_v5.h
Log:
Added arm_adi_v5.c/h, to replace cortex_swjdp.c/h. Better conformance to ARM Debug Interface rev 5 documentation and remoed code specific to the Cortex-M3 targets.
Added: trunk/src/target/arm_adi_v5.c
===================================================================
--- trunk/src/target/arm_adi_v5.c 2009-04-27 05:40:52 UTC (rev 1534)
+++ trunk/src/target/arm_adi_v5.c 2009-04-27 08:21:35 UTC (rev 1535)
@@ -0,0 +1,1121 @@
+/***************************************************************************
+ * Copyright (C) 2006 by Magnus Lundin *
+ * lu...@ml... *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * sp...@sp... *
+ * *
+ * Copyright (C) 2009 by Oyvind Harboe *
+ * oyv...@zy... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+/***************************************************************************
+ * *
+ * This file implements support for the ARM Debug Interface v5 (ADI_V5) *
+ * *
+ * ARM(tm) Debug Interface v5 Architecture Specification ARM IHI 0031A *
+ * *
+ * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316A *
+ * Cortex-M3(tm) TRM, ARM DDI 0337C *
+ * *
+***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "replacements.h"
+
+#include "arm_adi_v5.h"
+#include "jtag.h"
+#include "log.h"
+#include "time_support.h"
+#include <stdlib.h>
+
+/*
+ * Transaction Mode:
+ * swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+ * Uses Overrun checking mode and does not do actual JTAG send/receive or transaction
+ * result checking until swjdp_end_transaction()
+ * This must be done before using or deallocating any return variables.
+ * swjdp->trans_mode == TRANS_MODE_ATOMIC
+ * All reads and writes to the AHB bus are checked for valid completion, and return values
+ * are immediatley available.
+*/
+
+/***************************************************************************
+ * *
+ * DPACC and APACC scanchain access through JTAG-DP *
+ * *
+***************************************************************************/
+
+/* Scan out and in from target ordered u8 buffers */
+int adi_jtag_dp_scan(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue, u8 *ack)
+{
+ scan_field_t fields[2];
+ u8 out_addr_buf;
+
+ jtag_add_end_state(TAP_IDLE);
+ arm_jtag_set_instr(jtag_info, instr, NULL);
+
+ fields[0].tap = jtag_info->tap;
+ fields[0].num_bits = 3;
+ buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
+ fields[0].out_value = &out_addr_buf;
+ fields[0].out_mask = NULL;
+ fields[0].in_value = ack;
+ fields[0].in_check_value = NULL;
+ fields[0].in_check_mask = NULL;
+ fields[0].in_handler = NULL;
+ fields[0].in_handler_priv = NULL;
+
+ fields[1].tap = jtag_info->tap;
+ fields[1].num_bits = 32;
+ fields[1].out_value = outvalue;
+ fields[1].out_mask = NULL;
+ fields[1].in_value = invalue;
+ fields[1].in_handler = NULL;
+ fields[1].in_handler_priv = NULL;
+ fields[1].in_check_value = NULL;
+ fields[1].in_check_mask = NULL;
+
+ jtag_add_dr_scan(2, fields, TAP_INVALID);
+
+ return ERROR_OK;
+}
+
+/* Scan out and in from host ordered u32 variables */
+int adi_jtag_dp_scan_u32(arm_jtag_t *jtag_info, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue, u8 *ack)
+{
+ scan_field_t fields[2];
+ u8 out_value_buf[4];
+ u8 out_addr_buf;
+
+ jtag_add_end_state(TAP_IDLE);
+ arm_jtag_set_instr(jtag_info, instr, NULL);
+
+ fields[0].tap = jtag_info->tap;
+ fields[0].num_bits = 3;
+ buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
+ fields[0].out_value = &out_addr_buf;
+ fields[0].out_mask = NULL;
+ fields[0].in_value = ack;
+ fields[0].in_check_value = NULL;
+ fields[0].in_check_mask = NULL;
+ fields[0].in_handler = NULL;
+ fields[0].in_handler_priv = NULL;
+
+ fields[1].tap = jtag_info->tap;
+ fields[1].num_bits = 32;
+ buf_set_u32(out_value_buf, 0, 32, outvalue);
+ fields[1].out_value = out_value_buf;
+ fields[1].out_mask = NULL;
+ fields[1].in_value = NULL;
+ if (invalue)
+ {
+ fields[1].in_handler = arm_jtag_buf_to_u32;
+ fields[1].in_handler_priv = invalue;
+ }
+ else
+ {
+ fields[1].in_handler = NULL;
+ fields[1].in_handler_priv = NULL;
+ }
+ fields[1].in_check_value = NULL;
+ fields[1].in_check_mask = NULL;
+
+ jtag_add_dr_scan(2, fields, TAP_INVALID);
+
+ return ERROR_OK;
+}
+
+/* scan_inout_check adds one extra inscan for DPAP_READ commands to read variables */
+int scan_inout_check(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u8 *outvalue, u8 *invalue)
+{
+ adi_jtag_dp_scan(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
+ if ((RnW == DPAP_READ) && (invalue != NULL))
+ {
+ adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
+ }
+
+ /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and the check CTRL_STAT */
+ if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
+ {
+ return swjdp_transaction_endcheck(swjdp);
+ }
+
+ return ERROR_OK;
+}
+
+int scan_inout_check_u32(swjdp_common_t *swjdp, u8 instr, u8 reg_addr, u8 RnW, u32 outvalue, u32 *invalue)
+{
+ adi_jtag_dp_scan_u32(swjdp->jtag_info, instr, reg_addr, RnW, outvalue, NULL, NULL);
+ if ((RnW==DPAP_READ) && (invalue != NULL))
+ {
+ adi_jtag_dp_scan_u32(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
+ }
+
+ /* In TRANS_MODE_ATOMIC all SWJDP_IR_APACC transactions wait for ack=OK/FAULT and then check CTRL_STAT */
+ if ((instr == SWJDP_IR_APACC) && (swjdp->trans_mode == TRANS_MODE_ATOMIC))
+ {
+ return swjdp_transaction_endcheck(swjdp);
+ }
+
+ return ERROR_OK;
+}
+
+int swjdp_transaction_endcheck(swjdp_common_t *swjdp)
+{
+ int retval;
+ u32 ctrlstat;
+
+ /* too expensive to call keep_alive() here */
+
+#if 0
+ /* Danger!!!! BROKEN!!!! */
+ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ /* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
+ R956 introduced the check on return value here and now Michael Schwingen reports
+ that this code no longer works....
+
+ https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
+ */
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ {
+ LOG_ERROR("BUG: Why does this fail the first time????");
+ }
+ /* Why??? second time it works??? */
+#endif
+
+ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+
+ swjdp->ack = swjdp->ack & 0x7;
+
+ if (swjdp->ack != 2)
+ {
+ long long then=timeval_ms();
+ while (swjdp->ack != 2)
+ {
+ if (swjdp->ack == 1)
+ {
+ if ((timeval_ms()-then) > 1000)
+ {
+ LOG_WARNING("Timeout (1000ms) waiting for ACK = OK/FAULT in SWJDP transaction");
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ }
+ else
+ {
+ LOG_WARNING("Invalid ACK in SWJDP transaction");
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+ swjdp->ack = swjdp->ack & 0x7;
+ }
+ } else
+ {
+ /* common code path avoids fn to timeval_ms() */
+ }
+
+ /* Check for STICKYERR and STICKYORUN */
+ if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
+ {
+ LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
+ /* Check power to debug regions */
+ if ((ctrlstat & 0xf0000000) != 0xf0000000)
+ {
+ ahbap_debugport_init(swjdp);
+ }
+ else
+ {
+ u32 mem_ap_csw;
+
+ /* Print information about last AHBAP access */
+ LOG_ERROR("AHBAP Cached values: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
+ if (ctrlstat & SSTICKYORUN)
+ LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
+
+ if (ctrlstat & SSTICKYERR)
+ LOG_ERROR("SWJ-DP STICKY ERROR");
+
+ /* Clear Sticky Error Bits */
+ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_WRITE, swjdp->dp_ctrl_stat | SSTICKYORUN | SSTICKYERR, NULL);
+ scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+
+ LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
+
+ dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+ LOG_ERROR("Read MEM_AP_CSW 0x%x", mem_ap_csw);
+
+ }
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ return ERROR_OK;
+}
+
+/***************************************************************************
+ * *
+ * DP and MEM-AP register access through APACC and DPACC *
+ * *
+***************************************************************************/
+
+int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, u8 reg_addr)
+{
+ return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_WRITE, value, NULL);
+}
+
+int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, u8 reg_addr)
+{
+ return scan_inout_check_u32(swjdp, SWJDP_IR_DPACC, reg_addr, DPAP_READ, 0, value);
+}
+
+int dap_ap_select(swjdp_common_t *swjdp,u8 apsel)
+{
+ u32 select;
+ select = (apsel<<24) & 0xFF000000;
+
+ if (select != swjdp->apsel)
+ {
+ swjdp->apsel = select;
+ /* Switchin AP invalidates cached values */
+ swjdp->dp_select_value = -1;
+ swjdp->ap_csw_value = -1;
+ swjdp->ap_tar_value = -1;
+ }
+
+ return ERROR_OK;
+}
+
+int dap_dp_bankselect(swjdp_common_t *swjdp,u32 ap_reg)
+{
+ u32 select;
+ select = (ap_reg & 0x000000F0);
+
+ if (select != swjdp->dp_select_value)
+ {
+ dap_dp_write_reg(swjdp, select | swjdp->apsel, DP_SELECT);
+ swjdp->dp_select_value = select;
+ }
+
+ return ERROR_OK;
+}
+
+int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf)
+{
+ dap_dp_bankselect(swjdp, reg_addr);
+ scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
+
+ return ERROR_OK;
+}
+
+int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf)
+{
+ dap_dp_bankselect(swjdp, reg_addr);
+ scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, in_value_buf);
+
+ return ERROR_OK;
+}
+int dap_ap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value)
+{
+ u8 out_value_buf[4];
+
+ buf_set_u32(out_value_buf, 0, 32, value);
+ dap_dp_bankselect(swjdp, reg_addr);
+ scan_inout_check(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_WRITE, out_value_buf, NULL);
+
+ return ERROR_OK;
+}
+
+int dap_ap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value)
+{
+ dap_dp_bankselect(swjdp, reg_addr);
+ scan_inout_check_u32(swjdp, SWJDP_IR_APACC, reg_addr, DPAP_READ, 0, value);
+
+ return ERROR_OK;
+}
+
+/***************************************************************************
+ * *
+ * AHB-AP access to memory and system registers on AHB bus *
+ * *
+***************************************************************************/
+
+int dap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar)
+{
+ csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
+ if (csw != swjdp->ap_csw_value)
+ {
+ /* LOG_DEBUG("swjdp : Set CSW %x",csw); */
+ dap_ap_write_reg_u32(swjdp, AP_REG_CSW, csw );
+ swjdp->ap_csw_value = csw;
+ }
+ if (tar != swjdp->ap_tar_value)
+ {
+ /* LOG_DEBUG("swjdp : Set TAR %x",tar); */
+ dap_ap_write_reg_u32(swjdp, AP_REG_TAR, tar );
+ swjdp->ap_tar_value = tar;
+ }
+ if (csw & CSW_ADDRINC_MASK)
+ {
+ /* Do not cache TAR value when autoincrementing */
+ swjdp->ap_tar_value = -1;
+ }
+ return ERROR_OK;
+}
+
+/*****************************************************************************
+* *
+* mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value) *
+* *
+* Read a u32 value from memory or system register *
+* Functionally equivalent to target_read_u32(target, address, u32 *value), *
+* but with less overhead *
+*****************************************************************************/
+int mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
+{
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
+ dap_ap_read_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
+
+ return ERROR_OK;
+}
+
+int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value)
+{
+ mem_ap_read_u32(swjdp, address, value);
+
+ return swjdp_transaction_endcheck(swjdp);
+}
+
+/*****************************************************************************
+* *
+* mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value) *
+* *
+* Write a u32 value to memory or memory mapped register *
+* *
+*****************************************************************************/
+int mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value)
+{
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF, address & 0xFFFFFFF0);
+ dap_ap_write_reg_u32(swjdp, AP_REG_BD0 | (address & 0xC), value );
+
+ return ERROR_OK;
+}
+
+int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value)
+{
+ mem_ap_write_u32(swjdp, address, value);
+
+ return swjdp_transaction_endcheck(swjdp);
+}
+
+/*****************************************************************************
+* *
+* mem_ap_write_buf(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
+* *
+* Write a buffer in target order (little endian) *
+* *
+*****************************************************************************/
+int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 outvalue;
+ int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
+ u32 adr = address;
+ u8* pBuffer = buffer;
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ count >>= 2;
+ wcount = count;
+
+ /* if we have an unaligned access - reorder data */
+ if (adr & 0x3u)
+ {
+ for (writecount = 0; writecount < count; writecount++)
+ {
+ int i;
+ outvalue = *((u32*)pBuffer);
+
+ for (i = 0; i < 4; i++ )
+ {
+ *((u8*)pBuffer + (adr & 0x3)) = outvalue;
+ outvalue >>= 8;
+ adr++;
+ }
+ pBuffer += 4;
+ }
+ }
+
+ while (wcount > 0)
+ {
+ /* Adjust to write blocks within 4K aligned boundaries */
+ blocksize = (0x1000 - (0xFFF & address)) >> 2;
+ if (wcount < blocksize)
+ blocksize = wcount;
+
+ /* handle unaligned data at 4k boundary */
+ if (blocksize == 0)
+ blocksize = 1;
+
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+
+ for (writecount = 0; writecount < blocksize; writecount++)
+ {
+ dap_ap_write_reg(swjdp, AP_REG_DRW, buffer + 4 * writecount );
+ }
+
+ if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
+ {
+ wcount = wcount - blocksize;
+ address = address + 4 * blocksize;
+ buffer = buffer + 4 * blocksize;
+ }
+ else
+ {
+ errorcount++;
+ }
+
+ if (errorcount > 1)
+ {
+ LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ }
+
+ return retval;
+}
+
+int mem_ap_write_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 outvalue;
+ int retval = ERROR_OK;
+ int wcount, blocksize, writecount, i;
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ wcount = count >> 1;
+
+ while (wcount > 0)
+ {
+ int nbytes;
+
+ /* Adjust to read within 4K block boundaries */
+ blocksize = (0x1000 - (0xFFF & address)) >> 1;
+
+ if (wcount < blocksize)
+ blocksize = wcount;
+
+ /* handle unaligned data at 4k boundary */
+ if (blocksize == 0)
+ blocksize = 1;
+
+ dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+ writecount = blocksize;
+
+ do
+ {
+ nbytes = MIN((writecount << 1), 4);
+
+ if (nbytes < 4 )
+ {
+ if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ address += nbytes >> 1;
+ }
+ else
+ {
+ outvalue = *((u32*)buffer);
+
+ for (i = 0; i < nbytes; i++ )
+ {
+ *((u8*)buffer + (address & 0x3)) = outvalue;
+ outvalue >>= 8;
+ address++;
+ }
+
+ outvalue = *((u32*)buffer);
+ dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
+ if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ }
+
+ buffer += nbytes >> 1;
+ writecount -= nbytes >> 1;
+
+ } while (writecount);
+ wcount -= blocksize;
+ }
+
+ return retval;
+}
+
+int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 outvalue;
+ int retval = ERROR_OK;
+
+ if (count >= 4)
+ return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ while (count > 0)
+ {
+ dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ outvalue = *((u16*)buffer) << 8 * (address & 0x3);
+ dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
+ retval = swjdp_transaction_endcheck(swjdp);
+ count -= 2;
+ address += 2;
+ buffer += 2;
+ }
+
+ return retval;
+}
+
+int mem_ap_write_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 outvalue;
+ int retval = ERROR_OK;
+ int wcount, blocksize, writecount, i;
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ wcount = count;
+
+ while (wcount > 0)
+ {
+ int nbytes;
+
+ /* Adjust to read within 4K block boundaries */
+ blocksize = (0x1000 - (0xFFF & address));
+
+ if (wcount < blocksize)
+ blocksize = wcount;
+
+ dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ writecount = blocksize;
+
+ do
+ {
+ nbytes = MIN(writecount, 4);
+
+ if (nbytes < 4 )
+ {
+ if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ address += nbytes;
+ }
+ else
+ {
+ outvalue = *((u32*)buffer);
+
+ for (i = 0; i < nbytes; i++ )
+ {
+ *((u8*)buffer + (address & 0x3)) = outvalue;
+ outvalue >>= 8;
+ address++;
+ }
+
+ outvalue = *((u32*)buffer);
+ dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
+ if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ }
+
+ buffer += nbytes;
+ writecount -= nbytes;
+
+ } while (writecount);
+ wcount -= blocksize;
+ }
+
+ return retval;
+}
+
+int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 outvalue;
+ int retval = ERROR_OK;
+
+ if (count >= 4)
+ return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ while (count > 0)
+ {
+ dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ outvalue = *((u8*)buffer) << 8 * (address & 0x3);
+ dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue );
+ retval = swjdp_transaction_endcheck(swjdp);
+ count--;
+ address++;
+ buffer++;
+ }
+
+ return retval;
+}
+
+/*********************************************************************************
+* *
+* mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address) *
+* *
+* Read block fast in target order (little endian) into a buffer *
+* *
+**********************************************************************************/
+int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
+ u32 adr = address;
+ u8* pBuffer = buffer;
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ count >>= 2;
+ wcount = count;
+
+ while (wcount > 0)
+ {
+ /* Adjust to read within 4K block boundaries */
+ blocksize = (0x1000 - (0xFFF & address)) >> 2;
+ if (wcount < blocksize)
+ blocksize = wcount;
+
+ /* handle unaligned data at 4k boundary */
+ if (blocksize == 0)
+ blocksize = 1;
+
+ dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+
+ /* Scan out first read */
+ adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, NULL, NULL);
+ for (readcount = 0; readcount < blocksize - 1; readcount++)
+ {
+ /* Scan out read instruction and scan in previous value */
+ adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_APACC, AP_REG_DRW, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
+ }
+
+ /* Scan in last value */
+ adi_jtag_dp_scan(swjdp->jtag_info, SWJDP_IR_DPACC, DP_RDBUFF, DPAP_READ, 0, buffer + 4 * readcount, &swjdp->ack);
+ if (swjdp_transaction_endcheck(swjdp) == ERROR_OK)
+ {
+ wcount = wcount - blocksize;
+ address += 4 * blocksize;
+ buffer += 4 * blocksize;
+ }
+ else
+ {
+ errorcount++;
+ }
+
+ if (errorcount > 1)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+ }
+
+ /* if we have an unaligned access - reorder data */
+ if (adr & 0x3u)
+ {
+ for (readcount = 0; readcount < count; readcount++)
+ {
+ int i;
+ u32 data = *((u32*)pBuffer);
+
+ for (i = 0; i < 4; i++ )
+ {
+ *((u8*)pBuffer) = (data >> 8 * (adr & 0x3));
+ pBuffer++;
+ adr++;
+ }
+ }
+ }
+
+ return retval;
+}
+
+int mem_ap_read_buf_packed_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 invalue;
+ int retval = ERROR_OK;
+ int wcount, blocksize, readcount, i;
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ wcount = count >> 1;
+
+ while (wcount > 0)
+ {
+ int nbytes;
+
+ /* Adjust to read within 4K block boundaries */
+ blocksize = (0x1000 - (0xFFF & address)) >> 1;
+ if (wcount < blocksize)
+ blocksize = wcount;
+
+ dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+
+ /* handle unaligned data at 4k boundary */
+ if (blocksize == 0)
+ blocksize = 1;
+ readcount = blocksize;
+
+ do
+ {
+ dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
+ if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ nbytes = MIN((readcount << 1), 4);
+
+ for (i = 0; i < nbytes; i++ )
+ {
+ *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
+ buffer++;
+ address++;
+ }
+
+ readcount -= (nbytes >> 1);
+ } while (readcount);
+ wcount -= blocksize;
+ }
+
+ return retval;
+}
+
+int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 invalue, i;
+ int retval = ERROR_OK;
+
+ if (count >= 4)
+ return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ while (count > 0)
+ {
+ dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+ dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
+ retval = swjdp_transaction_endcheck(swjdp);
+ if (address & 0x1)
+ {
+ for (i = 0; i < 2; i++ )
+ {
+ *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
+ buffer++;
+ address++;
+ }
+ }
+ else
+ {
+ *((u16*)buffer) = (invalue >> 8 * (address & 0x3));
+ address += 2;
+ buffer += 2;
+ }
+ count -= 2;
+ }
+
+ return retval;
+}
+
+int mem_ap_read_buf_packed_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 invalue;
+ int retval = ERROR_OK;
+ int wcount, blocksize, readcount, i;
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ wcount = count;
+
+ while (wcount > 0)
+ {
+ int nbytes;
+
+ /* Adjust to read within 4K block boundaries */
+ blocksize = (0x1000 - (0xFFF & address));
+
+ if (wcount < blocksize)
+ blocksize = wcount;
+
+ dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+ readcount = blocksize;
+
+ do
+ {
+ dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
+ if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
+ {
+ LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+ return ERROR_JTAG_DEVICE_ERROR;
+ }
+
+ nbytes = MIN(readcount, 4);
+
+ for (i = 0; i < nbytes; i++ )
+ {
+ *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
+ buffer++;
+ address++;
+ }
+
+ readcount -= nbytes;
+ } while (readcount);
+ wcount -= blocksize;
+ }
+
+ return retval;
+}
+
+int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address)
+{
+ u32 invalue;
+ int retval = ERROR_OK;
+
+ if (count >= 4)
+ return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
+
+ swjdp->trans_mode = TRANS_MODE_COMPOSITE;
+
+ while (count > 0)
+ {
+ dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+ dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
+ retval = swjdp_transaction_endcheck(swjdp);
+ *((u8*)buffer) = (invalue >> 8 * (address & 0x3));
+ count--;
+ address++;
+ buffer++;
+ }
+
+ return retval;
+}
+
+int ahbap_debugport_init(swjdp_common_t *swjdp)
+{
+ u32 idreg, romaddr, dummy;
+ u32 ctrlstat;
+ int cnt = 0;
+ int retval;
+
+ LOG_DEBUG(" ");
+
+ swjdp->apsel = 0;
+ swjdp->ap_csw_value = -1;
+ swjdp->ap_tar_value = -1;
+ swjdp->trans_mode = TRANS_MODE_ATOMIC;
+ dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
+ dap_dp_write_reg(swjdp, SSTICKYERR, DP_CTRL_STAT);
+ dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
+
+ swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
+
+ dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
+ dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+
+ /* Check that we have debug power domains activated */
+ while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
+ {
+ LOG_DEBUG("swjdp: wait CDBGPWRUPACK");
+ dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+ alive_sleep(10);
+ }
+
+ while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
+ {
+ LOG_DEBUG("swjdp: wait CSYSPWRUPACK");
+ dap_dp_read_reg(swjdp, &ctrlstat, DP_CTRL_STAT);
+ if ((retval=jtag_execute_queue())!=ERROR_OK)
+ return retval;
+ alive_sleep(10);
+ }
+
+ dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
+ /* With debug power on we can activate OVERRUN checking */
+ swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
+ dap_dp_write_reg(swjdp, swjdp->dp_ctrl_stat, DP_CTRL_STAT);
+ dap_dp_read_reg(swjdp, &dummy, DP_CTRL_STAT);
+
+ dap_ap_read_reg_u32(swjdp, 0xFC, &idreg);
+ dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);
+
+ LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
+
+ return ERROR_OK;
+}
+
+
+char * class_description[16] ={
+ "Reserved",
+ "ROM table","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved","Reserved",
+ "CoreSight component","Reserved","Peripheral Test Block","Reserved","DESS","Generic IP component","Non standard layout"};
+
+int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel)
+{
+
+ u32 dbgbase,apid;
+ int romtable_present = 0;
+ u8 mem_ap;
+ u32 apselold;
+
+ apselold = swjdp->apsel;
+ dap_ap_select(swjdp, apsel);
+ dap_ap_read_reg_u32(swjdp, 0xF8, &dbgbase);
+ dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
+ swjdp_transaction_endcheck(swjdp);
+ /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
+ mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0));
+ command_print(cmd_ctx, "ap identification register 0x%8.8x", apid);
+ if (apid)
+ {
+ switch (apid&0x0F)
+ {
+ case 0:
+ command_print(cmd_ctx, "\tType is jtag-ap");
+ break;
+ case 1:
+ command_print(cmd_ctx, "\tType is mem-ap AHB");
+ break;
+ case 2:
+ command_print(cmd_ctx, "\tType is mem-ap APB");
+ break;
+ default:
+ command_print(cmd_ctx, "\tUnknown AP-type");
+ break;
+ }
+ command_print(cmd_ctx, "ap debugbase 0x%8.8x", dbgbase);
+ }
+ else
+ {
+ command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
+ }
+
+ romtable_present = ((mem_ap)&&(dbgbase != 0xFFFFFFFF));
+ if (romtable_present)
+ {
+ u32 cid0,cid1,cid2,cid3,memtype,romentry;
+ u16 entry_offset;
+ /* bit 16 of apid indicates a memory access port */
+ if (dbgbase&0x02)
+ {
+ command_print(cmd_ctx, "\tValid ROM table present");
+ }
+ else
+ {
+ command_print(cmd_ctx, "\tROM table in legacy format" );
+ }
+ /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec */
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF0, &cid0);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF4, &cid1);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFF8, &cid2);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3);
+ mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype);
+ swjdp_transaction_endcheck(swjdp);
+ command_print(cmd_ctx, "\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",cid3,cid2,cid1,cid0);
+ if (memtype&0x01)
+ {
+ command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
+ }
+ else
+ {
+ command_print(cmd_ctx, "\tMEMTYPE system memory not present. Dedicated debug bus" );
+ }
+
+ /* Now we read ROM table entries from dbgbase&0xFFFFF000)|0x000 until we get 0x00000000 */
+ entry_offset = 0;
+ do
+ {
+ mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry);
+ command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%x",entry_offset,romentry);
+ if (romentry&0x01)
+ {
+ u32 c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
+ u32 component_base = (u32)((dbgbase&0xFFFFF000)+(int)(romentry&0xFFFFF000));
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE0, &c_pid0);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE4, &c_pid1);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFE8, &c_pid2);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFEC, &c_pid3);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFD0, &c_pid4);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF0, &c_cid0);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF4, &c_cid1);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2);
+ mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3);
+ component_start = component_base - 0x1000*(c_pid4>>4);
+ command_print(cmd_ctx, "\t\tComponent base address 0x%x, pid4 0x%x, start address 0x%x",component_base,c_pid4,component_start);
+ command_print(cmd_ctx, "\t\tComponent cid1 0x%x, class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
+ command_print(cmd_ctx, "\t\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",c_cid3,c_cid2,c_cid1,c_cid0);
+ command_print(cmd_ctx, "\t\tPID3 0x%x, PID2 0x%x, PID1 0x%x, PID0, 0x%x",c_pid3,c_pid2,c_pid1,c_pid0);
+ /* For CoreSight components, (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */
+ }
+ else
+ {
+ if (romentry)
+ command_print(cmd_ctx, "\t\tComponent not present");
+ else
+ command_print(cmd_ctx, "\t\tEnd of ROM table");
+ }
+ entry_offset += 4;
+ } while (romentry>0);
+ }
+ else
+ {
+ command_print(cmd_ctx, "\tNo ROM table present");
+ }
+ dap_ap_select(swjdp, apselold);
+
+ return ERROR_OK;
+}
+
Added: trunk/src/target/arm_adi_v5.h
===================================================================
--- trunk/src/target/arm_adi_v5.h 2009-04-27 05:40:52 UTC (rev 1534)
+++ trunk/src/target/arm_adi_v5.h 2009-04-27 08:21:35 UTC (rev 1535)
@@ -0,0 +1,142 @@
+/***************************************************************************
+ * Copyright (C) 2006 by Magnus Lundin *
+ * lu...@ml... *
+ * *
+ * Copyright (C) 2008 by Spencer Oliver *
+ * sp...@sp... *
+ * *
+ * This program is free software; you can redistribute it and/or modify *
+ * it under the terms of the GNU General Public License as published by *
+ * the Free Software Foundation; either version 2 of the License, or *
+ * (at your option) any later version. *
+ * *
+ * This program is distributed in the hope that it will be useful, *
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
+ * *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program; if not, write to the *
+ * Free Software Foundation, Inc., *
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ ***************************************************************************/
+#ifndef ARM_ADI_V5_H
+#define ARM_ADI_V5_H
+
+#include "target.h"
+#include "register.h"
+#include "arm_jtag.h"
+
+#define SWJDP_IR_DPACC 0xA
+#define SWJDP_IR_APACC 0xB
+
+#define DPAP_WRITE 0
+#define DPAP_READ 1
+#define DP_ZERO 0
+#define DP_CTRL_STAT 0x4
+#define DP_SELECT 0x8
+#define DP_RDBUFF 0xC
+
+#define CORUNDETECT (1<<0)
+#define SSTICKYORUN (1<<1)
+#define SSTICKYERR (1<<5)
+#define CDBGRSTREQ (1<<26)
+#define CDBGRSTACK (1<<27)
+#define CDBGPWRUPREQ (1<<28)
+#define CDBGPWRUPACK (1<<29)
+#define CSYSPWRUPREQ (1<<30)
+#define CSYSPWRUPACK (1<<31)
+
+#define AP_REG_CSW 0x00
+#define AP_REG_TAR 0x04
+#define AP_REG_DRW 0x0C
+#define AP_REG_BD0 0x10
+#define AP_REG_BD1 0x14
+#define AP_REG_BD2 0x18
+#define AP_REG_BD3 0x1C
+#define AP_REG_DBGROMA 0xF8
+#define AP_REG_IDR 0xFC
+
+#define CSW_8BIT 0
+#define CSW_16BIT 1
+#define CSW_32BIT 2
+
+#define CSW_ADDRINC_MASK (3<<4)
+#define CSW_ADDRINC_OFF 0
+#define CSW_ADDRINC_SINGLE (1<<4)
+#define CSW_ADDRINC_PACKED (2<<4)
+#define CSW_HPROT (1<<25)
+#define CSW_MASTER_DEBUG (1<<29)
+#define CSW_DBGSWENABLE (1<<31)
+
+/* transaction mode */
+#define TRANS_MODE_NONE 0
+/* Transaction waits for previous to complete */
+#define TRANS_MODE_ATOMIC 1
+/* Freerunning transactions with delays and overrun checking */
+#define TRANS_MODE_COMPOSITE 2
+
+typedef struct swjdp_reg_s
+{
+ int addr;
+ arm_jtag_t *jtag_info;
+} swjdp_reg_t;
+
+typedef struct swjdp_common_s
+{
+ arm_jtag_t *jtag_info;
+ /* Control config */
+ u32 dp_ctrl_stat;
+ /* Support for several AP's in one DAP */
+ u32 apsel;
+ /* Register select cache */
+ u32 dp_select_value;
+ u32 ap_csw_value;
+ u32 ap_tar_value;
+ /* information about current pending SWjDP-AHBAP transaction */
+ u8 trans_mode;
+ u8 trans_rw;
+ u8 ack;
+} swjdp_common_t;
+
+/* Internal functions used in the module, partial transactions, use with caution */
+extern int dap_dp_write_reg(swjdp_common_t *swjdp, u32 value, u8 reg_addr);
+/* extern int swjdp_write_apacc(swjdp_common_t *swjdp, u32 value, u8 reg_addr); */
+extern int dap_dp_read_reg(swjdp_common_t *swjdp, u32 *value, u8 reg_addr);
+/* extern int swjdp_read_apacc(swjdp_common_t *swjdp, u32 *value, u8 reg_addr); */
+extern int dap_setup_accessport(swjdp_common_t *swjdp, u32 csw, u32 tar);
+extern int dap_ap_select(swjdp_common_t *swjdp,u8 apsel);
+
+extern int dap_ap_write_reg(swjdp_common_t *swjdp, u32 reg_addr, u8* out_value_buf);
+extern int dap_ap_write_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 value);
+extern int dap_ap_read_reg(swjdp_common_t *swjdp, u32 reg_addr, u8 *in_value_buf);
+extern int dap_ap_read_reg_u32(swjdp_common_t *swjdp, u32 reg_addr, u32 *value);
+
+/* External interface, partial operations must be completed with swjdp_transaction_endcheck() */
+extern int swjdp_transaction_endcheck(swjdp_common_t *swjdp);
+
+/* MEM-AP memory mapped bus single u32 register transfers, without endcheck */
+extern int mem_ap_read_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
+extern int mem_ap_write_u32(swjdp_common_t *swjdp, u32 address, u32 value);
+
+/* MEM-AP memory mapped bus transfers, single registers, complete transactions */
+extern int mem_ap_read_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 *value);
+extern int mem_ap_write_atomic_u32(swjdp_common_t *swjdp, u32 address, u32 value);
+
+/* MEM-AP memory mapped bus block transfers */
+extern int mem_ap_read_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+extern int mem_ap_read_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+extern int mem_ap_read_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+extern int mem_ap_write_buf_u8(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+extern int mem_ap_write_buf_u16(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+extern int mem_ap_write_buf_u32(swjdp_common_t *swjdp, u8 *buffer, int count, u32 address);
+
+/* Initialisation of the debug system, power domains and registers */
+extern int ahbap_debugport_init(swjdp_common_t *swjdp);
+
+extern int dap_info_command(struct command_context_s *cmd_ctx, swjdp_common_t *swjdp, int apsel);
+/* Commands for user dap access */
+extern int handle_dap_info_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+extern int handle_dap_apsel_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+
+#endif
|
|
From: <oh...@ma...> - 2009-04-27 07:40:57
|
Author: oharboe
Date: 2009-04-27 07:40:52 +0200 (Mon, 27 Apr 2009)
New Revision: 1534
Modified:
trunk/src/flash/mflash.c
Log:
Philippe Vachon <phi...@co...> 64 bit host fixes
Modified: trunk/src/flash/mflash.c
===================================================================
--- trunk/src/flash/mflash.c 2009-04-27 05:30:15 UTC (rev 1533)
+++ trunk/src/flash/mflash.c 2009-04-27 05:40:52 UTC (rev 1534)
@@ -473,14 +473,16 @@
residue = sect_cnt % 256;
for (i = 0; i < quotient; i++) {
- LOG_DEBUG("sect num : %u buff : 0x%8.8x", sect_num, (u32)buff_ptr);
+ LOG_DEBUG("sect num : %u buff : 0x%0lx", sect_num,
+ (unsigned long)buff_ptr);
mg_mflash_do_read_sects(buff_ptr, sect_num, 256);
sect_num += 256;
buff_ptr += 256 * MG_MFLASH_SECTOR_SIZE;
}
if (residue) {
- LOG_DEBUG("sect num : %u buff : %8.8x", sect_num, (u32)buff_ptr);
+ LOG_DEBUG("sect num : %u buff : %0lx", sect_num,
+ (unsigned long)buff_ptr);
mg_mflash_do_read_sects(buff_ptr, sect_num, residue);
}
@@ -542,14 +544,16 @@
residue = sect_cnt % 256;
for (i = 0; i < quotient; i++) {
- LOG_DEBUG("sect num : %u buff : %8.8x", sect_num, (u32)buff_ptr);
+ LOG_DEBUG("sect num : %u buff : %0lx", sect_num,
+ (unsigned long)buff_ptr);
mg_mflash_do_write_sects(buff_ptr, sect_num, 256);
sect_num += 256;
buff_ptr += 256 * MG_MFLASH_SECTOR_SIZE;
}
if (residue) {
- LOG_DEBUG("sect num : %u buff : %8.8x", sect_num, (u32)buff_ptr);
+ LOG_DEBUG("sect num : %u buff : %0lx", sect_num,
+ (unsigned long)buff_ptr);
mg_mflash_do_write_sects(buff_ptr, sect_num, residue);
}
|
|
From: <oh...@ma...> - 2009-04-27 07:30:19
|
Author: oharboe
Date: 2009-04-27 07:30:15 +0200 (Mon, 27 Apr 2009)
New Revision: 1533
Modified:
trunk/configure.in
Log:
Zach Welch <zw...@su...> add -Wcast-align and -Wbad-function-cast
Modified: trunk/configure.in
===================================================================
--- trunk/configure.in 2009-04-27 05:29:30 UTC (rev 1532)
+++ trunk/configure.in 2009-04-27 05:30:15 UTC (rev 1533)
@@ -776,6 +776,8 @@
GCC_WARNINGS="-Wall -Wstrict-prototypes -Wformat-security"
if test "${gcc_wextra}" = yes; then
GCC_WARNINGS="${GCC_WARNINGS} -Wextra -Wno-unused-parameter"
+ GCC_WARNINGS="${GCC_WARNINGS} -Wbad-function-cast"
+ GCC_WARNINGS="${GCC_WARNINGS} -Wcast-align"
fi
if test "${gcc_werror}" = yes; then
GCC_WARNINGS="${GCC_WARNINGS} -Werror"
|
|
From: <oh...@ma...> - 2009-04-27 07:29:36
|
Author: oharboe Date: 2009-04-27 07:29:30 +0200 (Mon, 27 Apr 2009) New Revision: 1532 Modified: trunk/src/helper/jim.c trunk/src/target/oocd_trace.c Log: Zach Welch <zw...@su...> wrap _GNU_SOURCE defines Modified: trunk/src/helper/jim.c =================================================================== --- trunk/src/helper/jim.c 2009-04-26 20:05:08 UTC (rev 1531) +++ trunk/src/helper/jim.c 2009-04-27 05:29:30 UTC (rev 1532) @@ -49,7 +49,9 @@ #define JIM_DYNLIB /* Dynamic library support for UNIX and WIN32 */ #endif /* JIM_ANSIC */ +#ifndef _GNU_SOURCE #define _GNU_SOURCE /* for vasprintf() */ +#endif #include <stdio.h> #include <stdlib.h> #include <string.h> Modified: trunk/src/target/oocd_trace.c =================================================================== --- trunk/src/target/oocd_trace.c 2009-04-26 20:05:08 UTC (rev 1531) +++ trunk/src/target/oocd_trace.c 2009-04-27 05:29:30 UTC (rev 1532) @@ -21,7 +21,9 @@ #include "config.h" #endif +#ifndef _GNU_SOURCE #define _GNU_SOURCE +#endif #include <string.h> #include <errno.h> |
