Menu
▾
▴
openocd-commit — OpenOCD commit maling list - read only
You can subscribe to this list here.
| 2008 |
Jan
|
Feb
|
Mar
|
Apr
|
May
|
Jun
|
Jul
|
Aug
|
Sep
|
Oct
|
Nov
|
Dec
(75) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 2009 |
Jan
(70) |
Feb
(20) |
Mar
(52) |
Apr
(149) |
May
(387) |
Jun
(466) |
Jul
(133) |
Aug
(87) |
Sep
(122) |
Oct
(140) |
Nov
(185) |
Dec
(105) |
| 2010 |
Jan
(85) |
Feb
(45) |
Mar
(75) |
Apr
(17) |
May
(41) |
Jun
(52) |
Jul
(33) |
Aug
(29) |
Sep
(36) |
Oct
(15) |
Nov
(26) |
Dec
(34) |
| 2011 |
Jan
(26) |
Feb
(25) |
Mar
(26) |
Apr
(29) |
May
(20) |
Jun
(27) |
Jul
(15) |
Aug
(32) |
Sep
(13) |
Oct
(64) |
Nov
(60) |
Dec
(10) |
| 2012 |
Jan
(64) |
Feb
(63) |
Mar
(39) |
Apr
(43) |
May
(54) |
Jun
(11) |
Jul
(30) |
Aug
(45) |
Sep
(11) |
Oct
(70) |
Nov
(24) |
Dec
(23) |
| 2013 |
Jan
(17) |
Feb
(8) |
Mar
(35) |
Apr
(40) |
May
(20) |
Jun
(24) |
Jul
(36) |
Aug
(25) |
Sep
(42) |
Oct
(40) |
Nov
(9) |
Dec
(21) |
| 2014 |
Jan
(29) |
Feb
(24) |
Mar
(60) |
Apr
(22) |
May
(22) |
Jun
(46) |
Jul
(11) |
Aug
(23) |
Sep
(26) |
Oct
(10) |
Nov
(14) |
Dec
(2) |
| 2015 |
Jan
(28) |
Feb
(47) |
Mar
(33) |
Apr
(58) |
May
(5) |
Jun
(1) |
Jul
|
Aug
(8) |
Sep
(12) |
Oct
(25) |
Nov
(58) |
Dec
(21) |
| 2016 |
Jan
(12) |
Feb
(40) |
Mar
(2) |
Apr
(1) |
May
(67) |
Jun
(2) |
Jul
(5) |
Aug
(36) |
Sep
|
Oct
(24) |
Nov
(17) |
Dec
(50) |
| 2017 |
Jan
(14) |
Feb
(16) |
Mar
(2) |
Apr
(35) |
May
(14) |
Jun
(16) |
Jul
(3) |
Aug
(3) |
Sep
|
Oct
(19) |
Nov
|
Dec
(16) |
| 2018 |
Jan
(55) |
Feb
(11) |
Mar
(34) |
Apr
(14) |
May
(4) |
Jun
(20) |
Jul
(39) |
Aug
(16) |
Sep
(17) |
Oct
(16) |
Nov
(20) |
Dec
(30) |
| 2019 |
Jan
(29) |
Feb
(24) |
Mar
(37) |
Apr
(26) |
May
(19) |
Jun
(21) |
Jul
(2) |
Aug
(3) |
Sep
(9) |
Oct
(12) |
Nov
(12) |
Dec
(12) |
| 2020 |
Jan
(47) |
Feb
(36) |
Mar
(54) |
Apr
(44) |
May
(37) |
Jun
(19) |
Jul
(32) |
Aug
(13) |
Sep
(16) |
Oct
(24) |
Nov
(32) |
Dec
(11) |
| 2021 |
Jan
(14) |
Feb
(5) |
Mar
(40) |
Apr
(32) |
May
(42) |
Jun
(31) |
Jul
(29) |
Aug
(47) |
Sep
(38) |
Oct
(17) |
Nov
(74) |
Dec
(33) |
| 2022 |
Jan
(11) |
Feb
(15) |
Mar
(40) |
Apr
(21) |
May
(39) |
Jun
(44) |
Jul
(19) |
Aug
(46) |
Sep
(79) |
Oct
(35) |
Nov
(21) |
Dec
(15) |
| 2023 |
Jan
(56) |
Feb
(13) |
Mar
(43) |
Apr
(28) |
May
(60) |
Jun
(15) |
Jul
(29) |
Aug
(28) |
Sep
(32) |
Oct
(21) |
Nov
(42) |
Dec
(39) |
| 2024 |
Jan
(35) |
Feb
(17) |
Mar
(28) |
Apr
(7) |
May
(14) |
Jun
(35) |
Jul
(30) |
Aug
(35) |
Sep
(30) |
Oct
(28) |
Nov
(38) |
Dec
(18) |
| 2025 |
Jan
(21) |
Feb
(28) |
Mar
(36) |
Apr
(35) |
May
(34) |
Jun
(58) |
Jul
(9) |
Aug
(54) |
Sep
(47) |
Oct
(15) |
Nov
(58) |
Dec
|
|
From: kc8apf at B. <kc...@ma...> - 2009-05-18 19:27:48
|
Author: kc8apf
Date: 2009-05-18 19:27:46 +0200 (Mon, 18 May 2009)
New Revision: 1817
Modified:
trunk/src/jtag/jtag.c
Log:
Add jtag_queue_command() by Michael Bruck <mb...@di...> [3/8]
Modified: trunk/src/jtag/jtag.c
===================================================================
--- trunk/src/jtag/jtag.c 2009-05-18 17:27:30 UTC (rev 1816)
+++ trunk/src/jtag/jtag.c 2009-05-18 17:27:46 UTC (rev 1817)
@@ -672,32 +672,31 @@
int MINIDRIVER(interface_jtag_add_plain_ir_scan)(int num_fields, scan_field_t *fields, tap_state_t state)
{
- int i;
- jtag_command_t **last_cmd;
+ /* allocate memory for a new list member */
- last_cmd = jtag_get_last_command_p();
+ jtag_command_t * cmd = cmd_queue_alloc(sizeof(jtag_command_t));
+
+ jtag_queue_command(cmd);
- /* allocate memory for a new list member */
- *last_cmd = cmd_queue_alloc(sizeof(jtag_command_t));
- (*last_cmd)->next = NULL;
- last_comand_pointer = &((*last_cmd)->next);
- (*last_cmd)->type = JTAG_SCAN;
+ cmd->type = JTAG_SCAN;
/* allocate memory for ir scan command */
- (*last_cmd)->cmd.scan = cmd_queue_alloc(sizeof(scan_command_t));
- (*last_cmd)->cmd.scan->ir_scan = true;
- (*last_cmd)->cmd.scan->num_fields = num_fields;
- (*last_cmd)->cmd.scan->fields = cmd_queue_alloc(num_fields * sizeof(scan_field_t));
- (*last_cmd)->cmd.scan->end_state = state;
+ cmd->cmd.scan = cmd_queue_alloc(sizeof(scan_command_t));
+ cmd->cmd.scan->ir_scan = true;
+ cmd->cmd.scan->num_fields = num_fields;
+ cmd->cmd.scan->fields = cmd_queue_alloc(num_fields * sizeof(scan_field_t));
+ cmd->cmd.scan->end_state = state;
- for( i = 0 ; i < num_fields ; i++ ){
+ for (int i = 0; i < num_fields; i++)
+ {
int num_bits = fields[i].num_bits;
int num_bytes = CEIL(fields[i].num_bits, 8);
- (*last_cmd)->cmd.scan->fields[i].tap = fields[i].tap;
- (*last_cmd)->cmd.scan->fields[i].num_bits = num_bits;
- (*last_cmd)->cmd.scan->fields[i].out_value = buf_cpy(fields[i].out_value, cmd_queue_alloc(num_bytes), num_bits);
- (*last_cmd)->cmd.scan->fields[i].in_value = fields[i].in_value;
+ cmd->cmd.scan->fields[i].tap = fields[i].tap;
+ cmd->cmd.scan->fields[i].num_bits = num_bits;
+ cmd->cmd.scan->fields[i].out_value = buf_cpy(fields[i].out_value, cmd_queue_alloc(num_bytes), num_bits);
+ cmd->cmd.scan->fields[i].in_value = fields[i].in_value;
}
+
return ERROR_OK;
}
|
|
From: kc8apf at B. <kc...@ma...> - 2009-05-18 19:27:33
|
Author: kc8apf
Date: 2009-05-18 19:27:30 +0200 (Mon, 18 May 2009)
New Revision: 1816
Modified:
trunk/src/jtag/jtag.c
Log:
Add jtag_queue_command() by Michael Bruck <mb...@di...> [2/8]
Modified: trunk/src/jtag/jtag.c
===================================================================
--- trunk/src/jtag/jtag.c 2009-05-18 17:27:00 UTC (rev 1815)
+++ trunk/src/jtag/jtag.c 2009-05-18 17:27:30 UTC (rev 1816)
@@ -590,28 +590,26 @@
int MINIDRIVER(interface_jtag_add_ir_scan)(int num_fields, scan_field_t *fields, tap_state_t state)
{
- jtag_command_t **last_cmd;
jtag_tap_t *tap;
int j;
int x;
int nth_tap;
int scan_size = 0;
- last_cmd = jtag_get_last_command_p();
-
/* allocate memory for a new list member */
- *last_cmd = cmd_queue_alloc(sizeof(jtag_command_t));
- (*last_cmd)->next = NULL;
- last_comand_pointer = &((*last_cmd)->next);
- (*last_cmd)->type = JTAG_SCAN;
+ jtag_command_t * cmd = cmd_queue_alloc(sizeof(jtag_command_t));
+
+ jtag_queue_command(cmd);
+
+ cmd->type = JTAG_SCAN;
/* allocate memory for ir scan command */
- (*last_cmd)->cmd.scan = cmd_queue_alloc(sizeof(scan_command_t));
- (*last_cmd)->cmd.scan->ir_scan = true;
+ cmd->cmd.scan = cmd_queue_alloc(sizeof(scan_command_t));
+ cmd->cmd.scan->ir_scan = true;
x = jtag_NumEnabledTaps();
- (*last_cmd)->cmd.scan->num_fields = x; /* one field per device */
- (*last_cmd)->cmd.scan->fields = cmd_queue_alloc(x * sizeof(scan_field_t));
- (*last_cmd)->cmd.scan->end_state = state;
+ cmd->cmd.scan->num_fields = x; /* one field per device */
+ cmd->cmd.scan->fields = cmd_queue_alloc(x * sizeof(scan_field_t));
+ cmd->cmd.scan->end_state = state;
nth_tap = -1;
tap = NULL;
@@ -628,9 +626,9 @@
assert(nth_tap < x );
scan_size = tap->ir_length;
- (*last_cmd)->cmd.scan->fields[nth_tap].tap = tap;
- (*last_cmd)->cmd.scan->fields[nth_tap].num_bits = scan_size;
- (*last_cmd)->cmd.scan->fields[nth_tap].in_value = NULL; /* do not collect input for tap's in bypass */
+ cmd->cmd.scan->fields[nth_tap].tap = tap;
+ cmd->cmd.scan->fields[nth_tap].num_bits = scan_size;
+ cmd->cmd.scan->fields[nth_tap].in_value = NULL; /* do not collect input for tap's in bypass */
/* search the list */
for (j = 0; j < num_fields; j++)
@@ -638,8 +636,8 @@
if (tap == fields[j].tap)
{
found = 1;
- (*last_cmd)->cmd.scan->fields[nth_tap].in_value = fields[j].in_value;
- (*last_cmd)->cmd.scan->fields[nth_tap].out_value = buf_cpy(fields[j].out_value, cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
+ cmd->cmd.scan->fields[nth_tap].in_value = fields[j].in_value;
+ cmd->cmd.scan->fields[nth_tap].out_value = buf_cpy(fields[j].out_value, cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
tap->bypass = 0;
break;
@@ -649,12 +647,12 @@
if (!found)
{
/* if a tap isn't listed, set it to BYPASS */
- (*last_cmd)->cmd.scan->fields[nth_tap].out_value = buf_set_ones(cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
+ cmd->cmd.scan->fields[nth_tap].out_value = buf_set_ones(cmd_queue_alloc(CEIL(scan_size, 8)), scan_size);
tap->bypass = 1;
}
/* update device information */
- buf_cpy((*last_cmd)->cmd.scan->fields[nth_tap].out_value, tap->cur_instr, scan_size);
+ buf_cpy(cmd->cmd.scan->fields[nth_tap].out_value, tap->cur_instr, scan_size);
}
assert(nth_tap == (x-1));
|
|
From: kc8apf at B. <kc...@ma...> - 2009-05-18 19:27:03
|
Author: kc8apf
Date: 2009-05-18 19:27:00 +0200 (Mon, 18 May 2009)
New Revision: 1815
Modified:
trunk/src/jtag/jtag.c
Log:
Add jtag_queue_command() by Michael Bruck <mb...@di...>
Modified: trunk/src/jtag/jtag.c
===================================================================
--- trunk/src/jtag/jtag.c 2009-05-18 17:23:52 UTC (rev 1814)
+++ trunk/src/jtag/jtag.c 2009-05-18 17:27:00 UTC (rev 1815)
@@ -439,6 +439,21 @@
return last_comand_pointer;
}
+
+void jtag_queue_command(jtag_command_t * cmd)
+{
+ jtag_command_t **last_cmd;
+
+ last_cmd = jtag_get_last_command_p();
+
+ *last_cmd = cmd;
+
+ (*last_cmd)->next = NULL;
+
+ last_comand_pointer = &((*last_cmd)->next);
+}
+
+
void* cmd_queue_alloc(size_t size)
{
cmd_queue_page_t **p_page = &cmd_queue_pages;
|
|
From: kc8apf at B. <kc...@ma...> - 2009-05-18 19:24:03
|
Author: kc8apf
Date: 2009-05-18 19:23:52 +0200 (Mon, 18 May 2009)
New Revision: 1814
Modified:
trunk/src/jtag/ft2232.c
Log:
ftdi_set_interface correctness by Strontium <str...@gm...>
Modified: trunk/src/jtag/ft2232.c
===================================================================
--- trunk/src/jtag/ft2232.c 2009-05-18 17:20:51 UTC (rev 1813)
+++ trunk/src/jtag/ft2232.c 2009-05-18 17:23:52 UTC (rev 1814)
@@ -1766,6 +1766,12 @@
if (ftdi_init(&ftdic) < 0)
return ERROR_JTAG_INIT_FAILED;
+ if (ftdi_set_interface(&ftdic, INTERFACE_A) < 0)
+ {
+ LOG_ERROR("unable to select FT2232 channel A: %s", ftdic.error_str);
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
/* context, vendor id, product id */
if (ftdi_usb_open_desc(&ftdic, vid, pid, ft2232_device_desc,
ft2232_serial) < 0)
@@ -1779,12 +1785,6 @@
return ERROR_JTAG_INIT_FAILED;
}
- if (ftdi_set_interface(&ftdic, INTERFACE_A) < 0)
- {
- LOG_ERROR("unable to select FT2232 channel A: %s", ftdic.error_str);
- return ERROR_JTAG_INIT_FAILED;
- }
-
if (ftdi_usb_reset(&ftdic) < 0)
{
LOG_ERROR("unable to reset ftdi device");
|
|
From: kc8apf at B. <kc...@ma...> - 2009-05-18 19:20:58
|
Author: kc8apf Date: 2009-05-18 19:20:51 +0200 (Mon, 18 May 2009) New Revision: 1813 Modified: trunk/PATCHES Log: PATCHES updates from David Brownell <da...@pa...> Modified: trunk/PATCHES =================================================================== --- trunk/PATCHES 2009-05-18 17:06:36 UTC (rev 1812) +++ trunk/PATCHES 2009-05-18 17:20:51 UTC (rev 1813) @@ -2,6 +2,9 @@ ope...@li... +Note that you can't send patches to that list unless +you're a member, despite what the list info page says. + The patch should be against svn trunk using an SVN diff. @@ -9,6 +12,10 @@ also write a short change log entry that maintainers can copy and paste into the commit message +(However, don't expect the maintainers to actually +include such entries in their commit messages if +they're longer than a single $SUBJECT line.) + Add yourself to the GPL copyright for non-trivial changes. To create a patch from the command line: |
|
From: kc8apf at B. <kc...@ma...> - 2009-05-18 19:06:38
|
Author: kc8apf
Date: 2009-05-18 19:06:36 +0200 (Mon, 18 May 2009)
New Revision: 1812
Modified:
trunk/src/jtag/jtag.c
Log:
JTAG state table updates (short table still disabled). Provided by Dick Hollenbeck <di...@so...>
Modified: trunk/src/jtag/jtag.c
===================================================================
--- trunk/src/jtag/jtag.c 2009-05-18 13:55:38 UTC (rev 1811)
+++ trunk/src/jtag/jtag.c 2009-05-18 17:06:36 UTC (rev 1812)
@@ -853,6 +853,9 @@
#endif
}
}
+
+ /* field_count represents the true number of fields setup*/
+ (*last_cmd)->cmd.scan->num_fields = field_count;
return ERROR_OK;
}
@@ -1315,7 +1318,7 @@
int i;
bit_count = jtag_scan_size(cmd);
- *buffer = malloc(CEIL(bit_count, 8));
+ *buffer = calloc(1,CEIL(bit_count, 8));
bit_count = 0;
@@ -3298,23 +3301,23 @@
/* to state: */
/* RESET IDLE DRSHIFT DRPAUSE IRSHIFT IRPAUSE */ /* from state: */
- { B8(1111111,7), B8(0,1), B8(00101,5), B8(01010,5), B8(001101,6), B8(010110,6) }, /* RESET */
- { B8(1111111,7), B8(0,1), B8(001,3), B8(0101,4), B8(0011,4), B8(01011,5) }, /* IDLE */
+ { B8(1111111,7), B8(0000000,7), B8(00101,5), B8(01010,5), B8(001101,6), B8(010110,6) }, /* RESET */
+ { B8(1111111,7), B8(0000000,7), B8(001,3), B8(0101,4), B8(0011,4), B8(01011,5) }, /* IDLE */
{ B8(1111111,7), B8(011,3), B8(00111,5), B8(01,2), B8(001111,6), B8(0101111,7) }, /* DRSHIFT */
- { B8(1111111,7), B8(011,3), B8(01,2), B8(0,1), B8(001111,6), B8(0101111,7) }, /* DRPAUSE */
+ { B8(1111111,7), B8(011,3), B8(01,2), B8(0,1), B8(001111,6), B8(0101111,7) }, /* DRPAUSE */
{ B8(1111111,7), B8(011,3), B8(00111,5), B8(010111,6), B8(001111,6), B8(01,2) }, /* IRSHIFT */
{ B8(1111111,7), B8(011,3), B8(00111,5), B8(010111,6), B8(01,2), B8(0,1) } /* IRPAUSE */
#else /* this is the old table, converted from hex and with the bit_count set to 7 for each combo, like before */
/* to state: */
- /* RESET IDLE DRSHIFT DRPAUSE IRSHIFT IRPAUSE */ /* from state: */
- { B8(1111111,7), B8(0000000,7), B8(0010111,7), B8(0001010,7), B8(0011011,7), B8(0010110,7) }, /* RESET */
- { B8(1111111,7), B8(0000000,7), B8(0100101,7), B8(0000101,7), B8(0101011,7), B8(0001011,7) }, /* IDLE */
- { B8(1111111,7), B8(0110001,7), B8(0000000,7), B8(0000001,7), B8(0001111,7), B8(0101111,7) }, /* DRSHIFT */
- { B8(1111111,7), B8(0110000,7), B8(0100000,7), B8(0010111,7), B8(0011110,7), B8(0101111,7) }, /* DRPAUSE */
- { B8(1111111,7), B8(0110001,7), B8(0000111,7), B8(0010111,7), B8(0000000,7), B8(0000001,7) }, /* IRSHIFT */
- { B8(1111111,7), B8(0110000,7), B8(0011100,7), B8(0010111,7), B8(0100000,7), B8(0101111,7) } /* IRPAUSE */
+ /* RESET IDLE DRSHIFT DRPAUSE IRSHIFT IRPAUSE */ /* from state: */
+ { B8(1111111,7), B8(0000000,7), B8(0010111,7), B8(0001010,7), B8(0011011,7), B8(0010110,7) }, /* RESET */
+ { B8(1111111,7), B8(0000000,7), B8(0100101,7), B8(0000101,7), B8(0101011,7), B8(0001011,7) }, /* IDLE */
+ { B8(1111111,7), B8(0110001,7), B8(0000000,7), B8(0000001,7), B8(0001111,7), B8(0101111,7) }, /* DRSHIFT */
+ { B8(1111111,7), B8(0110000,7), B8(0100000,7), B8(0010111,7), B8(0011110,7), B8(0101111,7) }, /* DRPAUSE */
+ { B8(1111111,7), B8(0110001,7), B8(0000111,7), B8(0010111,7), B8(0000000,7), B8(0000001,7) }, /* IRSHIFT */
+ { B8(1111111,7), B8(0110000,7), B8(0011100,7), B8(0010111,7), B8(0011110,7), B8(0101111,7) }, /* IRPAUSE */
#endif
|
|
From: oharboe at B. <oh...@ma...> - 2009-05-18 15:55:41
|
Author: oharboe
Date: 2009-05-18 15:55:38 +0200 (Mon, 18 May 2009)
New Revision: 1811
Modified:
trunk/src/helper/command.c
Log:
Remove unecessary(and poptentially harmful?) "" around arguments
passed in to "eval" in command.c
Modified: trunk/src/helper/command.c
===================================================================
--- trunk/src/helper/command.c 2009-05-18 13:07:37 UTC (rev 1810)
+++ trunk/src/helper/command.c 2009-05-18 13:55:38 UTC (rev 1811)
@@ -221,7 +221,7 @@
free((void *)full_name);
/* we now need to add an overrideable proc */
- const char *override_name=alloc_printf("proc %s%s%s {args} {if {[catch {eval \"ocd_%s%s%s $args\"}]==0} {return \"\"} else { return -code error }", t1, t2, t3, t1, t2, t3);
+ const char *override_name=alloc_printf("proc %s%s%s {args} {if {[catch {eval ocd_%s%s%s $args}]==0} {return \"\"} else { return -code error }", t1, t2, t3, t1, t2, t3);
Jim_Eval_Named(interp, override_name, __THIS__FILE__, __LINE__ );
free((void *)override_name);
|
|
From: oharboe at B. <oh...@ma...> - 2009-05-18 15:07:38
|
Author: oharboe
Date: 2009-05-18 15:07:37 +0200 (Mon, 18 May 2009)
New Revision: 1810
Modified:
trunk/src/helper/startup.tcl
Log:
less weird error messages for unknown commands. Check if command exists before trying it.
Modified: trunk/src/helper/startup.tcl
===================================================================
--- trunk/src/helper/startup.tcl 2009-05-18 07:10:48 UTC (rev 1809)
+++ trunk/src/helper/startup.tcl 2009-05-18 13:07:37 UTC (rev 1810)
@@ -88,9 +88,10 @@
# do the name mangling from "flash banks" to "flash_banks"
if {[llength $args]>=2} {
set cmd_name "[lindex $args 0]_[lindex $args 1]"
- # Fix?? add a check here if this is a command?
- # we'll strip away args until we fail anyway...
- return [eval "$cmd_name [lrange $args 2 end]"]
+ if {[catch {info body $cmd_name}]==0} {
+ # the command exists, try it...
+ return [eval "$cmd_name [lrange $args 2 end]"]
+ }
}
# This really is an unknown command.
return -code error "Unknown command: $args"
|
|
From: oharboe at B. <oh...@ma...> - 2009-05-18 09:10:57
|
Author: oharboe
Date: 2009-05-18 09:10:48 +0200 (Mon, 18 May 2009)
New Revision: 1809
Modified:
trunk/src/target/arm7_9_common.c
Log:
Dean Glazeski <dn...@gm...> fixed bug in checking of clocked back data in arm7_9_execute_fast_sys_speed. Not reported. There is a chance that this bug hid a deeper problem since it only partially disabled the check(mask & value were equal).
Modified: trunk/src/target/arm7_9_common.c
===================================================================
--- trunk/src/target/arm7_9_common.c 2009-05-18 07:04:58 UTC (rev 1808)
+++ trunk/src/target/arm7_9_common.c 2009-05-18 07:10:48 UTC (rev 1809)
@@ -50,6 +50,12 @@
int handle_arm7_9_dcc_downloads_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
int handle_arm7_9_etm_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc);
+/**
+ * Clear watchpoints for an ARM7/9 target.
+ *
+ * @param arm7_9 Pointer to the common struct for an ARM7/9 target
+ * @return JTAG error status after executing queue
+ */
static int arm7_9_clear_watchpoints(arm7_9_common_t *arm7_9)
{
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
@@ -62,6 +68,13 @@
return jtag_execute_queue();
}
+/**
+ * Assign a watchpoint to one of the two available hardware comparators in an
+ * ARM7 or ARM9 target.
+ *
+ * @param arm7_9 Pointer to the common struct for an ARM7/9 target
+ * @param breakpoint Pointer to the breakpoint to be used as a watchpoint
+ */
static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint)
{
if (!arm7_9->wp0_used)
@@ -82,7 +95,13 @@
}
}
-/* set up embedded ice registers */
+/**
+ * Setup an ARM7/9 target's embedded ICE registers for software breakpoints.
+ *
+ * @param arm7_9 Pointer to common struct for ARM7/9 targets
+ * @return Error codes if there is a problem finding a watchpoint or the result
+ * of executing the JTAG queue
+ */
static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
{
if (arm7_9->sw_breakpoints_added)
@@ -137,7 +156,12 @@
return jtag_execute_queue();
}
-/* set things up after a reset / on startup */
+/**
+ * Setup the common pieces for an ARM7/9 target after reset or on startup.
+ *
+ * @param target Pointer to an ARM7/9 target to setup
+ * @return Result of clearing the watchpoints on the target
+ */
int arm7_9_setup(target_t *target)
{
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -146,6 +170,18 @@
return arm7_9_clear_watchpoints(arm7_9);
}
+/**
+ * Retrieves the architecture information pointers for ARMv4/5 and ARM7/9
+ * targets. A return of ERROR_OK signifies that the target is a valid target
+ * and that the pointers have been set properly.
+ *
+ * @param target Pointer to the target device to get the pointers from
+ * @param armv4_5_p Pointer to be filled in with the common struct for ARMV4/5
+ * targets
+ * @param arm7_9_p Pointer to be filled in with the common struct for ARM7/9
+ * targets
+ * @return ERROR_OK if successful
+ */
int arm7_9_get_arch_pointers(target_t *target, armv4_5_common_t **armv4_5_p, arm7_9_common_t **arm7_9_p)
{
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -167,8 +203,16 @@
return ERROR_OK;
}
-/* we set up the breakpoint even if it is already set. Some action, e.g. reset
- * might have erased the values in embedded ice
+/**
+ * Set either a hardware or software breakpoint on an ARM7/9 target. The
+ * breakpoint is set up even if it is already set. Some actions, e.g. reset,
+ * might have erased the values in Embedded ICE.
+ *
+ * @param target Pointer to the target device to set the breakpoints on
+ * @param breakpoint Pointer to the breakpoint to be set
+ * @return For hardware breakpoints, this is the result of executing the JTAG
+ * queue. For software breakpoints, this will be the status of the
+ * required memory reads and writes
*/
int arm7_9_set_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
@@ -280,6 +324,18 @@
return retval;
}
+/**
+ * Unsets an existing breakpoint on an ARM7/9 target. If it is a hardware
+ * breakpoint, the watchpoint used will be freed and the Embedded ICE registers
+ * will be updated. Otherwise, the software breakpoint will be restored to its
+ * original instruction if it hasn't already been modified.
+ *
+ * @param target Pointer to ARM7/9 target to unset the breakpoint from
+ * @param breakpoint Pointer to breakpoint to be unset
+ * @return For hardware breakpoints, this is the result of executing the JTAG
+ * queue. For software breakpoints, this will be the status of the
+ * required memory reads and writes
+ */
int arm7_9_unset_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval = ERROR_OK;
@@ -347,6 +403,15 @@
return retval;
}
+/**
+ * Add a breakpoint to an ARM7/9 target. This makes sure that there are no
+ * dangling breakpoints and that the desired breakpoint can be added.
+ *
+ * @param target Pointer to the target ARM7/9 device to add a breakpoint to
+ * @param breakpoint Pointer to the breakpoint to be added
+ * @return An error status if there is a problem adding the breakpoint or the
+ * result of setting the breakpoint
+ */
int arm7_9_add_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -388,6 +453,16 @@
return arm7_9_set_breakpoint(target, breakpoint);
}
+/**
+ * Removes a breakpoint from an ARM7/9 target. This will make sure there are no
+ * dangling breakpoints and updates available watchpoints if it is a hardware
+ * breakpoint.
+ *
+ * @param target Pointer to the target to have a breakpoint removed
+ * @param breakpoint Pointer to the breakpoint to be removed
+ * @return Error status if there was a problem unsetting the breakpoint or the
+ * watchpoints could not be cleared
+ */
int arm7_9_remove_breakpoint(struct target_s *target, breakpoint_t *breakpoint)
{
int retval = ERROR_OK;
@@ -415,6 +490,16 @@
return ERROR_OK;
}
+/**
+ * Sets a watchpoint for an ARM7/9 target in one of the watchpoint units. It is
+ * considered a bug to call this function when there are no available watchpoint
+ * units.
+ *
+ * @param target Pointer to an ARM7/9 target to set a watchpoint on
+ * @param watchpoint Pointer to the watchpoint to be set
+ * @return Error status if watchpoint set fails or the result of executing the
+ * JTAG queue
+ */
int arm7_9_set_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
@@ -479,6 +564,14 @@
return ERROR_OK;
}
+/**
+ * Unset an existing watchpoint and clear the used watchpoint unit.
+ *
+ * @param target Pointer to the target to have the watchpoint removed
+ * @param watchpoint Pointer to the watchpoint to be removed
+ * @return Error status while trying to unset the watchpoint or the result of
+ * executing the JTAG queue
+ */
int arm7_9_unset_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
@@ -520,6 +613,14 @@
return ERROR_OK;
}
+/**
+ * Add a watchpoint to an ARM7/9 target. If there are no watchpoint units
+ * available, an error response is returned.
+ *
+ * @param target Pointer to the ARM7/9 target to add a watchpoint to
+ * @param watchpoint Pointer to the watchpoint to be added
+ * @return Error status while trying to add the watchpoint
+ */
int arm7_9_add_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
armv4_5_common_t *armv4_5 = target->arch_info;
@@ -546,6 +647,14 @@
return ERROR_OK;
}
+/**
+ * Remove a watchpoint from an ARM7/9 target. The watchpoint will be unset and
+ * the used watchpoint unit will be reopened.
+ *
+ * @param target Pointer to the target to remove a watchpoint from
+ * @param watchpoint Pointer to the watchpoint to be removed
+ * @return Result of trying to unset the watchpoint
+ */
int arm7_9_remove_watchpoint(struct target_s *target, watchpoint_t *watchpoint)
{
int retval = ERROR_OK;
@@ -565,6 +674,15 @@
return ERROR_OK;
}
+/**
+ * Restarts the target by sending a RESTART instruction and moving the JTAG
+ * state to IDLE. This includes a timeout waiting for DBGACK and SYSCOMP to be
+ * asserted by the processor.
+ *
+ * @param target Pointer to target to issue commands to
+ * @return Error status if there is a timeout or a problem while executing the
+ * JTAG queue
+ */
int arm7_9_execute_sys_speed(struct target_s *target)
{
int retval;
@@ -610,6 +728,14 @@
return ERROR_OK;
}
+/**
+ * Restarts the target by sending a RESTART instruction and moving the JTAG
+ * state to IDLE. This validates that DBGACK and SYSCOMP are set without
+ * waiting until they are.
+ *
+ * @param target Pointer to the target to issue commands to
+ * @return Always ERROR_OK
+ */
int arm7_9_execute_fast_sys_speed(struct target_s *target)
{
static int set=0;
@@ -642,7 +768,7 @@
}
/* read debug status register */
- embeddedice_read_reg_w_check(dbg_stat, check_value, check_value);
+ embeddedice_read_reg_w_check(dbg_stat, check_value, check_mask);
return ERROR_OK;
}
|
|
From: ntfreak at B. <nt...@ma...> - 2009-05-18 09:05:01
|
Author: ntfreak
Date: 2009-05-18 09:04:58 +0200 (Mon, 18 May 2009)
New Revision: 1808
Modified:
trunk/src/target/board/crossbow_tech_imote2.cfg
trunk/src/target/board/digi_connectcore_wi-9c.cfg
trunk/src/target/board/hitex_stm32-performancestick.cfg
trunk/src/target/board/hitex_str9-comstick.cfg
trunk/src/target/board/linksys_nslu2.cfg
trunk/src/target/board/pxa255_sst.cfg
trunk/src/target/board/str910-eval.cfg
trunk/src/target/board/zy1000.cfg
trunk/src/target/interface/hitex_str9-comstick.cfg
Log:
- add missing svn props from svn 1798 commit
Modified: trunk/src/target/board/crossbow_tech_imote2.cfg
===================================================================
--- trunk/src/target/board/crossbow_tech_imote2.cfg 2009-05-18 07:02:12 UTC (rev 1807)
+++ trunk/src/target/board/crossbow_tech_imote2.cfg 2009-05-18 07:04:58 UTC (rev 1808)
@@ -1,46 +1,46 @@
-# Crossbow Technology iMote2
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imote2
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-# PXA271 and an Intel Strataflash of 32 Megabytes (p30)
-#
-# Marvell/Intel PXA270 Script
-# set jtag_nsrst_delay to the delay introduced by your reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_nsrst_delay 800
-# set the jtag_ntrst_delay to the delay introduced by a reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_ntrst_delay 0
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst separate
-#jtag scan chain
-
-jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
-$_TARGETNAME configure -work-area-virt 0x0x5c000000 -work-area-phys 0x0x5c000000 -work-area-size 0x10000 -work-area-backup 1
-# maps to PXA internal RAM. If you are using a PXA255
-# you must initialize SDRAM or leave this option off
-
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-# works for P30 flash
-flash bank cfi 0x00000000 0x2000000 2 2 0
+# Crossbow Technology iMote2
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME imote2
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+# PXA271 and an Intel Strataflash of 32 Megabytes (p30)
+#
+# Marvell/Intel PXA270 Script
+# set jtag_nsrst_delay to the delay introduced by your reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_nsrst_delay 800
+# set the jtag_ntrst_delay to the delay introduced by a reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_ntrst_delay 0
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst separate
+#jtag scan chain
+
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
+$_TARGETNAME configure -work-area-virt 0x0x5c000000 -work-area-phys 0x0x5c000000 -work-area-size 0x10000 -work-area-backup 1
+# maps to PXA internal RAM. If you are using a PXA255
+# you must initialize SDRAM or leave this option off
+
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+# works for P30 flash
+flash bank cfi 0x00000000 0x2000000 2 2 0
Property changes on: trunk/src/target/board/crossbow_tech_imote2.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/target/board/digi_connectcore_wi-9c.cfg
===================================================================
--- trunk/src/target/board/digi_connectcore_wi-9c.cfg 2009-05-18 07:02:12 UTC (rev 1807)
+++ trunk/src/target/board/digi_connectcore_wi-9c.cfg 2009-05-18 07:04:58 UTC (rev 1808)
@@ -1,127 +1,127 @@
-######################################
-# Target: DIGI ConnectCore Wi-9C
-######################################
-
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ns9360
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # This config file was defaulting to big endian..
- set _ENDIAN big
-}
-
-
-# What's a good fallback frequency for this board if RCLK is
-# not available??
-jtag_rclk 1000
-
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0xFFFFFFFF
-}
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 0
-
-
-######################
-# Target configuration
-######################
-
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-$_TARGETNAME configure -event reset-init {
- mww 0x90600104 0x33313333
- mww 0xA0700000 0x00000001 # Enable the memory controller.
- mww 0xA0700024 0x00000006 # Set the refresh counter 6
- mww 0xA0700028 0x00000001 #
- mww 0xA0700030 0x00000001 # Set the precharge period
- mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
- mww 0xA070003C 0x00000001 # tAPR
- mww 0xA0700040 0x00000005 # tDAL
- mww 0xA0700044 0x00000001 # tWR
- mww 0xA0700048 0x00000006 # tRC 32 clock cycles
- mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
- mww 0xA0700054 0x00000001 # tRRD
- mww 0xA0700058 0x00000001 # tMRD
- mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
- mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
- mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
- mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
- #
- mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
- #
- mww 0xA0700020 0x00000103 # issue SDRAM PALL command
- #
- mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible
- #
- # Add some dummy writes to give the SDRAM time to settle, it needs two
- # AHB clock cycles, here we poke in the debugger flag, this lets
- # the software know that we are in the debugger
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- #
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- #
- mww 0xA0700024 0x00000030 # Set the refresh counter to 30
- mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
- #
- # Next we perform a read of RAM.
- # mw = move word.
- mdw 0x00022000
- # mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
- #
- mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
- mww 0xA0700100 0x00084280 # Enable buffer access
- mww 0xA0700120 0x00084280 # Enable buffer access
- mww 0xA0700140 0x00084280 # Enable buffer access
- mww 0xA0700160 0x00084280 # Enable buffer access
-
- #Set byte lane state (static mem 1)"
- mww 0xA0700220, 0x00000082
- #Flash Start
- mww 0xA09001F8, 0x50000000
- #Flash Mask Reg
- mww 0xA09001FC, 0xFF000001
- mww 0xA0700028, 0x00000001
-
- # RAMAddr = 0x00020000
- # RAMSize = 0x00004000
-
- # Set the processor mode
- reg cpsr 0xd3
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
-
-#####################
-# Flash configuration
-#####################
-
-#M29DW323DB - not working
-#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x50000000 0x0400000 2 2 0
-
-
-
+######################################
+# Target: DIGI ConnectCore Wi-9C
+######################################
+
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME ns9360
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # This config file was defaulting to big endian..
+ set _ENDIAN big
+}
+
+
+# What's a good fallback frequency for this board if RCLK is
+# not available??
+jtag_rclk 1000
+
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xFFFFFFFF
+}
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 0
+
+
+######################
+# Target configuration
+######################
+
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+$_TARGETNAME configure -event reset-init {
+ mww 0x90600104 0x33313333
+ mww 0xA0700000 0x00000001 # Enable the memory controller.
+ mww 0xA0700024 0x00000006 # Set the refresh counter 6
+ mww 0xA0700028 0x00000001 #
+ mww 0xA0700030 0x00000001 # Set the precharge period
+ mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
+ mww 0xA070003C 0x00000001 # tAPR
+ mww 0xA0700040 0x00000005 # tDAL
+ mww 0xA0700044 0x00000001 # tWR
+ mww 0xA0700048 0x00000006 # tRC 32 clock cycles
+ mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
+ mww 0xA0700054 0x00000001 # tRRD
+ mww 0xA0700058 0x00000001 # tMRD
+ mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
+ mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
+ mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
+ mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
+ #
+ mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
+ mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
+ mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
+ mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
+ #
+ mww 0xA0700020 0x00000103 # issue SDRAM PALL command
+ #
+ mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible
+ #
+ # Add some dummy writes to give the SDRAM time to settle, it needs two
+ # AHB clock cycles, here we poke in the debugger flag, this lets
+ # the software know that we are in the debugger
+ mww 0xA0900000 0x00000002
+ mww 0xA0900000 0x00000002
+ mww 0xA0900000 0x00000002
+ mww 0xA0900000 0x00000002
+ mww 0xA0900000 0x00000002
+ #
+ mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
+ #
+ mww 0xA0700024 0x00000030 # Set the refresh counter to 30
+ mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
+ #
+ # Next we perform a read of RAM.
+ # mw = move word.
+ mdw 0x00022000
+ # mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
+ #
+ mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
+ mww 0xA0700100 0x00084280 # Enable buffer access
+ mww 0xA0700120 0x00084280 # Enable buffer access
+ mww 0xA0700140 0x00084280 # Enable buffer access
+ mww 0xA0700160 0x00084280 # Enable buffer access
+
+ #Set byte lane state (static mem 1)"
+ mww 0xA0700220, 0x00000082
+ #Flash Start
+ mww 0xA09001F8, 0x50000000
+ #Flash Mask Reg
+ mww 0xA09001FC, 0xFF000001
+ mww 0xA0700028, 0x00000001
+
+ # RAMAddr = 0x00020000
+ # RAMSize = 0x00004000
+
+ # Set the processor mode
+ reg cpsr 0xd3
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
+
+#####################
+# Flash configuration
+#####################
+
+#M29DW323DB - not working
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>
+flash bank cfi 0x50000000 0x0400000 2 2 0
+
+
+
Property changes on: trunk/src/target/board/digi_connectcore_wi-9c.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/target/board/hitex_stm32-performancestick.cfg
===================================================================
--- trunk/src/target/board/hitex_stm32-performancestick.cfg 2009-05-18 07:02:12 UTC (rev 1807)
+++ trunk/src/target/board/hitex_stm32-performancestick.cfg 2009-05-18 07:04:58 UTC (rev 1808)
@@ -1,50 +1,50 @@
-# Hitex stm32 performance stick
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32_hitex
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# set jtag speed
-jtag_khz 500
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-#jtag scan chain
-# The CPU
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # See STM Document RM0008
- # Section 26.6.3
- set _CPUTAPID 0x3ba00477
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# The boundery scan register, leave the "expected-id" undefined.
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1
-
-# configure str750 connected to jtag chain
-jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-
-#
-flash bank stm32x 0 0 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
+# Hitex stm32 performance stick
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32_hitex
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+# set jtag speed
+jtag_khz 500
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+# The CPU
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.3
+ set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# The boundery scan register, leave the "expected-id" undefined.
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1
+
+# configure str750 connected to jtag chain
+jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
+
+#
+flash bank stm32x 0 0 0 0 0
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
Property changes on: trunk/src/target/board/hitex_stm32-performancestick.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/target/board/hitex_str9-comstick.cfg
===================================================================
--- trunk/src/target/board/hitex_str9-comstick.cfg 2009-05-18 07:02:12 UTC (rev 1807)
+++ trunk/src/target/board/hitex_str9-comstick.cfg 2009-05-18 07:04:58 UTC (rev 1808)
@@ -1,72 +1,72 @@
-# Hitex STR9-comStick
-# http://www.hitex.com/index.php?id=383
-# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.
-
-source [find interface/hitex_str9-comstick.cfg]
-
-# set jtag speed
-jtag_khz 3000
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists FLASHTAPID ] } {
- set _FLASHTAPID $FLASHTAPID
-} else {
- set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID ] } {
- set _BSTAPID $BSTAPID
-} else {
- # Found on STR9-comStick, revision STR912CS-A1
- set _BSTAPID1 0x1457f041
- # Found on STR9-comStick, revision STR912CS-A2
- set _BSTAPID2 0x2457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- #jtag_rclk 3000
-
- # -- Enable 96K RAM
- # PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
-
- str9x flash_config 0 4 2 0 0x80000
- flash protect 0 0 7 off
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
+# Hitex STR9-comStick
+# http://www.hitex.com/index.php?id=383
+# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.
+
+source [find interface/hitex_str9-comstick.cfg]
+
+# set jtag speed
+jtag_khz 3000
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists FLASHTAPID ] } {
+ set _FLASHTAPID $FLASHTAPID
+} else {
+ set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ # Found on STR9-comStick, revision STR912CS-A1
+ set _BSTAPID1 0x1457f041
+ # Found on STR9-comStick, revision STR912CS-A2
+ set _BSTAPID2 0x2457f041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
+
+$_TARGETNAME configure -event reset-init {
+ # We can increase speed now that we know the target is halted.
+ #jtag_rclk 3000
+
+ # -- Enable 96K RAM
+ # PFQBC enabled / DTCM & AHB wait-states disabled
+ mww 0x5C002034 0x0191
+
+ str9x flash_config 0 4 2 0 0x80000
+ flash protect 0 0 7 off
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank str9x 0x00000000 0x00080000 0 0 0
+flash bank str9x 0x00080000 0x00008000 0 0 0
Property changes on: trunk/src/target/board/hitex_str9-comstick.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/target/board/linksys_nslu2.cfg
===================================================================
--- trunk/src/target/board/linksys_nslu2.cfg 2009-05-18 07:02:12 UTC (rev 1807)
+++ trunk/src/target/board/linksys_nslu2.cfg 2009-05-18 07:04:58 UTC (rev 1808)
@@ -1,8 +1,8 @@
-# This is for the LinkSys (CISCO) NSLU2 board
-# It is an Intel XSCALE IXP420 CPU.
-
-source [find target/ixp42x.cfg]
-# The _TARGETNAME is set by the above.
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
-
+# This is for the LinkSys (CISCO) NSLU2 board
+# It is an Intel XSCALE IXP420 CPU.
+
+source [find target/ixp42x.cfg]
+# The _TARGETNAME is set by the above.
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
+
Property changes on: trunk/src/target/board/linksys_nslu2.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/target/board/pxa255_sst.cfg
===================================================================
--- trunk/src/target/board/pxa255_sst.cfg 2009-05-18 07:02:12 UTC (rev 1807)
+++ trunk/src/target/board/pxa255_sst.cfg 2009-05-18 07:04:58 UTC (rev 1808)
@@ -1,15 +1,15 @@
-# A PXA255 test board with SST 39LF400A flash
-#
-# At reset the memory map is as follows. Note that
-# the memory map changes later on as the application
-# starts...
-#
-# RAM at 0x4000000
-# Flash at 0x00000000
-#
-source [find target/pxa255.cfg]
-# Target name is set by above
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
-# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options]
-flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
-
+# A PXA255 test board with SST 39LF400A flash
+#
+# At reset the memory map is as follows. Note that
+# the memory map changes later on as the application
+# starts...
+#
+# RAM at 0x4000000
+# Flash at 0x00000000
+#
+source [find target/pxa255.cfg]
+# Target name is set by above
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
+# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options]
+flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
+
Property changes on: trunk/src/target/board/pxa255_sst.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/target/board/str910-eval.cfg
===================================================================
--- trunk/src/target/board/str910-eval.cfg 2009-05-18 07:02:12 UTC (rev 1807)
+++ trunk/src/target/board/str910-eval.cfg 2009-05-18 07:04:58 UTC (rev 1808)
@@ -1,61 +1,61 @@
-# str910-eval eval board
-#
-# Need reset scripts
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists FLASHTAPID ] } {
- set _FLASHTAPID $FLASHTAPID
-} else {
- set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
-
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID ] } {
- set _BSTAPID $BSTAPID
-} else {
- set _BSTAPID 0x1457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
-
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- #jtag_rclk 3000
-
- # -- Enable 96K RAM
- # PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
-
- str9x flash_config 0 4 2 0 0x80000
- flash protect 0 0 7 off
-}
-
-#flash bank str9x <base> <size> 0 0 <target#> <variant>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
+# str910-eval eval board
+#
+# Need reset scripts
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists FLASHTAPID ] } {
+ set _FLASHTAPID $FLASHTAPID
+} else {
+ set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ set _BSTAPID 0x1457f041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+ # We can increase speed now that we know the target is halted.
+ #jtag_rclk 3000
+
+ # -- Enable 96K RAM
+ # PFQBC enabled / DTCM & AHB wait-states disabled
+ mww 0x5C002034 0x0191
+
+ str9x flash_config 0 4 2 0 0x80000
+ flash protect 0 0 7 off
+}
+
+#flash bank str9x <base> <size> 0 0 <target#> <variant>
+flash bank str9x 0x00000000 0x00080000 0 0 0
+flash bank str9x 0x00080000 0x00008000 0 0 0
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
Property changes on: trunk/src/target/board/str910-eval.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/target/board/zy1000.cfg
===================================================================
--- trunk/src/target/board/zy1000.cfg 2009-05-18 07:02:12 UTC (rev 1807)
+++ trunk/src/target/board/zy1000.cfg 2009-05-18 07:04:58 UTC (rev 1808)
@@ -1,110 +1,110 @@
-#Script for ZY1000
-
-#Atmel ties SRST & TRST together, at which point it makes
-#no sense to use TRST, but use TMS instead.
-#
-#The annoying thing with tying SRST & TRST together is that
-#there is no way to halt the CPU *before and during* the
-#SRST reset, which means that the CPU will run a number
-#of cycles before it can be halted(as much as milliseconds).
-reset_config srst_only srst_pulls_trst
-
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME zy1000
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x1f0f0f0f
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-# at CPU CLK <32kHz this must be disabled
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
-$_TARGETNAME configure -event reset-init {
- # Set up chip selects & timings
- mww 0xFFE00000 0x0100273D
- mww 0xFFE00004 0x08002125
- mww 0xFFEe0008 0x02002125
- mww 0xFFE0000c 0x03002125
- mww 0xFFE00010 0x40000000
- mww 0xFFE00014 0x50000000
- mww 0xFFE00018 0x60000000
- mww 0xFFE0001c 0x70000000
- mww 0xFFE00020 0x00000001
- mww 0xFFE00024 0x00000000
-
- # remap
- mww 0xFFFFF124 0xFFFFFFFF
- mww 0xffff0010 0x100
- mww 0xffff0034 0x100
-
- #disable 16x5x UART interrupts
- mww 0x08020004 0
-}
-
-# required for usable performance. Used for lots of
-# other things than flash programming.
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
-
-jtag_khz 16000
-
-
-proc production_info {} {
- return "Serial number is official MAC number. Format XXXXXXXXXXXX"
-}
-
-# There is no return value from this procedure. If it is
-# successful it does not throw an exception
-#
-# Progress messages are output via puts
-proc production {firmwarefile serialnumber} {
- if {[string length $serialnumber]!=12} {
- puts "Invalid serial number"
- return
- }
-
- puts "Power cycling target"
- power off
- sleep 3000
- power on
- sleep 1000
- reset init
- flash write_image erase $firmwarefile 0x1000000 bin
- verify_image $firmwarefile 0x1000000 bin
-
- # Big endian... weee!!!!
- puts "Setting MAC number to $serialnumber"
- flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2 3][string range $serialnumber 0 1]0000" 1
- flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10 11][string range $serialnumber 8 9][string range $serialnumber 6 7][string range $serialnumber 4 5]" 1
- puts "Production successful"
-}
-
-
-proc production_test {} {
- power on
- sleep 1000
- target_request debugmsgs enable
- reset run
- sleep 25000
- target_request debugmsgs disable
- return "See IP address above..."
-}
+#Script for ZY1000
+
+#Atmel ties SRST & TRST together, at which point it makes
+#no sense to use TRST, but use TMS instead.
+#
+#The annoying thing with tying SRST & TRST together is that
+#there is no way to halt the CPU *before and during* the
+#SRST reset, which means that the CPU will run a number
+#of cycles before it can be halted(as much as milliseconds).
+reset_config srst_only srst_pulls_trst
+
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME zy1000
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x1f0f0f0f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+
+# at CPU CLK <32kHz this must be disabled
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
+$_TARGETNAME configure -event reset-init {
+ # Set up chip selects & timings
+ mww 0xFFE00000 0x0100273D
+ mww 0xFFE00004 0x08002125
+ mww 0xFFEe0008 0x02002125
+ mww 0xFFE0000c 0x03002125
+ mww 0xFFE00010 0x40000000
+ mww 0xFFE00014 0x50000000
+ mww 0xFFE00018 0x60000000
+ mww 0xFFE0001c 0x70000000
+ mww 0xFFE00020 0x00000001
+ mww 0xFFE00024 0x00000000
+
+ # remap
+ mww 0xFFFFF124 0xFFFFFFFF
+ mww 0xffff0010 0x100
+ mww 0xffff0034 0x100
+
+ #disable 16x5x UART interrupts
+ mww 0x08020004 0
+}
+
+# required for usable performance. Used for lots of
+# other things than flash programming.
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
+
+jtag_khz 16000
+
+
+proc production_info {} {
+ return "Serial number is official MAC number. Format XXXXXXXXXXXX"
+}
+
+# There is no return value from this procedure. If it is
+# successful it does not throw an exception
+#
+# Progress messages are output via puts
+proc production {firmwarefile serialnumber} {
+ if {[string length $serialnumber]!=12} {
+ puts "Invalid serial number"
+ return
+ }
+
+ puts "Power cycling target"
+ power off
+ sleep 3000
+ power on
+ sleep 1000
+ reset init
+ flash write_image erase $firmwarefile 0x1000000 bin
+ verify_image $firmwarefile 0x1000000 bin
+
+ # Big endian... weee!!!!
+ puts "Setting MAC number to $serialnumber"
+ flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2 3][string range $serialnumber 0 1]0000" 1
+ flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10 11][string range $serialnumber 8 9][string range $serialnumber 6 7][string range $serialnumber 4 5]" 1
+ puts "Production successful"
+}
+
+
+proc production_test {} {
+ power on
+ sleep 1000
+ target_request debugmsgs enable
+ reset run
+ sleep 25000
+ target_request debugmsgs disable
+ return "See IP address above..."
+}
Property changes on: trunk/src/target/board/zy1000.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: trunk/src/target/interface/hitex_str9-comstick.cfg
===================================================================
--- trunk/src/target/interface/hitex_str9-comstick.cfg 2009-05-18 07:02:12 UTC (rev 1807)
+++ trunk/src/target/interface/hitex_str9-comstick.cfg 2009-05-18 07:04:58 UTC (rev 1808)
@@ -1,11 +1,11 @@
-#
-# Hitex STR9-comStick
-#
-# http://www.hitex.com/index.php?id=383
-#
-
-interface ft2232
-ft2232_device_desc "STR9-comStick A"
-ft2232_layout comstick
-ft2232_vid_pid 0x0640 0x002c
-
+#
+# Hitex STR9-comStick
+#
+# http://www.hitex.com/index.php?id=383
+#
+
+interface ft2232
+ft2232_device_desc "STR9-comStick A"
+ft2232_layout comstick
+ft2232_vid_pid 0x0640 0x002c
+
Property changes on: trunk/src/target/interface/hitex_str9-comstick.cfg
___________________________________________________________________
Name: svn:eol-style
+ native
|
|
From: oharboe at B. <oh...@ma...> - 2009-05-18 09:02:21
|
Author: oharboe
Date: 2009-05-18 09:02:12 +0200 (Mon, 18 May 2009)
New Revision: 1807
Modified:
trunk/src/target/arm11.c
trunk/src/target/arm11.h
trunk/src/target/arm11_dbgtap.c
Log:
Michael Bruck <mb...@di...> ARM11 cleanup stale dependencies with generic arm code; added comments and whitespace fixes
Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c 2009-05-18 04:47:06 UTC (rev 1806)
+++ trunk/src/target/arm11.c 2009-05-18 07:02:12 UTC (rev 1807)
@@ -1,5 +1,6 @@
/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
+ * Michael Bruck *
* *
* Copyright (C) 2008 Oyvind Harboe oyv...@zy... *
* *
@@ -336,7 +337,9 @@
if (*dscr & ARM11_DSCR_CORE_HALTED)
{
/** \todo TODO: this needs further scrutiny because
- * arm11_on_enter_debug_state() never gets properly called
+ * arm11_on_enter_debug_state() never gets properly called.
+ * As a result we don't read the actual register states from
+ * the target.
*/
arm11->target->state = TARGET_HALTED;
@@ -389,8 +392,8 @@
scan_field_t chain5_fields[3];
arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
- arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
- arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
+ arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
+ arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
@@ -679,7 +682,7 @@
enum target_state old_state = target->state;
LOG_DEBUG("enter TARGET_HALTED");
- target->state = TARGET_HALTED;
+ target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
arm11_on_enter_debug_state(arm11);
@@ -692,7 +695,7 @@
if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
{
LOG_DEBUG("enter TARGET_RUNNING");
- target->state = TARGET_RUNNING;
+ target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
}
}
@@ -1369,7 +1372,6 @@
int timeout_ms, void *arch_info)
{
arm11_common_t *arm11 = target->arch_info;
- armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
// enum armv4_5_state core_state = arm11->core_state;
// enum armv4_5_mode core_mode = arm11->core_mode;
u32 context[16];
@@ -1378,11 +1380,6 @@
int retval = ERROR_OK;
LOG_DEBUG("Running algorithm");
- if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
- {
- LOG_ERROR("current target isn't an ARMV4/5 target");
- return ERROR_TARGET_INVALID;
- }
if (target->state != TARGET_HALTED)
{
@@ -1441,6 +1438,12 @@
exit(-1);
}
*/
+
+
+/* arm11 at this point only supports ARM not THUMB mode
+ however if this test needs to be reactivated the current state can be read back
+ from CPSR */
+#if 0
if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
{
LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
@@ -1448,6 +1451,7 @@
arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
arm11->reg_list[ARM11_RC_CPSR].valid = 1;
}
+#endif
if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
{
@@ -1535,12 +1539,6 @@
arm11->target = target;
- /* prepare JTAG information for the new target */
- arm11->jtag_info.tap = target->tap;
- arm11->jtag_info.scann_size = 5;
-
- CHECK_RETVAL(arm_jtag_setup_connection(&arm11->jtag_info));
-
if (target->tap==NULL)
return ERROR_FAIL;
@@ -1956,7 +1954,7 @@
RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)",
memwrite_error_fatal)
- )
+ ) /* memwrite */
RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
memrw_no_increment)
@@ -1972,7 +1970,7 @@
RC_FINAL( "mcr", "Write Coprocessor register",
arm11_handle_mcr)
- )
+ ) /* arm11 */
return ERROR_OK;
}
Modified: trunk/src/target/arm11.h
===================================================================
--- trunk/src/target/arm11.h 2009-05-18 04:47:06 UTC (rev 1806)
+++ trunk/src/target/arm11.h 2009-05-18 07:02:12 UTC (rev 1807)
@@ -1,5 +1,6 @@
/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
+ * Michael Bruck *
* *
* Copyright (C) 2008 Georg Acher <ac...@in...> *
* *
@@ -22,7 +23,9 @@
#ifndef ARM11_H
#define ARM11_H
-#include "embeddedice.h"
+#include "target.h"
+#include "register.h"
+#include "jtag.h"
#define asizeof(x) (sizeof(x) / sizeof((x)[0]))
@@ -78,8 +81,6 @@
{
target_t * target; /**< Reference back to the owner */
- arm_jtag_t jtag_info; /**< Handler to access assigned JTAG device */
-
/** \name Processor type detection */
/*@{*/
Modified: trunk/src/target/arm11_dbgtap.c
===================================================================
--- trunk/src/target/arm11_dbgtap.c 2009-05-18 04:47:06 UTC (rev 1806)
+++ trunk/src/target/arm11_dbgtap.c 2009-05-18 07:02:12 UTC (rev 1807)
@@ -1,5 +1,6 @@
/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
+ * Michael Bruck *
* *
* Copyright (C) 2008 Oyvind Harboe oyv...@zy... *
* *
@@ -81,7 +82,7 @@
*/
void arm11_setup_field(arm11_common_t * arm11, int num_bits, void * out_data, void * in_data, scan_field_t * field)
{
- field->tap = arm11->jtag_info.tap;
+ field->tap = arm11->target->tap;
field->num_bits = num_bits;
field->out_value = out_data;
field->in_value = in_data;
@@ -99,7 +100,7 @@
void arm11_add_IR(arm11_common_t * arm11, u8 instr, tap_state_t state)
{
jtag_tap_t *tap;
- tap = arm11->jtag_info.tap;
+ tap = arm11->target->tap;
if (buf_get_u32(tap->cur_instr, 0, 5) == instr)
{
@@ -211,7 +212,8 @@
* same as CP14 c1
*
* \param arm11 Target state variable.
- * \return DSCR content
+ * \param value DSCR content
+ * \return Error status
*
* \remarks This is a stand-alone function that executes the JTAG command queue.
*/
|
|
From: kc8apf at B. <kc...@ma...> - 2009-05-18 06:47:10
|
Author: kc8apf
Date: 2009-05-18 06:47:06 +0200 (Mon, 18 May 2009)
New Revision: 1806
Modified:
trunk/doc/openocd.texi
Log:
Relocate documentation on working area to better align with use of new syntax. Provided by David Brownell <da...@pa...>
Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi 2009-05-18 04:45:42 UTC (rev 1805)
+++ trunk/doc/openocd.texi 2009-05-18 04:47:06 UTC (rev 1806)
@@ -2082,13 +2082,23 @@
@section Target Config/Cget Options
These options can be specified when the target is created, or later
via the configure option or to query the target via cget.
+
+You should specify a working area if you can; typically it uses some
+on-chip SRAM. Such a working area can speed up many things, including bulk
+writes to target memory; flash operations like checking to see if memory needs
+to be erased; GDB memory checksumming; and may help perform otherwise
+unavailable operations (like some coprocessor operations on ARM7/9 systems).
@itemize @bullet
@item @b{-type} - returns the target type
@item @b{-event NAME BODY} see Target events
-@item @b{-work-area-virt [ADDRESS]} specify/set the work area
-@item @b{-work-area-phys [ADDRESS]} specify/set the work area
+@item @b{-work-area-virt [ADDRESS]} specify/set the work area base address
+which will be used when an MMU is active.
+@item @b{-work-area-phys [ADDRESS]} specify/set the work area base address
+which will be used when an MMU is inactive.
@item @b{-work-area-size [ADDRESS]} specify/set the work area
-@item @b{-work-area-backup [0|1]} does the work area get backed up
+@item @b{-work-area-backup [0|1]} does the work area get backed up;
+by default, it doesn't. When possible, use a working_area that doesn't
+need to be backed up, since performing a backup slows down operations.
@item @b{-endian [big|little]}
@item @b{-variant [NAME]} some chips have variants OpenOCD needs to know about
@item @b{-chain-position DOTTED.NAME} the tap name this target refers to.
@@ -2144,15 +2154,6 @@
@end example
@* The target# is a the 0 based target numerical index.
-This command specifies a working area for the debugger to use. This
-may be used to speed-up downloads to target memory and flash
-operations, or to perform otherwise unavailable operations (some
-coprocessor operations on ARM7/9 systems, for example). The last
-parameter decides whether the memory should be preserved
-(<@var{backup}>) or can simply be overwritten (<@var{nobackup}>). If
-possible, use a working_area that doesn't need to be backed up, as
-performing a backup slows down operation.
-
@node Flash Configuration
@chapter Flash programming
@cindex Flash Configuration
@@ -2810,7 +2811,7 @@
@*Enable the use of the debug communications channel (DCC) to write larger (>128 byte)
amounts of memory. DCC downloads offer a huge speed increase, but might be potentially
unsafe, especially with targets running at very low speeds. This command was introduced
-with OpenOCD rev. 60.
+with OpenOCD rev. 60, and requires a few bytes of working area.
@end itemize
@subsection ARM720T specific commands
|
|
From: kc8apf at B. <kc...@ma...> - 2009-05-18 06:45:47
|
Author: kc8apf Date: 2009-05-18 06:45:42 +0200 (Mon, 18 May 2009) New Revision: 1805 Modified: trunk/src/target/arm7_9_common.c Log: Fix logically inverted comment Modified: trunk/src/target/arm7_9_common.c =================================================================== --- trunk/src/target/arm7_9_common.c 2009-05-18 04:44:28 UTC (rev 1804) +++ trunk/src/target/arm7_9_common.c 2009-05-18 04:45:42 UTC (rev 1805) @@ -2591,7 +2591,7 @@ register_command(cmd_ctx, arm7_9_cmd, "dbgrq", handle_arm7_9_dbgrq_command, COMMAND_ANY, "use EmbeddedICE dbgrq instead of breakpoint for target halt requests <enable|disable>"); register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access", handle_arm7_9_fast_memory_access_command, - COMMAND_ANY, "use fast memory accesses instead of slower but potentially unsafe slow accesses <enable|disable>"); + COMMAND_ANY, "use fast memory accesses instead of slower but potentially safer accesses <enable|disable>"); register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads", handle_arm7_9_dcc_downloads_command, COMMAND_ANY, "use DCC downloads for larger memory writes <enable|disable>"); |
|
From: kc8apf at B. <kc...@ma...> - 2009-05-18 06:44:41
|
Author: kc8apf
Date: 2009-05-18 06:44:28 +0200 (Mon, 18 May 2009)
New Revision: 1804
Modified:
trunk/doc/openocd.texi
trunk/src/flash/ecos.c
trunk/src/flash/flash.c
trunk/src/flash/lpc3180_nand_controller.c
trunk/src/flash/mflash.c
trunk/src/flash/orion_nand.c
trunk/src/flash/s3c24xx_nand.c
trunk/src/target/etb.c
trunk/src/target/etm.c
trunk/src/target/etm_dummy.c
trunk/src/target/image.c
trunk/src/target/target.c
trunk/src/target/target.h
trunk/src/target/target/ti_dm355.cfg
trunk/src/target/xscale.c
Log:
Consolidate target selection code into single get_target() that handles both names and numbers. Provided by David Brownell <da...@pa...>
Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/doc/openocd.texi 2009-05-18 04:44:28 UTC (rev 1804)
@@ -881,6 +881,8 @@
At no time should the name ``target0'' (the default target name if
none was specified) be used. The name ``target0'' is a hard coded name
- the next target on the board will be some other number.
+In the same way, avoid using target numbers even when they are
+permitted; use the right target name(s) for your board.
The user (or board file) should reasonably be able to:
@@ -1702,7 +1704,8 @@
@item @b{Note: Deprecated} - Index Numbers
@* Prior to 28/nov/2008, JTAG taps where numbered from 0..N this
feature is still present, however its use is highly discouraged and
-should not be counted upon.
+should not be counted upon. Update all of your scripts to use
+TAP names rather than numbers.
@item @b{Multiple chips}
@* If your board has multiple chips, you should be
able to @b{source} two configuration files, in the proper order, and
@@ -2045,8 +2048,8 @@
@itemize @bullet
@item @b{NAME}
@* Is the name of the debug target. By convention it should be the tap
-DOTTED.NAME, this name is also used to create the target object
-command.
+DOTTED.NAME. This name is also used to create the target object
+command, and in other places the target needs to be identified.
@item @b{TYPE}
@* Specifies the target type, i.e.: ARM7TDMI, or Cortex-M3. Currently supported targets are:
@comment START types
@@ -2254,7 +2257,7 @@
@example
@b{flash bank} <@var{driver}> <@var{base}> <@var{size}> <@var{chip_width}>
-<@var{bus_width}> <@var{target#}> [@var{driver_options ...}]
+<@var{bus_width}> <@var{target}> [@var{driver_options ...}]
@end example
@cindex flash bank
@*Configures a flash bank at <@var{base}> of <@var{size}> bytes and <@var{chip_width}>
@@ -2274,8 +2277,9 @@
on the flash chip.
@b{flash bank cfi} <@var{base}> <@var{size}> <@var{chip_width}> <@var{bus_width}>
-<@var{target#}> [@var{jedec_probe}|@var{x16_as_x8}]
-@*CFI flashes require the number of the target they're connected to as an additional
+<@var{target}> [@var{jedec_probe}|@var{x16_as_x8}]
+@*CFI flashes require the name or number of the target they're connected to
+as an additional
argument. The CFI driver makes use of a working area (specified for the target)
to significantly speed up operation.
@@ -2289,12 +2293,13 @@
@subsubsection lpc2000 options
@cindex lpc2000 options
-@b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
+@b{flash bank lpc2000} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
<@var{clock}> [@var{calc_checksum}]
@*LPC flashes don't require the chip and bus width to be specified. Additional
parameters are the <@var{variant}>, which may be @var{lpc2000_v1} (older LPC21xx and LPC22xx)
-or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx), the number
-of the target this flash belongs to (first is 0), the frequency at which the core
+or @var{lpc2000_v2} (LPC213x, LPC214x, LPC210[123], LPC23xx and LPC24xx),
+the name or number of the target this flash belongs to (first is 0),
+the frequency at which the core
is currently running (in kHz - must be an integral number), and the optional keyword
@var{calc_checksum}, telling the driver to calculate a valid checksum for the exception
vector table.
@@ -2303,20 +2308,20 @@
@subsubsection at91sam7 options
@cindex at91sam7 options
-@b{flash bank at91sam7} 0 0 0 0 <@var{target#}>
-@*AT91SAM7 flashes only require the @var{target#}, all other values are looked up after
+@b{flash bank at91sam7} 0 0 0 0 <@var{target}>
+@*AT91SAM7 flashes only require the @var{target}, all other values are looked up after
reading the chip-id and type.
@subsubsection str7 options
@cindex str7 options
-@b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target#}> <@var{variant}>
+@b{flash bank str7x} <@var{base}> <@var{size}> 0 0 <@var{target}> <@var{variant}>
@*variant can be either STR71x, STR73x or STR75x.
@subsubsection str9 options
@cindex str9 options
-@b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
+@b{flash bank str9x} <@var{base}> <@var{size}> 0 0 <@var{target}>
@*The str9 needs the flash controller to be configured prior to Flash programming, e.g.
@example
str9x flash_config 0 4 2 0 0x80000
@@ -2325,7 +2330,7 @@
@subsubsection str9 options (str9xpec driver)
-@b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target#}>
+@b{flash bank str9xpec} <@var{base}> <@var{size}> 0 0 <@var{target}>
@*Before using the flash commands the turbo mode must be enabled using str9xpec
@option{enable_turbo} <@var{num>.}
@@ -2335,25 +2340,25 @@
@subsubsection Stellaris (LM3Sxxx) options
@cindex Stellaris (LM3Sxxx) options
-@b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*Stellaris flash plugin only require the @var{target#}.
+@b{flash bank stellaris} <@var{base}> <@var{size}> 0 0 <@var{target}>
+@*Stellaris flash plugin only require the @var{target}.
@subsubsection stm32x options
@cindex stm32x options
-@b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target#}>
-@*stm32x flash plugin only require the @var{target#}.
+@b{flash bank stm32x} <@var{base}> <@var{size}> 0 0 <@var{target}>
+@*stm32x flash plugin only require the @var{target}.
@subsubsection aduc702x options
@cindex aduc702x options
-@b{flash bank aduc702x} 0 0 0 0 <@var{target#}>
-@*The aduc702x flash plugin works with Analog Devices model numbers ADUC7019 through ADUC7028. The setup command only requires the @var{target#} argument (all devices in this family have the same memory layout).
+@b{flash bank aduc702x} 0 0 0 0 <@var{target}>
+@*The aduc702x flash plugin works with Analog Devices model numbers ADUC7019 through ADUC7028. The setup command only requires the @var{target} argument (all devices in this family have the same memory layout).
@subsection mFlash Configuration
@cindex mFlash Configuration
@b{mflash bank} <@var{soc}> <@var{base}> <@var{chip_width}> <@var{bus_width}>
-<@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target #}>
+<@var{RST pin}> <@var{WP pin}> <@var{DPD pin}> <@var{target}>
@cindex mflash bank
@*Configures a mflash for <@var{soc}> host bank at
<@var{base}>. <@var{chip_width}> and <@var{bus_width}> are bytes
Modified: trunk/src/flash/ecos.c
===================================================================
--- trunk/src/flash/ecos.c 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/flash/ecos.c 2009-05-18 04:44:28 UTC (rev 1804)
@@ -164,10 +164,10 @@
bank->sectors[i].is_protected = 0;
}
- info->target = get_target_by_num(strtoul(args[5], NULL, 0));
+ info->target = get_target(args[5]);
if (info->target == NULL)
{
- LOG_ERROR("no target '%i' configured", (int)strtoul(args[5], NULL, 0));
+ LOG_ERROR("target '%s' not defined", args[5]);
return ERROR_FAIL;
}
return ERROR_OK;
Modified: trunk/src/flash/flash.c
===================================================================
--- trunk/src/flash/flash.c 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/flash/flash.c 2009-05-18 04:44:28 UTC (rev 1804)
@@ -261,9 +261,9 @@
return ERROR_COMMAND_SYNTAX_ERROR;
}
- if ((target = get_target_by_num(strtoul(args[5], NULL, 0))) == NULL)
+ if ((target = get_target(args[5])) == NULL)
{
- LOG_ERROR("target %lu not defined", strtoul(args[5], NULL, 0));
+ LOG_ERROR("target '%s' not defined", args[5]);
return ERROR_FAIL;
}
Modified: trunk/src/flash/lpc3180_nand_controller.c
===================================================================
--- trunk/src/flash/lpc3180_nand_controller.c 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/flash/lpc3180_nand_controller.c 2009-05-18 04:44:28 UTC (rev 1804)
@@ -71,10 +71,10 @@
lpc3180_info = malloc(sizeof(lpc3180_nand_controller_t));
device->controller_priv = lpc3180_info;
- lpc3180_info->target = get_target_by_num(strtoul(args[1], NULL, 0));
+ lpc3180_info->target = get_target(args[1]);
if (!lpc3180_info->target)
{
- LOG_ERROR("no target '%s' configured", args[1]);
+ LOG_ERROR("target '%s' not defined", args[1]);
return ERROR_NAND_DEVICE_INVALID;
}
Modified: trunk/src/flash/mflash.c
===================================================================
--- trunk/src/flash/mflash.c 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/flash/mflash.c 2009-05-18 04:44:28 UTC (rev 1804)
@@ -795,9 +795,9 @@
return ERROR_COMMAND_SYNTAX_ERROR;
}
- if ((target = get_target_by_num(strtoul(args[7], NULL, 0))) == NULL)
+ if ((target = get_target(args[7])) == NULL)
{
- LOG_ERROR("target %lu not defined", strtoul(args[7], NULL, 0));
+ LOG_ERROR("target '%s' not defined", args[7]);
return ERROR_FAIL;
}
Modified: trunk/src/flash/orion_nand.c
===================================================================
--- trunk/src/flash/orion_nand.c 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/flash/orion_nand.c 2009-05-18 04:44:28 UTC (rev 1804)
@@ -210,9 +210,9 @@
}
device->controller_priv = hw;
- hw->target = get_target_by_num(strtoul(args[1], NULL, 0));
+ hw->target = get_target(args[1]);
if (!hw->target) {
- LOG_ERROR("no target '%s' configured", args[1]);
+ LOG_ERROR("target '%s' not defined", args[1]);
free(hw);
return ERROR_NAND_DEVICE_INVALID;
}
Modified: trunk/src/flash/s3c24xx_nand.c
===================================================================
--- trunk/src/flash/s3c24xx_nand.c 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/flash/s3c24xx_nand.c 2009-05-18 04:44:28 UTC (rev 1804)
@@ -46,12 +46,12 @@
device->controller_priv = s3c24xx_info;
- s3c24xx_info->target = get_target_by_num(strtoul(args[1], NULL, 0));
+ s3c24xx_info->target = get_target(args[1]);
if (s3c24xx_info->target == NULL) {
- LOG_ERROR("no target '%s' configured", args[1]);
+ LOG_ERROR("target '%s' not defined", args[1]);
return NULL;
}
-
+
return s3c24xx_info;
}
Modified: trunk/src/target/etb.c
===================================================================
--- trunk/src/target/etb.c 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/target/etb.c 2009-05-18 04:44:28 UTC (rev 1804)
@@ -372,11 +372,11 @@
return ERROR_COMMAND_SYNTAX_ERROR;
}
- target = get_target_by_num(strtoul(args[0], NULL, 0));
+ target = get_target(args[0]);
if (!target)
{
- LOG_ERROR("target number '%s' not defined", args[0]);
+ LOG_ERROR("target '%s' not defined", args[0]);
return ERROR_FAIL;
}
Modified: trunk/src/target/etm.c
===================================================================
--- trunk/src/target/etm.c 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/target/etm.c 2009-05-18 04:44:28 UTC (rev 1804)
@@ -1205,11 +1205,10 @@
return ERROR_COMMAND_SYNTAX_ERROR;
}
- target = get_target_by_num(strtoul(args[0], NULL, 0));
-
+ target = get_target(args[0]);
if (!target)
{
- LOG_ERROR("target number '%s' not defined", args[0]);
+ LOG_ERROR("target '%s' not defined", args[0]);
return ERROR_FAIL;
}
Modified: trunk/src/target/etm_dummy.c
===================================================================
--- trunk/src/target/etm_dummy.c 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/target/etm_dummy.c 2009-05-18 04:44:28 UTC (rev 1804)
@@ -31,11 +31,11 @@
armv4_5_common_t *armv4_5;
arm7_9_common_t *arm7_9;
- target = get_target_by_num(strtoul(args[0], NULL, 0));
+ target = get_target(args[0]);
if (!target)
{
- LOG_ERROR("target number '%s' not defined", args[0]);
+ LOG_ERROR("target '%s' not defined", args[0]);
return ERROR_FAIL;
}
Modified: trunk/src/target/image.c
===================================================================
--- trunk/src/target/image.c 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/target/image.c 2009-05-18 04:44:28 UTC (rev 1804)
@@ -711,10 +711,11 @@
}
else if (image->type == IMAGE_MEMORY)
{
- target_t *target = get_target_by_num(strtoul(url, NULL, 0));
- if (target==NULL)
+ target_t *target = get_target(url);
+
+ if (target == NULL)
{
- LOG_ERROR("Target '%s' does not exist", url);
+ LOG_ERROR("target '%s' not defined", url);
return ERROR_FAIL;
}
Modified: trunk/src/target/target/ti_dm355.cfg
===================================================================
--- trunk/src/target/target/ti_dm355.cfg 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/target/target/ti_dm355.cfg 2009-05-18 04:44:28 UTC (rev 1804)
@@ -56,8 +56,5 @@
arm7_9 dcc_downloads enable
# trace setup
-# FIXME we ought to be able to say "... config $_TARGETNAME ..."
-# (not "config 0") facilitating additional targets (e.g. other chips)
-etm config 0 16 normal full etb
-etb config 0 $_CHIPNAME.etb
-
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/target/target.c 2009-05-18 04:44:28 UTC (rev 1804)
@@ -320,8 +320,36 @@
*buffer = value;
}
+/* return a pointer to a configured target; id is name or number */
+target_t *get_target(const char *id)
+{
+ target_t *target;
+ char *endptr;
+ int num;
+
+ /* try as tcltarget name */
+ for (target = all_targets; target; target = target->next) {
+ if (target->cmd_name == NULL)
+ continue;
+ if (strcmp(id, target->cmd_name) == 0)
+ return target;
+ }
+
+ /* no match, try as number */
+ num = strtoul(id, &endptr, 0);
+ if (*endptr != 0)
+ return NULL;
+
+ for (target = all_targets; target; target = target->next) {
+ if (target->target_number == num)
+ return target;
+ }
+
+ return NULL;
+}
+
/* returns a pointer to the n-th configured target */
-target_t* get_target_by_num(int num)
+static target_t *get_target_by_num(int num)
{
target_t *target = all_targets;
@@ -1333,35 +1361,16 @@
static int handle_targets_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
- char *cp;
target_t *target = all_targets;
if (argc == 1)
{
- /* try as tcltarget name */
- for( target = all_targets ; target ; target = target->next ){
- if( target->cmd_name ){
- if( 0 == strcmp( args[0], target->cmd_name ) ){
- /* MATCH */
- goto Match;
- }
- }
- }
- /* no match, try as number */
-
- int num = strtoul(args[0], &cp, 0 );
- if( *cp != 0 ){
- /* then it was not a number */
- command_print( cmd_ctx, "Target: %s unknown, try one of:\n", args[0] );
+ target = get_target(args[0]);
+ if (target == NULL) {
+ command_print(cmd_ctx,"Target: %s is unknown, try one of:\n", args[0] );
goto DumpTargets;
}
- target = get_target_by_num( num );
- if( target == NULL ){
- command_print(cmd_ctx,"Target: %s is unknown, try one of:\n", args[0] );
- goto DumpTargets;
- }
- Match:
cmd_ctx->current_target = target->target_number;
return ERROR_OK;
}
Modified: trunk/src/target/target.h
===================================================================
--- trunk/src/target/target.h 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/target/target.h 2009-05-18 04:44:28 UTC (rev 1804)
@@ -371,7 +371,7 @@
extern target_t* get_current_target(struct command_context_s *cmd_ctx);
extern int get_num_by_target(target_t *query_target);
-extern target_t* get_target_by_num(int num);
+extern target_t *get_target(const char *id);
extern int target_write_buffer(struct target_s *target, u32 address, u32 size, u8 *buffer);
extern int target_read_buffer(struct target_s *target, u32 address, u32 size, u8 *buffer);
Modified: trunk/src/target/xscale.c
===================================================================
--- trunk/src/target/xscale.c 2009-05-18 04:40:11 UTC (rev 1803)
+++ trunk/src/target/xscale.c 2009-05-18 04:44:28 UTC (rev 1804)
@@ -3147,9 +3147,9 @@
return ERROR_OK;
}
- if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
+ if ((target = get_target(args[0])) == NULL)
{
- LOG_ERROR("no target '%s' configured", args[0]);
+ LOG_ERROR("target '%s' not defined", args[0]);
return ERROR_FAIL;
}
@@ -3187,9 +3187,10 @@
return ERROR_COMMAND_SYNTAX_ERROR;
}
- if ((target = get_target_by_num(strtoul(args[0], NULL, 0))) == NULL)
+ target = get_target(args[0]);
+ if (target == NULL)
{
- LOG_ERROR("no target '%s' configured", args[0]);
+ LOG_ERROR("target '%s' not defined", args[0]);
return ERROR_FAIL;
}
|
|
From: kc8apf at B. <kc...@ma...> - 2009-05-18 06:40:21
|
Author: kc8apf
Date: 2009-05-18 06:40:11 +0200 (Mon, 18 May 2009)
New Revision: 1803
Modified:
trunk/doc/openocd.texi
Log:
ETM/ETB documentation from David Brownell <da...@pa...>
Modified: trunk/doc/openocd.texi
===================================================================
--- trunk/doc/openocd.texi 2009-05-18 04:37:33 UTC (rev 1802)
+++ trunk/doc/openocd.texi 2009-05-18 04:40:11 UTC (rev 1803)
@@ -1014,6 +1014,7 @@
@item @b{cpu}
@item @b{flash}
@item @b{bs}
+@item @b{etb}
@item @b{jrc}
@item @b{unknownN} - it happens :-(
@end itemize
@@ -1048,6 +1049,27 @@
If present, the MMU, the MPU and the CACHE should be disabled.
+Some ARM cores are equipped with trace support, which permits
+examination of the instruction and data bus activity. Trace
+activity is controlled through an ``Embedded Trace Module'' (ETM)
+on one of the core's scan chains. The ETM emits voluminous data
+through a ``trace port''. The trace port is accessed in one
+of two ways. When its signals are pinned out from the chip,
+boards may provide a special high speed debugging connector;
+software support for this is not configured by default, use
+the ``--enable-oocd_trace'' option. Alternatively, trace data
+may be stored an on-chip SRAM which is packaged as an ``Embedded
+Trace Buffer'' (ETB). An ETB has its own TAP, usually right after
+its associated ARM core. OpenOCD supports the ETM, and your
+target configuration should set it up with the relevant trace
+port: ``etb'' for chips which use that, else the board-specific
+option will be either ``oocd_trace'' or ``dummy''.
+
+@example
+etm config $_TARGETNAME 16 normal full etb
+etb config $_TARGETNAME $_CHIPNAME.etb
+@end example
+
@subsection Internal Flash Configuration
This applies @b{ONLY TO MICROCONTROLLERS} that have flash built in.
@@ -1640,6 +1662,7 @@
@item @b{cpu} - the main CPU of the chip, alternatively @b{foo.arm} and @b{foo.dsp}
@item @b{flash} - if the chip has a flash tap, example: str912.flash
@item @b{bs} - for boundary scan if this is a seperate tap.
+@item @b{etb} - for an embedded trace buffer (example: an ARM ETB11)
@item @b{jrc} - for JTAG route controller (example: OMAP3530 found on Beagleboards)
@item @b{unknownN} - where N is a number if you have no idea what the tap is for
@item @b{Other names} - Freescale IMX31 has a SDMA (smart dma) with a JTAG tap, that tap should be called the ``sdma'' tap.
|
|
From: kc8apf at B. <kc...@ma...> - 2009-05-18 06:37:49
|
Author: kc8apf
Date: 2009-05-18 06:37:33 +0200 (Mon, 18 May 2009)
New Revision: 1802
Modified:
trunk/src/flash/lpc3180_nand_controller.c
trunk/src/flash/nand.c
trunk/src/flash/nand.h
trunk/src/flash/s3c2410_nand.c
trunk/src/flash/s3c2412_nand.c
trunk/src/flash/s3c2440_nand.c
trunk/src/flash/s3c2443_nand.c
trunk/src/flash/s3c24xx_nand.c
trunk/src/flash/s3c24xx_nand.h
trunk/src/flash/stellaris.h
trunk/src/flash/stm32x.h
trunk/src/flash/str7x.h
Log:
Whitespace cleanup from David Brownell <da...@pa...>
Modified: trunk/src/flash/lpc3180_nand_controller.c
===================================================================
--- trunk/src/flash/lpc3180_nand_controller.c 2009-05-17 13:00:36 UTC (rev 1801)
+++ trunk/src/flash/lpc3180_nand_controller.c 2009-05-18 04:37:33 UTC (rev 1802)
@@ -61,13 +61,13 @@
static int lpc3180_nand_device_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct nand_device_s *device)
{
lpc3180_nand_controller_t *lpc3180_info;
-
+
if (argc < 3)
{
LOG_WARNING("incomplete 'lpc3180' nand flash configuration");
return ERROR_FLASH_BANK_INVALID;
}
-
+
lpc3180_info = malloc(sizeof(lpc3180_nand_controller_t));
device->controller_priv = lpc3180_info;
@@ -81,22 +81,22 @@
lpc3180_info->osc_freq = strtoul(args[2], NULL, 0);
if ((lpc3180_info->osc_freq < 1000) || (lpc3180_info->osc_freq > 20000))
{
- LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
+ LOG_WARNING("LPC3180 oscillator frequency should be between 1000 and 20000 kHz, was %i", lpc3180_info->osc_freq);
}
lpc3180_info->selected_controller = LPC3180_NO_CONTROLLER;
lpc3180_info->sw_write_protection = 0;
lpc3180_info->sw_wp_lower_bound = 0x0;
lpc3180_info->sw_wp_upper_bound = 0x0;
-
+
return ERROR_OK;
}
static int lpc3180_register_commands(struct command_context_s *cmd_ctx)
{
command_t *lpc3180_cmd = register_command(cmd_ctx, NULL, "lpc3180", NULL, COMMAND_ANY, "commands specific to the LPC3180 NAND flash controllers");
-
+
register_command(cmd_ctx, lpc3180_cmd, "select", handle_lpc3180_select_command, COMMAND_EXEC, "select <'mlc'|'slc'> controller (default is mlc)");
-
+
return ERROR_OK;
}
@@ -112,20 +112,20 @@
if (!lock)
LOG_WARNING("PLL is not locked");
-
+
if (!bypass && direct) /* direct mode */
return (m * fclkin) / n;
-
+
if (bypass && !direct) /* bypass mode */
return fclkin / (2 * p);
-
+
if (bypass & direct) /* direct bypass mode */
return fclkin;
-
+
if (feedback) /* integer mode */
return m * (fclkin / n);
else /* non-integer mode */
- return (m / (2 * p)) * (fclkin / n);
+ return (m / (2 * p)) * (fclkin / n);
}
static float lpc3180_cycle_time(lpc3180_nand_controller_t *lpc3180_info)
@@ -136,20 +136,20 @@
int hclk;
int hclk_pll;
float cycle;
-
+
/* calculate timings */
-
- /* determine current SYSCLK (13'MHz or main oscillator) */
+
+ /* determine current SYSCLK (13'MHz or main oscillator) */
target_read_u32(target, 0x40004050, &sysclk_ctrl);
-
+
if ((sysclk_ctrl & 1) == 0)
sysclk = lpc3180_info->osc_freq;
else
sysclk = 13000;
-
+
/* determine selected HCLK source */
target_read_u32(target, 0x40004044, &pwr_ctrl);
-
+
if ((pwr_ctrl & (1 << 2)) == 0) /* DIRECT RUN mode */
{
hclk = sysclk;
@@ -160,21 +160,21 @@
hclk_pll = lpc3180_pll(sysclk, hclkpll_ctrl);
target_read_u32(target, 0x40004040, &hclkdiv_ctrl);
-
+
if (pwr_ctrl & (1 << 10)) /* ARM_CLK and HCLK use PERIPH_CLK */
{
hclk = hclk_pll / (((hclkdiv_ctrl & 0x7c) >> 2) + 1);
}
else /* HCLK uses HCLK_PLL */
{
- hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
+ hclk = hclk_pll / (1 << (hclkdiv_ctrl & 0x3));
}
}
-
+
LOG_DEBUG("LPC3180 HCLK currently clocked at %i kHz", hclk);
-
+
cycle = (1.0 / hclk) * 1000000.0;
-
+
return cycle;
}
@@ -185,20 +185,20 @@
int bus_width = (device->bus_width) ? (device->bus_width) : 8;
int address_cycles = (device->address_cycles) ? (device->address_cycles) : 3;
int page_size = (device->page_size) ? (device->page_size) : 512;
-
+
if (target->state != TARGET_HALTED)
{
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
/* sanitize arguments */
if ((bus_width != 8) && (bus_width != 16))
{
LOG_ERROR("LPC3180 only supports 8 or 16 bit bus width, not %i", bus_width);
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
-
+
/* The LPC3180 only brings out 8 bit NAND data bus, but the controller
* would support 16 bit, too, so we just warn about this for now
*/
@@ -206,44 +206,44 @@
{
LOG_WARNING("LPC3180 only supports 8 bit bus width");
}
-
+
/* inform calling code about selected bus width */
device->bus_width = bus_width;
-
+
if ((address_cycles != 3) && (address_cycles != 4))
{
LOG_ERROR("LPC3180 only supports 3 or 4 address cycles, not %i", address_cycles);
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
-
+
if ((page_size != 512) && (page_size != 2048))
{
LOG_ERROR("LPC3180 only supports 512 or 2048 byte pages, not %i", page_size);
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
-
+
/* select MLC controller if none is currently selected */
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
LOG_DEBUG("no LPC3180 NAND flash controller selected, using default 'mlc'");
lpc3180_info->selected_controller = LPC3180_MLC_CONTROLLER;
}
-
+
if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
{
u32 mlc_icr_value = 0x0;
float cycle;
int twp, twh, trp, treh, trhz, trbwb, tcea;
-
+
/* FLASHCLK_CTRL = 0x22 (enable clock for MLC flash controller) */
target_write_u32(target, 0x400040c8, 0x22);
-
+
/* MLC_CEH = 0x0 (Force nCE assert) */
target_write_u32(target, 0x200b804c, 0x0);
-
+
/* MLC_LOCK = 0xa25e (unlock protected registers) */
target_write_u32(target, 0x200b8044, 0xa25e);
-
+
/* MLC_ICR = configuration */
if (lpc3180_info->sw_write_protection)
mlc_icr_value |= 0x8;
@@ -254,10 +254,10 @@
if (bus_width == 16)
mlc_icr_value |= 0x1;
target_write_u32(target, 0x200b8030, mlc_icr_value);
-
+
/* calculate NAND controller timings */
cycle = lpc3180_cycle_time(lpc3180_info);
-
+
twp = ((40 / cycle) + 1);
twh = ((20 / cycle) + 1);
trp = ((30 / cycle) + 1);
@@ -265,14 +265,14 @@
trhz = ((30 / cycle) + 1);
trbwb = ((100 / cycle) + 1);
tcea = ((45 / cycle) + 1);
-
+
/* MLC_LOCK = 0xa25e (unlock protected registers) */
target_write_u32(target, 0x200b8044, 0xa25e);
-
+
/* MLC_TIME_REG */
- target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
- ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
- ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
+ target_write_u32(target, 0x200b8034, (twp & 0xf) | ((twh & 0xf) << 4) |
+ ((trp & 0xf) << 8) | ((treh & 0xf) << 12) | ((trhz & 0x7) << 16) |
+ ((trbwb & 0x1f) << 19) | ((tcea & 0x3) << 24));
lpc3180_reset(device);
}
@@ -281,30 +281,30 @@
float cycle;
int r_setup, r_hold, r_width, r_rdy;
int w_setup, w_hold, w_width, w_rdy;
-
+
/* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
target_write_u32(target, 0x400040c8, 0x05);
-
+
/* SLC_CFG = 0x (Force nCE assert, ECC enabled, WIDTH = bus_width) */
target_write_u32(target, 0x20020014, 0x28 | (bus_width == 16) ? 1 : 0);
-
+
/* calculate NAND controller timings */
cycle = lpc3180_cycle_time(lpc3180_info);
-
+
r_setup = w_setup = 0;
r_hold = w_hold = 10 / cycle;
r_width = 30 / cycle;
w_width = 40 / cycle;
r_rdy = w_rdy = 100 / cycle;
-
+
/* SLC_TAC: SLC timing arcs register */
target_write_u32(target, 0x2002002c, (r_setup & 0xf) | ((r_hold & 0xf) << 4) |
((r_width & 0xf) << 8) | ((r_rdy & 0xf) << 12) | ((w_setup & 0xf) << 16) |
- ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
-
+ ((w_hold & 0xf) << 20) | ((w_width & 0xf) << 24) | ((w_rdy & 0xf) << 28));
+
lpc3180_reset(device);
}
-
+
return ERROR_OK;
}
@@ -312,13 +312,13 @@
{
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
-
+
if (target->state != TARGET_HALTED)
{
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
@@ -339,14 +339,14 @@
{
/* SLC_CTRL = 0x6 (ECC_CLEAR, SW_RESET) */
target_write_u32(target, 0x20020010, 0x6);
-
+
if (!lpc3180_controller_ready(device, 100))
{
LOG_ERROR("LPC3180 NAND controller timed out after reset");
return ERROR_NAND_OPERATION_TIMEOUT;
}
}
-
+
return ERROR_OK;
}
@@ -354,13 +354,13 @@
{
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
-
+
if (target->state != TARGET_HALTED)
{
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
@@ -375,8 +375,8 @@
{
/* SLC_CMD = command */
target_write_u32(target, 0x20020008, command);
- }
-
+ }
+
return ERROR_OK;
}
@@ -384,13 +384,13 @@
{
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
-
+
if (target->state != TARGET_HALTED)
{
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
@@ -406,7 +406,7 @@
/* SLC_ADDR = address */
target_write_u32(target, 0x20020004, address);
}
-
+
return ERROR_OK;
}
@@ -414,13 +414,13 @@
{
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
-
+
if (target->state != TARGET_HALTED)
{
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
@@ -436,7 +436,7 @@
/* SLC_DATA = data */
target_write_u32(target, 0x20020000, data);
}
-
+
return ERROR_OK;
}
@@ -444,13 +444,13 @@
{
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
-
+
if (target->state != TARGET_HALTED)
{
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
@@ -481,7 +481,7 @@
/* data = SLC_DATA, must use 32-bit access */
target_read_u32(target, 0x20020000, &data32);
-
+
if (device->bus_width == 8)
{
u8 *data8 = data;
@@ -497,8 +497,8 @@
LOG_ERROR("BUG: bus_width neither 8 nor 16 bit");
return ERROR_NAND_OPERATION_FAILED;
}
- }
-
+ }
+
return ERROR_OK;
}
@@ -508,13 +508,13 @@
target_t *target = lpc3180_info->target;
int retval;
u8 status;
-
+
if (target->state != TARGET_HALTED)
{
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
@@ -525,30 +525,30 @@
u8 *page_buffer;
u8 *oob_buffer;
int quarter, num_quarters;
-
+
if (!data && oob)
{
LOG_ERROR("LPC3180 MLC controller can't write OOB data only");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
-
+
if (oob && (oob_size > 6))
{
LOG_ERROR("LPC3180 MLC controller can't write more than 6 bytes of OOB data");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
-
+
if (data_size > (u32)device->page_size)
{
LOG_ERROR("data size exceeds page size");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
-
+
/* MLC_CMD = sequential input */
target_write_u32(target, 0x200b8000, NAND_CMD_SEQIN);
page_buffer = malloc(512);
- oob_buffer = malloc(6);
+ oob_buffer = malloc(6);
if (device->page_size == 512)
{
@@ -558,7 +558,7 @@
/* MLC_ADDR = row */
target_write_u32(target, 0x200b8004, page & 0xff);
target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
-
+
if (device->address_cycles == 4)
target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
}
@@ -572,17 +572,17 @@
target_write_u32(target, 0x200b8004, page & 0xff);
target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
}
-
+
/* when using the MLC controller, we have to treat a large page device
* as being made out of four quarters, each the size of a small page device
*/
num_quarters = (device->page_size == 2048) ? 4 : 1;
-
+
for (quarter = 0; quarter < num_quarters; quarter++)
{
int thisrun_data_size = (data_size > 512) ? 512 : data_size;
int thisrun_oob_size = (oob_size > 6) ? 6 : oob_size;
-
+
memset(page_buffer, 0xff, 512);
if (data)
{
@@ -590,7 +590,7 @@
data_size -= thisrun_data_size;
data += thisrun_data_size;
}
-
+
memset(oob_buffer, 0xff, (device->page_size == 512) ? 6 : 24);
if (oob)
{
@@ -598,38 +598,38 @@
oob_size -= thisrun_oob_size;
oob += thisrun_oob_size;
}
-
+
/* write MLC_ECC_ENC_REG to start encode cycle */
target_write_u32(target, 0x200b8008, 0x0);
-
+
target->type->write_memory(target, 0x200a8000, 4, 128, page_buffer + (quarter * 512));
target->type->write_memory(target, 0x200a8000, 1, 6, oob_buffer + (quarter * 6));
-
+
/* write MLC_ECC_AUTO_ENC_REG to start auto encode */
target_write_u32(target, 0x200b8010, 0x0);
-
+
if (!lpc3180_controller_ready(device, 1000))
{
LOG_ERROR("timeout while waiting for completion of auto encode cycle");
return ERROR_NAND_OPERATION_FAILED;
}
}
-
+
/* MLC_CMD = auto program command */
target_write_u32(target, 0x200b8000, NAND_CMD_PAGEPROG);
-
+
if ((retval = nand_read_status(device, &status)) != ERROR_OK)
{
LOG_ERROR("couldn't read status");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
if (status & NAND_STATUS_FAIL)
{
LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
return ERROR_NAND_OPERATION_FAILED;
}
-
+
free(page_buffer);
free(oob_buffer);
}
@@ -637,7 +637,7 @@
{
return nand_write_page_raw(device, page, data, data_size, oob, oob_size);
}
-
+
return ERROR_OK;
}
@@ -645,13 +645,13 @@
{
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
-
+
if (target->state != TARGET_HALTED)
{
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
if (lpc3180_info->selected_controller == LPC3180_NO_CONTROLLER)
{
LOG_ERROR("BUG: no LPC3180 NAND flash controller selected");
@@ -672,13 +672,13 @@
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
#endif
-
+
if (data_size > (u32)device->page_size)
{
LOG_ERROR("data size exceeds page size");
return ERROR_NAND_OPERATION_NOT_SUPPORTED;
}
-
+
if (device->page_size == 2048)
{
page_buffer = malloc(2048);
@@ -689,10 +689,10 @@
page_buffer = malloc(512);
oob_buffer = malloc(16);
}
-
+
if (!data && oob)
{
- /* MLC_CMD = Read OOB
+ /* MLC_CMD = Read OOB
* we can use the READOOB command on both small and large page devices,
* as the controller translates the 0x50 command to a 0x0 with appropriate
* positioning of the serial buffer read pointer
@@ -704,7 +704,7 @@
/* MLC_CMD = Read0 */
target_write_u32(target, 0x200b8000, NAND_CMD_READ0);
}
-
+
if (device->page_size == 512)
{
/* small page device */
@@ -714,7 +714,7 @@
/* MLC_ADDR = row */
target_write_u32(target, 0x200b8004, page & 0xff);
target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
-
+
if (device->address_cycles == 4)
target_write_u32(target, 0x200b8004, (page >> 16) & 0xff);
}
@@ -728,24 +728,24 @@
/* MLC_ADDR = row */
target_write_u32(target, 0x200b8004, page & 0xff);
target_write_u32(target, 0x200b8004, (page >> 8) & 0xff);
-
+
/* MLC_CMD = Read Start */
target_write_u32(target, 0x200b8000, NAND_CMD_READSTART);
}
-
+
while (page_bytes_done < (u32)device->page_size)
{
/* MLC_ECC_AUTO_DEC_REG = dummy */
target_write_u32(target, 0x200b8014, 0xaa55aa55);
-
+
if (!lpc3180_controller_ready(device, 1000))
{
LOG_ERROR("timeout while waiting for completion of auto decode cycle");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
target_read_u32(target, 0x200b8048, &mlc_isr);
-
+
if (mlc_isr & 0x8)
{
if (mlc_isr & 0x40)
@@ -753,15 +753,15 @@
LOG_ERROR("uncorrectable error detected: 0x%2.2x", mlc_isr);
return ERROR_NAND_OPERATION_FAILED;
}
-
+
LOG_WARNING("%i symbol error detected and corrected", ((mlc_isr & 0x30) >> 4) + 1);
}
-
+
if (data)
{
target->type->read_memory(target, 0x200a8000, 4, 128, page_buffer + page_bytes_done);
}
-
+
if (oob)
{
target->type->read_memory(target, 0x200a8000, 4, 4, oob_buffer + oob_bytes_done);
@@ -770,13 +770,13 @@
page_bytes_done += 512;
oob_bytes_done += 16;
}
-
+
if (data)
memcpy(data, page_buffer, data_size);
-
+
if (oob)
memcpy(oob, oob_buffer, oob_size);
-
+
free(page_buffer);
free(oob_buffer);
}
@@ -784,7 +784,7 @@
{
return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
}
-
+
return ERROR_OK;
}
@@ -793,20 +793,20 @@
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
u8 status = 0x0;
-
+
if (target->state != TARGET_HALTED)
{
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
do
{
if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
{
/* Read MLC_ISR, wait for controller to become ready */
target_read_u8(target, 0x200b8048, &status);
-
+
if (status & 2)
return 1;
}
@@ -818,7 +818,7 @@
alive_sleep(1);
} while (timeout-- > 0);
-
+
return 0;
}
@@ -826,65 +826,65 @@
{
lpc3180_nand_controller_t *lpc3180_info = device->controller_priv;
target_t *target = lpc3180_info->target;
-
+
if (target->state != TARGET_HALTED)
{
LOG_ERROR("target must be halted to use LPC3180 NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
do
{
if (lpc3180_info->selected_controller == LPC3180_MLC_CONTROLLER)
- {
+ {
u8 status = 0x0;
-
+
/* Read MLC_ISR, wait for NAND flash device to become ready */
target_read_u8(target, 0x200b8048, &status);
-
+
if (status & 1)
return 1;
}
else if (lpc3180_info->selected_controller == LPC3180_SLC_CONTROLLER)
{
u32 status = 0x0;
-
+
/* Read SLC_STAT and check READY bit */
target_read_u32(target, 0x20020018, &status);
-
+
if (status & 1)
return 1;
}
-
+
alive_sleep(1);
} while (timeout-- > 0);
-
- return 0;
+
+ return 0;
}
static int handle_lpc3180_select_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
nand_device_t *device = NULL;
lpc3180_nand_controller_t *lpc3180_info = NULL;
- char *selected[] =
+ char *selected[] =
{
"no", "mlc", "slc"
};
-
+
if ((argc < 1) || (argc > 2))
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
-
+
device = get_nand_device_by_num(strtoul(args[0], NULL, 0));
if (!device)
{
command_print(cmd_ctx, "nand device '#%s' is out of bounds", args[0]);
return ERROR_OK;
}
-
+
lpc3180_info = device->controller_priv;
-
+
if (argc == 2)
{
if (strcmp(args[1], "mlc") == 0)
@@ -900,8 +900,8 @@
return ERROR_COMMAND_SYNTAX_ERROR;
}
}
-
+
command_print(cmd_ctx, "%s controller selected", selected[lpc3180_info->selected_controller]);
-
+
return ERROR_OK;
}
Modified: trunk/src/flash/nand.c
===================================================================
--- trunk/src/flash/nand.c 2009-05-17 13:00:36 UTC (rev 1801)
+++ trunk/src/flash/nand.c 2009-05-18 04:37:33 UTC (rev 1802)
@@ -216,17 +216,17 @@
{
int i;
int retval;
-
+
if (argc < 1)
{
LOG_WARNING("incomplete flash device nand configuration");
return ERROR_FLASH_BANK_INVALID;
}
-
+
for (i = 0; nand_flash_controllers[i]; i++)
{
nand_device_t *p, *c;
-
+
if (strcmp(args[0], nand_flash_controllers[i]->name) == 0)
{
/* register flash specific commands */
@@ -235,7 +235,7 @@
LOG_ERROR("couldn't register '%s' commands", args[0]);
return retval;
}
-
+
c = malloc(sizeof(nand_device_t));
c->controller = nand_flash_controllers[i];
@@ -254,7 +254,7 @@
free(c);
return ERROR_OK;
}
-
+
/* put NAND device in linked list */
if (nand_devices)
{
@@ -267,7 +267,7 @@
{
nand_devices = c;
}
-
+
return ERROR_OK;
}
}
@@ -281,16 +281,16 @@
{
LOG_ERROR("%i: %s", i, nand_flash_controllers[i]->name);
}
-
+
return ERROR_OK;
}
int nand_register_commands(struct command_context_s *cmd_ctx)
{
nand_cmd = register_command(cmd_ctx, NULL, "nand", NULL, COMMAND_ANY, "NAND specific commands");
-
+
register_command(cmd_ctx, nand_cmd, "device", handle_nand_device_command, COMMAND_CONFIG, NULL);
-
+
return ERROR_OK;
}
@@ -317,7 +317,7 @@
register_command(cmd_ctx, nand_cmd, "raw_access", handle_nand_raw_access_command, COMMAND_EXEC,
"raw access to NAND flash device <num> ['enable'|'disable']");
}
-
+
return ERROR_OK;
}
@@ -333,7 +333,7 @@
return p;
}
}
-
+
return NULL;
}
@@ -342,17 +342,17 @@
u32 page = 0x0;
int i;
u8 oob[6];
-
+
if ((first < 0) || (first >= device->num_blocks))
first = 0;
-
+
if ((last >= device->num_blocks) || (last == -1))
last = device->num_blocks - 1;
-
+
for (i = first; i < last; i++)
{
nand_read_page(device, page, NULL, 0, oob, 6);
-
+
if (((device->device->options & NAND_BUSWIDTH_16) && ((oob[0] & oob[1]) != 0xff))
|| (((device->page_size == 512) && (oob[5] != 0xff)) ||
((device->page_size == 2048) && (oob[0] != 0xff))))
@@ -364,10 +364,10 @@
{
device->blocks[i].is_bad = 0;
}
-
+
page += (device->erase_size / device->page_size);
}
-
+
return ERROR_OK;
}
@@ -375,12 +375,12 @@
{
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
-
+
/* Send read status command */
device->controller->command(device, NAND_CMD_STATUS);
-
+
alive_sleep(1);
-
+
/* read status */
if (device->device->options & NAND_BUSWIDTH_16)
{
@@ -392,7 +392,7 @@
{
device->controller->read_data(device, status);
}
-
+
return ERROR_OK;
}
@@ -427,13 +427,13 @@
/* clear device data */
device->device = NULL;
device->manufacturer = NULL;
-
+
/* clear device parameters */
device->bus_width = 0;
device->address_cycles = 0;
device->page_size = 0;
device->erase_size = 0;
-
+
/* initialize controller (device parameters are zero, use controller default) */
if ((retval = device->controller->init(device) != ERROR_OK))
{
@@ -450,13 +450,13 @@
return ERROR_NAND_OPERATION_FAILED;
}
}
-
+
device->controller->command(device, NAND_CMD_RESET);
device->controller->reset(device);
device->controller->command(device, NAND_CMD_READID);
device->controller->address(device, 0x0);
-
+
if (device->bus_width == 8)
{
device->controller->read_data(device, &manufacturer_id);
@@ -470,7 +470,7 @@
device->controller->read_data(device, &data_buf);
device_id = data_buf & 0xff;
}
-
+
for (i = 0; nand_flash_ids[i].name; i++)
{
if (nand_flash_ids[i].id == device_id)
@@ -479,7 +479,7 @@
break;
}
}
-
+
for (i = 0; nand_manuf_ids[i].name; i++)
{
if (nand_manuf_ids[i].id == manufacturer_id)
@@ -488,25 +488,25 @@
break;
}
}
-
+
if (!device->manufacturer)
{
device->manufacturer = &nand_manuf_ids[0];
device->manufacturer->id = manufacturer_id;
}
-
+
if (!device->device)
{
LOG_ERROR("unknown NAND flash device found, manufacturer id: 0x%2.2x device id: 0x%2.2x",
manufacturer_id, device_id);
return ERROR_NAND_OPERATION_FAILED;
}
-
+
LOG_DEBUG("found %s (%s)", device->device->name, device->manufacturer->name);
-
+
/* initialize device parameters */
-
- /* bus width */
+
+ /* bus width */
if (device->device->options & NAND_BUSWIDTH_16)
device->bus_width = 16;
else
@@ -536,7 +536,7 @@
id_buff[5] = data_buf >> 8;
}
}
-
+
/* page size */
if (device->device->page_size == 0)
{
@@ -551,7 +551,7 @@
{
device->page_size = device->device->page_size;
}
-
+
/* number of address cycles */
if (device->page_size <= 512)
{
@@ -579,7 +579,7 @@
device->address_cycles = 6;
}
}
-
+
/* erase size */
if (device->device->erase_size == 0)
{
@@ -602,7 +602,7 @@
{
device->erase_size = device->device->erase_size;
}
-
+
/* initialize controller, but leave parameters at the controllers default */
if ((retval = device->controller->init(device) != ERROR_OK))
{
@@ -620,10 +620,10 @@
return ERROR_NAND_OPERATION_FAILED;
}
}
-
+
device->num_blocks = (device->device->chip_size * 1024) / (device->erase_size / 1024);
device->blocks = malloc(sizeof(nand_block_t) * device->num_blocks);
-
+
for (i = 0; i < device->num_blocks; i++)
{
device->blocks[i].size = device->erase_size;
@@ -631,7 +631,7 @@
device->blocks[i].is_erased = -1;
device->blocks[i].is_bad = -1;
}
-
+
return ERROR_OK;
}
@@ -641,13 +641,13 @@
u32 page;
u8 status;
int retval;
-
+
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
-
+
if ((first_block < 0) || (last_block > device->num_blocks))
return ERROR_INVALID_ARGUMENTS;
-
+
/* make sure we know if a block is bad before erasing it */
for (i = first_block; i <= last_block; i++)
{
@@ -657,25 +657,25 @@
break;
}
}
-
+
for (i = first_block; i <= last_block; i++)
{
/* Send erase setup command */
device->controller->command(device, NAND_CMD_ERASE1);
-
+
page = i * (device->erase_size / device->page_size);
-
+
/* Send page address */
if (device->page_size <= 512)
{
/* row */
device->controller->address(device, page & 0xff);
device->controller->address(device, (page >> 8) & 0xff);
-
+
/* 3rd cycle only on devices with more than 32 MiB */
if (device->address_cycles >= 4)
device->controller->address(device, (page >> 16) & 0xff);
-
+
/* 4th cycle only on devices with more than 8 GiB */
if (device->address_cycles >= 5)
device->controller->address(device, (page >> 24) & 0xff);
@@ -685,12 +685,12 @@
/* row */
device->controller->address(device, page & 0xff);
device->controller->address(device, (page >> 8) & 0xff);
-
+
/* 3rd cycle only on devices with more than 128 MiB */
if (device->address_cycles >= 5)
device->controller->address(device, (page >> 16) & 0xff);
}
-
+
/* Send erase confirm command */
device->controller->command(device, NAND_CMD_ERASE2);
@@ -701,13 +701,13 @@
LOG_ERROR("timeout waiting for NAND flash block erase to complete");
return ERROR_NAND_OPERATION_TIMEOUT;
}
-
+
if ((retval = nand_read_status(device, &status)) != ERROR_OK)
{
LOG_ERROR("couldn't read status");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
if (status & 0x1)
{
LOG_ERROR("erase operation didn't pass, status: 0x%2.2x", status);
@@ -716,7 +716,7 @@
device->blocks[i].is_erased = 1;
}
-
+
return ERROR_OK;
}
@@ -724,74 +724,74 @@
static int nand_read_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
{
u8 *page;
-
+
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
-
+
if (address % device->page_size)
{
LOG_ERROR("reads need to be page aligned");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
page = malloc(device->page_size);
-
+
while (data_size > 0 )
{
u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
u32 page_address;
-
-
+
+
page_address = address / device->page_size;
-
+
nand_read_page(device, page_address, page, device->page_size, NULL, 0);
memcpy(data, page, thisrun_size);
-
+
address += thisrun_size;
data += thisrun_size;
data_size -= thisrun_size;
}
-
+
free(page);
-
+
return ERROR_OK;
}
static int nand_write_plain(struct nand_device_s *device, u32 address, u8 *data, u32 data_size)
{
u8 *page;
-
+
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
-
+
if (address % device->page_size)
{
LOG_ERROR("writes need to be page aligned");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
page = malloc(device->page_size);
-
+
while (data_size > 0 )
{
u32 thisrun_size = (data_size > device->page_size) ? device->page_size : data_size;
u32 page_address;
-
+
memset(page, 0xff, device->page_size);
memcpy(page, data, thisrun_size);
-
+
page_address = address / device->page_size;
-
+
nand_write_page(device, page_address, page, device->page_size, NULL, 0);
-
+
address += thisrun_size;
data += thisrun_size;
data_size -= thisrun_size;
}
-
+
free(page);
-
+
return ERROR_OK;
}
#endif
@@ -802,7 +802,7 @@
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
-
+
block = page / (device->erase_size / device->page_size);
if (device->blocks[block].is_erased == 1)
device->blocks[block].is_erased = 0;
@@ -817,7 +817,7 @@
{
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
-
+
if (device->use_raw || device->controller->read_page == NULL)
return nand_read_page_raw(device, page, data, data_size, oob, oob_size);
else
@@ -827,7 +827,7 @@
int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
{
u32 i;
-
+
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
@@ -838,14 +838,14 @@
device->controller->command(device, NAND_CMD_READ0);
else
device->controller->command(device, NAND_CMD_READOOB);
-
+
/* column (always 0, we start at the beginning of a page/OOB area) */
device->controller->address(device, 0x0);
-
+
/* row */
device->controller->address(device, page & 0xff);
device->controller->address(device, (page >> 8) & 0xff);
-
+
/* 4th cycle only on devices with more than 32 MiB */
if (device->address_cycles >= 4)
device->controller->address(device, (page >> 16) & 0xff);
@@ -858,7 +858,7 @@
{
/* large page device */
device->controller->command(device, NAND_CMD_READ0);
-
+
/* column (0 when we start at the beginning of a page,
* or 2048 for the beginning of OOB area)
*/
@@ -867,7 +867,7 @@
device->controller->address(device, 0x0);
else
device->controller->address(device, 0x8);
-
+
/* row */
device->controller->address(device, page & 0xff);
device->controller->address(device, (page >> 8) & 0xff);
@@ -879,14 +879,14 @@
/* large page devices need a start command */
device->controller->command(device, NAND_CMD_READSTART);
}
-
+
if (device->controller->nand_ready) {
if (!device->controller->nand_ready(device, 100))
return ERROR_NAND_OPERATION_TIMEOUT;
} else {
alive_sleep(1);
}
-
+
if (data)
{
if (device->controller->read_block_data != NULL)
@@ -910,7 +910,7 @@
}
}
}
-
+
if (oob)
{
if (device->controller->read_block_data != NULL)
@@ -934,8 +934,8 @@
}
}
}
-
- return ERROR_OK;
+
+ return ERROR_OK;
}
int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size)
@@ -943,21 +943,21 @@
u32 i;
int retval;
u8 status;
-
+
if (!device->device)
return ERROR_NAND_DEVICE_NOT_PROBED;
device->controller->command(device, NAND_CMD_SEQIN);
-
+
if (device->page_size <= 512)
{
/* column (always 0, we start at the beginning of a page/OOB area) */
device->controller->address(device, 0x0);
-
+
/* row */
device->controller->address(device, page & 0xff);
device->controller->address(device, (page >> 8) & 0xff);
-
+
/* 4th cycle only on devices with more than 32 MiB */
if (device->address_cycles >= 4)
device->controller->address(device, (page >> 16) & 0xff);
@@ -976,7 +976,7 @@
device->controller->address(device, 0x0);
else
device->controller->address(device, 0x8);
-
+
/* row */
device->controller->address(device, page & 0xff);
device->controller->address(device, (page >> 8) & 0xff);
@@ -985,7 +985,7 @@
if (device->address_cycles >= 5)
device->controller->address(device, (page >> 16) & 0xff);
}
-
+
if (data)
{
if (device->controller->write_block_data != NULL)
@@ -1010,7 +1010,7 @@
}
}
}
-
+
if (oob)
{
if (device->controller->write_block_data != NULL)
@@ -1035,41 +1035,41 @@
}
}
}
-
+
device->controller->command(device, NAND_CMD_PAGEPROG);
-
+
retval = device->controller->nand_ready ?
device->controller->nand_ready(device, 100) :
nand_poll_ready(device, 100);
if (!retval)
return ERROR_NAND_OPERATION_TIMEOUT;
-
+
if ((retval = nand_read_status(device, &status)) != ERROR_OK)
{
LOG_ERROR("couldn't read status");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
if (status & NAND_STATUS_FAIL)
{
LOG_ERROR("write operation didn't pass, status: 0x%2.2x", status);
return ERROR_NAND_OPERATION_FAILED;
}
-
- return ERROR_OK;
+
+ return ERROR_OK;
}
int handle_nand_list_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
nand_device_t *p;
int i = 0;
-
+
if (!nand_devices)
{
command_print(cmd_ctx, "no NAND flash devices configured");
return ERROR_OK;
}
-
+
for (p = nand_devices; p; p = p->next)
{
if (p->device)
@@ -1078,7 +1078,7 @@
else
command_print(cmd_ctx, "#%i: not probed");
}
-
+
return ERROR_OK;
}
@@ -1089,13 +1089,13 @@
int j = 0;
int first = -1;
int last = -1;
-
+
if ((argc < 1) || (argc > 3))
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
-
+
if (argc == 2)
{
first = last = strtoul(args[1], NULL, 0);
@@ -1105,7 +1105,7 @@
first = strtoul(args[1], NULL, 0);
last = strtoul(args[2], NULL, 0);
}
-
+
p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
if (p)
{
@@ -1113,24 +1113,24 @@
{
if (first >= p->num_blocks)
first = p->num_blocks - 1;
-
+
if (last >= p->num_blocks)
last = p->num_blocks - 1;
-
+
command_print(cmd_ctx, "#%i: %s (%s) pagesize: %i, buswidth: %i, erasesize: %i",
i++, p->device->name, p->manufacturer->name, p->page_size, p->bus_width, p->erase_size);
-
+
for (j = first; j <= last; j++)
{
char *erase_state, *bad_state;
-
+
if (p->blocks[j].is_erased == 0)
erase_state = "not erased";
else if (p->blocks[j].is_erased == 1)
erase_state = "erased";
else
erase_state = "erase state unknown";
-
+
if (p->blocks[j].is_bad == 0)
bad_state = "";
else if (p->blocks[j].is_bad == 1)
@@ -1148,7 +1148,7 @@
command_print(cmd_ctx, "#%i: not probed");
}
}
-
+
return ERROR_OK;
}
@@ -1156,12 +1156,12 @@
{
nand_device_t *p;
int retval;
-
+
if (argc != 1)
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
-
+
p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
if (p)
{
@@ -1182,7 +1182,7 @@
{
command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
}
-
+
return ERROR_OK;
}
@@ -1190,19 +1190,19 @@
{
nand_device_t *p;
int retval;
-
+
if (argc != 3)
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
-
+
p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
if (p)
{
int first = strtoul(args[1], NULL, 0);
int last = strtoul(args[2], NULL, 0);
-
+
if ((retval = nand_erase(p, first, last)) == ERROR_OK)
{
command_print(cmd_ctx, "successfully erased blocks %i to %i on NAND flash device '%s'", first, last, p->device->name);
@@ -1220,7 +1220,7 @@
{
command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
}
-
+
return ERROR_OK;
}
@@ -1230,19 +1230,19 @@
int retval;
int first = -1;
int last = -1;
-
+
if ((argc < 1) || (argc > 3) || (argc == 2))
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
-
+
if (argc == 3)
{
first = strtoul(args[1], NULL, 0);
last = strtoul(args[2], NULL, 0);
}
-
+
p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
if (p)
{
@@ -1263,20 +1263,20 @@
{
command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
}
-
+
return ERROR_OK;
}
static int handle_nand_copy_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
nand_device_t *p;
-
+
if (argc != 4)
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
-
+
p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
if (p)
{
@@ -1286,7 +1286,7 @@
{
command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
}
-
+
return ERROR_OK;
}
@@ -1296,20 +1296,20 @@
u32 binary_size;
u32 buf_cnt;
enum oob_formats oob_format = NAND_OOB_NONE;
-
+
fileio_t fileio;
-
+
duration_t duration;
char *duration_text;
-
+
nand_device_t *p;
-
+
if (argc < 3)
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
-
+
p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
if (p)
{
@@ -1318,9 +1318,9 @@
u8 *oob = NULL;
u32 oob_size = 0;
const int *eccpos = NULL;
-
+
offset = strtoul(args[2], NULL, 0);
-
+
if (argc > 3)
{
int i;
@@ -1341,16 +1341,16 @@
}
}
}
-
+
duration_start_measure(&duration);
if (fileio_open(&fileio, args[1], FILEIO_READ, FILEIO_BINARY) != ERROR_OK)
{
return ERROR_OK;
}
-
+
buf_cnt = binary_size = fileio.size;
-
+
if (!(oob_format & NAND_OOB_ONLY))
{
page_size = p->page_size;
@@ -1368,7 +1368,7 @@
}
oob = malloc(oob_size);
}
-
+
if (offset % p->page_size)
{
command_print(cmd_ctx, "only page size aligned offsets and sizes are supported");
@@ -1377,11 +1377,11 @@
free(page);
return ERROR_OK;
}
-
+
while (buf_cnt > 0)
{
u32 size_read;
-
+
if (NULL != page)
{
fileio_read(&fileio, page_size, page, &size_read);
@@ -1428,7 +1428,7 @@
memset(oob + size_read, 0xff, oob_size - size_read);
}
}
-
+
if (nand_write_page(p, offset / p->page_size, page, page_size, oob, oob_size) != ERROR_OK)
{
command_print(cmd_ctx, "failed writing file %s to NAND flash %s at offset 0x%8.8x",
@@ -1458,19 +1458,19 @@
{
command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
}
-
+
return ERROR_OK;
}
static int handle_nand_dump_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
nand_device_t *p;
-
+
if (argc < 4)
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
-
+
p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
if (p)
{
@@ -1480,7 +1480,7 @@
duration_t duration;
char *duration_text;
int retval;
-
+
u8 *page = NULL;
u32 page_size = 0;
u8 *oob = NULL;
@@ -1489,7 +1489,7 @@
u32 size = strtoul(args[3], NULL, 0);
u32 bytes_done = 0;
enum oob_formats oob_format = NAND_OOB_NONE;
-
+
if (argc > 4)
{
int i;
@@ -1500,16 +1500,16 @@
else if (!strcmp(args[i], "oob_only"))
oob_format |= NAND_OOB_RAW | NAND_OOB_ONLY;
else
- command_print(cmd_ctx, "unknown option: '%s'", args[i]);
+ command_print(cmd_ctx, "unknown option: '%s'", args[i]);
}
}
-
+
if ((address % p->page_size) || (size % p->page_size))
{
command_print(cmd_ctx, "only page size aligned addresses and sizes are supported");
return ERROR_OK;
}
-
+
if (!(oob_format & NAND_OOB_ONLY))
{
page_size = p->page_size;
@@ -1524,14 +1524,14 @@
oob_size = 64;
oob = malloc(oob_size);
}
-
+
if (fileio_open(&fileio, args[1], FILEIO_WRITE, FILEIO_BINARY) != ERROR_OK)
{
return ERROR_OK;
}
-
+
duration_start_measure(&duration);
-
+
while (size > 0)
{
u32 size_written;
@@ -1539,27 +1539,27 @@
{
command_print(cmd_ctx, "reading NAND flash page failed");
free(page);
- free(oob);
+ free(oob);
fileio_close(&fileio);
return ERROR_OK;
}
-
+
if (NULL != page)
{
fileio_write(&fileio, page_size, page, &size_written);
bytes_done += page_size;
}
-
+
if (NULL != oob)
{
fileio_write(&fileio, oob_size, oob, &size_written);
bytes_done += oob_size;
}
-
+
size -= p->page_size;
address += p->page_size;
}
-
+
free(page);
page = NULL;
free(oob);
@@ -1580,19 +1580,19 @@
{
command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
}
-
+
return ERROR_OK;
}
static int handle_nand_raw_access_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc)
{
nand_device_t *p;
-
+
if ((argc < 1) || (argc > 2))
{
return ERROR_COMMAND_SYNTAX_ERROR;
}
-
+
p = get_nand_device_by_num(strtoul(args[0], NULL, 0));
if (p)
{
@@ -1613,7 +1613,7 @@
return ERROR_COMMAND_SYNTAX_ERROR;
}
}
-
+
command_print(cmd_ctx, "raw access is %s", (p->use_raw) ? "enabled" : "disabled");
}
else
@@ -1625,6 +1625,6 @@
{
command_print(cmd_ctx, "NAND flash device '#%s' is out of bounds", args[0]);
}
-
+
return ERROR_OK;
}
Modified: trunk/src/flash/nand.h
===================================================================
--- trunk/src/flash/nand.h 2009-05-17 13:00:36 UTC (rev 1801)
+++ trunk/src/flash/nand.h 2009-05-18 04:37:33 UTC (rev 1802)
@@ -99,7 +99,7 @@
typedef struct nand_manufacturer_s
{
- int id;
+ int id;
char *name;
} nand_manufacturer_t;
@@ -115,43 +115,43 @@
/* Option constants for bizarre disfunctionality and real features
*/
-enum {
+enum {
/* Chip can not auto increment pages */
NAND_NO_AUTOINCR = 0x00000001,
-
+
/* Buswitdh is 16 bit */
NAND_BUSWIDTH_16 = 0x00000002,
-
+
/* Device supports partial programming without padding */
NAND_NO_PADDING = 0x00000004,
-
+
/* Chip has cache program function */
NAND_CACHEPRG = 0x00000008,
-
+
/* Chip has copy back function */
NAND_COPYBACK = 0x00000010,
-
+
/* AND Chip which has 4 banks and a confusing page / block
* assignment. See Renesas datasheet for further information */
NAND_IS_AND = 0x00000020,
-
+
/* Chip has a array of 4 pages which can be read without
* additional ready /busy waits */
NAND_4PAGE_ARRAY = 0x00000040,
-
+
/* Chip requires that BBT is periodically rewritten to prevent
* bits from adjacent blocks from 'leaking' in altering data.
* This happens with the Renesas AG-AND chips, possibly others. */
BBT_AUTO_REFRESH = 0x00000080,
-
+
/* Chip does not require ready check on read. True
* for all large page devices, as they do not support
* autoincrement.*/
NAND_NO_READRDY = 0x00000100,
-
+
/* Options valid for Samsung large page devices */
NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
-
+
/* Options for new chips with large page size. The pagesize and the
* erasesize is determined from the extended id bytes
*/
@@ -175,7 +175,7 @@
NAND_CMD_READID = 0x90,
NAND_CMD_ERASE2 = 0xd0,
NAND_CMD_RESET = 0xff,
-
+
/* Extended commands for large page devices */
NAND_CMD_READSTART = 0x30,
NAND_CMD_RNDOUTSTART = 0xE0,
@@ -198,7 +198,7 @@
NAND_OOB_NONE = 0x0, /* no OOB data at all */
NAND_OOB_RAW = 0x1, /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */
NAND_OOB_ONLY = 0x2, /* only OOB data */
- NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
+ NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
NAND_OOB_SW_ECC_KW = 0x40, /* when writing, use Marvell's Kirkwood bootrom format */
NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
Modified: trunk/src/flash/s3c2410_nand.c
===================================================================
--- trunk/src/flash/s3c2410_nand.c 2009-05-17 13:00:36 UTC (rev 1801)
+++ trunk/src/flash/s3c2410_nand.c 2009-05-18 04:37:33 UTC (rev 1802)
@@ -59,7 +59,7 @@
struct nand_device_s *device)
{
s3c24xx_nand_controller_t *info;
-
+
info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
if (info == NULL) {
return ERROR_NAND_DEVICE_INVALID;
@@ -70,7 +70,7 @@
info->addr = S3C2410_NFADDR;
info->data = S3C2410_NFDATA;
info->nfstat = S3C2410_NFSTAT;
-
+
return ERROR_OK;
}
@@ -79,7 +79,7 @@
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
- target_write_u32(target, S3C2410_NFCONF,
+ target_write_u32(target, S3C2410_NFCONF,
S3C2410_NFCONF_EN | S3C2410_NFCONF_TACLS(3) |
S3C2410_NFCONF_TWRPH0(5) | S3C2410_NFCONF_TWRPH1(3));
@@ -95,7 +95,7 @@
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
target_write_u32(target, S3C2410_NFDATA, data);
return ERROR_OK;
}
@@ -104,13 +104,13 @@
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
-
+
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
- target_read_u8(target, S3C2410_NFDATA, data);
+ target_read_u8(target, S3C2410_NFDATA, data);
return ERROR_OK;
}
@@ -124,14 +124,14 @@
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
do {
target_read_u8(target, S3C2410_NFSTAT, &status);
-
+
if (status & S3C2410_NFSTAT_BUSY)
return 1;
- alive_sleep(1);
+ alive_sleep(1);
} while (timeout-- > 0);
return 0;
Modified: trunk/src/flash/s3c2412_nand.c
===================================================================
--- trunk/src/flash/s3c2412_nand.c 2009-05-17 13:00:36 UTC (rev 1801)
+++ trunk/src/flash/s3c2412_nand.c 2009-05-18 04:37:33 UTC (rev 1802)
@@ -69,7 +69,7 @@
info->addr = S3C2440_NFADDR;
info->data = S3C2440_NFDATA;
info->nfstat = S3C2412_NFSTAT;
-
+
return ERROR_OK;
}
Modified: trunk/src/flash/s3c2440_nand.c
===================================================================
--- trunk/src/flash/s3c2440_nand.c 2009-05-17 13:00:36 UTC (rev 1801)
+++ trunk/src/flash/s3c2440_nand.c 2009-05-18 04:37:33 UTC (rev 1802)
@@ -59,7 +59,7 @@
struct nand_device_s *device)
{
s3c24xx_nand_controller_t *info;
-
+
info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
if (info == NULL) {
return ERROR_NAND_DEVICE_INVALID;
@@ -70,7 +70,7 @@
info->addr = S3C2440_NFADDR;
info->data = S3C2440_NFDATA;
info->nfstat = S3C2440_NFSTAT;
-
+
return ERROR_OK;
}
@@ -100,10 +100,10 @@
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
- do {
+
+ do {
target_read_u8(target, s3c24xx_info->nfstat, &status);
-
+
if (status & S3C2440_NFSTAT_READY)
return 1;
@@ -130,7 +130,7 @@
return ERROR_NAND_OPERATION_FAILED;
}
- while (data_size >= 4) {
+ while (data_size >= 4) {
target_read_u32(target, nfdata, &tmp);
data[0] = tmp;
@@ -164,7 +164,7 @@
return ERROR_NAND_OPERATION_FAILED;
}
- while (data_size >= 4) {
+ while (data_size >= 4) {
tmp = le_to_h_u32(data);
target_write_u32(target, nfdata, tmp);
Modified: trunk/src/flash/s3c2443_nand.c
===================================================================
--- trunk/src/flash/s3c2443_nand.c 2009-05-17 13:00:36 UTC (rev 1801)
+++ trunk/src/flash/s3c2443_nand.c 2009-05-18 04:37:33 UTC (rev 1802)
@@ -58,7 +58,7 @@
struct nand_device_s *device)
{
s3c24xx_nand_controller_t *info;
-
+
info = s3c24xx_nand_device_command(cmd_ctx, cmd, args, argc, device);
if (info == NULL) {
return ERROR_NAND_DEVICE_INVALID;
@@ -69,7 +69,7 @@
info->addr = S3C2440_NFADDR;
info->data = S3C2440_NFDATA;
info->nfstat = S3C2412_NFSTAT;
-
+
return ERROR_OK;
}
Modified: trunk/src/flash/s3c24xx_nand.c
===================================================================
--- trunk/src/flash/s3c24xx_nand.c 2009-05-17 13:00:36 UTC (rev 1801)
+++ trunk/src/flash/s3c24xx_nand.c 2009-05-18 04:37:33 UTC (rev 1802)
@@ -37,7 +37,7 @@
struct nand_device_s *device)
{
s3c24xx_nand_controller_t *s3c24xx_info;
-
+
s3c24xx_info = malloc(sizeof(s3c24xx_nand_controller_t));
if (s3c24xx_info == NULL) {
LOG_ERROR("no memory for nand controller\n");
@@ -69,9 +69,9 @@
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
target_write_u32(target, s3c24xx_info->cmd, 0xff);
-
+
return ERROR_OK;
}
@@ -79,7 +79,7 @@
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
-
+
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
@@ -94,12 +94,12 @@
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
-
+
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
target_write_u16(target, s3c24xx_info->addr, address);
return ERROR_OK;
}
@@ -113,7 +113,7 @@
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
}
-
+
target_write_u8(target, s3c24xx_info->data, data);
return ERROR_OK;
}
@@ -122,7 +122,7 @@
{
s3c24xx_nand_controller_t *s3c24xx_info = device->controller_priv;
target_t *target = s3c24xx_info->target;
-
+
if (target->state != TARGET_HALTED) {
LOG_ERROR("target must be halted to use S3C24XX NAND flash controller");
return ERROR_NAND_OPERATION_FAILED;
Modified: trunk/src/flash/s3c24xx_nand.h
===================================================================
--- trunk/src/flash/s3c24xx_nand.h 2009-05-17 13:00:36 UTC (rev 1801)
+++ trunk/src/flash/s3c24xx_nand.h 2009-05-18 04:37:33 UTC (rev 1802)
@@ -30,12 +30,12 @@
typedef struct s3c24xx_nand_controller_s
{
struct target_s *target;
-
+
/* register addresses */
u32 cmd;
u32 addr;
u32 data;
- u32 nfstat;
+ u32 nfstat;
} s3c24xx_nand_controller_t;
/* Default to using the un-translated NAND register based address */
Modified: trunk/src/flash/stellaris.h
===================================================================
--- trunk/src/flash/stellaris.h 2009-05-17 13:00:36 UTC (rev 1801)
+++ trunk/src/flash/stellaris.h 2009-05-18 04:37:33 UTC (rev 1802)
@@ -47,7 +47,6 @@
u32 rcc;
u8 mck_valid;
u32 mck_freq;
-
} stellaris_flash_bank_t;
/* STELLARIS control registers */
@@ -66,7 +65,7 @@
#define FMPRE 0x130
#define FMPPE 0x134
-#define USECRL 0x140
+#define USECRL 0x140
#define FLASH_CONTROL_BASE 0x400FD000
#define FLASH_FMA (FLASH_CONTROL_BASE|0x000)
@@ -87,7 +86,7 @@
#define FMC_COMT (1<<3)
#define FMC_MERASE (1<<2)
#define FMC_ERASE (1<<1)
-#define FMC_WRITE (1<<0)
+#define FMC_WRITE (1<<0)
/* STELLARIS constants */
Modified: trunk/src/flash/stm32x.h
===================================================================
--- trunk/src/flash/stm32x.h 2009-05-17 13:00:36 UTC (rev 1801)
+++ trunk/src/flash/stm32x.h 2009-05-18 04:37:33 UTC (rev 1802)
@@ -66,17 +66,17 @@
#define FLASH_PG (1<<0)
#define FLASH_PER (1<<1)
-#define FLASH_MER (1<<2)
+#define FLASH_MER (1<<2)
#define FLASH_OPTPG (1<<4)
#define FLASH_OPTER (1<<5)
#define FLASH_STRT (1<<6)
#define FLASH_LOCK (1<<7)
#define FLASH_OPTWRE (1<<9)
-/* FLASH_SR regsiter bits */
+/* FLASH_SR register bits */
#define FLASH_BSY (1<<0)
-#define FLASH_PGERR (1<<2)
+#define FLASH_PGERR (1<<2)
#define FLASH_WRPRTERR (1<<4)
#define FLASH_EOP (1<<5)
Modified: trunk/src/flash/str7x.h
===================================================================
--- trunk/src/flash/str7x.h 2009-05-17 13:00:36 UTC (rev 1801)
+++ trunk/src/flash/str7x.h 2009-05-18 04:37:33 UTC (rev 1802)
@@ -59,14 +59,14 @@
#define FLASH_AR 0x00000010
#define FLASH_ER 0x00000014
#define FLASH_NVWPAR 0x0000DFB0
-#define FLASH_NVAPR0 0x0000DFB8
-#define FLASH_NVAPR1 0x0000DFBC
+#define FLASH_NVAPR0 0x0000DFB8
+#define FLASH_NVAPR1 0x0000DFBC
/* FLASH_CR0 register bits */
#define FLASH_WMS 0x80000000
#define FLASH_SUSP 0x40000000
-#define FLASH_WPG 0x20000000
+#define FLASH_WPG 0x20000000
#define FLASH_DWPG 0x10000000
#define FLASH_SER 0x08000000
#define FLASH_SPR 0x01000000
@@ -76,7 +76,7 @@
#define FLASH_BSYA1 0x00000004
#define FLASH_BSYA0 0x00000002
-/* FLASH_CR1 regsiter bits */
+/* FLASH_CR1 register bits */
#define FLASH_B1S 0x02000000
#define FLASH_B0S 0x01000000
|
|
From: <oh...@ma...> - 2009-05-17 15:00:39
|
Author: oharboe
Date: 2009-05-17 15:00:36 +0200 (Sun, 17 May 2009)
New Revision: 1801
Modified:
trunk/src/target/target.c
Log:
fix array2mem/mem2array when used as a "method" on a target.
Modified: trunk/src/target/target.c
===================================================================
--- trunk/src/target/target.c 2009-05-16 20:09:07 UTC (rev 1800)
+++ trunk/src/target/target.c 2009-05-17 13:00:36 UTC (rev 1801)
@@ -1285,8 +1285,8 @@
/* script procedures */
register_command(cmd_ctx, NULL, "profile", handle_profile_command, COMMAND_EXEC, "profiling samples the CPU PC");
- register_jim(cmd_ctx, "ocd_mem2array", jim_mem2array, "read memory and return as a TCL array for script processing");
- register_jim(cmd_ctx, "ocd_array2mem", jim_array2mem, "convert a TCL array to memory locations and write the values");
+ register_jim(cmd_ctx, "ocd_mem2array", jim_mem2array, "read memory and return as a TCL array for script processing <ARRAYNAME> <WIDTH=32/16/8> <ADDRESS> <COUNT>");
+ register_jim(cmd_ctx, "ocd_array2mem", jim_array2mem, "convert a TCL array to memory locations and write the values <ARRAYNAME> <WIDTH=32/16/8> <ADDRESS> <COUNT>");
register_command(cmd_ctx, NULL, "fast_load_image", handle_fast_load_image_command, COMMAND_ANY,
"same args as load_image, image stored in memory - mainly for profiling purposes");
@@ -2721,7 +2721,7 @@
return JIM_ERR;
}
- return target_mem2array(interp, target, argc,argv);
+ return target_mem2array(interp, target, argc-1, argv+1);
}
static int target_mem2array(Jim_Interp *interp, target_t *target, int argc, Jim_Obj *const *argv)
@@ -2742,25 +2742,25 @@
* argv[3] = memory address
* argv[4] = count of times to read
*/
- if (argc != 5) {
+ if (argc != 4) {
Jim_WrongNumArgs(interp, 1, argv, "varname width addr nelems");
return JIM_ERR;
}
- varname = Jim_GetString(argv[1], &len);
+ varname = Jim_GetString(argv[0], &len);
/* given "foo" get space for worse case "foo(%d)" .. add 20 */
- e = Jim_GetLong(interp, argv[2], &l);
+ e = Jim_GetLong(interp, argv[1], &l);
width = l;
if (e != JIM_OK) {
return e;
}
- e = Jim_GetLong(interp, argv[3], &l);
+ e = Jim_GetLong(interp, argv[2], &l);
addr = l;
if (e != JIM_OK) {
return e;
}
- e = Jim_GetLong(interp, argv[4], &l);
+ e = Jim_GetLong(interp, argv[3], &l);
len = l;
if (e != JIM_OK) {
return e;
@@ -2903,7 +2903,7 @@
return JIM_ERR;
}
- return target_array2mem( interp,target, argc, argv );
+ return target_array2mem( interp,target, argc-1, argv+1 );
}
static int target_array2mem(Jim_Interp *interp, target_t *target, int argc, Jim_Obj *const *argv)
@@ -2924,25 +2924,25 @@
* argv[3] = memory address
* argv[4] = count to write
*/
- if (argc != 5) {
+ if (argc != 4) {
Jim_WrongNumArgs(interp, 1, argv, "varname width addr nelems");
return JIM_ERR;
}
- varname = Jim_GetString(argv[1], &len);
+ varname = Jim_GetString(argv[0], &len);
/* given "foo" get space for worse case "foo(%d)" .. add 20 */
- e = Jim_GetLong(interp, argv[2], &l);
+ e = Jim_GetLong(interp, argv[1], &l);
width = l;
if (e != JIM_OK) {
return e;
}
- e = Jim_GetLong(interp, argv[3], &l);
+ e = Jim_GetLong(interp, argv[2], &l);
addr = l;
if (e != JIM_OK) {
return e;
}
- e = Jim_GetLong(interp, argv[4], &l);
+ e = Jim_GetLong(interp, argv[3], &l);
len = l;
if (e != JIM_OK) {
return e;
|
|
From: <oh...@ma...> - 2009-05-16 22:09:14
|
Author: oharboe
Date: 2009-05-16 22:09:07 +0200 (Sat, 16 May 2009)
New Revision: 1800
Modified:
trunk/src/jtag/amt_jtagaccel.c
trunk/src/jtag/arm-jtag-ew.c
trunk/src/jtag/bitbang.c
trunk/src/jtag/ft2232.c
trunk/src/jtag/gw16012.c
trunk/src/jtag/jlink.c
trunk/src/jtag/jtag.c
trunk/src/jtag/jtag.h
trunk/src/jtag/rlink/rlink.c
trunk/src/jtag/usbprog.c
trunk/src/jtag/vsllink.c
Log:
Michael Bruck <mb...@di...> change 'ir_scan' from 'int' to 'bool' to document its semantics
Modified: trunk/src/jtag/amt_jtagaccel.c
===================================================================
--- trunk/src/jtag/amt_jtagaccel.c 2009-05-16 14:59:10 UTC (rev 1799)
+++ trunk/src/jtag/amt_jtagaccel.c 2009-05-16 20:09:07 UTC (rev 1800)
@@ -233,7 +233,7 @@
amt_jtagaccel_state_move();
}
-static void amt_jtagaccel_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
+static void amt_jtagaccel_scan(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size)
{
int bits_left = scan_size;
int bit_count = 0;
Modified: trunk/src/jtag/arm-jtag-ew.c
===================================================================
--- trunk/src/jtag/arm-jtag-ew.c 2009-05-16 14:59:10 UTC (rev 1799)
+++ trunk/src/jtag/arm-jtag-ew.c 2009-05-16 20:09:07 UTC (rev 1800)
@@ -72,7 +72,7 @@
static void armjtagew_state_move(void);
static void armjtagew_path_move(int num_states, tap_state_t *path);
static void armjtagew_runtest(int num_cycles);
-static void armjtagew_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command);
+static void armjtagew_scan(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command);
static void armjtagew_reset(int trst, int srst);
//static void armjtagew_simple_command(u8 command);
static int armjtagew_get_status(void);
@@ -401,7 +401,7 @@
}
}
-static void armjtagew_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command)
+static void armjtagew_scan(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command)
{
tap_state_t saved_end_state;
Modified: trunk/src/jtag/bitbang.c
===================================================================
--- trunk/src/jtag/bitbang.c 2009-05-16 14:59:10 UTC (rev 1799)
+++ trunk/src/jtag/bitbang.c 2009-05-16 20:09:07 UTC (rev 1800)
@@ -168,7 +168,7 @@
-static void bitbang_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
+static void bitbang_scan(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size)
{
tap_state_t saved_end_state = tap_get_end_state();
int bit_cnt;
Modified: trunk/src/jtag/ft2232.c
===================================================================
--- trunk/src/jtag/ft2232.c 2009-05-16 14:59:10 UTC (rev 1799)
+++ trunk/src/jtag/ft2232.c 2009-05-16 20:09:07 UTC (rev 1800)
@@ -573,7 +573,7 @@
}
-void ft2232_add_scan(int ir_scan, enum scan_type type, u8* buffer, int scan_size)
+void ft2232_add_scan(bool ir_scan, enum scan_type type, u8* buffer, int scan_size)
{
int num_bytes = (scan_size + 7) / 8;
int bits_left = scan_size;
Modified: trunk/src/jtag/gw16012.c
===================================================================
--- trunk/src/jtag/gw16012.c 2009-05-16 14:59:10 UTC (rev 1799)
+++ trunk/src/jtag/gw16012.c 2009-05-16 20:09:07 UTC (rev 1800)
@@ -263,7 +263,7 @@
gw16012_state_move();
}
-static void gw16012_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
+static void gw16012_scan(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size)
{
int bits_left = scan_size;
int bit_count = 0;
Modified: trunk/src/jtag/jlink.c
===================================================================
--- trunk/src/jtag/jlink.c 2009-05-16 14:59:10 UTC (rev 1799)
+++ trunk/src/jtag/jlink.c 2009-05-16 20:09:07 UTC (rev 1800)
@@ -83,7 +83,7 @@
static void jlink_state_move(void);
static void jlink_path_move(int num_states, tap_state_t *path);
static void jlink_runtest(int num_cycles);
-static void jlink_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command);
+static void jlink_scan(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command);
static void jlink_reset(int trst, int srst);
static void jlink_simple_command(u8 command);
static int jlink_get_status(void);
@@ -434,7 +434,7 @@
}
}
-static void jlink_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command)
+static void jlink_scan(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command)
{
tap_state_t saved_end_state;
Modified: trunk/src/jtag/jtag.c
===================================================================
--- trunk/src/jtag/jtag.c 2009-05-16 14:59:10 UTC (rev 1799)
+++ trunk/src/jtag/jtag.c 2009-05-16 20:09:07 UTC (rev 1800)
@@ -592,7 +592,7 @@
/* allocate memory for ir scan command */
(*last_cmd)->cmd.scan = cmd_queue_alloc(sizeof(scan_command_t));
- (*last_cmd)->cmd.scan->ir_scan = 1;
+ (*last_cmd)->cmd.scan->ir_scan = true;
x = jtag_NumEnabledTaps();
(*last_cmd)->cmd.scan->num_fields = x; /* one field per device */
(*last_cmd)->cmd.scan->fields = cmd_queue_alloc(x * sizeof(scan_field_t));
@@ -672,7 +672,7 @@
/* allocate memory for ir scan command */
(*last_cmd)->cmd.scan = cmd_queue_alloc(sizeof(scan_command_t));
- (*last_cmd)->cmd.scan->ir_scan = 1;
+ (*last_cmd)->cmd.scan->ir_scan = true;
(*last_cmd)->cmd.scan->num_fields = num_fields;
(*last_cmd)->cmd.scan->fields = cmd_queue_alloc(num_fields * sizeof(scan_field_t));
(*last_cmd)->cmd.scan->end_state = state;
@@ -797,7 +797,7 @@
/* allocate memory for dr scan command */
(*last_cmd)->cmd.scan = cmd_queue_alloc(sizeof(scan_command_t));
- (*last_cmd)->cmd.scan->ir_scan = 0;
+ (*last_cmd)->cmd.scan->ir_scan = false;
(*last_cmd)->cmd.scan->num_fields = num_fields + bypass_devices;
(*last_cmd)->cmd.scan->fields = cmd_queue_alloc((num_fields + bypass_devices) * sizeof(scan_field_t));
(*last_cmd)->cmd.scan->end_state = state;
@@ -891,7 +891,7 @@
/* allocate memory for dr scan command */
(*last_cmd)->cmd.scan = cmd_queue_alloc(sizeof(scan_command_t));
- (*last_cmd)->cmd.scan->ir_scan = 0;
+ (*last_cmd)->cmd.scan->ir_scan = false;
(*last_cmd)->cmd.scan->num_fields = num_fields + bypass_devices;
(*last_cmd)->cmd.scan->fields = cmd_queue_alloc((num_fields + bypass_devices) * sizeof(scan_field_t));
(*last_cmd)->cmd.scan->end_state = end_state;
@@ -970,7 +970,7 @@
/* allocate memory for scan command */
(*last_cmd)->cmd.scan = cmd_queue_alloc(sizeof(scan_command_t));
- (*last_cmd)->cmd.scan->ir_scan = 0;
+ (*last_cmd)->cmd.scan->ir_scan = false;
(*last_cmd)->cmd.scan->num_fields = num_fields;
(*last_cmd)->cmd.scan->fields = cmd_queue_alloc(num_fields * sizeof(scan_field_t));
(*last_cmd)->cmd.scan->end_state = state;
Modified: trunk/src/jtag/jtag.h
===================================================================
--- trunk/src/jtag/jtag.h 2009-05-16 14:59:10 UTC (rev 1799)
+++ trunk/src/jtag/jtag.h 2009-05-16 20:09:07 UTC (rev 1800)
@@ -287,7 +287,7 @@
typedef struct scan_command_s
{
- int ir_scan; /* instruction/not data scan */
+ bool ir_scan; /* instruction/not data scan */
int num_fields; /* number of fields in *fields array */
scan_field_t* fields; /* pointer to an array of data scan fields */
tap_state_t end_state; /* TAP state in which JTAG commands should finish */
Modified: trunk/src/jtag/rlink/rlink.c
===================================================================
--- trunk/src/jtag/rlink/rlink.c 2009-05-16 14:59:10 UTC (rev 1799)
+++ trunk/src/jtag/rlink/rlink.c 2009-05-16 20:09:07 UTC (rev 1800)
@@ -1094,7 +1094,7 @@
u8 *buffer,
int scan_size
) {
- int ir_scan;
+ bool ir_scan;
tap_state_t saved_end_state;
int byte_bits;
int extra_bits;
Modified: trunk/src/jtag/usbprog.c
===================================================================
--- trunk/src/jtag/usbprog.c 2009-05-16 14:59:10 UTC (rev 1799)
+++ trunk/src/jtag/usbprog.c 2009-05-16 20:09:07 UTC (rev 1800)
@@ -58,7 +58,7 @@
static void usbprog_state_move(void);
static void usbprog_path_move(pathmove_command_t *cmd);
static void usbprog_runtest(int num_cycles);
-static void usbprog_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size);
+static void usbprog_scan(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size);
jtag_interface_t usbprog_interface =
{
@@ -336,7 +336,7 @@
*/
}
-static void usbprog_scan(int ir_scan, enum scan_type type, u8 *buffer, int scan_size)
+static void usbprog_scan(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size)
{
tap_state_t saved_end_state = tap_get_end_state();
Modified: trunk/src/jtag/vsllink.c
===================================================================
--- trunk/src/jtag/vsllink.c 2009-05-16 14:59:10 UTC (rev 1799)
+++ trunk/src/jtag/vsllink.c 2009-05-16 20:09:07 UTC (rev 1800)
@@ -204,9 +204,9 @@
static void vsllink_stableclocks_dma(int num_cycles, int tms);
static void vsllink_stableclocks_normal(int num_cycles, int tms);
static void (*vsllink_stableclocks)(int num_cycles, int tms);
-static void vsllink_scan_dma(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command);
-static void vsllink_scan_normal(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command);
-static void (*vsllink_scan)(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command);
+static void vsllink_scan_dma(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command);
+static void vsllink_scan_normal(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command);
+static void (*vsllink_scan)(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command);
static void vsllink_reset(int trst, int srst);
static void vsllink_simple_command(u8 command);
static int vsllink_connect(void);
@@ -1189,7 +1189,7 @@
}
}
-static void vsllink_scan_normal(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command)
+static void vsllink_scan_normal(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command)
{
tap_state_t saved_end_state;
u8 bits_left, tms_tmp, tdi_len;
@@ -1305,7 +1305,7 @@
tap_set_state(tap_get_end_state());
}
-static void vsllink_scan_dma(int ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command)
+static void vsllink_scan_dma(bool ir_scan, enum scan_type type, u8 *buffer, int scan_size, scan_command_t *command)
{
tap_state_t saved_end_state;
|
|
From: <oh...@ma...> - 2009-05-16 16:59:15
|
Author: oharboe
Date: 2009-05-16 16:59:10 +0200 (Sat, 16 May 2009)
New Revision: 1799
Modified:
trunk/src/flash/at91sam7.c
Log:
fix naming of at91sam7 driver
Modified: trunk/src/flash/at91sam7.c
===================================================================
--- trunk/src/flash/at91sam7.c 2009-05-16 14:57:02 UTC (rev 1798)
+++ trunk/src/flash/at91sam7.c 2009-05-16 14:59:10 UTC (rev 1799)
@@ -62,7 +62,7 @@
flash_driver_t at91sam7_flash =
{
- .name = "at91sam7_new",
+ .name = "at91sam7",
.register_commands = at91sam7_register_commands,
.flash_bank_command = at91sam7_flash_bank_command,
.erase = at91sam7_erase,
@@ -104,7 +104,7 @@
static int at91sam7_register_commands(struct command_context_s *cmd_ctx)
{
- command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7_new", NULL, COMMAND_ANY, NULL);
+ command_t *at91sam7_cmd = register_command(cmd_ctx, NULL, "at91sam7", NULL, COMMAND_ANY, NULL);
register_command(cmd_ctx, at91sam7_cmd, "gpnvm", at91sam7_handle_gpnvm_command, COMMAND_EXEC,
"at91sam7 gpnvm <bit> set|clear, set or clear one gpnvm bit");
|
|
From: <oh...@ma...> - 2009-05-16 16:57:09
|
Author: oharboe
Date: 2009-05-16 16:57:02 +0200 (Sat, 16 May 2009)
New Revision: 1798
Added:
trunk/src/target/board/crossbow_tech_imote2.cfg
trunk/src/target/board/digi_connectcore_wi-9c.cfg
trunk/src/target/board/hitex_stm32-performancestick.cfg
trunk/src/target/board/hitex_str9-comstick.cfg
trunk/src/target/board/linksys_nslu2.cfg
trunk/src/target/board/pxa255_sst.cfg
trunk/src/target/board/str910-eval.cfg
trunk/src/target/board/zy1000.cfg
trunk/src/target/interface/hitex_str9-comstick.cfg
Removed:
trunk/src/target/board/hitex_str9_comstick.cfg
trunk/src/target/interface/str9-comstick.cfg
trunk/src/target/target/imote2.cfg
trunk/src/target/target/nslu2.cfg
trunk/src/target/target/pxa255_sst.cfg
trunk/src/target/target/stm32stick.cfg
trunk/src/target/target/str910-eval.cfg
trunk/src/target/target/str9comstick.cfg
trunk/src/target/target/wi-9c.cfg
trunk/src/target/target/zy1000.cfg
Log:
Freddie Chopin <fre...@op...> move files about to where they belong
Added: trunk/src/target/board/crossbow_tech_imote2.cfg
===================================================================
--- trunk/src/target/board/crossbow_tech_imote2.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/board/crossbow_tech_imote2.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -0,0 +1,46 @@
+# Crossbow Technology iMote2
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME imote2
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # force an error till we get a good number
+ set _CPUTAPID 0xffffffff
+}
+
+# PXA271 and an Intel Strataflash of 32 Megabytes (p30)
+#
+# Marvell/Intel PXA270 Script
+# set jtag_nsrst_delay to the delay introduced by your reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_nsrst_delay 800
+# set the jtag_ntrst_delay to the delay introduced by a reset circuit
+# the rest of the needed delays are built into the openocd program
+jtag_ntrst_delay 0
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst separate
+#jtag scan chain
+
+jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
+$_TARGETNAME configure -work-area-virt 0x0x5c000000 -work-area-phys 0x0x5c000000 -work-area-size 0x10000 -work-area-backup 1
+# maps to PXA internal RAM. If you are using a PXA255
+# you must initialize SDRAM or leave this option off
+
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+# works for P30 flash
+flash bank cfi 0x00000000 0x2000000 2 2 0
Added: trunk/src/target/board/digi_connectcore_wi-9c.cfg
===================================================================
--- trunk/src/target/board/digi_connectcore_wi-9c.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/board/digi_connectcore_wi-9c.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -0,0 +1,127 @@
+######################################
+# Target: DIGI ConnectCore Wi-9C
+######################################
+
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME ns9360
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ # This config file was defaulting to big endian..
+ set _ENDIAN big
+}
+
+
+# What's a good fallback frequency for this board if RCLK is
+# not available??
+jtag_rclk 1000
+
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0xFFFFFFFF
+}
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+jtag_nsrst_delay 200
+jtag_ntrst_delay 0
+
+
+######################
+# Target configuration
+######################
+
+target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
+$_TARGETNAME configure -event reset-init {
+ mww 0x90600104 0x33313333
+ mww 0xA0700000 0x00000001 # Enable the memory controller.
+ mww 0xA0700024 0x00000006 # Set the refresh counter 6
+ mww 0xA0700028 0x00000001 #
+ mww 0xA0700030 0x00000001 # Set the precharge period
+ mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
+ mww 0xA070003C 0x00000001 # tAPR
+ mww 0xA0700040 0x00000005 # tDAL
+ mww 0xA0700044 0x00000001 # tWR
+ mww 0xA0700048 0x00000006 # tRC 32 clock cycles
+ mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
+ mww 0xA0700054 0x00000001 # tRRD
+ mww 0xA0700058 0x00000001 # tMRD
+ mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
+ mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
+ mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
+ mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
+ #
+ mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
+ mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
+ mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
+ mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
+ #
+ mww 0xA0700020 0x00000103 # issue SDRAM PALL command
+ #
+ mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible
+ #
+ # Add some dummy writes to give the SDRAM time to settle, it needs two
+ # AHB clock cycles, here we poke in the debugger flag, this lets
+ # the software know that we are in the debugger
+ mww 0xA0900000 0x00000002
+ mww 0xA0900000 0x00000002
+ mww 0xA0900000 0x00000002
+ mww 0xA0900000 0x00000002
+ mww 0xA0900000 0x00000002
+ #
+ mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
+ mdw 0xA0900000
+ #
+ mww 0xA0700024 0x00000030 # Set the refresh counter to 30
+ mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
+ #
+ # Next we perform a read of RAM.
+ # mw = move word.
+ mdw 0x00022000
+ # mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
+ #
+ mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
+ mww 0xA0700100 0x00084280 # Enable buffer access
+ mww 0xA0700120 0x00084280 # Enable buffer access
+ mww 0xA0700140 0x00084280 # Enable buffer access
+ mww 0xA0700160 0x00084280 # Enable buffer access
+
+ #Set byte lane state (static mem 1)"
+ mww 0xA0700220, 0x00000082
+ #Flash Start
+ mww 0xA09001F8, 0x50000000
+ #Flash Mask Reg
+ mww 0xA09001FC, 0xFF000001
+ mww 0xA0700028, 0x00000001
+
+ # RAMAddr = 0x00020000
+ # RAMSize = 0x00004000
+
+ # Set the processor mode
+ reg cpsr 0xd3
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
+
+#####################
+# Flash configuration
+#####################
+
+#M29DW323DB - not working
+#flash bank cfi <base> <size> <chip width> <bus width> <target#>
+flash bank cfi 0x50000000 0x0400000 2 2 0
+
+
+
Added: trunk/src/target/board/hitex_stm32-performancestick.cfg
===================================================================
--- trunk/src/target/board/hitex_stm32-performancestick.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/board/hitex_stm32-performancestick.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -0,0 +1,50 @@
+# Hitex stm32 performance stick
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME stm32_hitex
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+# set jtag speed
+jtag_khz 500
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+
+#jtag scan chain
+# The CPU
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ # See STM Document RM0008
+ # Section 26.6.3
+ set _CPUTAPID 0x3ba00477
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+# The boundery scan register, leave the "expected-id" undefined.
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1
+
+# configure str750 connected to jtag chain
+jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
+
+#
+flash bank stm32x 0 0 0 0 0
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
Added: trunk/src/target/board/hitex_str9-comstick.cfg
===================================================================
--- trunk/src/target/board/hitex_str9-comstick.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/board/hitex_str9-comstick.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -0,0 +1,72 @@
+# Hitex STR9-comStick
+# http://www.hitex.com/index.php?id=383
+# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.
+
+source [find interface/hitex_str9-comstick.cfg]
+
+# set jtag speed
+jtag_khz 3000
+
+jtag_nsrst_delay 100
+jtag_ntrst_delay 100
+#use combined on interfaces or targets that can't set TRST/SRST separately
+reset_config trst_and_srst
+#jtag scan chain
+#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists FLASHTAPID ] } {
+ set _FLASHTAPID $FLASHTAPID
+} else {
+ set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ # Found on STR9-comStick, revision STR912CS-A1
+ set _BSTAPID1 0x1457f041
+ # Found on STR9-comStick, revision STR912CS-A2
+ set _BSTAPID2 0x2457f041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
+
+$_TARGETNAME configure -event reset-init {
+ # We can increase speed now that we know the target is halted.
+ #jtag_rclk 3000
+
+ # -- Enable 96K RAM
+ # PFQBC enabled / DTCM & AHB wait-states disabled
+ mww 0x5C002034 0x0191
+
+ str9x flash_config 0 4 2 0 0x80000
+ flash protect 0 0 7 off
+}
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
+
+#flash bank <driver> <base> <size> <chip_width> <bus_width>
+flash bank str9x 0x00000000 0x00080000 0 0 0
+flash bank str9x 0x00080000 0x00008000 0 0 0
Deleted: trunk/src/target/board/hitex_str9_comstick.cfg
===================================================================
--- trunk/src/target/board/hitex_str9_comstick.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/board/hitex_str9_comstick.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -1,11 +0,0 @@
-#
-# Hitex STR9-comStick
-#
-# http://www.hitex.com/index.php?id=383
-#
-
-# This works for the STR9-comStick revisions STR912CS-A1 and STR912CS-A2.
-
-source [find interface/str9-comstick.cfg]
-source [find target/str9comstick.cfg]
-
Added: trunk/src/target/board/linksys_nslu2.cfg
===================================================================
--- trunk/src/target/board/linksys_nslu2.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/board/linksys_nslu2.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -0,0 +1,8 @@
+# This is for the LinkSys (CISCO) NSLU2 board
+# It is an Intel XSCALE IXP420 CPU.
+
+source [find target/ixp42x.cfg]
+# The _TARGETNAME is set by the above.
+
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
+
Added: trunk/src/target/board/pxa255_sst.cfg
===================================================================
--- trunk/src/target/board/pxa255_sst.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/board/pxa255_sst.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -0,0 +1,15 @@
+# A PXA255 test board with SST 39LF400A flash
+#
+# At reset the memory map is as follows. Note that
+# the memory map changes later on as the application
+# starts...
+#
+# RAM at 0x4000000
+# Flash at 0x00000000
+#
+source [find target/pxa255.cfg]
+# Target name is set by above
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
+# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options]
+flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
+
Added: trunk/src/target/board/str910-eval.cfg
===================================================================
--- trunk/src/target/board/str910-eval.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/board/str910-eval.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -0,0 +1,61 @@
+# str910-eval eval board
+#
+# Need reset scripts
+reset_config trst_and_srst
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME str912
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+if { [info exists FLASHTAPID ] } {
+ set _FLASHTAPID $FLASHTAPID
+} else {
+ set _FLASHTAPID 0x04570041
+}
+jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
+
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x25966041
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+if { [info exists BSTAPID ] } {
+ set _BSTAPID $BSTAPID
+} else {
+ set _BSTAPID 0x1457f041
+}
+jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
+$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
+
+$_TARGETNAME configure -event reset-init {
+ # We can increase speed now that we know the target is halted.
+ #jtag_rclk 3000
+
+ # -- Enable 96K RAM
+ # PFQBC enabled / DTCM & AHB wait-states disabled
+ mww 0x5C002034 0x0191
+
+ str9x flash_config 0 4 2 0 0x80000
+ flash protect 0 0 7 off
+}
+
+#flash bank str9x <base> <size> 0 0 <target#> <variant>
+flash bank str9x 0x00000000 0x00080000 0 0 0
+flash bank str9x 0x00080000 0x00008000 0 0 0
+
+# For more information about the configuration files, take a look at:
+# openocd.texi
Added: trunk/src/target/board/zy1000.cfg
===================================================================
--- trunk/src/target/board/zy1000.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/board/zy1000.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -0,0 +1,110 @@
+#Script for ZY1000
+
+#Atmel ties SRST & TRST together, at which point it makes
+#no sense to use TRST, but use TMS instead.
+#
+#The annoying thing with tying SRST & TRST together is that
+#there is no way to halt the CPU *before and during* the
+#SRST reset, which means that the CPU will run a number
+#of cycles before it can be halted(as much as milliseconds).
+reset_config srst_only srst_pulls_trst
+
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ set _CHIPNAME zy1000
+}
+
+if { [info exists ENDIAN] } {
+ set _ENDIAN $ENDIAN
+} else {
+ set _ENDIAN little
+}
+
+
+#jtag scan chain
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ set _CPUTAPID 0x1f0f0f0f
+}
+jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+
+set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
+target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
+
+# at CPU CLK <32kHz this must be disabled
+arm7_9 fast_memory_access enable
+arm7_9 dcc_downloads enable
+
+flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
+$_TARGETNAME configure -event reset-init {
+ # Set up chip selects & timings
+ mww 0xFFE00000 0x0100273D
+ mww 0xFFE00004 0x08002125
+ mww 0xFFEe0008 0x02002125
+ mww 0xFFE0000c 0x03002125
+ mww 0xFFE00010 0x40000000
+ mww 0xFFE00014 0x50000000
+ mww 0xFFE00018 0x60000000
+ mww 0xFFE0001c 0x70000000
+ mww 0xFFE00020 0x00000001
+ mww 0xFFE00024 0x00000000
+
+ # remap
+ mww 0xFFFFF124 0xFFFFFFFF
+ mww 0xffff0010 0x100
+ mww 0xffff0034 0x100
+
+ #disable 16x5x UART interrupts
+ mww 0x08020004 0
+}
+
+# required for usable performance. Used for lots of
+# other things than flash programming.
+$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
+
+jtag_khz 16000
+
+
+proc production_info {} {
+ return "Serial number is official MAC number. Format XXXXXXXXXXXX"
+}
+
+# There is no return value from this procedure. If it is
+# successful it does not throw an exception
+#
+# Progress messages are output via puts
+proc production {firmwarefile serialnumber} {
+ if {[string length $serialnumber]!=12} {
+ puts "Invalid serial number"
+ return
+ }
+
+ puts "Power cycling target"
+ power off
+ sleep 3000
+ power on
+ sleep 1000
+ reset init
+ flash write_image erase $firmwarefile 0x1000000 bin
+ verify_image $firmwarefile 0x1000000 bin
+
+ # Big endian... weee!!!!
+ puts "Setting MAC number to $serialnumber"
+ flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2 3][string range $serialnumber 0 1]0000" 1
+ flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10 11][string range $serialnumber 8 9][string range $serialnumber 6 7][string range $serialnumber 4 5]" 1
+ puts "Production successful"
+}
+
+
+proc production_test {} {
+ power on
+ sleep 1000
+ target_request debugmsgs enable
+ reset run
+ sleep 25000
+ target_request debugmsgs disable
+ return "See IP address above..."
+}
Added: trunk/src/target/interface/hitex_str9-comstick.cfg
===================================================================
--- trunk/src/target/interface/hitex_str9-comstick.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/interface/hitex_str9-comstick.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -0,0 +1,11 @@
+#
+# Hitex STR9-comStick
+#
+# http://www.hitex.com/index.php?id=383
+#
+
+interface ft2232
+ft2232_device_desc "STR9-comStick A"
+ft2232_layout comstick
+ft2232_vid_pid 0x0640 0x002c
+
Deleted: trunk/src/target/interface/str9-comstick.cfg
===================================================================
--- trunk/src/target/interface/str9-comstick.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/interface/str9-comstick.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -1,11 +0,0 @@
-#
-# Hitex STR9-comStick
-#
-# http://www.hitex.com/index.php?id=383
-#
-
-interface ft2232
-ft2232_device_desc "STR9-comStick A"
-ft2232_layout comstick
-ft2232_vid_pid 0x0640 0x002c
-
Deleted: trunk/src/target/target/imote2.cfg
===================================================================
--- trunk/src/target/target/imote2.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/target/imote2.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -1,46 +0,0 @@
-# iMote2
-#
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME imote2
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # force an error till we get a good number
- set _CPUTAPID 0xffffffff
-}
-
-# PXA271 and an Intel Strataflash of 32 Megabytes (p30)
-#
-# Marvell/Intel PXA270 Script
-# set jtag_nsrst_delay to the delay introduced by your reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_nsrst_delay 800
-# set the jtag_ntrst_delay to the delay introduced by a reset circuit
-# the rest of the needed delays are built into the openocd program
-jtag_ntrst_delay 0
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst separate
-#jtag scan chain
-
-jtag newtap $_CHIPNAME cpu -irlen 7 -ircapture 0x1 -irmask 0x7f -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME xscale -endian $_ENDIAN -chain-position $_TARGETNAME -variant pxa27x
-$_TARGETNAME configure -work-area-virt 0x0x5c000000 -work-area-phys 0x0x5c000000 -work-area-size 0x10000 -work-area-backup 1
-# maps to PXA internal RAM. If you are using a PXA255
-# you must initialize SDRAM or leave this option off
-
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-# works for P30 flash
-flash bank cfi 0x00000000 0x2000000 2 2 0
Deleted: trunk/src/target/target/nslu2.cfg
===================================================================
--- trunk/src/target/target/nslu2.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/target/nslu2.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -1,8 +0,0 @@
-# This is for the LinkSys (CISCO) NSLU2 board
-# It is an Intel XSCALE IXP420 CPU.
-
-source [find target/ixp42x.cfg]
-# The _TARGETNAME is set by the above.
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x10000 -work-area-backup 0
-
Deleted: trunk/src/target/target/pxa255_sst.cfg
===================================================================
--- trunk/src/target/target/pxa255_sst.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/target/pxa255_sst.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -1,15 +0,0 @@
-# A PXA255 test board with SST 39LF400A flash
-#
-# At reset the memory map is as follows. Note that
-# the memory map changes later on as the application
-# starts...
-#
-# RAM at 0x4000000
-# Flash at 0x00000000
-#
-source [find target/pxa255.cfg]
-# Target name is set by above
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
-# flash bank <driver> <base> <size> <chip_width> <bus_width> <targetNum> [options]
-flash bank cfi 0x00000000 0x80000 2 2 0 jedec_probe
-
Deleted: trunk/src/target/target/stm32stick.cfg
===================================================================
--- trunk/src/target/target/stm32stick.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/target/stm32stick.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -1,50 +0,0 @@
-# Hitex stm32 performance stick
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME stm32_hitex
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-# set jtag speed
-jtag_khz 500
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-
-#jtag scan chain
-# The CPU
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- # See STM Document RM0008
- # Section 26.6.3
- set _CPUTAPID 0x3ba00477
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-# The boundery scan register, leave the "expected-id" undefined.
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1
-
-# configure str750 connected to jtag chain
-jtag newtap $_CHIPNAME unknown -irlen 4 -ircapture 0x1 -irmask 0x0f
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0
-
-#
-flash bank stm32x 0 0 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
Deleted: trunk/src/target/target/str910-eval.cfg
===================================================================
--- trunk/src/target/target/str910-eval.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/target/str910-eval.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -1,61 +0,0 @@
-# str910-eval eval board
-#
-# Need reset scripts
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists FLASHTAPID ] } {
- set _FLASHTAPID $FLASHTAPID
-} else {
- set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
-
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID ] } {
- set _BSTAPID $BSTAPID
-} else {
- set _BSTAPID 0x1457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-virt 0x50000000 -work-area-size 16384 -work-area-backup 1
-
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- #jtag_rclk 3000
-
- # -- Enable 96K RAM
- # PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
-
- str9x flash_config 0 4 2 0 0x80000
- flash protect 0 0 7 off
-}
-
-#flash bank str9x <base> <size> 0 0 <target#> <variant>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
-
-# For more information about the configuration files, take a look at:
-# openocd.texi
Deleted: trunk/src/target/target/str9comstick.cfg
===================================================================
--- trunk/src/target/target/str9comstick.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/target/str9comstick.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -1,68 +0,0 @@
-#Hitex STR9 Comstick
-
-# set jtag speed
-jtag_khz 3000
-
-jtag_nsrst_delay 100
-jtag_ntrst_delay 100
-#use combined on interfaces or targets that can't set TRST/SRST separately
-reset_config trst_and_srst
-#jtag scan chain
-#format L IRC IRCM IDCODE (Length, IR Capture, IR Capture Mask, IDCODE)
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME str912
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-if { [info exists FLASHTAPID ] } {
- set _FLASHTAPID $FLASHTAPID
-} else {
- set _FLASHTAPID 0x04570041
-}
-jtag newtap $_CHIPNAME flash -irlen 8 -ircapture 0x1 -irmask 0x1 -expected-id $_FLASHTAPID
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x25966041
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-if { [info exists BSTAPID ] } {
- set _BSTAPID $BSTAPID
-} else {
- # Found on STR9-comStick, revision STR912CS-A1
- set _BSTAPID1 0x1457f041
- # Found on STR9-comStick, revision STR912CS-A2
- set _BSTAPID2 0x2457f041
-}
-jtag newtap $_CHIPNAME bs -irlen 5 -ircapture 0x1 -irmask 0x1 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm966e -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm966e
-
-$_TARGETNAME configure -event reset-init {
- # We can increase speed now that we know the target is halted.
- #jtag_rclk 3000
-
- # -- Enable 96K RAM
- # PFQBC enabled / DTCM & AHB wait-states disabled
- mww 0x5C002034 0x0191
-
- str9x flash_config 0 4 2 0 0x80000
- flash protect 0 0 7 off
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
-
-#flash bank <driver> <base> <size> <chip_width> <bus_width>
-flash bank str9x 0x00000000 0x00080000 0 0 0
-flash bank str9x 0x00080000 0x00008000 0 0 0
Deleted: trunk/src/target/target/wi-9c.cfg
===================================================================
--- trunk/src/target/target/wi-9c.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/target/wi-9c.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -1,128 +0,0 @@
-# FIXME: THIS IS A *BOARD* not a CHIP configuration.
-######################################
-# Target: DIGI ConnectCore Wi-9C
-######################################
-
-reset_config trst_and_srst
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME ns9360
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- # This config file was defaulting to big endian..
- set _ENDIAN big
-}
-
-
-# What's a good fallback frequency for this board if RCLK is
-# not available??
-jtag_rclk 1000
-
-
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0xFFFFFFFF
-}
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-jtag_nsrst_delay 200
-jtag_ntrst_delay 0
-
-
-######################
-# Target configuration
-######################
-
-target create $_TARGETNAME arm926ejs -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm926ejs
-$_TARGETNAME configure -event reset-init {
- mww 0x90600104 0x33313333
- mww 0xA0700000 0x00000001 # Enable the memory controller.
- mww 0xA0700024 0x00000006 # Set the refresh counter 6
- mww 0xA0700028 0x00000001 #
- mww 0xA0700030 0x00000001 # Set the precharge period
- mww 0xA0700034 0x00000004 # Active to precharge command period is 16 clock cycles
- mww 0xA070003C 0x00000001 # tAPR
- mww 0xA0700040 0x00000005 # tDAL
- mww 0xA0700044 0x00000001 # tWR
- mww 0xA0700048 0x00000006 # tRC 32 clock cycles
- mww 0xA070004C 0x00000006 # tRFC 32 clock cycles
- mww 0xA0700054 0x00000001 # tRRD
- mww 0xA0700058 0x00000001 # tMRD
- mww 0xA0700100 0x00004280 # Dynamic Config 0 (cs4)
- mww 0xA0700120 0x00004280 # Dynamic Config 1 (cs5)
- mww 0xA0700140 0x00004280 # Dynamic Config 2 (cs6)
- mww 0xA0700160 0x00004280 # Dynamic Config 3 (cs7)
- #
- mww 0xA0700104 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700124 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700144 0x00000203 # CAS latency is 2 at 100 MHz
- mww 0xA0700164 0x00000203 # CAS latency is 2 at 100 MHz
- #
- mww 0xA0700020 0x00000103 # issue SDRAM PALL command
- #
- mww 0xA0700024 0x00000001 # Set the refresh counter to be as small as possible
- #
- # Add some dummy writes to give the SDRAM time to settle, it needs two
- # AHB clock cycles, here we poke in the debugger flag, this lets
- # the software know that we are in the debugger
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- mww 0xA0900000 0x00000002
- #
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- mdw 0xA0900000
- #
- mww 0xA0700024 0x00000030 # Set the refresh counter to 30
- mww 0xA0700020 0x00000083 # Issue SDRAM MODE command
- #
- # Next we perform a read of RAM.
- # mw = move word.
- mdw 0x00022000
- # mw 0x00022000:P, r3 # 22000 for cas2 latency, 32000 for cas 3
- #
- mww 0xA0700020 0x00000003 # issue SDRAM NORMAL command
- mww 0xA0700100 0x00084280 # Enable buffer access
- mww 0xA0700120 0x00084280 # Enable buffer access
- mww 0xA0700140 0x00084280 # Enable buffer access
- mww 0xA0700160 0x00084280 # Enable buffer access
-
- #Set byte lane state (static mem 1)"
- mww 0xA0700220, 0x00000082
- #Flash Start
- mww 0xA09001F8, 0x50000000
- #Flash Mask Reg
- mww 0xA09001FC, 0xFF000001
- mww 0xA0700028, 0x00000001
-
- # RAMAddr = 0x00020000
- # RAMSize = 0x00004000
-
- # Set the processor mode
- reg cpsr 0xd3
-}
-
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00000000 -work-area-size 0x1000 -work-area-backup 1
-
-#####################
-# Flash configuration
-#####################
-
-#M29DW323DB - not working
-#flash bank cfi <base> <size> <chip width> <bus width> <target#>
-flash bank cfi 0x50000000 0x0400000 2 2 0
-
-
-
Deleted: trunk/src/target/target/zy1000.cfg
===================================================================
--- trunk/src/target/target/zy1000.cfg 2009-05-15 23:35:27 UTC (rev 1797)
+++ trunk/src/target/target/zy1000.cfg 2009-05-16 14:57:02 UTC (rev 1798)
@@ -1,110 +0,0 @@
-#Script for ZY1000
-
-#Atmel ties SRST & TRST together, at which point it makes
-#no sense to use TRST, but use TMS instead.
-#
-#The annoying thing with tying SRST & TRST together is that
-#there is no way to halt the CPU *before and during* the
-#SRST reset, which means that the CPU will run a number
-#of cycles before it can be halted(as much as milliseconds).
-reset_config srst_only srst_pulls_trst
-
-
-if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
-} else {
- set _CHIPNAME zy1000
-}
-
-if { [info exists ENDIAN] } {
- set _ENDIAN $ENDIAN
-} else {
- set _ENDIAN little
-}
-
-
-#jtag scan chain
-if { [info exists CPUTAPID ] } {
- set _CPUTAPID $CPUTAPID
-} else {
- set _CPUTAPID 0x1f0f0f0f
-}
-jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-
-set _TARGETNAME [format "%s.cpu" $_CHIPNAME]
-target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAME -variant arm7tdmi-s_r4
-
-# at CPU CLK <32kHz this must be disabled
-arm7_9 fast_memory_access enable
-arm7_9 dcc_downloads enable
-
-flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
-$_TARGETNAME configure -event reset-init {
- # Set up chip selects & timings
- mww 0xFFE00000 0x0100273D
- mww 0xFFE00004 0x08002125
- mww 0xFFEe0008 0x02002125
- mww 0xFFE0000c 0x03002125
- mww 0xFFE00010 0x40000000
- mww 0xFFE00014 0x50000000
- mww 0xFFE00018 0x60000000
- mww 0xFFE0001c 0x70000000
- mww 0xFFE00020 0x00000001
- mww 0xFFE00024 0x00000000
-
- # remap
- mww 0xFFFFF124 0xFFFFFFFF
- mww 0xffff0010 0x100
- mww 0xffff0034 0x100
-
- #disable 16x5x UART interrupts
- mww 0x08020004 0
-}
-
-# required for usable performance. Used for lots of
-# other things than flash programming.
-$_TARGETNAME configure -work-area-virt 0 -work-area-phys 0x00020000 -work-area-size 0x20000 -work-area-backup 0
-
-jtag_khz 16000
-
-
-proc production_info {} {
- return "Serial number is official MAC number. Format XXXXXXXXXXXX"
-}
-
-# There is no return value from this procedure. If it is
-# successful it does not throw an exception
-#
-# Progress messages are output via puts
-proc production {firmwarefile serialnumber} {
- if {[string length $serialnumber]!=12} {
- puts "Invalid serial number"
- return
- }
-
- puts "Power cycling target"
- power off
- sleep 3000
- power on
- sleep 1000
- reset init
- flash write_image erase $firmwarefile 0x1000000 bin
- verify_image $firmwarefile 0x1000000 bin
-
- # Big endian... weee!!!!
- puts "Setting MAC number to $serialnumber"
- flash fillw [expr 0x1030000-0x8] "0x[string range $serialnumber 2 3][string range $serialnumber 0 1]0000" 1
- flash fillw [expr 0x1030000-0x4] "0x[string range $serialnumber 10 11][string range $serialnumber 8 9][string range $serialnumber 6 7][string range $serialnumber 4 5]" 1
- puts "Production successful"
-}
-
-
-proc production_test {} {
- power on
- sleep 1000
- target_request debugmsgs enable
- reset run
- sleep 25000
- target_request debugmsgs disable
- return "See IP address above..."
-}
|
|
From: <zw...@ma...> - 2009-05-16 01:35:33
|
Author: zwelch
Date: 2009-05-16 01:35:27 +0200 (Sat, 16 May 2009)
New Revision: 1797
Modified:
trunk/src/helper/jim.c
Log:
Initialize a more variables in jim.c to allow gcc-4.4 to build.
Fix provided by Benjamin Schmidt <De...@gm...>.
Modified: trunk/src/helper/jim.c
===================================================================
--- trunk/src/helper/jim.c 2009-05-15 22:10:32 UTC (rev 1796)
+++ trunk/src/helper/jim.c 2009-05-15 23:35:27 UTC (rev 1797)
@@ -7642,8 +7642,8 @@
scanned += 1;
break;
case 'd': case 'o': case 'x': case 'u': case 'i': {
- jim_wide jwvalue;
- long lvalue;
+ jim_wide jwvalue = 0;
+ long lvalue = 0;
char *endp; /* Position where the number finished */
int base = descr->type == 'o' ? 8
: descr->type == 'x' ? 16
|
|
From: <zw...@ma...> - 2009-05-16 00:10:35
|
Author: zwelch
Date: 2009-05-16 00:10:32 +0200 (Sat, 16 May 2009)
New Revision: 1796
Modified:
trunk/src/helper/jim.c
Log:
Initialize value of objPtr local variable; prevents warning w/ gcc-4.4.
Modified: trunk/src/helper/jim.c
===================================================================
--- trunk/src/helper/jim.c 2009-05-15 21:10:35 UTC (rev 1795)
+++ trunk/src/helper/jim.c 2009-05-15 22:10:32 UTC (rev 1796)
@@ -5919,7 +5919,7 @@
int Jim_DictKeysVector(Jim_Interp *interp, Jim_Obj *dictPtr,
Jim_Obj *const *keyv, int keyc, Jim_Obj **objPtrPtr, int flags)
{
- Jim_Obj *objPtr;
+ Jim_Obj *objPtr = NULL;
int i;
if (keyc == 0) {
|
|
From: <oh...@ma...> - 2009-05-15 23:10:40
|
Author: oharboe Date: 2009-05-15 23:10:35 +0200 (Fri, 15 May 2009) New Revision: 1795 Modified: trunk/src/helper/jim.h Log: fix -fno-common/Mac build problems. Modified: trunk/src/helper/jim.h =================================================================== --- trunk/src/helper/jim.h 2009-05-15 20:35:53 UTC (rev 1794) +++ trunk/src/helper/jim.h 2009-05-15 21:10:35 UTC (rev 1795) @@ -632,7 +632,7 @@ #define JIM_API( X ) X #else #ifndef __JIM_CORE__ -# if defined JIM_EXTENSION || defined JIM_EMBEDDED +# if defined JIM_EMBEDDED # define JIM_API(x) (*x) # define JIM_STATIC # else |
|
From: <oh...@ma...> - 2009-05-15 22:35:56
|
Author: oharboe
Date: 2009-05-15 22:35:53 +0200 (Fri, 15 May 2009)
New Revision: 1794
Modified:
trunk/src/helper/command.c
trunk/src/helper/command.h
Log:
Less wrong handling of JIM_EMBEDDED, follow Jim Tcl doc's and only use JIM_EMBEDDED in a single .c file. Still broken w/-fno-common(i.e. Mac OS).
Modified: trunk/src/helper/command.c
===================================================================
--- trunk/src/helper/command.c 2009-05-15 09:03:52 UTC (rev 1793)
+++ trunk/src/helper/command.c 2009-05-15 20:35:53 UTC (rev 1794)
@@ -30,6 +30,11 @@
#include "config.h"
#endif
+#if !BUILD_ECOSBOARD
+/* see Embedder-HOWTO.txt in Jim Tcl project hosted on BerliOS*/
+#define JIM_EMBEDDED
+#endif
+
// @todo the inclusion of target.h here is a layering violation
#include "target.h"
#include "command.h"
@@ -675,7 +680,7 @@
context->output_handler = NULL;
context->output_handler_priv = NULL;
-#ifdef JIM_EMBEDDED
+#if !BUILD_ECOSBOARD
Jim_InitEmbedded();
/* Create an interpreter */
interp = Jim_CreateInterp();
@@ -721,7 +726,7 @@
add_default_dirs();
-#ifdef JIM_EMBEDDED
+#if !BUILD_ECOSBOARD
Jim_EventLoopOnLoad(interp);
#endif
if (Jim_Eval_Named(interp, startup_tcl, "embedded:startup.tcl",1)==JIM_ERR)
@@ -800,7 +805,7 @@
void process_jim_events(void)
{
-#ifdef JIM_EMBEDDED
+#if !BUILD_ECOSBOARD
static int recursion = 0;
if (!recursion)
Modified: trunk/src/helper/command.h
===================================================================
--- trunk/src/helper/command.h 2009-05-15 09:03:52 UTC (rev 1793)
+++ trunk/src/helper/command.h 2009-05-15 20:35:53 UTC (rev 1794)
@@ -32,7 +32,6 @@
/* Jim is provied by eCos */
#include <cyg/jimtcl/jim.h>
#else
-#define JIM_EMBEDDED
#include "jim.h"
#endif
|
|
From: oharboe at B. <oh...@ma...> - 2009-05-15 11:03:53
|
Author: oharboe Date: 2009-05-15 11:03:52 +0200 (Fri, 15 May 2009) New Revision: 1793 Modified: trunk/src/helper/command.h Log: revert to 1775. 1790 causes SEGFAULT w/Cygwin. Modified: trunk/src/helper/command.h =================================================================== --- trunk/src/helper/command.h 2009-05-15 02:22:27 UTC (rev 1792) +++ trunk/src/helper/command.h 2009-05-15 09:03:52 UTC (rev 1793) @@ -32,6 +32,7 @@ /* Jim is provied by eCos */ #include <cyg/jimtcl/jim.h> #else +#define JIM_EMBEDDED #include "jim.h" #endif |
