openocd-commit — OpenOCD commit maling list - read only

[Openocd-svn] r2320 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:17:03 +0200 (Sun, 21 Jun 2009)
New Revision: 2320

Modified:
   trunk/src/target/mips32.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/mips32.c
===================================================================
--- trunk/src/target/mips32.c	2009-06-21 03:16:52 UTC (rev 2319)
+++ trunk/src/target/mips32.c	2009-06-21 03:17:03 UTC (rev 2320)
@@ -164,7 +164,7 @@
 	reg_value = buf_get_u32(mips32->core_cache->reg_list[num].value, 0, 32);
 	mips_core_reg = mips32->core_cache->reg_list[num].arch_info;
 	mips32->core_regs[num] = reg_value;
-	LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
+	LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 	mips32->core_cache->reg_list[num].valid = 1;
 	mips32->core_cache->reg_list[num].dirty = 0;
 	
@@ -264,7 +264,7 @@
 		exit(-1);
 	}
 	
-	LOG_USER("target halted due to %s, pc: 0x%8.8x",
+	LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
 		Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
 		buf_get_u32(mips32->core_cache->reg_list[MIPS32_PC].value, 0, 32));
 	
@@ -414,7 +414,7 @@
 			return retval;
 	}
 	
-	LOG_DEBUG("DCR 0x%x numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
+	LOG_DEBUG("DCR 0x%" PRIx32 " numinst %i numdata %i", dcr, mips32->num_inst_bpoints, mips32->num_data_bpoints);
 	
 	mips32->bp_scanned = 1;
 	

[Openocd-svn] r2319 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:16:52 +0200 (Sun, 21 Jun 2009)
New Revision: 2319

Modified:
   trunk/src/target/image.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/image.c
===================================================================
--- trunk/src/target/image.c	2009-06-21 03:16:46 UTC (rev 2318)
+++ trunk/src/target/image.c	2009-06-21 03:16:52 UTC (rev 2319)
@@ -174,7 +174,7 @@
 		uint8_t cal_checksum = 0;
 		uint32_t bytes_read = 0;
 
-		if (sscanf(&lpszLine[bytes_read], ":%2x%4x%2x", &count, &address, &record_type) != 3)
+		if (sscanf(&lpszLine[bytes_read], ":%2" SCNx32 "%4" SCNx32 "%2" SCNx32 , &count, &address, &record_type) != 3)
 		{
 			return ERROR_IMAGE_FORMAT_ERROR;
 		}
@@ -269,7 +269,7 @@
 			/* but we must consume it, and do not create an error.  */
 			while (count-- > 0)
 			{
-				sscanf(&lpszLine[bytes_read], "%2x", &dummy);
+				sscanf(&lpszLine[bytes_read], "%2" SCNx32 , &dummy);
 				cal_checksum += (uint8_t)dummy;
 				bytes_read += 2;
 			}
@@ -305,7 +305,7 @@
 		{
 			uint32_t start_address;
 
-			sscanf(&lpszLine[bytes_read], "%8x", &start_address);
+			sscanf(&lpszLine[bytes_read], "%8" SCNx32, &start_address);
 			cal_checksum += (uint8_t)(start_address >> 24);
 			cal_checksum += (uint8_t)(start_address >> 16);
 			cal_checksum += (uint8_t)(start_address >> 8);
@@ -317,11 +317,11 @@
 		}
 		else
 		{
-			LOG_ERROR("unhandled IHEX record type: %i", record_type);
+		  LOG_ERROR("unhandled IHEX record type: %i", (int)record_type);
 			return ERROR_IMAGE_FORMAT_ERROR;
 		}
 
-		sscanf(&lpszLine[bytes_read], "%2x", &checksum);
+		sscanf(&lpszLine[bytes_read], "%2" SCNx32 , &checksum);
 		bytes_read += 2;
 
 		if ((uint8_t)checksum != (uint8_t)(~cal_checksum + 1))
@@ -446,14 +446,14 @@
 
 	*size_read = 0;
 
-	LOG_DEBUG("load segment %d at 0x%x (sz=0x%x)",section,offset,size);
+	LOG_DEBUG("load segment %d at 0x%" PRIx32 " (sz=0x%" PRIx32 ")",section,offset,size);
 
 	/* read initialized data in current segment if any */
 	if (offset<field32(elf,segment->p_filesz))
 	{
 		/* maximal size present in file for the current segment */
 		read_size = MIN(size, field32(elf,segment->p_filesz)-offset);
-		LOG_DEBUG("read elf: size = 0x%x at 0x%x",read_size,
+		LOG_DEBUG("read elf: size = 0x%" PRIx32 " at 0x%" PRIx32 "",read_size,
 			field32(elf,segment->p_offset)+offset);
 		/* read initialized area of the segment */
 		if ((retval = fileio_seek(&elf->fileio, field32(elf,segment->p_offset)+offset)) != ERROR_OK)
@@ -509,7 +509,7 @@
 		uint32_t bytes_read = 0;
 
 		/* get record type and record length */
-		if (sscanf(&lpszLine[bytes_read], "S%1x%2x", &record_type, &count) != 2)
+		if (sscanf(&lpszLine[bytes_read], "S%1" SCNx32 "%2" SCNx32 , &record_type, &count) != 2)
 		{
 			return ERROR_IMAGE_FORMAT_ERROR;
 		}
@@ -537,7 +537,7 @@
 			{
 				case 1:
 					/* S1 - 16 bit address data record */
-					sscanf(&lpszLine[bytes_read], "%4x", &address);
+					sscanf(&lpszLine[bytes_read], "%4" SCNx32, &address);
 					cal_checksum += (uint8_t)(address >> 8);
 					cal_checksum += (uint8_t)address;
 					bytes_read += 4;
@@ -546,7 +546,7 @@
 
 				case 2:
 					/* S2 - 24 bit address data record */
-					sscanf(&lpszLine[bytes_read], "%6x", &address);
+					sscanf(&lpszLine[bytes_read], "%6" SCNx32 , &address);
 					cal_checksum += (uint8_t)(address >> 16);
 					cal_checksum += (uint8_t)(address >> 8);
 					cal_checksum += (uint8_t)address;
@@ -556,7 +556,7 @@
 
 				case 3:
 					/* S3 - 32 bit address data record */
-					sscanf(&lpszLine[bytes_read], "%8x", &address);
+					sscanf(&lpszLine[bytes_read], "%8" SCNx32 , &address);
 					cal_checksum += (uint8_t)(address >> 24);
 					cal_checksum += (uint8_t)(address >> 16);
 					cal_checksum += (uint8_t)(address >> 8);
@@ -603,7 +603,7 @@
 
 			while (count-- > 0)
 			{
-				sscanf(&lpszLine[bytes_read], "%2x", &dummy);
+				sscanf(&lpszLine[bytes_read], "%2" SCNx32 , &dummy);
 				cal_checksum += (uint8_t)dummy;
 				bytes_read += 2;
 			}
@@ -627,12 +627,12 @@
 		}
 		else
 		{
-			LOG_ERROR("unhandled S19 record type: %i", record_type);
+		  LOG_ERROR("unhandled S19 record type: %i", (int)(record_type));
 			return ERROR_IMAGE_FORMAT_ERROR;
 		}
 
 		/* account for checksum, will always be 0xFF */
-		sscanf(&lpszLine[bytes_read], "%2x", &checksum);
+		sscanf(&lpszLine[bytes_read], "%2" SCNx32 , &checksum);
 		cal_checksum += (uint8_t)checksum;
 		bytes_read += 2;
 
@@ -783,7 +783,7 @@
 	/* don't read past the end of a section */
 	if (offset + size > image->sections[section].size)
 	{
-		LOG_DEBUG("read past end of section: 0x%8.8x + 0x%8.8x > 0x%8.8x",
+		LOG_DEBUG("read past end of section: 0x%8.8" PRIx32 " + 0x%8.8" PRIx32 " > 0x%8.8" PRIx32 "",
 				offset, size, image->sections[section].size);
 		return ERROR_INVALID_ARGUMENTS;
 	}

[Openocd-svn] r2318 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:16:46 +0200 (Sun, 21 Jun 2009)
New Revision: 2318

Modified:
   trunk/src/target/feroceon.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/feroceon.c
===================================================================
--- trunk/src/target/feroceon.c	2009-06-21 03:16:38 UTC (rev 2317)
+++ trunk/src/target/feroceon.c	2009-06-21 03:16:46 UTC (rev 2318)
@@ -297,7 +297,7 @@
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 
-	LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
+	LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
 
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 0);

[Openocd-svn] r2317 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:16:38 +0200 (Sun, 21 Jun 2009)
New Revision: 2317

Modified:
   trunk/src/target/fa526.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/fa526.c
===================================================================
--- trunk/src/target/fa526.c	2009-06-21 03:16:29 UTC (rev 2316)
+++ trunk/src/target/fa526.c	2009-06-21 03:16:38 UTC (rev 2317)
@@ -187,7 +187,7 @@
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 
-	LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
+	LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
 
 	/* MSR1 fetched */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);

[Openocd-svn] r2316 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:16:29 +0200 (Sun, 21 Jun 2009)
New Revision: 2316

Modified:
   trunk/src/target/etm.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/etm.c
===================================================================
--- trunk/src/target/etm.c	2009-06-21 03:16:22 UTC (rev 2315)
+++ trunk/src/target/etm.c	2009-06-21 03:16:29 UTC (rev 2316)
@@ -403,7 +403,7 @@
 	uint8_t reg_addr = etm_reg->addr & 0x7f;
 	scan_field_t fields[3];
 
-	LOG_DEBUG("%i: 0x%8.8x", etm_reg->addr, value);
+	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", etm_reg->addr, value);
 
 	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(etm_reg->jtag_info, 0x6);
@@ -801,19 +801,19 @@
 					next_pc = ctx->last_branch;
 					break;
 				case 0x1:	/* tracing enabled */
-					command_print(cmd_ctx, "--- tracing enabled at 0x%8.8x ---", ctx->last_branch);
+					command_print(cmd_ctx, "--- tracing enabled at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
 					ctx->pipe_index++;
 					continue;
 					break;
 				case 0x2:	/* trace restarted after FIFO overflow */
-					command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8x ---", ctx->last_branch);
+					command_print(cmd_ctx, "--- trace restarted after FIFO overflow at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
 					ctx->pipe_index++;
 					continue;
 					break;
 				case 0x3:	/* exit from debug state */
-					command_print(cmd_ctx, "--- exit from debug state at 0x%8.8x ---", ctx->last_branch);
+					command_print(cmd_ctx, "--- exit from debug state at 0x%8.8" PRIx32 " ---", ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
 					ctx->pipe_index++;
 					continue;
@@ -825,14 +825,14 @@
 					 */
 					if (!current_pc_ok)
 					{
-						command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8x ---", next_pc);
+						command_print(cmd_ctx, "--- periodic synchronization point at 0x%8.8" PRIx32 " ---", next_pc);
 						ctx->current_pc = next_pc;
 						ctx->pipe_index++;
 						continue;
 					}
 					break;
 				default:	/* reserved */
-					LOG_ERROR("BUG: branch reason code 0x%x is reserved", ctx->last_branch_reason);
+					LOG_ERROR("BUG: branch reason code 0x%" PRIx32 " is reserved", ctx->last_branch_reason);
 					exit(-1);
 					break;
 			}
@@ -854,7 +854,7 @@
 				}
 				else
 				{
-					command_print(cmd_ctx, "exception vector 0x%2.2x", ctx->last_branch);
+					command_print(cmd_ctx, "exception vector 0x%2.2" PRIx32 "", ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
 					ctx->pipe_index++;
 					continue;
@@ -917,7 +917,7 @@
 
 				if (ctx->ptr_ok)
 				{
-					command_print(cmd_ctx, "address: 0x%8.8x", ctx->last_ptr);
+					command_print(cmd_ctx, "address: 0x%8.8" PRIx32 "", ctx->last_ptr);
 				}
 			}
 
@@ -933,7 +933,7 @@
 							uint32_t data;
 							if (etmv1_data(ctx, 4, &data) != 0)
 								return ERROR_ETM_ANALYSIS_FAILED;
-							command_print(cmd_ctx, "data: 0x%8.8x", data);
+							command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
 						}
 					}
 				}
@@ -942,7 +942,7 @@
 					uint32_t data;
 					if (etmv1_data(ctx, arm_access_size(&instruction), &data) != 0)
 						return ERROR_ETM_ANALYSIS_FAILED;
-					command_print(cmd_ctx, "data: 0x%8.8x", data);
+					command_print(cmd_ctx, "data: 0x%8.8" PRIx32 "", data);
 				}
 			}
 
@@ -984,7 +984,7 @@
 			if (ctx->tracemode & ETMV1_CYCLE_ACCURATE)
 			{
 				snprintf(cycles_text, 32, " (%i %s)",
-					cycles,
+					 (int)cycles,
 					(cycles == 1) ? "cycle" : "cycles");
 			}
 
@@ -1343,17 +1343,17 @@
 	etm_sys_config_reg = &arm7_9->etm_ctx->reg_cache->reg_list[ETM_SYS_CONFIG];
 
 	etm_get_reg(etm_config_reg);
-	command_print(cmd_ctx, "pairs of address comparators: %i", buf_get_u32(etm_config_reg->value, 0, 4));
-	command_print(cmd_ctx, "pairs of data comparators: %i", buf_get_u32(etm_config_reg->value, 4, 4));
-	command_print(cmd_ctx, "memory map decoders: %i", buf_get_u32(etm_config_reg->value, 8, 5));
-	command_print(cmd_ctx, "number of counters: %i", buf_get_u32(etm_config_reg->value, 13, 3));
+	command_print(cmd_ctx, "pairs of address comparators: %i", (int)buf_get_u32(etm_config_reg->value, 0, 4));
+	command_print(cmd_ctx, "pairs of data comparators: %i", (int)buf_get_u32(etm_config_reg->value, 4, 4));
+	command_print(cmd_ctx, "memory map decoders: %i", (int)buf_get_u32(etm_config_reg->value, 8, 5));
+	command_print(cmd_ctx, "number of counters: %i", (int)buf_get_u32(etm_config_reg->value, 13, 3));
 	command_print(cmd_ctx, "sequencer %spresent",
 			(buf_get_u32(etm_config_reg->value, 16, 1) == 1) ? "" : "not ");
-	command_print(cmd_ctx, "number of ext. inputs: %i", buf_get_u32(etm_config_reg->value, 17, 3));
-	command_print(cmd_ctx, "number of ext. outputs: %i", buf_get_u32(etm_config_reg->value, 20, 3));
+	command_print(cmd_ctx, "number of ext. inputs: %i", (int)buf_get_u32(etm_config_reg->value, 17, 3));
+	command_print(cmd_ctx, "number of ext. outputs: %i",(int) buf_get_u32(etm_config_reg->value, 20, 3));
 	command_print(cmd_ctx, "FIFO full %spresent",
 			(buf_get_u32(etm_config_reg->value, 23, 1) == 1) ? "" : "not ");
-	command_print(cmd_ctx, "protocol version: %i", buf_get_u32(etm_config_reg->value, 28, 3));
+	command_print(cmd_ctx, "protocol version: %i", (int)buf_get_u32(etm_config_reg->value, 28, 3));
 
 	etm_get_reg(etm_sys_config_reg);
 
@@ -1431,7 +1431,7 @@
 
 		if (arm7_9->etm_ctx->trace_depth > 0)
 		{
-			command_print(cmd_ctx, "%i frames of trace data read", arm7_9->etm_ctx->trace_depth);
+			command_print(cmd_ctx, "%i frames of trace data read", (int)(arm7_9->etm_ctx->trace_depth));
 		}
 	}
 
@@ -1618,11 +1618,13 @@
 		etm_ctx->trace_data = NULL;
 	}
 
-	fileio_read_u32(&file, &etm_ctx->capture_status);
-	fileio_read_u32(&file, &etm_ctx->portmode);
-	fileio_read_u32(&file, &etm_ctx->tracemode);
-	fileio_read_u32(&file, &etm_ctx->trace_depth);
-
+	{
+	  uint32_t tmp;
+	  fileio_read_u32(&file, &tmp); etm_ctx->capture_status = tmp;
+	  fileio_read_u32(&file, &tmp); etm_ctx->portmode = tmp;
+	  fileio_read_u32(&file, &tmp); etm_ctx->tracemode = tmp;
+	  fileio_read_u32(&file, &etm_ctx->trace_depth);
+	}
 	etm_ctx->trace_data = malloc(sizeof(etmv1_trace_data_t) * etm_ctx->trace_depth);
 	if (etm_ctx->trace_data == NULL)
 	{
@@ -1682,7 +1684,7 @@
 		}
 	}
 
-	command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", etm_ctx->trigger_percent);
+	command_print(cmd_ctx, "%i percent of the tracebuffer reserved for after the trigger", ((int)(etm_ctx->trigger_percent)));
 
 	return ERROR_OK;
 }

[Openocd-svn] r2315 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:16:22 +0200 (Sun, 21 Jun 2009)
New Revision: 2315

Modified:
   trunk/src/target/etb.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/etb.c
===================================================================
--- trunk/src/target/etb.c	2009-06-21 03:16:18 UTC (rev 2314)
+++ trunk/src/target/etb.c	2009-06-21 03:16:22 UTC (rev 2315)
@@ -224,7 +224,7 @@
 	uint8_t reg_addr = etb_reg->addr & 0x7f;
 	scan_field_t fields[3];
 
-	LOG_DEBUG("%i", etb_reg->addr);
+	LOG_DEBUG("%i", (int)(etb_reg->addr));
 
 	jtag_set_end_state(TAP_IDLE);
 	etb_scann(etb_reg->etb, 0x0);
@@ -313,7 +313,7 @@
 	uint8_t reg_addr = etb_reg->addr & 0x7f;
 	scan_field_t fields[3];
 
-	LOG_DEBUG("%i: 0x%8.8x", etb_reg->addr, value);
+	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
 
 	jtag_set_end_state(TAP_IDLE);
 	etb_scann(etb_reg->etb, 0x0);
@@ -470,7 +470,7 @@
 
 			if (etb_timeout == 0)
 			{
-				LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
+				LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%" PRIx32 "",
 					buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
 			}
 

[Openocd-svn] r2314 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:16:18 +0200 (Sun, 21 Jun 2009)
New Revision: 2314

Modified:
   trunk/src/target/embeddedice.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/embeddedice.c
===================================================================
--- trunk/src/target/embeddedice.c	2009-06-21 03:16:14 UTC (rev 2313)
+++ trunk/src/target/embeddedice.c	2009-06-21 03:16:18 UTC (rev 2314)
@@ -186,7 +186,7 @@
 			 */
 			if (strcmp(target_get_name(target), "feroceon") == 0)
 				break;
-			LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8x)", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
+			LOG_ERROR("unknown EmbeddedICE version (comms ctrl: 0x%8.8" PRIx32 ")", buf_get_u32(reg_list[EICE_COMMS_CTRL].value, 0, 32));
 	}
 
 	return reg_cache;
@@ -367,7 +367,7 @@
 {
 	embeddedice_reg_t *ice_reg = reg->arch_info;
 
-	LOG_DEBUG("%i: 0x%8.8x", ice_reg->addr, value);
+	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
 
 	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(ice_reg->jtag_info, 0x2);

[Openocd-svn] r2313 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:16:14 +0200 (Sun, 21 Jun 2009)
New Revision: 2313

Modified:
   trunk/src/target/cortex_m3.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/cortex_m3.c
===================================================================
--- trunk/src/target/cortex_m3.c	2009-06-21 03:16:09 UTC (rev 2312)
+++ trunk/src/target/cortex_m3.c	2009-06-21 03:16:14 UTC (rev 2313)
@@ -175,7 +175,7 @@
 	mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 	/* Write Debug Fault Status Register to enable processing to resume ?? Try with and without this !! */
 	mem_ap_write_atomic_u32(swjdp, NVIC_DFSR, cortex_m3->nvic_dfsr);
-	LOG_DEBUG(" NVIC_DFSR 0x%x", cortex_m3->nvic_dfsr);
+	LOG_DEBUG(" NVIC_DFSR 0x%" PRIx32 "", cortex_m3->nvic_dfsr);
 
 	return ERROR_OK;
 }
@@ -249,7 +249,7 @@
 	cortex_m3_dwt_comparator_t *dwt_list = cortex_m3->dwt_comparator_list;
 
 	mem_ap_read_atomic_u32(swjdp, DCB_DEMCR, &dcb_demcr);
-	LOG_DEBUG("DCB_DEMCR = 0x%8.8x",dcb_demcr);
+	LOG_DEBUG("DCB_DEMCR = 0x%8.8" PRIx32 "",dcb_demcr);
 
 	/* this regsiter is used for emulated dcc channel */
 	mem_ap_write_u32(swjdp, DCB_DCRDR, 0);
@@ -366,7 +366,7 @@
 			break;
 	}
 	swjdp_transaction_endcheck(swjdp);
-	LOG_DEBUG("%s SHCSR 0x%x, SR 0x%x, CFSR 0x%x, AR 0x%x", armv7m_exception_string(armv7m->exception_number), \
+	LOG_DEBUG("%s SHCSR 0x%" PRIx32 ", SR 0x%" PRIx32 ", CFSR 0x%" PRIx32 ", AR 0x%" PRIx32 "", armv7m_exception_string(armv7m->exception_number), \
 		shcsr, except_sr, cfsr, except_ar);
 	return ERROR_OK;
 }
@@ -441,7 +441,7 @@
 		cortex_m3_examine_exception_reason(target);
 	}
 
-	LOG_DEBUG("entered debug state in core mode: %s at PC 0x%x, target->state: %s",
+	LOG_DEBUG("entered debug state in core mode: %s at PC 0x%" PRIx32 ", target->state: %s",
 		armv7m_mode_strings[armv7m->core_mode],
 		*(uint32_t*)(armv7m->core_cache->reg_list[15].value),
 		Jim_Nvp_value2name_simple( nvp_target_state, target->state )->name);
@@ -485,7 +485,7 @@
 	if (target->state == TARGET_RESET)
 	{
 		/* Cannot switch context while running so endreset is called with target->state == TARGET_RESET */
-		LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%x", cortex_m3->dcb_dhcsr);
+		LOG_DEBUG("Exit from reset with dcb_dhcsr 0x%" PRIx32 "", cortex_m3->dcb_dhcsr);
 		cortex_m3_endreset_event(target);
 		target->state = TARGET_RUNNING;
 		prev_target_state = TARGET_RUNNING;
@@ -595,12 +595,12 @@
 			mem_ap_read_atomic_u32(swjdp, NVIC_DFSR, &cortex_m3->nvic_dfsr);
 			if ((dcb_dhcsr & S_HALT) && (cortex_m3->nvic_dfsr & DFSR_VCATCH))
 			{
-				LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%x, nvic_dfsr 0x%x", dcb_dhcsr, cortex_m3->nvic_dfsr);
+				LOG_DEBUG("system reset-halted, dcb_dhcsr 0x%" PRIx32 ", nvic_dfsr 0x%" PRIx32 "", dcb_dhcsr, cortex_m3->nvic_dfsr);
 				cortex_m3_poll(target);
 				return ERROR_OK;
 			}
 			else
-				LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%x, %i ms", dcb_dhcsr, timeout);
+				LOG_DEBUG("waiting for system reset-halt, dcb_dhcsr 0x%" PRIx32 ", %i ms", dcb_dhcsr, timeout);
 		}
 		timeout++;
 		alive_sleep(1);
@@ -664,7 +664,7 @@
 		/* Single step past breakpoint at current address */
 		if ((breakpoint = breakpoint_find(target, resume_pc)))
 		{
-			LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
+			LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
 			cortex_m3_unset_breakpoint(target, breakpoint);
 			cortex_m3_single_step_core(target);
 			cortex_m3_set_breakpoint(target, breakpoint);
@@ -682,13 +682,13 @@
 	{
 		target->state = TARGET_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-		LOG_DEBUG("target resumed at 0x%x", resume_pc);
+		LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
 	}
 	else
 	{
 		target->state = TARGET_DEBUG_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
-		LOG_DEBUG("target debug resumed at 0x%x", resume_pc);
+		LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
 	}
 
 	return ERROR_OK;
@@ -734,12 +734,12 @@
 	if (breakpoint)
 		cortex_m3_set_breakpoint(target, breakpoint);
 
-	LOG_DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
+	LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 
 	cortex_m3_debug_entry(target);
 	target_call_event_callbacks(target, TARGET_EVENT_HALTED);
 
-	LOG_DEBUG("target stepped dcb_dhcsr = 0x%x nvic_icsr = 0x%x", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
+	LOG_DEBUG("target stepped dcb_dhcsr = 0x%" PRIx32 " nvic_icsr = 0x%" PRIx32 "", cortex_m3->dcb_dhcsr, cortex_m3->nvic_icsr);
 	return ERROR_OK;
 }
 
@@ -921,7 +921,7 @@
 		comparator_list[fp_num].used = 1;
 		comparator_list[fp_num].fpcr_value = (breakpoint->address & 0x1FFFFFFC) | hilo | 1;
 		target_write_u32(target, comparator_list[fp_num].fpcr_address, comparator_list[fp_num].fpcr_value);
-		LOG_DEBUG("fpc_num %i fpcr_value 0x%x", fp_num, comparator_list[fp_num].fpcr_value);
+		LOG_DEBUG("fpc_num %i fpcr_value 0x%" PRIx32 "", fp_num, comparator_list[fp_num].fpcr_value);
 		if (!cortex_m3->fpb_enabled)
 		{
 			LOG_DEBUG("FPB wasn't enabled, do it now");
@@ -1114,7 +1114,7 @@
 		target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address, comparator_list[dwt_num].comp);
 		target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x4, comparator_list[dwt_num].mask);
 		target_write_u32(target, comparator_list[dwt_num].dwt_comparator_address|0x8, comparator_list[dwt_num].function);
-		LOG_DEBUG("dwt_num %i 0x%x 0x%x 0x%x", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function);
+		LOG_DEBUG("dwt_num %i 0x%" PRIx32 " 0x%" PRIx32 " 0x%" PRIx32 "", dwt_num, comparator_list[dwt_num].comp, comparator_list[dwt_num].mask, comparator_list[dwt_num].function);
 	}
 	else
 	{
@@ -1235,7 +1235,7 @@
 			LOG_ERROR("JTAG failure %i",retval);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
-		LOG_DEBUG("load from core reg %i  value 0x%x",num,*value);
+		LOG_DEBUG("load from core reg %i  value 0x%" PRIx32 "",(int)num,*value);
 	}
 	else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
 	{
@@ -1261,7 +1261,7 @@
 				break;
 		}
 
-		LOG_DEBUG("load from special reg %i value 0x%x", num, *value);
+		LOG_DEBUG("load from special reg %i value 0x%" PRIx32 "", (int)num, *value);
 	}
 	else
 	{
@@ -1300,7 +1300,7 @@
 			armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
-		LOG_DEBUG("write core reg %i value 0x%x", num, value);
+		LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", (int)num, value);
 	}
 	else if (type == ARMV7M_REGISTER_CORE_SP) /* Special purpose core register */
 	{
@@ -1329,7 +1329,7 @@
 
 		cortexm3_dap_write_coreregister_u32(swjdp, reg, 20);
 
-		LOG_DEBUG("write special reg %i value 0x%x ", num, value);
+		LOG_DEBUG("write special reg %i value 0x%" PRIx32 " ", (int)num, value);
 	}
 	else
 	{
@@ -1441,7 +1441,7 @@
 
 		if (((cpuid >> 4) & 0xc3f) == 0xc23)
 			LOG_DEBUG("CORTEX-M3 processor detected");
-		LOG_DEBUG("cpuid: 0x%8.8x", cpuid);
+		LOG_DEBUG("cpuid: 0x%8.8" PRIx32 "", cpuid);
 
 		target_read_u32(target, NVIC_ICTR, &ictr);
 		cortex_m3->intlinesnum = (ictr & 0x1F) + 1;
@@ -1449,7 +1449,7 @@
 		for (i = 0; i < cortex_m3->intlinesnum; i++)
 		{
 			target_read_u32(target, NVIC_ISE0 + 4 * i, cortex_m3->intsetenable + i);
-			LOG_DEBUG("interrupt enable[%i] = 0x%8.8x", i, cortex_m3->intsetenable[i]);
+			LOG_DEBUG("interrupt enable[%i] = 0x%8.8" PRIx32 "", i, cortex_m3->intsetenable[i]);
 		}
 
 		/* Setup FPB */
@@ -1465,7 +1465,7 @@
 			cortex_m3->fp_comparator_list[i].type = (i < cortex_m3->fp_num_code) ? FPCR_CODE : FPCR_LITERAL;
 			cortex_m3->fp_comparator_list[i].fpcr_address = FP_COMP0 + 4 * i;
 		}
-		LOG_DEBUG("FPB fpcr 0x%x, numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
+		LOG_DEBUG("FPB fpcr 0x%" PRIx32 ", numcode %i, numlit %i", fpcr, cortex_m3->fp_num_code, cortex_m3->fp_num_lit);
 
 		/* Setup DWT */
 		target_read_u32(target, DWT_CTRL, &dwtcr);

[Openocd-svn] r2312 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:16:09 +0200 (Sun, 21 Jun 2009)
New Revision: 2312

Modified:
   trunk/src/target/breakpoints.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/breakpoints.c
===================================================================
--- trunk/src/target/breakpoints.c	2009-06-21 03:16:05 UTC (rev 2311)
+++ trunk/src/target/breakpoints.c	2009-06-21 03:16:09 UTC (rev 2312)
@@ -84,7 +84,7 @@
 		}
 	}
 	
-	LOG_DEBUG("added %s breakpoint at 0x%8.8x of length 0x%8.8x", 
+	LOG_DEBUG("added %s breakpoint at 0x%8.8" PRIx32 " of length 0x%8.8x", 
 		breakpoint_type_strings[(*breakpoint_p)->type],
 		(*breakpoint_p)->address, (*breakpoint_p)->length);
 	
@@ -134,7 +134,7 @@
 	}
 	else
 	{
-		LOG_ERROR("no breakpoint at address 0x%8.8x found", address);
+		LOG_ERROR("no breakpoint at address 0x%8.8" PRIx32 " found", address);
 	}
 }
 
@@ -207,7 +207,7 @@
 		}
 	}
 	
-	LOG_DEBUG("added %s watchpoint at 0x%8.8x of length 0x%8.8x",
+	LOG_DEBUG("added %s watchpoint at 0x%8.8" PRIx32 " of length 0x%8.8x",
 		watchpoint_rw_strings[(*watchpoint_p)->rw],
 		(*watchpoint_p)->address, (*watchpoint_p)->length);
 	
@@ -253,7 +253,7 @@
 	}
 	else
 	{
-		LOG_ERROR("no watchpoint at address 0x%8.8x found", address);
+		LOG_ERROR("no watchpoint at address 0x%8.8" PRIx32 " found", address);
 	}
 }
 

[Openocd-svn] r2311 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:16:05 +0200 (Sun, 21 Jun 2009)
New Revision: 2311

Modified:
   trunk/src/target/armv7m.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/armv7m.c
===================================================================
--- trunk/src/target/armv7m.c	2009-06-21 03:15:59 UTC (rev 2310)
+++ trunk/src/target/armv7m.c	2009-06-21 03:16:05 UTC (rev 2311)
@@ -231,7 +231,7 @@
 		armv7m->core_cache->reg_list[num].dirty = armv7m->core_cache->reg_list[num].valid;
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
-	LOG_DEBUG("write core reg %i value 0x%x", num , reg_value);
+	LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num , reg_value);
 	armv7m->core_cache->reg_list[num].valid = 1;
 	armv7m->core_cache->reg_list[num].dirty = 0;
 
@@ -316,7 +316,7 @@
 	armv7m->load_core_reg_u32(target, ARMV7M_REGISTER_CORE_GP, 15, &pc);
 	if (pc != exit_point)
 	{
-		LOG_DEBUG("failed algoritm halted at 0x%x ", pc);
+		LOG_DEBUG("failed algoritm halted at 0x%" PRIx32 " ", pc);
 		return ERROR_TARGET_TIMEOUT;
 	}
 
@@ -444,7 +444,7 @@
 		regvalue = buf_get_u32(armv7m->core_cache->reg_list[i].value, 0, 32);
 		if (regvalue != context[i])
 		{
-			LOG_DEBUG("restoring register %s with value 0x%8.8x", armv7m->core_cache->reg_list[i].name, context[i]);
+			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", armv7m->core_cache->reg_list[i].name, context[i]);
 			buf_set_u32(armv7m->core_cache->reg_list[i].value, 0, 32, context[i]);
 			armv7m->core_cache->reg_list[i].valid = 1;
 			armv7m->core_cache->reg_list[i].dirty = 1;
@@ -461,7 +461,7 @@
 	/* get pointers to arch-specific information */
 	armv7m_common_t *armv7m = target->arch_info;
 
-	LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8x pc: 0x%8.8x",
+	LOG_USER("target halted due to %s, current mode: %s %s\nxPSR: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
 		 Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
 		armv7m_mode_strings[armv7m->core_mode],
 		armv7m_exception_string(armv7m->exception_number),
@@ -720,7 +720,7 @@
 
 	dap_ap_read_reg_u32(swjdp, 0xF8, &baseaddr);
 	retval = swjdp_transaction_endcheck(swjdp);
-	command_print(cmd_ctx, "0x%8.8x", baseaddr);
+	command_print(cmd_ctx, "0x%8.8" PRIx32 "", baseaddr);
 
 	if (apselsave != apsel)
 	{
@@ -756,7 +756,7 @@
 
 	dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
 	retval = swjdp_transaction_endcheck(swjdp);
-	command_print(cmd_ctx, "0x%8.8x", apid);
+	command_print(cmd_ctx, "0x%8.8" PRIx32 "", apid);
 	if (apselsave != apsel)
 	{
 		dap_ap_select(swjdp, apselsave);
@@ -782,7 +782,7 @@
 	dap_ap_select(swjdp, apsel);
 	dap_ap_read_reg_u32(swjdp, 0xFC, &apid);
 	retval = swjdp_transaction_endcheck(swjdp);
-	command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8x", apsel, apid);
+	command_print(cmd_ctx, "ap %i selected, identification register 0x%8.8" PRIx32 "", (int)apsel, apid);
 
 	return retval;
 }
@@ -801,7 +801,7 @@
 	}
 
 	swjdp->memaccess_tck = memaccess_tck;
-	command_print(cmd_ctx, "memory bus access delay set to %i tck", swjdp->memaccess_tck);
+	command_print(cmd_ctx, "memory bus access delay set to %i tck", (int)(swjdp->memaccess_tck));
 
 	return ERROR_OK;
 }

[Openocd-svn] r2310 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:15:59 +0200 (Sun, 21 Jun 2009)
New Revision: 2310

Modified:
   trunk/src/target/armv4_5_mmu.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/armv4_5_mmu.c
===================================================================
--- trunk/src/target/armv4_5_mmu.c	2009-06-21 03:15:51 UTC (rev 2309)
+++ trunk/src/target/armv4_5_mmu.c	2009-06-21 03:15:59 UTC (rev 2310)
@@ -43,7 +43,7 @@
 		4, 1, (uint8_t*)&first_lvl_descriptor);
 	first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&first_lvl_descriptor);
 
-	LOG_DEBUG("1st lvl desc: %8.8x", first_lvl_descriptor);
+	LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
 
 	if ((first_lvl_descriptor & 0x3) == 0)
 	{
@@ -88,7 +88,7 @@
 
 	second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t*)&second_lvl_descriptor);
 
-	LOG_DEBUG("2nd lvl desc: %8.8x", second_lvl_descriptor);
+	LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
 
 	if ((second_lvl_descriptor & 0x3) == 0)
 	{
@@ -200,7 +200,7 @@
 			switch (pa)
 			{
 				case ERROR_TARGET_TRANSLATION_FAULT:
-					command_print(cmd_ctx, "no valid translation for 0x%8.8x", va);
+					command_print(cmd_ctx, "no valid translation for 0x%8.8" PRIx32 "", va);
 					break;
 				default:
 					command_print(cmd_ctx, "unknown translation error");
@@ -208,8 +208,8 @@
 			return ERROR_OK;
 		}
 
-		command_print(cmd_ctx, "0x%8.8x -> 0x%8.8x, type: %s, cb: %i, domain: %i, ap: %2.2x",
-			va, pa, armv4_5_mmu_page_type_names[type], cb, domain, ap);
+		command_print(cmd_ctx, "0x%8.8" PRIx32 " -> 0x%8.8" PRIx32 ", type: %s, cb: %i, domain: %d, ap: %2.2x",
+			      va, pa, armv4_5_mmu_page_type_names[type], (int)cb, domain, (int)ap);
 	}
 
 	return ERROR_OK;
@@ -282,12 +282,12 @@
 	for (i = 0; i < count; i++)
 	{
 		if (i%8 == 0)
-			output_len += snprintf(output + output_len, 128 - output_len, "0x%8.8x: ", address + (i*size));
+			output_len += snprintf(output + output_len, 128 - output_len, "0x%8.8" PRIx32 ": ", address + (i*size));
 
 		switch (size)
 		{
 			case 4:
-				output_len += snprintf(output + output_len, 128 - output_len, "%8.8x ", target_buffer_get_u32(target, &buffer[i*4]));
+				output_len += snprintf(output + output_len, 128 - output_len, "%8.8" PRIx32 " ", target_buffer_get_u32(target, &buffer[i*4]));
 				break;
 			case 2:
 				output_len += snprintf(output + output_len, 128 - output_len, "%4.4x ", target_buffer_get_u16(target, &buffer[i*2]));

[Openocd-svn] r2309 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:15:51 +0200 (Sun, 21 Jun 2009)
New Revision: 2309

Modified:
   trunk/src/target/armv4_5.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/armv4_5.c
===================================================================
--- trunk/src/target/armv4_5.c	2009-06-21 03:15:47 UTC (rev 2308)
+++ trunk/src/target/armv4_5.c	2009-06-21 03:15:51 UTC (rev 2309)
@@ -297,7 +297,7 @@
 		exit(-1);
 	}
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
+	LOG_USER("target halted in %s state due to %s, current mode: %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
 			 armv4_5_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
 			 armv4_5_mode_strings[armv4_5_mode_to_number(armv4_5->core_mode)],
@@ -339,12 +339,16 @@
 			{
 				armv4_5->full_context(target);
 			}
-			output_len += snprintf(output + output_len, 128 - output_len, "%8s: %8.8x ", ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
-				buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
+			output_len += snprintf(output + output_len, 
+					       128 - output_len, 
+					       "%8s: %8.8" PRIx32 " ", 
+					       ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).name,
+					       buf_get_u32(ARMV4_5_CORE_REG_MODENUM(armv4_5->core_cache, mode, num).value, 0, 32));
 		}
 		command_print(cmd_ctx, "%s", output);
 	}
-	command_print(cmd_ctx, "    cpsr: %8.8x spsr_fiq: %8.8x spsr_irq: %8.8x spsr_svc: %8.8x spsr_abt: %8.8x spsr_und: %8.8x",
+	command_print(cmd_ctx,
+		      "    cpsr: %8.8" PRIx32 " spsr_fiq: %8.8" PRIx32 " spsr_irq: %8.8" PRIx32 " spsr_svc: %8.8" PRIx32 " spsr_abt: %8.8" PRIx32 " spsr_und: %8.8" PRIx32 "",
 			  buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32),
 			  buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_FIQ].value, 0, 32),
 			  buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_SPSR_IRQ].value, 0, 32),
@@ -507,7 +511,7 @@
 	}
 	if (buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point)
 	{
-		LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
+		LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
 			buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 		return ERROR_TARGET_TIMEOUT;
 	}
@@ -654,7 +658,7 @@
 		regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32);
 		if (regvalue != context[i])
 		{
-			LOG_DEBUG("restoring register %s with value 0x%8.8x", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
+			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "", ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).name, context[i]);
 			buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).value, 0, 32, context[i]);
 			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).valid = 1;
 			ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5_algorithm_info->core_mode, i).dirty = 1;

[Openocd-svn] r2308 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:15:47 +0200 (Sun, 21 Jun 2009)
New Revision: 2308

Modified:
   trunk/src/target/arm_disassembler.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/arm_disassembler.c
===================================================================
--- trunk/src/target/arm_disassembler.c	2009-06-21 03:15:42 UTC (rev 2307)
+++ trunk/src/target/arm_disassembler.c	2009-06-21 03:15:47 UTC (rev 2308)
@@ -45,7 +45,7 @@
 	{
 		instruction->type = ARM_PLD;
 		
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tPLD ...TODO...", address, opcode);
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tPLD ...TODO...", address, opcode);
 		
 		return ERROR_OK;
 	}
@@ -63,7 +63,7 @@
 {
 	instruction->type = ARM_SWI;
 	
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tSWI 0x%6.6x", address, opcode, (opcode & 0xffffff));
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSWI 0x%6.6" PRIx32 "", address, opcode, (opcode & 0xffffff));
 	
 	return ERROR_OK;
 }
@@ -92,7 +92,7 @@
 	
 	target_address = address + 8 + offset;
 	
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBLX 0x%8.8x", address, opcode, target_address);
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX 0x%8.8" PRIx32 "", address, opcode, target_address);
 	
 	instruction->info.b_bl_bx_blx.reg_operand = -1;
 	instruction->info.b_bl_bx_blx.target_address = target_address;
@@ -126,7 +126,7 @@
 	else
 		instruction->type = ARM_B;
 	
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tB%s%s 0x%8.8x", address, opcode,
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tB%s%s 0x%8.8" PRIx32 , address, opcode,
 			 (L) ? "L" : "", COND(opcode), target_address);
 	
 	instruction->info.b_bl_bx_blx.reg_operand = -1;
@@ -166,7 +166,7 @@
 			mnemonic = "MRRC";
 		}
 		
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s p%i, %x, r%i, r%i, c%i",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, %x, r%i, r%i, c%i",
 				 address, opcode, mnemonic, COND(opcode), cp_num, cp_opcode, Rd, Rn, CRm);
 	}
 	else /* LDC or STC */
@@ -205,7 +205,7 @@
 		else if ((opcode & 0x01200000) == 0x00000000) /* unindexed */
 			snprintf(addressing_mode, 32, "[r%i], #0x%2.2x", Rn, offset);
 
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s p%i, c%i, %s",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s p%i, c%i, %s",
 				 address, opcode, mnemonic, ((opcode & 0xf0000000) == 0xf0000000) ? COND(opcode) : "2",
 				 (N) ? "L" : "",
 				 cp_num, CRd, addressing_mode);
@@ -246,7 +246,7 @@
 		
 		opcode_1 = (opcode & 0x00e00000) >> 21;
 		
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s p%i, 0x%2.2x, r%i, c%i, c%i, 0x%2.2x",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, 0x%2.2x, r%i, c%i, c%i, 0x%2.2x",
 				 address, opcode, mnemonic, cond,
 				 cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2);
 	}
@@ -257,7 +257,7 @@
 		
 		opcode_1 = (opcode & 0x00f00000) >> 20;
 		
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s p%i, 0x%2.2x, c%i, c%i, c%i, 0x%2.2x",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s p%i, 0x%2.2x, c%i, c%i, c%i, 0x%2.2x",
 				 address, opcode, mnemonic, cond,
 				 cp_num, opcode_1, CRd_Rd, CRn, CRm, opcode_2);
 	}
@@ -342,7 +342,7 @@
 	{
 		uint32_t offset_12 = (opcode & 0xfff);
 		if (offset_12)
-			snprintf(offset, 32, ", #%s0x%x", (U) ? "" : "-", offset_12);
+			snprintf(offset, 32, ", #%s0x%" PRIx32 "", (U) ? "" : "-", offset_12);
 		else
 			snprintf(offset, 32, "%s", "");
 		
@@ -406,7 +406,7 @@
 	{
 		if (W == 0) /* offset */
 		{
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i%s]",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]",
 					 address, opcode, operation, COND(opcode), suffix,
 					 Rd, Rn, offset);
 			
@@ -414,7 +414,7 @@
 		}
 		else /* pre-indexed */
 		{
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i%s]!",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i%s]!",
 					 address, opcode, operation, COND(opcode), suffix,
 					 Rd, Rn, offset);
 			
@@ -423,7 +423,7 @@
 	}
 	else /* post-indexed */
 	{
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i]%s",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i]%s",
 				 address, opcode, operation, COND(opcode), suffix,
 				 Rd, Rn, offset);
 		
@@ -512,7 +512,7 @@
 	if (I) /* Immediate offset/index (#+-<offset_8>)*/
 	{
 		uint32_t offset_8 = ((opcode & 0xf00) >> 4) | (opcode & 0xf);
-		snprintf(offset, 32, "#%s0x%x", (U) ? "" : "-", offset_8);
+		snprintf(offset, 32, "#%s0x%" PRIx32 "", (U) ? "" : "-", offset_8);
 		
 		instruction->info.load_store.offset_mode = 0;
 		instruction->info.load_store.offset.offset = offset_8;
@@ -533,7 +533,7 @@
 	{
 		if (W == 0) /* offset */
 		{
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i, %s]",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]",
 					 address, opcode, operation, COND(opcode), suffix,
 					 Rd, Rn, offset);
 			
@@ -541,7 +541,7 @@
 		}
 		else /* pre-indexed */
 		{
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i, %s]!",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i, %s]!",
 					 address, opcode, operation, COND(opcode), suffix,
 					 Rd, Rn, offset);
 		
@@ -550,7 +550,7 @@
 	}
 	else /* post-indexed */
 	{
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, [r%i], %s",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, [r%i], %s",
 				 address, opcode, operation, COND(opcode), suffix,
 				 Rd, Rn, offset);
 	
@@ -640,7 +640,7 @@
 		}
 	}
 	
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i%s, {%s}%s",
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i%s, {%s}%s",
 			 address, opcode, mnemonic, COND(opcode), addressing_mode,
 			 Rn, (W) ? "!" : "", reg_list, (S) ? "^" : "");
 	
@@ -667,13 +667,13 @@
 			if (opcode & 0x00200000)
 			{
 				instruction->type = ARM_MLA;
-				snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tMLA%s%s r%i, r%i, r%i, r%i",
+				snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMLA%s%s r%i, r%i, r%i, r%i",
 						address, opcode, COND(opcode), (S) ? "S" : "", Rd, Rm, Rs, Rn);
 			}
 			else
 			{
 				instruction->type = ARM_MUL;
-				snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tMUL%s%s r%i, r%i, r%i",
+				snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMUL%s%s r%i, r%i, r%i",
 						 address, opcode, COND(opcode), (S) ? "S" : "", Rd, Rm, Rs);
 			}
 			
@@ -711,7 +711,7 @@
 					break;
 			}
 			
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, r%i, r%i, r%i",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, r%i, r%i, r%i",
 						address, opcode, mnemonic, COND(opcode), (S) ? "S" : "",
 						RdLow, RdHi, Rm, Rs);
 			
@@ -729,7 +729,7 @@
 			/* examine B flag */
 			instruction->type = (opcode & 0x00400000) ? ARM_SWPB : ARM_SWP;
 			
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s r%i, r%i, [r%i]",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, r%i, [r%i]",
 					 address, opcode, (opcode & 0x00400000) ? "SWPB" : "SWP", COND(opcode), Rd, Rm, Rn);
 			return ERROR_OK;
 		}
@@ -755,7 +755,7 @@
 			uint8_t immediate = (opcode & 0xff);
 			uint8_t rotate = (opcode & 0xf00);
 			
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tMSR%s %s_%s%s%s%s, 0x%8.8x",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, 0x%8.8" PRIx32 ,
 					 address, opcode, COND(opcode), PSR,
 					 (opcode & 0x10000) ? "c" : "",
 					 (opcode & 0x20000) ? "x" : "",
@@ -767,7 +767,7 @@
 		else /* register variant */
 		{
 			uint8_t Rm = opcode & 0xf;
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tMSR%s %s_%s%s%s%s, r%i",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMSR%s %s_%s%s%s%s, r%i",
 					 address, opcode, COND(opcode), PSR,
 					 (opcode & 0x10000) ? "c" : "",
 					 (opcode & 0x20000) ? "x" : "",
@@ -785,7 +785,7 @@
 		instruction->type = ARM_MRS;
 		Rd = (opcode & 0x0000f000) >> 12;
 			
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tMRS%s r%i, %s",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tMRS%s r%i, %s",
 				 address, opcode, COND(opcode), Rd, PSR);
 	}
 	
@@ -808,7 +808,7 @@
 		instruction->type = ARM_BX;
 		Rm = opcode & 0xf;
 		
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBX%s r%i",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBX%s r%i",
 				 address, opcode, COND(opcode), Rm);
 		
 		instruction->info.b_bl_bx_blx.reg_operand = Rm;
@@ -823,7 +823,7 @@
 		Rm = opcode & 0xf;
 		Rd = (opcode & 0xf000) >> 12;
 
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tCLZ%s r%i, r%i",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tCLZ%s r%i, r%i",
 				 address, opcode, COND(opcode), Rd, Rm);
 	}
 	
@@ -834,7 +834,7 @@
 		instruction->type = ARM_BLX;
 		Rm = opcode & 0xf;
 		
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBLX%s r%i",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX%s r%i",
 				 address, opcode, COND(opcode), Rm);
 				 
 		instruction->info.b_bl_bx_blx.reg_operand = Rm;
@@ -870,7 +870,7 @@
 				break;
 		}
 		
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s r%i, r%i, r%i",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, r%i, r%i",
 				 address, opcode, mnemonic, COND(opcode), Rd, Rm, Rn);
 	}
 	
@@ -881,7 +881,7 @@
 		instruction->type = ARM_BKPT;
 		immediate = ((opcode & 0x000fff00) >> 4) | (opcode & 0xf);
 		
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBKPT 0x%4.4x",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBKPT 0x%4.4" PRIx32 "",
 				 address, opcode, immediate);	
 	}
 	
@@ -901,7 +901,7 @@
 			Rs = (opcode & 0xf00) >> 8;
 			Rn = (opcode & 0xf000) >> 12;
 			
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tSMLA%s%s%s r%i, r%i, r%i, r%i",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLA%s%s%s r%i, r%i, r%i, r%i",
 					 address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode),
 					 Rd, Rm, Rs, Rn);
 		}
@@ -916,7 +916,7 @@
 			Rm = (opcode & 0xf);
 			Rs = (opcode & 0xf00) >> 8;
 			
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tSMLA%s%s%s r%i, r%i, r%i, r%i",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLA%s%s%s r%i, r%i, r%i, r%i",
 					 address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode),
 					 RdLow, RdHi, Rm, Rs);
 		}
@@ -931,7 +931,7 @@
 			Rs = (opcode & 0xf00) >> 8;
 			Rn = (opcode & 0xf000) >> 12;
 
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tSMLAW%s%s r%i, r%i, r%i, r%i",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMLAW%s%s r%i, r%i, r%i, r%i",
 					 address, opcode, (y) ? "T" : "B", COND(opcode),
 					 Rd, Rm, Rs, Rn);
 		}
@@ -945,7 +945,7 @@
 			Rm = (opcode & 0xf);
 			Rs = (opcode & 0xf00) >> 8;
 			
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tSMULW%s%s%s r%i, r%i, r%i",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMULW%s%s%s r%i, r%i, r%i",
 					 address, opcode, (x) ? "T" : "B", (y) ? "T" : "B", COND(opcode),
 					 Rd, Rm, Rs);
 		}
@@ -959,7 +959,7 @@
 			Rm = (opcode & 0xf);
 			Rs = (opcode & 0xf00) >> 8;
 			
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tSMULW%s%s r%i, r%i, r%i",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tSMULW%s%s r%i, r%i, r%i",
 					 address, opcode, (y) ? "T" : "B", COND(opcode),
 					 Rd, Rm, Rs);
 		}
@@ -1061,7 +1061,7 @@
 		
 		immediate = ror(immed_8, rotate_imm * 2);
 		
-		snprintf(shifter_operand, 32, "#0x%x", immediate);
+		snprintf(shifter_operand, 32, "#0x%" PRIx32 "", immediate);
 		
 		instruction->info.data_proc.variant = 0;
 		instruction->info.data_proc.shifter_operand.immediate.immediate = immediate;
@@ -1152,22 +1152,22 @@
 	
 	if ((op < 0x8) || (op == 0xc) || (op == 0xe)) /* <opcode3>{<cond>}{S} <Rd>, <Rn>, <shifter_operand> */
 	{
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, r%i, %s",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, r%i, %s",
 				 address, opcode, mnemonic, COND(opcode),
 				 (S) ? "S" : "", Rd, Rn, shifter_operand);
 	}
 	else if ((op == 0xd) || (op == 0xf)) /* <opcode1>{<cond>}{S} <Rd>, <shifter_operand> */
 	{
 		if (opcode==0xe1a00000) /* print MOV r0,r0 as NOP */
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tNOP",address, opcode);
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tNOP",address, opcode);
 		else
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s%s r%i, %s",
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s%s r%i, %s",
 				 address, opcode, mnemonic, COND(opcode),
 				 (S) ? "S" : "", Rd, shifter_operand);
 	}
 	else /* <opcode2>{<cond>} <Rn>, <shifter_operand> */
 	{
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\t%s%s r%i, %s",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s%s r%i, %s",
 				 address, opcode, mnemonic, COND(opcode),
 				 Rn, shifter_operand);
 	}
@@ -1192,7 +1192,7 @@
 		if ((opcode & 0x0e000000) == 0x08000000)
 		{
 			instruction->type = ARM_UNDEFINED_INSTRUCTION;
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
 			return ERROR_OK;
 		}
 		
@@ -1217,7 +1217,7 @@
 		if ((opcode & 0x0f000000) == 0x0f000000)
 		{
 			instruction->type = ARM_UNDEFINED_INSTRUCTION;
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
 			return ERROR_OK;
 		}
 	}
@@ -1243,7 +1243,7 @@
 		if ((opcode & 0x0fb00000) == 0x03000000)
 		{
 			instruction->type = ARM_UNDEFINED_INSTRUCTION;
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
 			return ERROR_OK;
 		}
 				
@@ -1269,7 +1269,7 @@
 		if ((opcode & 0x00000010) == 0x00000010)
 		{
 			instruction->type = ARM_UNDEFINED_INSTRUCTION;
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tUNDEFINED INSTRUCTION", address, opcode);
 			return ERROR_OK;
 		}
 		
@@ -1358,7 +1358,7 @@
 	}
 	/* TODO: deals correctly with dual opcodes BL/BLX ... */
 
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s 0x%8.8x", address, opcode,mnemonic, target_address);
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s 0x%8.8" PRIx32 , address, opcode,mnemonic, target_address);
 	
 	instruction->info.b_bl_bx_blx.reg_operand = -1;
 	instruction->info.b_bl_bx_blx.target_address = target_address;
@@ -1394,14 +1394,14 @@
 	{
 		instruction->info.data_proc.variant = 0; /*immediate*/
 		instruction->info.data_proc.shifter_operand.immediate.immediate = Rm_imm;
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, r%i, #%d",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, #%d",
 				 address, opcode, mnemonic, Rd, Rn, Rm_imm);
 	}
 	else
 	{
 		instruction->info.data_proc.variant = 1; /*immediate shift*/
 		instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm_imm;
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, r%i, r%i",
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, r%i",
 				 address, opcode, mnemonic, Rd, Rn, Rm_imm);
 	}
 
@@ -1446,7 +1446,7 @@
 	instruction->info.data_proc.shifter_operand.immediate_shift.Rm = Rm;
 	instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = imm;
 
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, r%i, #0x%02x",
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i, #0x%02x" ,
 				 address, opcode, mnemonic, Rd, Rm, imm);
 
 	return ERROR_OK;
@@ -1487,7 +1487,7 @@
 			break;
 	}
 	
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, #0x%02x",
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, #0x%02x" ,
 				 address, opcode, mnemonic, Rd, imm);
 
 	return ERROR_OK;
@@ -1539,18 +1539,18 @@
 					if (H1)
 					{
 						instruction->type = ARM_BLX;
-						snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tBLX r%i", address, opcode, Rm);
+						snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBLX r%i", address, opcode, Rm);
 					}
 					else
 					{
 						instruction->type = ARM_BX;
-						snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tBX r%i", address, opcode, Rm);
+						snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBX r%i", address, opcode, Rm);
 					}
 				}
 				else
 				{
 					instruction->type = ARM_UNDEFINED_INSTRUCTION;
-					snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
+					snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
 				}
 				return ERROR_OK;	
 				break;
@@ -1646,7 +1646,7 @@
 		}
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, r%i",
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, r%i",
 				 address, opcode, mnemonic, Rd, Rm);
 
 	return ERROR_OK;
@@ -1660,7 +1660,7 @@
 	instruction->type = ARM_LDR;
 	immediate = opcode & 0x000000ff;
 
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tLDR r%i, [PC, #0x%x]", address, opcode, Rd, immediate*4);
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tLDR r%i, [PC, #0x%" PRIx32 "]", address, opcode, Rd, immediate*4);
 
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = 15 /*PC*/;
@@ -1715,7 +1715,7 @@
 			break;
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, [r%i, r%i]", address, opcode, mnemonic, Rd, Rn, Rm);
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, [r%i, r%i]", address, opcode, mnemonic, Rd, Rn, Rm);
 	
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = Rn;
@@ -1759,7 +1759,7 @@
 		shift = 0;
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s%c r%i, [r%i, #0x%x]", address, opcode, mnemonic, suffix, Rd, Rn, offset<<shift);
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s%c r%i, [r%i, #0x%" PRIx32 "]", address, opcode, mnemonic, suffix, Rd, Rn, offset<<shift);
 	
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = Rn;
@@ -1788,7 +1788,7 @@
 		mnemonic = "STR";
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s r%i, [SP, #0x%x]", address, opcode, mnemonic, Rd, offset*4);
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s r%i, [SP, #0x%" PRIx32 "]", address, opcode, mnemonic, Rd, offset*4);
 	
 	instruction->info.load_store.Rd = Rd;
 	instruction->info.load_store.Rn = 13 /*SP*/;
@@ -1820,7 +1820,7 @@
 		Rn = 15;
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tADD r%i, %s, #0x%x", address, opcode, Rd,reg_name, imm*4);
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tADD r%i, %s, #0x%" PRIx32 "", address, opcode, Rd,reg_name, imm*4);
 
 	instruction->info.data_proc.variant = 0 /* immediate */;
 	instruction->info.data_proc.Rd = Rd;
@@ -1848,7 +1848,7 @@
 		mnemonic = "ADD";
 	}
 
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s SP, #0x%x", address, opcode, mnemonic, imm*4);
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s SP, #0x%" PRIx32 "", address, opcode, mnemonic, imm*4);
 
 	instruction->info.data_proc.variant = 0 /* immediate */;
 	instruction->info.data_proc.Rd = 13 /*SP*/;
@@ -1864,7 +1864,7 @@
 	
 	instruction->type = ARM_BKPT;
 
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tBKPT 0x%02x", address, opcode, imm);
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tBKPT 0x%02" PRIx32 "", address, opcode, imm);
 
 	return ERROR_OK;
 }
@@ -1927,7 +1927,7 @@
 	else /* invalid op : no registers */
     		reg_names[0] = '\0';
 
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\t%s %s{%s}", address, opcode, mnemonic, ptr_name,reg_names);
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\t%s %s{%s}", address, opcode, mnemonic, ptr_name,reg_names);
 
 	instruction->info.load_store_multiple.register_list = reg_list;
 	instruction->info.load_store_multiple.Rn = Rn;
@@ -1945,13 +1945,13 @@
 	if (cond == 0xf)
 	{
 		instruction->type = ARM_SWI;
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tSWI 0x%02x", address, opcode, offset);
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tSWI 0x%02" PRIx32 , address, opcode, offset);
 		return ERROR_OK;
 	}
 	else if (cond == 0xe)
 	{
 		instruction->type = ARM_UNDEFINED_INSTRUCTION;
-		snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
+		snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
 		return ERROR_OK;
 	}
 
@@ -1961,7 +1961,7 @@
 	
 	target_address = address + 4 + (offset<<1);
 
-	snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tB%s 0x%8.8x", address, opcode,
+	snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tB%s 0x%8.8" PRIx32 , address, opcode,
 			 arm_condition_strings[cond], target_address);
 	
 	instruction->type = ARM_B;
@@ -2042,7 +2042,7 @@
 		else
 		{
 			instruction->type = ARM_UNDEFINED_INSTRUCTION;
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%4.4x\tUNDEFINED INSTRUCTION", address, opcode);
 			return ERROR_OK;
 		}
 	}
@@ -2065,7 +2065,7 @@
 		if ((opcode & 0xf801) == 0xe801)
 		{
 			instruction->type = ARM_UNDEFINED_INSTRUCTION;
-			snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
+			snprintf(instruction->text, 128, "0x%8.8" PRIx32 "\t0x%8.8x\tUNDEFINED INSTRUCTION", address, opcode);
 			return ERROR_OK;
 		}
 		else

[Openocd-svn] r2307 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:15:42 +0200 (Sun, 21 Jun 2009)
New Revision: 2307

Modified:
   trunk/src/target/arm_adi_v5.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/arm_adi_v5.c
===================================================================
--- trunk/src/target/arm_adi_v5.c	2009-06-21 03:15:36 UTC (rev 2306)
+++ trunk/src/target/arm_adi_v5.c	2009-06-21 03:15:42 UTC (rev 2307)
@@ -240,7 +240,7 @@
 	/* Check for STICKYERR and STICKYORUN */
 	if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
 	{
-		LOG_DEBUG("swjdp: CTRL/STAT error 0x%x", ctrlstat);
+		LOG_DEBUG("swjdp: CTRL/STAT error 0x%" PRIx32 "", ctrlstat);
 		/* Check power to debug regions */
 		if ((ctrlstat & 0xf0000000) != 0xf0000000)
 		{
@@ -251,7 +251,7 @@
 			uint32_t mem_ap_csw, mem_ap_tar;
 
 			/* Print information about last AHBAP access */
-			LOG_ERROR("AHBAP Cached values: dp_select 0x%x, ap_csw 0x%x, ap_tar 0x%x", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
+			LOG_ERROR("AHBAP Cached values: dp_select 0x%" PRIx32 ", ap_csw 0x%" PRIx32 ", ap_tar 0x%" PRIx32 "", swjdp->dp_select_value, swjdp->ap_csw_value, swjdp->ap_tar_value);
 			if (ctrlstat & SSTICKYORUN)
 				LOG_ERROR("SWJ-DP OVERRUN - check clock or reduce jtag speed");
 
@@ -264,13 +264,13 @@
 			if ((retval=jtag_execute_queue())!=ERROR_OK)
 				return retval;
 
-			LOG_DEBUG("swjdp: status 0x%x", ctrlstat);
+			LOG_DEBUG("swjdp: status 0x%" PRIx32 "", ctrlstat);
 
 			dap_ap_read_reg_u32(swjdp, AP_REG_CSW, &mem_ap_csw);
 			dap_ap_read_reg_u32(swjdp, AP_REG_TAR, &mem_ap_tar);
 			if ((retval=jtag_execute_queue())!=ERROR_OK)
 				return retval;
-			LOG_ERROR("Read MEM_AP_CSW 0x%x, MEM_AP_TAR 0x%x", mem_ap_csw, mem_ap_tar);
+			LOG_ERROR("Read MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%" PRIx32 "", mem_ap_csw, mem_ap_tar);
 
 		}
 		if ((retval=jtag_execute_queue())!=ERROR_OK)
@@ -508,7 +508,7 @@
 
 		if (errorcount > 1)
 		{
-			LOG_WARNING("Block write error address 0x%x, wcount 0x%x", address, wcount);
+			LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
 	}
@@ -550,7 +550,7 @@
 			{
 				if (mem_ap_write_buf_u16(swjdp, buffer, nbytes, address) != ERROR_OK)
 				{
-					LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+					LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 					return ERROR_JTAG_DEVICE_ERROR;
 				}
 
@@ -572,7 +572,7 @@
 				dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 				if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 				{
-					LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+					LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 					return ERROR_JTAG_DEVICE_ERROR;
 				}
 			}
@@ -642,7 +642,7 @@
 			{
 				if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
 				{
-					LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+					LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 					return ERROR_JTAG_DEVICE_ERROR;
 				}
 
@@ -664,7 +664,7 @@
 				dap_ap_write_reg_u32(swjdp, AP_REG_DRW, outvalue);
 				if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 				{
-					LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+					LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 					return ERROR_JTAG_DEVICE_ERROR;
 				}
 			}
@@ -756,7 +756,7 @@
 
 		if (errorcount > 1)
 		{
-			LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+			LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 			return ERROR_JTAG_DEVICE_ERROR;
 		}
 	}
@@ -813,7 +813,7 @@
 			dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
 			if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 			{
-				LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+				LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 				return ERROR_JTAG_DEVICE_ERROR;
 			}
 
@@ -905,7 +905,7 @@
 			dap_ap_read_reg_u32(swjdp, AP_REG_DRW, &invalue );
 			if (swjdp_transaction_endcheck(swjdp) != ERROR_OK)
 			{
-				LOG_WARNING("Block read error address 0x%x, count 0x%x", address, count);
+				LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 				return ERROR_JTAG_DEVICE_ERROR;
 			}
 
@@ -1002,7 +1002,7 @@
 	dap_ap_read_reg_u32(swjdp, 0xFC, &idreg);
 	dap_ap_read_reg_u32(swjdp, 0xF8, &romaddr);
 
-	LOG_DEBUG("AHB-AP ID Register 0x%x, Debug ROM Address 0x%x", idreg, romaddr);
+	LOG_DEBUG("AHB-AP ID Register 0x%" PRIx32 ", Debug ROM Address 0x%" PRIx32 "", idreg, romaddr);
 
 	return ERROR_OK;
 }
@@ -1028,7 +1028,7 @@
 	swjdp_transaction_endcheck(swjdp);
 	/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
 	mem_ap = ((apid&0x10000)&&((apid&0x0F)!=0));
-	command_print(cmd_ctx, "ap identification register 0x%8.8x", apid);
+	command_print(cmd_ctx, "ap identification register 0x%8.8" PRIx32 "", apid);
 	if (apid)
 	{
 		switch (apid&0x0F)
@@ -1046,7 +1046,7 @@
 				command_print(cmd_ctx, "\tUnknown AP-type");
 			break;
 		}
-		command_print(cmd_ctx, "ap debugbase 0x%8.8x", dbgbase);
+		command_print(cmd_ctx, "ap debugbase 0x%8.8" PRIx32 "", dbgbase);
 	}
 	else
 	{
@@ -1074,7 +1074,7 @@
 		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFFC, &cid3);
 		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000)|0xFCC, &memtype);
 		swjdp_transaction_endcheck(swjdp);
-		command_print(cmd_ctx, "\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",cid3,cid2,cid1,cid0);
+		command_print(cmd_ctx, "\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 " CID0, 0x%" PRIx32,cid3,cid2,cid1,cid0);
 		if (memtype&0x01)
 		{
 			command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
@@ -1089,7 +1089,7 @@
 		do
 		{
 			mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000)|entry_offset, &romentry);
-			command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%x",entry_offset,romentry);
+			command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
 			if (romentry&0x01)
 			{
 				uint32_t c_cid0,c_cid1,c_cid2,c_cid3,c_pid0,c_pid1,c_pid2,c_pid3,c_pid4,component_start;
@@ -1104,10 +1104,10 @@
 				mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFF8, &c_cid2);
 				mem_ap_read_atomic_u32(swjdp, (component_base&0xFFFFF000)|0xFFC, &c_cid3);
 				component_start = component_base - 0x1000*(c_pid4>>4);
-				command_print(cmd_ctx, "\t\tComponent base address 0x%x, pid4 0x%x, start address 0x%x",component_base,c_pid4,component_start);
-				command_print(cmd_ctx, "\t\tComponent cid1 0x%x, class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
-				command_print(cmd_ctx, "\t\tCID3 0x%x, CID2 0x%x, CID1 0x%x, CID0, 0x%x",c_cid3,c_cid2,c_cid1,c_cid0);
-				command_print(cmd_ctx, "\t\tPID3 0x%x, PID2 0x%x, PID1 0x%x, PID0, 0x%x",c_pid3,c_pid2,c_pid1,c_pid0);
+				command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32 ", pid4 0x%" PRIx32 ", start address 0x%" PRIx32 "",component_base,c_pid4,component_start);
+				command_print(cmd_ctx, "\t\tComponent cid1 0x%" PRIx32 ", class is %s",c_cid1,class_description[(c_cid1>>4)&0xF]); /* Se ARM DDI 0314 C Table 2.2 */
+				command_print(cmd_ctx, "\t\tCID3 0x%" PRIx32 ", CID2 0x%" PRIx32 ", CID1 0x%" PRIx32 ", CID0, 0x%" PRIx32 "",c_cid3,c_cid2,c_cid1,c_cid0);
+				command_print(cmd_ctx, "\t\tPID3 0x%" PRIx32 ", PID2 0x%" PRIx32 ", PID1 0x%" PRIx32 ", PID0, 0x%" PRIx32 "",c_pid3,c_pid2,c_pid1,c_pid0);
 				/* For CoreSight components,  (c_cid1>>4)&0xF==9 , we also read 0xFC8 DevId and 0xFCC DevType */
 			}
 			else

[Openocd-svn] r2306 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:15:36 +0200 (Sun, 21 Jun 2009)
New Revision: 2306

Modified:
   trunk/src/target/arm9tdmi.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/arm9tdmi.c
===================================================================
--- trunk/src/target/arm9tdmi.c	2009-06-21 03:15:32 UTC (rev 2305)
+++ trunk/src/target/arm9tdmi.c	2009-06-21 03:15:36 UTC (rev 2306)
@@ -511,7 +511,7 @@
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 
-	LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
+	LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
 
 	/* MSR1 fetched */
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), 0, NULL, 0);

[Openocd-svn] r2305 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:15:32 +0200 (Sun, 21 Jun 2009)
New Revision: 2305

Modified:
   trunk/src/target/arm966e.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/arm966e.c
===================================================================
--- trunk/src/target/arm966e.c	2009-06-21 03:15:28 UTC (rev 2304)
+++ trunk/src/target/arm966e.c	2009-06-21 03:15:32 UTC (rev 2305)
@@ -295,7 +295,7 @@
 				return retval;
 			}
 
-			command_print(cmd_ctx, "%i: %8.8x", address, value);
+			command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
 		}
 		else if (argc == 2)
 		{
@@ -305,7 +305,7 @@
 				command_print(cmd_ctx, "couldn't access reg %i", address);
 				return ERROR_OK;
 			}
-			command_print(cmd_ctx, "%i: %8.8x", address, value);
+			command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
 		}
 	}
 

[Openocd-svn] r2304 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:15:28 +0200 (Sun, 21 Jun 2009)
New Revision: 2304

Modified:
   trunk/src/target/arm926ejs.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/arm926ejs.c
===================================================================
--- trunk/src/target/arm926ejs.c	2009-06-21 03:15:24 UTC (rev 2303)
+++ trunk/src/target/arm926ejs.c	2009-06-21 03:15:28 UTC (rev 2304)
@@ -433,7 +433,7 @@
 	/* examine cp15 control reg */
 	arm926ejs->read_cp15(target, 0, 0, 1, 0, &arm926ejs->cp15_control_reg);
 	jtag_execute_queue();
-	LOG_DEBUG("cp15_control_reg: %8.8x", arm926ejs->cp15_control_reg);
+	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
 
 	if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1)
 	{
@@ -453,7 +453,7 @@
 	arm926ejs->read_cp15(target, 0, 1, 5, 0, &arm926ejs->i_fsr);
 	arm926ejs->read_cp15(target, 0, 0, 6, 0, &arm926ejs->d_far);
 
-	LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x",
+	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
 		arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 
 	uint32_t cache_dbg_ctrl;
@@ -544,7 +544,7 @@
 
 	LOG_USER(
 			"target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8x pc: 0x%8.8x\n"
+			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 			"MMU: %s, D-Cache: %s, I-Cache: %s",
 			 armv4_5_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple( nvp_target_debug_reason,target->debug_reason)->name,
@@ -789,7 +789,7 @@
 			return retval;
 		}
 
-		command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
+		command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
 	}
 	else
 	{
@@ -799,7 +799,7 @@
 			command_print(cmd_ctx, "couldn't access register");
 			return ERROR_OK;
 		}
-		command_print(cmd_ctx, "%i %i %i %i: %8.8x", opcode_1, opcode_2, CRn, CRm, value);
+		command_print(cmd_ctx, "%i %i %i %i: %8.8" PRIx32 "", opcode_1, opcode_2, CRn, CRm, value);
 	}
 
 	return ERROR_OK;

[Openocd-svn] r2303 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:15:24 +0200 (Sun, 21 Jun 2009)
New Revision: 2303

Modified:
   trunk/src/target/arm920t.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/arm920t.c
===================================================================
--- trunk/src/target/arm920t.c	2009-06-21 03:15:16 UTC (rev 2302)
+++ trunk/src/target/arm920t.c	2009-06-21 03:15:24 UTC (rev 2303)
@@ -381,7 +381,7 @@
 	/* examine cp15 control reg */
 	arm920t_read_cp15_physical(target, 0x2, &arm920t->cp15_control_reg);
 	jtag_execute_queue();
-	LOG_DEBUG("cp15_control_reg: %8.8x", arm920t->cp15_control_reg);
+	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm920t->cp15_control_reg);
 
 	if (arm920t->armv4_5_mmu.armv4_5_cache.ctype == -1)
 	{
@@ -402,7 +402,7 @@
 	arm920t_read_cp15_interpreted(target, 0xee160f10, 0x0, &arm920t->d_far);
 	arm920t_read_cp15_interpreted(target, 0xee160f30, 0x0, &arm920t->i_far);
 
-	LOG_DEBUG("D FSR: 0x%8.8x, D FAR: 0x%8.8x, I FSR: 0x%8.8x, I FAR: 0x%8.8x",
+	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 ", I FAR: 0x%8.8" PRIx32 "",
 		arm920t->d_fsr, arm920t->d_far, arm920t->i_fsr, arm920t->i_far);
 
 	if (arm920t->preserve_cache)
@@ -498,7 +498,7 @@
 	}
 
 	LOG_USER(	"target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8x pc: 0x%8.8x\n"
+			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 			"MMU: %s, D-Cache: %s, I-Cache: %s",
 			 armv4_5_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple(nvp_target_debug_reason, target->debug_reason)->name,
@@ -832,12 +832,12 @@
 
 			/* mask LFSR[6] */
 			regs[9] &= 0xfffffffe;
-			fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
+			fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 
 			for (i = 1; i < 9; i++)
 			{
 				 d_cache[segment][index].data[i] = regs[i];
-				 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
+				 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
 			}
 
 		}
@@ -918,12 +918,12 @@
 
 			/* mask LFSR[6] */
 			regs[9] &= 0xfffffffe;
-			fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8x, content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
+			fprintf(output, "\nsegment: %i, index: %i, CAM: 0x%8.8" PRIx32 ", content (%s):\n", segment, index, regs[9], (regs[9] & 0x10) ? "valid" : "invalid");
 
 			for (i = 1; i < 9; i++)
 			{
 				 i_cache[segment][index].data[i] = regs[i];
-				 fprintf(output, "%i: 0x%8.8x\n", i-1, regs[i]);
+				 fprintf(output, "%i: 0x%8.8" PRIx32 "\n", i-1, regs[i]);
 			}
 		}
 
@@ -1226,13 +1226,13 @@
 	fprintf(output, "D TLB content:\n");
 	for (i = 0; i < 64; i++)
 	{
-		fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
+		fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, d_tlb[i].cam, d_tlb[i].ram1, d_tlb[i].ram2, (d_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
 	}
 
 	fprintf(output, "\n\nI TLB content:\n");
 	for (i = 0; i < 64; i++)
 	{
-		fprintf(output, "%i: 0x%8.8x 0x%8.8x 0x%8.8x %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
+		fprintf(output, "%i: 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " 0x%8.8" PRIx32 " %s\n", i, i_tlb[i].cam, i_tlb[i].ram1, i_tlb[i].ram2, (i_tlb[i].cam & 0x20) ? "(valid)" : "(invalid)");
 	}
 
 	command_print(cmd_ctx, "mmu content successfully output to %s", args[0]);
@@ -1298,7 +1298,7 @@
 				return retval;
 			}
 
-			command_print(cmd_ctx, "%i: %8.8x", address, value);
+			command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
 		}
 		else if (argc == 2)
 		{
@@ -1308,7 +1308,7 @@
 				command_print(cmd_ctx, "couldn't access reg %i", address);
 				return ERROR_OK;
 			}
-			command_print(cmd_ctx, "%i: %8.8x", address, value);
+			command_print(cmd_ctx, "%i: %8.8" PRIx32 "", address, value);
 		}
 	}
 
@@ -1349,21 +1349,21 @@
 			uint32_t value;
 			if ((retval = arm920t_read_cp15_interpreted(target, opcode, 0x0, &value)) != ERROR_OK)
 			{
-				command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
+				command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
 				return ERROR_OK;
 			}
 
-			command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
+			command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
 		}
 		else if (argc == 2)
 		{
 			uint32_t value = strtoul(args[1], NULL, 0);
 			if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, 0)) != ERROR_OK)
 			{
-				command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
+				command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
 				return ERROR_OK;
 			}
-			command_print(cmd_ctx, "%8.8x: %8.8x", opcode, value);
+			command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 "", opcode, value);
 		}
 		else if (argc == 3)
 		{
@@ -1371,10 +1371,10 @@
 			uint32_t address = strtoul(args[2], NULL, 0);
 			if ((retval = arm920t_write_cp15_interpreted(target, opcode, value, address)) != ERROR_OK)
 			{
-				command_print(cmd_ctx, "couldn't execute %8.8x", opcode);
+				command_print(cmd_ctx, "couldn't execute %8.8" PRIx32 "", opcode);
 				return ERROR_OK;
 			}
-			command_print(cmd_ctx, "%8.8x: %8.8x %8.8x", opcode, value, address);
+			command_print(cmd_ctx, "%8.8" PRIx32 ": %8.8" PRIx32 " %8.8" PRIx32 "", opcode, value, address);
 		}
 	}
 	else

[Openocd-svn] r2302 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:15:16 +0200 (Sun, 21 Jun 2009)
New Revision: 2302

Modified:
   trunk/src/target/arm7tdmi.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/arm7tdmi.c
===================================================================
--- trunk/src/target/arm7tdmi.c	2009-06-21 03:15:10 UTC (rev 2301)
+++ trunk/src/target/arm7tdmi.c	2009-06-21 03:15:16 UTC (rev 2302)
@@ -458,7 +458,7 @@
 	arm7_9_common_t *arm7_9 = armv4_5->arch_info;
 	arm_jtag_t *jtag_info = &arm7_9->jtag_info;
 
-	LOG_DEBUG("xpsr: %8.8x, spsr: %i", xpsr, spsr);
+	LOG_DEBUG("xpsr: %8.8" PRIx32 ", spsr: %i", xpsr, spsr);
 
 	/* MSR1 fetched */
 	arm7tdmi_clock_out(jtag_info, ARMV4_5_MSR_IM(xpsr & 0xff, 0, 1, spsr), NULL, 0);

[Openocd-svn] r2301 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:15:10 +0200 (Sun, 21 Jun 2009)
New Revision: 2301

Modified:
   trunk/src/target/arm7_9_common.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/arm7_9_common.c
===================================================================
--- trunk/src/target/arm7_9_common.c	2009-06-21 03:15:03 UTC (rev 2300)
+++ trunk/src/target/arm7_9_common.c	2009-06-21 03:15:10 UTC (rev 2301)
@@ -290,7 +290,7 @@
 			}
 			if (verify != arm7_9->arm_bkpt)
 			{
-				LOG_ERROR("Unable to set 32 bit software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
+				LOG_ERROR("Unable to set 32 bit software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
 				return ERROR_OK;
 			}
 		}
@@ -314,7 +314,7 @@
 			}
 			if (verify != arm7_9->thumb_bkpt)
 			{
-				LOG_ERROR("Unable to set thumb software breakpoint at address %08x - check that memory is read/writable", breakpoint->address);
+				LOG_ERROR("Unable to set thumb software breakpoint at address %08" PRIx32 " - check that memory is read/writable", breakpoint->address);
 				return ERROR_OK;
 			}
 		}
@@ -721,7 +721,7 @@
 	}
 	if (timeout)
 	{
-		LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %x", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
+		LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "", buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 		return ERROR_TARGET_TIMEOUT;
 	}
 
@@ -1363,7 +1363,7 @@
 		/* Entered debug from Thumb mode */
 		armv4_5->core_state = ARMV4_5_STATE_THUMB;
 		arm7_9->change_to_arm(target, &r0_thumb, &pc_thumb);
-		LOG_DEBUG("r0_thumb: 0x%8.8x, pc_thumb: 0x%8.8x", r0_thumb, pc_thumb);
+		LOG_DEBUG("r0_thumb: 0x%8.8" PRIx32 ", pc_thumb: 0x%8.8" PRIx32 "", r0_thumb, pc_thumb);
 	}
 	else
 	{
@@ -1430,13 +1430,13 @@
 
 	for (i=0; i<=15; i++)
 	{
-		LOG_DEBUG("r%i: 0x%8.8x", i, context[i]);
+		LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
 		buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
 		ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
 	}
 
-	LOG_DEBUG("entered debug state at PC 0x%x", context[15]);
+	LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
 
 	if (armv4_5_mode_to_number(armv4_5->core_mode)==-1)
 		return ERROR_FAIL;
@@ -1662,7 +1662,7 @@
 					num_regs++;
 					reg->dirty = 0;
 					reg->valid = 1;
-					LOG_DEBUG("writing register %i of mode %s with value 0x%8.8x", j, armv4_5_mode_strings[i], regs[j]);
+					LOG_DEBUG("writing register %i of mode %s with value 0x%8.8" PRIx32 "", j, armv4_5_mode_strings[i], regs[j]);
 				}
 			}
 
@@ -1675,7 +1675,7 @@
 			reg_arch_info = reg->arch_info;
 			if ((reg->dirty) && (reg_arch_info->mode != ARMV4_5_MODE_ANY))
 			{
-				LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8x", i, buf_get_u32(reg->value, 0, 32));
+				LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "", i, buf_get_u32(reg->value, 0, 32));
 				arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
 			}
 		}
@@ -1689,20 +1689,20 @@
 		tmp_cpsr = buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & 0xE0;
 		tmp_cpsr |= armv4_5_number_to_mode(i);
 		tmp_cpsr &= ~0x20;
-		LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", tmp_cpsr);
+		LOG_DEBUG("writing lower 8 bit of cpsr with value 0x%2.2x", (unsigned)(tmp_cpsr));
 		arm7_9->write_xpsr_im8(target, tmp_cpsr & 0xff, 0, 0);
 	}
 	else if (armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty == 1)
 	{
 		/* CPSR has been changed, full restore necessary (mask T bit) */
-		LOG_DEBUG("writing cpsr with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
+		LOG_DEBUG("writing cpsr with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32));
 		arm7_9->write_xpsr(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 32) & ~0x20, 0);
 		armv4_5->core_cache->reg_list[ARMV4_5_CPSR].dirty = 0;
 		armv4_5->core_cache->reg_list[ARMV4_5_CPSR].valid = 1;
 	}
 
 	/* restore PC */
-	LOG_DEBUG("writing PC with value 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+	LOG_DEBUG("writing PC with value 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 	arm7_9->write_pc(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 	armv4_5->core_cache->reg_list[15].dirty = 0;
 
@@ -1807,7 +1807,7 @@
 	{
 		if ((breakpoint = breakpoint_find(target, buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32))))
 		{
-			LOG_DEBUG("unset breakpoint at 0x%8.8x", breakpoint->address);
+			LOG_DEBUG("unset breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
 			if ((retval = arm7_9_unset_breakpoint(target, breakpoint)) != ERROR_OK)
 			{
 				return retval;
@@ -1819,7 +1819,7 @@
 			{
 				uint32_t current_opcode;
 				target_read_u32(target, current_pc, &current_opcode);
-				LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
+				LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
 				return retval;
 			}
 
@@ -1863,9 +1863,9 @@
 			}
 
 			arm7_9_debug_entry(target);
-			LOG_DEBUG("new PC after step: 0x%8.8x", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
+			LOG_DEBUG("new PC after step: 0x%8.8" PRIx32 "", buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
 
-			LOG_DEBUG("set breakpoint at 0x%8.8x", breakpoint->address);
+			LOG_DEBUG("set breakpoint at 0x%8.8" PRIx32 "", breakpoint->address);
 			if ((retval = arm7_9_set_breakpoint(target, breakpoint)) != ERROR_OK)
 			{
 				return retval;
@@ -2024,7 +2024,7 @@
 	{
 		uint32_t current_opcode;
 		target_read_u32(target, current_pc, &current_opcode);
-		LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
+		LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "", current_opcode);
 		return retval;
 	}
 
@@ -2221,7 +2221,7 @@
 	int retval;
 	int last_reg = 0;
 
-	LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
+	LOG_DEBUG("address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
 
 	if (target->state != TARGET_HALTED)
 	{
@@ -2374,7 +2374,7 @@
 
 	if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
 	{
-		LOG_WARNING("memory read caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
+		LOG_WARNING("memory read caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 
@@ -2557,7 +2557,7 @@
 
 	if (((cpsr & 0x1f) == ARMV4_5_MODE_ABT) && (armv4_5->core_mode != ARMV4_5_MODE_ABT))
 	{
-		LOG_WARNING("memory write caused data abort (address: 0x%8.8x, size: 0x%x, count: 0x%x)", address, size, count);
+		LOG_WARNING("memory write caused data abort (address: 0x%8.8" PRIx32 ", size: 0x%" PRIx32 ", count: 0x%" PRIx32 ")", address, size, count);
 
 		arm7_9->write_xpsr_im8(target, buf_get_u32(armv4_5->core_cache->reg_list[ARMV4_5_CPSR].value, 0, 8) & ~0x20, 0, 0);
 
@@ -2679,7 +2679,7 @@
 		uint32_t endaddress=buf_get_u32(reg_params[0].value, 0, 32);
 		if (endaddress!=(address+count*4))
 		{
-			LOG_ERROR("DCC write failed, expected end address 0x%08x got 0x%0x", (address+count*4), endaddress);
+			LOG_ERROR("DCC write failed, expected end address 0x%08" PRIx32 " got 0x%0" PRIx32 "", (address+count*4), endaddress);
 			retval=ERROR_FAIL;
 		}
 	}

[Openocd-svn] r2300 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:15:03 +0200 (Sun, 21 Jun 2009)
New Revision: 2300

Modified:
   trunk/src/target/arm720t.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/arm720t.c
===================================================================
--- trunk/src/target/arm720t.c	2009-06-21 03:14:58 UTC (rev 2299)
+++ trunk/src/target/arm720t.c	2009-06-21 03:15:03 UTC (rev 2300)
@@ -140,7 +140,7 @@
 	else
 		LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
 #else
-		LOG_DEBUG("out: %8.8x, instruction: %i, clock: %i", out, instruction, clock);
+		LOG_DEBUG("out: %8.8" PRIx32 ", instruction: %i, clock: %i", out, instruction, clock);
 #endif
 
 	return ERROR_OK;
@@ -235,7 +235,7 @@
 	/* examine cp15 control reg */
 	arm720t_read_cp15(target, 0xee110f10, &arm720t->cp15_control_reg);
 	jtag_execute_queue();
-	LOG_DEBUG("cp15_control_reg: %8.8x", arm720t->cp15_control_reg);
+	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
 
 	arm720t->armv4_5_mmu.mmu_enabled = (arm720t->cp15_control_reg & 0x1U) ? 1 : 0;
 	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = (arm720t->cp15_control_reg & 0x4U) ? 1 : 0;
@@ -316,7 +316,7 @@
 	}
 
 	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
-			"cpsr: 0x%8.8x pc: 0x%8.8x\n"
+			"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "\n"
 			"MMU: %s, Cache: %s",
 			 armv4_5_state_strings[armv4_5->core_state],
 			 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name ,
@@ -534,7 +534,7 @@
 			uint32_t value;
 			if ((retval = arm720t_read_cp15(target, opcode, &value)) != ERROR_OK)
 			{
-				command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
+				command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 				return ERROR_OK;
 			}
 
@@ -543,17 +543,17 @@
 				return retval;
 			}
 
-			command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
+			command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 		}
 		else if (argc == 2)
 		{
 			uint32_t value = strtoul(args[1], NULL, 0);
 			if ((retval = arm720t_write_cp15(target, opcode, value)) != ERROR_OK)
 			{
-				command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8x", opcode);
+				command_print(cmd_ctx, "couldn't access cp15 with opcode 0x%8.8" PRIx32 "", opcode);
 				return ERROR_OK;
 			}
-			command_print(cmd_ctx, "0x%8.8x: 0x%8.8x", opcode, value);
+			command_print(cmd_ctx, "0x%8.8" PRIx32 ": 0x%8.8" PRIx32 "", opcode, value);
 		}
 	}
 

[Openocd-svn] r2299 - trunk/src/target

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:14:58 +0200 (Sun, 21 Jun 2009)
New Revision: 2299

Modified:
   trunk/src/target/arm11.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/target/arm11.c
===================================================================
--- trunk/src/target/arm11.c	2009-06-21 03:01:21 UTC (rev 2298)
+++ trunk/src/target/arm11.c	2009-06-21 03:14:58 UTC (rev 2299)
@@ -531,18 +531,18 @@
 		if (!arm11->reg_list[i].valid)
 		{
 			if (arm11->reg_history[i].valid)
-				LOG_DEBUG("%8s INVALID	 (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
+				LOG_DEBUG("%8s INVALID	 (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_history[i].value);
 		}
 		else
 		{
 			if (arm11->reg_history[i].valid)
 			{
 				if (arm11->reg_history[i].value != arm11->reg_values[i])
-					LOG_DEBUG("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
+					LOG_DEBUG("%8s %08" PRIx32 " (%08" PRIx32 ")", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
 			}
 			else
 			{
-				LOG_DEBUG("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
+				LOG_DEBUG("%8s %08" PRIx32 " (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
 			}
 		}
 	}
@@ -585,7 +585,7 @@
 
 		if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
 		{
-			LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08x)", DSCR);
+			LOG_ERROR("wDTR/rDTR inconsistent (DSCR %08" PRIx32 ")", DSCR);
 		}
 	}
 
@@ -672,7 +672,7 @@
 
 	CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 
-	LOG_DEBUG("DSCR %08x", dscr);
+	LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 
 	CHECK_RETVAL(arm11_check_init(arm11, &dscr));
 
@@ -708,7 +708,7 @@
 {
 	arm11_common_t * arm11 = target->arch_info;
 
-	LOG_USER("target halted due to %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
+	LOG_USER("target halted due to %s\ncpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "",
 			 Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
 			 R(CPSR),
 			 R(PC));
@@ -801,7 +801,7 @@
 	if (!current)
 		R(PC) = address;
 
-	LOG_DEBUG("RESUME PC %08x%s", R(PC), !current ? "!" : "");
+	LOG_DEBUG("RESUME PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 
 	/* clear breakpoints/watchpoints and VCR*/
 	arm11_sc7_clear_vbw(arm11);
@@ -817,7 +817,7 @@
 		{
 			if (bp->address == R(PC))
 			{
-				LOG_DEBUG("must step over %08x", bp->address);
+				LOG_DEBUG("must step over %08" PRIx32 "", bp->address);
 				arm11_step(target, 1, 0, 0);
 				break;
 			}
@@ -840,7 +840,7 @@
 
 			arm11_sc7_run(arm11, brp, asizeof(brp));
 
-			LOG_DEBUG("Add BP " ZU " at %08x", brp_num, bp->address);
+			LOG_DEBUG("Add BP " ZU " at %08" PRIx32 "", brp_num, bp->address);
 
 			brp_num++;
 		}
@@ -860,7 +860,7 @@
 
 		CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 
-		LOG_DEBUG("DSCR %08x", dscr);
+		LOG_DEBUG("DSCR %08" PRIx32 "", dscr);
 
 		if (dscr & ARM11_DSCR_CORE_RESTARTED)
 			break;
@@ -902,7 +902,7 @@
 	if (!current)
 		R(PC) = address;
 
-	LOG_DEBUG("STEP PC %08x%s", R(PC), !current ? "!" : "");
+	LOG_DEBUG("STEP PC %08" PRIx32 "%s", R(PC), !current ? "!" : "");
 
 	/** \todo TODO: Thumb not supported here */
 
@@ -979,7 +979,7 @@
 
 			CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
 
-			LOG_DEBUG("DSCR %08x", dscr);
+			LOG_DEBUG("DSCR %08" PRIx32 "e", dscr);
 
 			if ((dscr & (ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED)) ==
 				(ARM11_DSCR_CORE_RESTARTED | ARM11_DSCR_CORE_HALTED))
@@ -1102,7 +1102,7 @@
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	LOG_DEBUG("ADDR %08x  SIZE %08x  COUNT %08x", address, size, count);
+	LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 
 	arm11_common_t * arm11 = target->arch_info;
 
@@ -1183,7 +1183,7 @@
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	LOG_DEBUG("ADDR %08x  SIZE %08x  COUNT %08x", address, size, count);
+	LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "", address, size, count);
 
 	arm11_common_t * arm11 = target->arch_info;
 
@@ -1267,7 +1267,7 @@
 
 		if (address + size * count != r0)
 		{
-			LOG_ERROR("Data transfer failed. (%d)", (r0 - address) - size * count);
+			LOG_ERROR("Data transfer failed. (%d)", (int)((r0 - address) - size * count));
 
 			if (arm11_config_memwrite_burst)
 				LOG_ERROR("use 'arm11 memwrite burst disable' to disable fast burst mode");
@@ -1396,11 +1396,11 @@
 	for (size_t i = 0; i < 16; i++)
 	{
 		context[i] = buf_get_u32((uint8_t*)(&arm11->reg_values[i]),0,32);
-		LOG_DEBUG("Save %zi: 0x%x",i,context[i]);
+		LOG_DEBUG("Save %zi: 0x%" PRIx32 "",i,context[i]);
 	}
 
 	cpsr = buf_get_u32((uint8_t*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
-	LOG_DEBUG("Save CPSR: 0x%x", cpsr);
+	LOG_DEBUG("Save CPSR: 0x%" PRIx32 "", cpsr);
 
 	for (int i = 0; i < num_mem_params; i++)
 	{
@@ -1479,7 +1479,7 @@
 
 	if (buf_get_u32(arm11->reg_list[15].value, 0, 32) != exit_point)
 	{
-		LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
+		LOG_WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
 			buf_get_u32(arm11->reg_list[15].value, 0, 32));
 		retval = ERROR_TARGET_TIMEOUT;
 		goto del_breakpoint;
@@ -1519,11 +1519,11 @@
 	// Restore context
 	for (size_t i = 0; i < 16; i++)
 	{
-		LOG_DEBUG("restoring register %s with value 0x%8.8x",
+		LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
 			 arm11->reg_list[i].name, context[i]);
 		arm11_set_reg(&arm11->reg_list[i], (uint8_t*)&context[i]);
 	}
-	LOG_DEBUG("restoring CPSR with value 0x%8.8x", cpsr);
+	LOG_DEBUG("restoring CPSR with value 0x%8.8" PRIx32 "", cpsr);
 	arm11_set_reg(&arm11->reg_list[ARM11_RC_CPSR], (uint8_t*)&cpsr);
 
 //	arm11->core_state = core_state;
@@ -1620,9 +1620,9 @@
 	arm11->free_brps = arm11->brp;
 	arm11->free_wrps = arm11->wrp;
 
-	LOG_DEBUG("IDCODE %08x IMPLEMENTOR %02x DIDR %08x",
+	LOG_DEBUG("IDCODE %08" PRIx32 " IMPLEMENTOR %02x DIDR %08" PRIx32 "",
 		arm11->device_id,
-		arm11->implementor,
+		(int)(arm11->implementor),
 		arm11->didr);
 
 	/* as a side-effect this reads DSCR and thus
@@ -1815,7 +1815,7 @@
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	LOG_INFO("VCR 0x%08X", arm11_vcr);
+	LOG_INFO("VCR 0x%08" PRIx32 "", arm11_vcr);
 	return ERROR_OK;
 }
 
@@ -1887,8 +1887,9 @@
 
 		if (values[i] > arm11_coproc_instruction_limits[i])
 		{
-			LOG_ERROR("Parameter %ld out of bounds (%d max). %s",
-				(long)(i + 2), arm11_coproc_instruction_limits[i],
+			LOG_ERROR("Parameter %ld out of bounds (%" PRId32 " max). %s",
+				  (long)(i + 2), 
+				  arm11_coproc_instruction_limits[i],
 				read ? arm11_mrc_syntax : arm11_mcr_syntax);
 			return -1;
 		}
@@ -1911,17 +1912,21 @@
 		uint32_t result;
 		arm11_run_instr_data_from_core_via_r0(arm11, instr, &result);
 
-		LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08x (%d)",
-			values[0], values[1], values[2], values[3], values[4], result, result);
+		LOG_INFO("MRC p%d, %d, R0, c%d, c%d, %d = 0x%08" PRIx32 " (%" PRId32 ")",
+			 (int)(values[0]), 
+			 (int)(values[1]), 
+			 (int)(values[2]), 
+			 (int)(values[3]), 
+			 (int)(values[4]), result, result);
 	}
 	else
 	{
 		arm11_run_instr_data_to_core_via_r0(arm11, instr, values[5]);
 
-		LOG_INFO("MRC p%d, %d, R0 (#0x%08x), c%d, c%d, %d",
-			values[0], values[1],
-			values[5],
-			values[2], values[3], values[4]);
+		LOG_INFO("MRC p%d, %d, R0 (#0x%08" PRIx32 "), c%d, c%d, %d",
+			 (int)(values[0]), (int)(values[1]),
+			 values[5],
+			 (int)(values[2]), (int)(values[3]), (int)(values[4]));
 	}
 
 	arm11_run_instr_data_finish(arm11);

[Openocd-svn] r2298 - trunk/src/server

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:01:21 +0200 (Sun, 21 Jun 2009)
New Revision: 2298

Modified:
   trunk/src/server/gdb_server.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/server/gdb_server.c
===================================================================
--- trunk/src/server/gdb_server.c	2009-06-21 03:00:43 UTC (rev 2297)
+++ trunk/src/server/gdb_server.c	2009-06-21 03:01:21 UTC (rev 2298)
@@ -1186,7 +1186,7 @@
 
 	buffer = malloc(len);
 
-	LOG_DEBUG("addr: 0x%8.8x, len: 0x%8.8x", addr, len);
+	LOG_DEBUG("addr: 0x%8.8" PRIx32 ", len: 0x%8.8" PRIx32 "", addr, len);
 
 	retval = target_read_buffer(target, addr, len, buffer);
 
@@ -1266,12 +1266,12 @@
 
 	buffer = malloc(len);
 
-	LOG_DEBUG("addr: 0x%8.8x, len: 0x%8.8x", addr, len);
+	LOG_DEBUG("addr: 0x%8.8" PRIx32 ", len: 0x%8.8" PRIx32 "", addr, len);
 
 	for (i=0; i<len; i++)
 	{
 		uint32_t tmp;
-		sscanf(separator + 2*i, "%2x", &tmp);
+		sscanf(separator + 2*i, "%2" SCNx32 , &tmp);
 		buffer[i] = tmp;
 	}
 
@@ -1321,7 +1321,7 @@
 	retval = ERROR_OK;
 	if (len)
 	{
-		LOG_DEBUG("addr: 0x%8.8x, len: 0x%8.8x", addr, len);
+		LOG_DEBUG("addr: 0x%8.8" PRIx32 ", len: 0x%8.8" PRIx32 "", addr, len);
 
 		retval = target_write_buffer(target, addr, len, (uint8_t*)separator);
 	}
@@ -1587,7 +1587,7 @@
 			for (i=0; i < (packet_size - 6)/2; i++)
 			{
 				uint32_t tmp;
-				sscanf(packet + 6 + 2*i, "%2x", &tmp);
+				sscanf(packet + 6 + 2*i, "%2" SCNx32 , &tmp);
 				cmd[i] = tmp;
 			}
 			cmd[(packet_size - 6)/2] = 0x0;
@@ -1631,7 +1631,7 @@
 
 			if (retval == ERROR_OK)
 			{
-				snprintf(gdb_reply, 10, "C%8.8x", checksum);
+				snprintf(gdb_reply, 10, "C%8.8" PRIx32 "", checksum);
 				gdb_put_packet(connection, gdb_reply, 9);
 			}
 			else
@@ -1946,7 +1946,7 @@
 			}
 		else
 		{
-			LOG_DEBUG("wrote %u bytes from vFlash image to flash", written);
+			LOG_DEBUG("wrote %u bytes from vFlash image to flash", (unsigned)written);
 			gdb_put_packet(connection, "OK", 2);
 		}
 

[Openocd-svn] r2297 - trunk/src/pld

[<du...@ma...>]

Author: duane
Date: 2009-06-21 05:00:43 +0200 (Sun, 21 Jun 2009)
New Revision: 2297

Modified:
   trunk/src/pld/virtex2.c
   trunk/src/pld/xilinx_bit.c
Log:
C99 printf() -Werror fixes

Modified: trunk/src/pld/virtex2.c
===================================================================
--- trunk/src/pld/virtex2.c	2009-06-21 02:59:39 UTC (rev 2296)
+++ trunk/src/pld/virtex2.c	2009-06-21 03:00:43 UTC (rev 2297)
@@ -138,7 +138,7 @@
 
 	jtag_execute_queue();
 
-	LOG_DEBUG("status: 0x%8.8x", *status);
+	LOG_DEBUG("status: 0x%8.8" PRIx32 "", *status);
 
 	return ERROR_OK;
 }
@@ -213,7 +213,7 @@
 
 	virtex2_read_stat(device, &status);
 
-	command_print(cmd_ctx, "virtex2 status register: 0x%8.8x", status);
+	command_print(cmd_ctx, "virtex2 status register: 0x%8.8" PRIx32 "", status);
 
 	return ERROR_OK;
 }

Modified: trunk/src/pld/xilinx_bit.c
===================================================================
--- trunk/src/pld/xilinx_bit.c	2009-06-21 02:59:39 UTC (rev 2296)
+++ trunk/src/pld/xilinx_bit.c	2009-06-21 03:00:43 UTC (rev 2297)
@@ -128,7 +128,7 @@
 	if (read_section(input_file, 4, 'e', &bit_file->length, &bit_file->data) != ERROR_OK)
 		return ERROR_PLD_FILE_LOAD_FAILED;
 
-	LOG_DEBUG("bit_file: %s %s %s,%s %i", bit_file->source_file, bit_file->part_name,
+	LOG_DEBUG("bit_file: %s %s %s,%s %" PRIi32 "", bit_file->source_file, bit_file->part_name,
 		bit_file->date, bit_file->time, bit_file->length);
 
 	fclose(input_file);

[Openocd-svn] r2296 - trunk/src/helper

[<du...@ma...>]

Author: duane
Date: 2009-06-21 04:59:39 +0200 (Sun, 21 Jun 2009)
New Revision: 2296

Modified:
   trunk/src/helper/types.h
Log:
C99 Type updates, include inttypes.h - it is catagorically required

Modified: trunk/src/helper/types.h
===================================================================
--- trunk/src/helper/types.h	2009-06-20 18:19:21 UTC (rev 2295)
+++ trunk/src/helper/types.h	2009-06-21 02:59:39 UTC (rev 2296)
@@ -29,6 +29,9 @@
 #ifdef HAVE_STDINT_H
 #include <stdint.h>
 #endif
+#ifdef HAVE_INTTYPES_H
+#include <inttypes.h>
+#endif
 
 typedef struct jtag_tap_s jtag_tap_t;