openocd-commit — OpenOCD commit maling list - read only

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-131-gd7dba8d

[David B. <dbr...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  d7dba8d346bed622ab4269723d1d1c8992d3353b (commit)
      from  1cda3e64e4555d64496709b23f0af1da8f3a7034 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit d7dba8d346bed622ab4269723d1d1c8992d3353b
Author: David Brownell <dbr...@us...>
Date:   Wed Mar 24 16:04:26 2010 -0700

    FT2232 Messaaging fix
    
    The init cleanup patch overlooked a message which was
    wrongly specific to the "usbjtag" layout.  Fix.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/jtag/drivers/ft2232.c b/src/jtag/drivers/ft2232.c
index dd11aec..93d1c4a 100644
--- a/src/jtag/drivers/ft2232.c
+++ b/src/jtag/drivers/ft2232.c
@@ -2433,7 +2433,7 @@ static int ftx232_init_tail(void)
 
 	if (((ft2232_write(buf, 3, &bytes_written)) != ERROR_OK) || (bytes_written != 3))
 	{
-		LOG_ERROR("couldn't initialize FT2232 with 'USBJTAG' layout");
+		LOG_ERROR("couldn't initialize FT2232 DBUS");
 		return ERROR_JTAG_INIT_FAILED;
 	}
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/ft2232.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-130-g1cda3e6

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  1cda3e64e4555d64496709b23f0af1da8f3a7034 (commit)
       via  9f1d9499ce5d15f25c3d0f150348e16deb2e7aaf (commit)
      from  721502f1d3a0d506bc0e814926368fbedda60028 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 1cda3e64e4555d64496709b23f0af1da8f3a7034
Author: Antonio Borneo <bor...@gm...>
Date:   Wed Mar 24 12:08:45 2010 +0800

    server: review unused symbols
    
    Remove unused function
    
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/server/server.c b/src/server/server.c
index 1a6250c..0d3273b 100644
--- a/src/server/server.c
+++ b/src/server/server.c
@@ -233,34 +233,6 @@ int add_service(char *name, enum connection_type type, unsigned short port, int
 	return ERROR_OK;
 }
 
-int remove_service(unsigned short port)
-{
-	struct service **p = &services;
-	struct service *c;
-
-	/* find service */
-	while ((c = *p))
-	{
-		if (c->port == port)
-		{
-			if (c->name)
-				free(c->name);
-
-			if (c->priv)
-				free(c->priv);
-
-			/* delete service */
-			*p = c->next;
-			free(c);
-		}
-
-		/* redirect p to next list pointer */
-		p = &(*p)->next;
-	}
-
-	return ERROR_OK;
-}
-
 static int remove_services(void)
 {
 	struct service *c = services;

commit 9f1d9499ce5d15f25c3d0f150348e16deb2e7aaf
Author: Antonio Borneo <bor...@gm...>
Date:   Wed Mar 24 12:06:45 2010 +0800

    server: review scope of functions and data
    
    Add "static" qualifier to private functions and data.
    
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/server/server.c b/src/server/server.c
index 173beb8..1a6250c 100644
--- a/src/server/server.c
+++ b/src/server/server.c
@@ -40,7 +40,7 @@
 #endif
 
 
-struct service *services = NULL;
+static struct service *services = NULL;
 
 /* shutdown_openocd == 1: exit the main event loop, and quit the debugger */
 static int shutdown_openocd = 0;
@@ -48,7 +48,7 @@ static int shutdown_openocd = 0;
 /* set when using pipes rather than tcp */
 int server_use_pipes = 0;
 
-int add_connection(struct service *service, struct command_context *cmd_ctx)
+static int add_connection(struct service *service, struct command_context *cmd_ctx)
 {
 	socklen_t address_size;
 	struct connection *c, **p;
@@ -112,7 +112,7 @@ int add_connection(struct service *service, struct command_context *cmd_ctx)
 	return ERROR_OK;
 }
 
-int remove_connection(struct service *service, struct connection *connection)
+static int remove_connection(struct service *service, struct connection *connection)
 {
 	struct connection **p = &service->connections;
 	struct connection *c;
@@ -261,7 +261,7 @@ int remove_service(unsigned short port)
 	return ERROR_OK;
 }
 
-int remove_services(void)
+static int remove_services(void)
 {
 	struct service *c = services;
 

-----------------------------------------------------------------------

Summary of changes:
 src/server/server.c |   36 ++++--------------------------------
 1 files changed, 4 insertions(+), 32 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-128-g721502f

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  721502f1d3a0d506bc0e814926368fbedda60028 (commit)
      from  4be9eded7f723af8fe755b1ef62469e87d1003bc (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 721502f1d3a0d506bc0e814926368fbedda60028
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Mar 22 08:27:03 2010 +0100

    zy1000: fix optimisaion bug in dcc writes
    
    Introduced & corrected since 0.4.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index 6f75e59..b8abc89 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -828,23 +828,17 @@ void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer,
 		}
 	} else
 	{
-		tap_state_t end_state = TAP_IDLE;
-		tap_state_t shift_end_state = TAP_DRSHIFT;
-		if (post_bits == 0)
-			shift_end_state = end_state;
-
 		shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, pre_bits, 0);
 		int i;
 		for (i = 0; i < count - 1; i++)
 		{
 			/* Fewer pokes means we get to use the FIFO more efficiently */
 			shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, little));
-			shiftValueInner(TAP_DRSHIFT, shift_end_state, 6 + post_bits + pre_bits, (reg_addr | (1 << 5)));
+			shiftValueInner(TAP_DRSHIFT, TAP_IDLE, 6 + post_bits + pre_bits, (reg_addr | (1 << 5)));
 			buffer += 4;
 		}
 		shiftValueInner(TAP_DRSHIFT, TAP_DRSHIFT, 32, fast_target_buffer_get_u32(buffer, little));
-		shiftValueInner(TAP_DRSHIFT, shift_end_state, 6, reg_addr | (1 << 5));
-		shiftValueInner(shift_end_state, end_state, post_bits, 0);
+		shiftValueInner(TAP_DRSHIFT, TAP_IDLE, 6 + post_bits, (reg_addr | (1 << 5)));
 	}
 }
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/zy1000/zy1000.c |   10 ++--------
 1 files changed, 2 insertions(+), 8 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-127-g4be9ede

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  4be9eded7f723af8fe755b1ef62469e87d1003bc (commit)
      from  ccfaed8bc7936d7a1640bf69df52ac65ca38e298 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 4be9eded7f723af8fe755b1ef62469e87d1003bc
Author: Mike Dunn <mik...@ne...>
Date:   Sat Mar 20 10:53:47 2010 -0400

    fix software breakpoints on xscale
    
    This patch fixes xscale software breakpoints by cleaning the dcache and
    invalidating the icache after the bkpt instruction is inserted or removed.  The
    icache operation is necessary in order to flush the fetch buffers, even if the
    icache is disabled (see section 4.2.7 of the xscale core developer's manual).
    The dcache is presumed to be enabled; no harm done if not.  The dcache is also
    invalidated after cleaning in order to safeguard against a future load of
    invalid data, in the event that cache_clean_address points to memory that is
    valid and in use.
    
    Also corrected a confusing typo I noticed in a comment.
    
    TODO (or not TODO...?): the xscale's 2K "mini dcache" is not cleaned.  This
    cache is not used unless the 'X' bit in the page table entry is set.  This is a
    proprietary xscale extension to the ARM architecture.  If a target's OS or
    executive makes use of this for memory regions holding code, the breakpoint
    problem will persist.  Flushing the mini dcache requires that 2K of valid
    cacheable memory (mapped with 'X' bit set) be designated by the user for this
    purpose.  The debug handler that gets downloaded to the target will also need to
    be extended.

diff --git a/src/target/xscale.c b/src/target/xscale.c
index 0f1953d..e578a77 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -2125,7 +2125,7 @@ static int xscale_set_breakpoint(struct target *target,
 			{
 				return retval;
 			}
-			/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
+			/* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 			if ((retval = target_write_u32(target, breakpoint->address, xscale->arm_bkpt)) != ERROR_OK)
 			{
 				return retval;
@@ -2138,13 +2138,18 @@ static int xscale_set_breakpoint(struct target *target,
 			{
 				return retval;
 			}
-			/* write the original instruction in target endianness (arm7_9->arm_bkpt is host endian) */
+			/* write the bkpt instruction in target endianness (arm7_9->arm_bkpt is host endian) */
 			if ((retval = target_write_u32(target, breakpoint->address, xscale->thumb_bkpt)) != ERROR_OK)
 			{
 				return retval;
 			}
 		}
 		breakpoint->set = 1;
+
+		xscale_send_u32(target, 0x50);   /* clean dcache */
+		xscale_send_u32(target, xscale->cache_clean_address);
+		xscale_send_u32(target, 0x51);   /* invalidate dcache */
+		xscale_send_u32(target, 0x52);   /* invalidate icache and flush fetch buffers */
 	}
 
 	return ERROR_OK;
@@ -2225,6 +2230,11 @@ static int xscale_unset_breakpoint(struct target *target,
 			}
 		}
 		breakpoint->set = 0;
+
+		xscale_send_u32(target, 0x50);   /* clean dcache */
+		xscale_send_u32(target, xscale->cache_clean_address);
+		xscale_send_u32(target, 0x51);   /* invalidate dcache */
+		xscale_send_u32(target, 0x52);   /* invalidate icache and flush fetch buffers */
 	}
 
 	return ERROR_OK;

-----------------------------------------------------------------------

Summary of changes:
 src/target/xscale.c |   14 ++++++++++++--
 1 files changed, 12 insertions(+), 2 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-126-gccfaed8

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  ccfaed8bc7936d7a1640bf69df52ac65ca38e298 (commit)
      from  c2f714bd4482cfe3c09efdc57e8b6b7e8536e181 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit ccfaed8bc7936d7a1640bf69df52ac65ca38e298
Author: Øyvind Harboe <oyv...@zy...>
Date:   Mon Mar 22 07:21:09 2010 +0100

    bitq: fix warning now that out_value is const
    
    This was an easy one. Just add the missing "const" to a
    local variable definition.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/drivers/bitq.c b/src/jtag/drivers/bitq.c
index bffc475..79ca349 100644
--- a/src/jtag/drivers/bitq.c
+++ b/src/jtag/drivers/bitq.c
@@ -226,7 +226,7 @@ void bitq_scan_field(struct scan_field* field, int pause)
 	int bit_cnt;
 	int tdo_req;
 
-	uint8_t* out_ptr;
+	const uint8_t* out_ptr;
 	uint8_t  out_mask;
 
 	if (field->in_value)

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/bitq.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-125-gc2f714b

[David B. <dbr...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  c2f714bd4482cfe3c09efdc57e8b6b7e8536e181 (commit)
      from  b7811b76795aaeacfea0473bdca2c44826f20501 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit c2f714bd4482cfe3c09efdc57e8b6b7e8536e181
Author: David Brownell <dbr...@us...>
Date:   Sun Mar 21 22:49:23 2010 -0700

    ft2232 init mess cleanup
    
    In the ft2232 driver, initialization for many layouts punts to a routine
    called usbjtag_init(), instead of a routine specific to each layout.
    
    That routine is  a mess  built around a "what type layout am I" core.
    That's a bad design ... in this case, especially so, since it bypasses
    the layout-specific dispatch which was just done, and obfuscates the
    initialization which is at least somewhat generic, instead of being
    specific to the "usbjtag" layout.
    
    Split and document out the generic parts of usbjtag_init(), and make
    the rest of those layouts have layout-specific init methods.  Also,
    rename usbjtag_reset() ... that also was not specific to the "usbjtag"
    layout, and thus contributed to the previous code structure confusion.
    
    (Eventually, all layout-specific code (and method tables) should probably
    live in files specific to each layout.  These changes will facilitate
    those and other cleanups to this driver.)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/jtag/drivers/ft2232.c b/src/jtag/drivers/ft2232.c
index 8e835c5..dd11aec 100644
--- a/src/jtag/drivers/ft2232.c
+++ b/src/jtag/drivers/ft2232.c
@@ -172,6 +172,8 @@ struct ft2232_layout {
 /* init procedures for supported layouts */
 static int usbjtag_init(void);
 static int jtagkey_init(void);
+static int lm3s811_jtag_init(void);
+static int icdi_jtag_init(void);
 static int olimex_jtag_init(void);
 static int flyswatter_init(void);
 static int turtle_init(void);
@@ -181,12 +183,13 @@ static int axm0432_jtag_init(void);
 static int sheevaplug_init(void);
 static int icebear_jtag_init(void);
 static int cortino_jtag_init(void);
+static int signalyzer_init(void);
 static int signalyzer_h_init(void);
 static int ktlink_init(void);
 static int redbee_init(void);
 
 /* reset procedures for supported layouts */
-static void usbjtag_reset(int trst, int srst);
+static void ftx23_reset(int trst, int srst);
 static void jtagkey_reset(int trst, int srst);
 static void olimex_jtag_reset(int trst, int srst);
 static void flyswatter_reset(int trst, int srst);
@@ -211,7 +214,7 @@ static const struct ft2232_layout  ft2232_layouts[] =
 {
 	{ .name = "usbjtag",
 		.init = usbjtag_init,
-		.reset = usbjtag_reset,
+		.reset = ftx23_reset,
 	},
 	{ .name = "jtagkey",
 		.init = jtagkey_init,
@@ -226,16 +229,16 @@ static const struct ft2232_layout  ft2232_layouts[] =
 		.reset = jtagkey_reset,
 	},
 	{ .name = "signalyzer",
-		.init = usbjtag_init,
-		.reset = usbjtag_reset,
+		.init = signalyzer_init,
+		.reset = ftx23_reset,
 	},
 	{ .name = "evb_lm3s811",
-		.init = usbjtag_init,
-		.reset = usbjtag_reset,
+		.init = lm3s811_jtag_init,
+		.reset = ftx23_reset,
 	},
 	{ .name = "luminary_icdi",
-		.init = usbjtag_init,
-		.reset = usbjtag_reset,
+		.init = icdi_jtag_init,
+		.reset = ftx23_reset,
 	},
 	{ .name = "olimex-jtag",
 		.init = olimex_jtag_init,
@@ -298,14 +301,23 @@ static const struct ft2232_layout  ft2232_layouts[] =
 	{ .name = NULL, /* END OF TABLE */ },
 };
 
-static uint8_t                  nTRST, nTRSTnOE, nSRST, nSRSTnOE;
+/* bitmask used to drive nTRST; usually a GPIOLx signal */
+static uint8_t                  nTRST;
+static uint8_t                  nTRSTnOE;
+/* bitmask used to drive nSRST; usually a GPIOLx signal */
+static uint8_t                  nSRST;
+static uint8_t                  nSRSTnOE;
 
 /** the layout being used with this debug session */
 static const struct ft2232_layout *layout;
 
+/** default bitmask values ddriven on DBUS: TCK/TDI/TDO/TMS and GPIOL(0..4) */
 static uint8_t                  low_output     = 0x0;
+/** default direction bitmask for DBUS: TCK/TDI/TDO/TMS and GPIOL(0..4) */
 static uint8_t                  low_direction  = 0x0;
+/** default value bitmask for CBUS GPIOH(0..4) */
 static uint8_t                  high_output    = 0x0;
+/** default direction bitmask for CBUS GPIOH(0..4) */
 static uint8_t                  high_direction = 0x0;
 
 #if BUILD_FT2232_FTD2XX == 1
@@ -1340,7 +1352,8 @@ static int ft2232_predict_scan_in(int scan_size, enum scan_type type)
 	return predicted_size;
 }
 
-static void usbjtag_reset(int trst, int srst)
+/* semi-generic FT2232/FT4232 reset code */
+static void ftx23_reset(int trst, int srst)
 {
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
 	if (trst == 1)
@@ -2371,60 +2384,23 @@ static int ft2232_init(void)
 	return ERROR_OK;
 }
 
-static int usbjtag_init(void)
+/** Updates defaults for DBUS signals:  the four JTAG signals
+ * (TCK, TDI, TDO, TMS) and * the four GPIOL signals.
+ */
+static inline void ftx232_init_head(void)
 {
-	uint8_t  buf[3];
-	uint32_t bytes_written;
-	char *ft2232_layout = layout->name;
-
 	low_output    = 0x08;
 	low_direction = 0x0b;
+}
 
-	if (strcmp(ft2232_layout, "usbjtag") == 0)
-	{
-		nTRST    = 0x10;
-		nTRSTnOE = 0x10;
-		nSRST    = 0x40;
-		nSRSTnOE = 0x40;
-	}
-	else if (strcmp(ft2232_layout, "signalyzer") == 0)
-	{
-		nTRST    = 0x10;
-		nTRSTnOE = 0x10;
-		nSRST    = 0x20;
-		nSRSTnOE = 0x20;
-	}
-	else if (strcmp(ft2232_layout, "evb_lm3s811") == 0)
-	{
-		/* There are multiple revisions of LM3S811 eval boards:
-		 * - Rev B (and older?) boards have no SWO trace support.
-		 * - Rev C boards add ADBUS_6 DBG_ENn and BDBUS_4 SWO_EN;
-		 *   they should use the "luminary_icdi" layout instead.
-		 */
-		nTRST = 0x0;
-		nTRSTnOE = 0x00;
-		nSRST = 0x20;
-		nSRSTnOE = 0x20;
-		low_output    = 0x88;
-		low_direction = 0x8b;
-	}
-	else if (strcmp(ft2232_layout, "luminary_icdi") == 0)
-	{
-		/* Most Luminary eval boards support SWO trace output,
-		 * and should use this "luminary_icdi" layout.
-		 */
-		nTRST = 0x0;
-		nTRSTnOE = 0x00;
-		nSRST = 0x20;
-		nSRSTnOE = 0x20;
-		low_output    = 0x88;
-		low_direction = 0xcb;
-	}
-	else
-	{
-		LOG_ERROR("BUG: usbjtag_init called for unknown layout '%s'", ft2232_layout);
-		return ERROR_JTAG_INIT_FAILED;
-	}
+/** Initializes DBUS signals:  the four JTAG signals (TCK, TDI, TDO, TMS),
+ * the four GPIOL signals.  Initialization covers value and direction,
+ * as customized for each layout.
+ */
+static int ftx232_init_tail(void)
+{
+	uint8_t  buf[3];
+	uint32_t bytes_written;
 
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
 	if (jtag_reset_config & RESET_TRST_OPEN_DRAIN)
@@ -2464,6 +2440,69 @@ static int usbjtag_init(void)
 	return ERROR_OK;
 }
 
+static int usbjtag_init(void)
+{
+	/*
+	 * NOTE:  This is now _specific_ to the "usbjtag" layout.
+	 * Don't try cram any more layouts into this.
+	 */
+	ftx232_init_head();
+
+	nTRST    = 0x10;
+	nTRSTnOE = 0x10;
+	nSRST    = 0x40;
+	nSRSTnOE = 0x40;
+
+	return ftx232_init_tail();
+}
+
+static int lm3s811_jtag_init(void)
+{
+	ftx232_init_head();
+
+	/* There are multiple revisions of LM3S811 eval boards:
+	 * - Rev B (and older?) boards have no SWO trace support.
+	 * - Rev C boards add ADBUS_6 DBG_ENn and BDBUS_4 SWO_EN;
+	 *   they should use the "luminary_icdi" layout instead.
+	 */
+	nTRST = 0x0;
+	nTRSTnOE = 0x00;
+	nSRST = 0x20;
+	nSRSTnOE = 0x20;
+	low_output    = 0x88;
+	low_direction = 0x8b;
+
+	return ftx232_init_tail();
+}
+
+static int icdi_jtag_init(void)
+{
+	ftx232_init_head();
+
+	/* Most Luminary eval boards support SWO trace output,
+	 * and should use this "luminary_icdi" layout.
+	 */
+	nTRST = 0x0;
+	nTRSTnOE = 0x00;
+	nSRST = 0x20;
+	nSRSTnOE = 0x20;
+	low_output    = 0x88;
+	low_direction = 0xcb;
+
+	return ftx232_init_tail();
+}
+
+static int signalyzer_init(void)
+{
+	ftx232_init_head();
+
+	nTRST    = 0x10;
+	nTRSTnOE = 0x10;
+	nSRST    = 0x20;
+	nSRSTnOE = 0x20;
+	return ftx232_init_tail();
+}
+
 static int axm0432_jtag_init(void)
 {
 	uint8_t  buf[3];

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/ft2232.c |  159 ++++++++++++++++++++++++++++-----------------
 1 files changed, 99 insertions(+), 60 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-124-gb7811b7

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  b7811b76795aaeacfea0473bdca2c44826f20501 (commit)
      from  5dcad2d34fc40659018da2cf75ceeacd3abea860 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit b7811b76795aaeacfea0473bdca2c44826f20501
Author: Øyvind Harboe <oyv...@zy...>
Date:   Sun Mar 21 19:20:26 2010 +0100

    arm breakpoints: amended fix comment
    
    the handling of caches, should be moved into the breakpoint
    specific callbacks rather than being plonked into generic
    memory write fn's.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 4916de1..99f7dca 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -567,7 +567,11 @@ int arm920t_write_memory(struct target *target, uint32_t address,
 
 	/* FIX!!!! this should be cleaned up and made much more general. The
 	 * plan is to write up and test on arm920t specifically and
-	 * then generalize and clean up afterwards. */
+	 * then generalize and clean up afterwards.
+	 *
+	 * Also it should be moved to the callbacks that handle breakpoints
+	 * specifically and not the generic memory write fn's. See XScale code.
+	 */
 	if (arm920t->armv4_5_mmu.mmu_enabled && (count == 1) &&
 			((size==2) || (size==4)))
 	{
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index ff18bae..1f753a6 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -579,7 +579,12 @@ int arm926ejs_write_memory(struct target *target, uint32_t address,
 
 	/* FIX!!!! this should be cleaned up and made much more general. The
 	 * plan is to write up and test on arm926ejs specifically and
-	 * then generalize and clean up afterwards. */
+	 * then generalize and clean up afterwards.
+	 *
+	 *
+	 * Also it should be moved to the callbacks that handle breakpoints
+	 * specifically and not the generic memory write fn's. See XScale code.
+	 **/
 	if (arm926ejs->armv4_5_mmu.mmu_enabled && (count == 1) && ((size==2) || (size==4)))
 	{
 		/* special case the handling of single word writes to bypass MMU

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm920t.c   |    6 +++++-
 src/target/arm926ejs.c |    7 ++++++-
 2 files changed, 11 insertions(+), 2 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-123-g5dcad2d

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  5dcad2d34fc40659018da2cf75ceeacd3abea860 (commit)
       via  96949890ee29ab4b3ca15802302c5d93358b69e1 (commit)
      from  3b310dbac5ae1db7fb768aa0789bbe101137c7e1 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 5dcad2d34fc40659018da2cf75ceeacd3abea860
Author: Øyvind Harboe <oyv...@zy...>
Date:   Fri Mar 19 22:06:01 2010 +0100

    jtag: make out_value const
    
    Tightens up the jtag_add_xxx_scan() API
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index a6d16e9..cdc02ab 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -2,7 +2,7 @@
 *   Copyright (C) 2005 by Dominic Rath                                    *
 *   Dom...@gm...                                                   *
 *                                                                         *
-*   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+*   Copyright (C) 2007-2010 Øyvind Harboe                                 *
 *   oyv...@zy...                                               *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
@@ -112,7 +112,7 @@ struct scan_field {
 	/// The number of bits this field specifies (up to 32)
 	int num_bits;
 	/// A pointer to value to be scanned into the device
-	uint8_t* out_value;
+	const uint8_t* out_value;
 	/// A pointer to a 32-bit memory location for data scanned out
 	uint8_t* in_value;
 
diff --git a/src/jtag/tcl.c b/src/jtag/tcl.c
index 90081cd..25516cf 100644
--- a/src/jtag/tcl.c
+++ b/src/jtag/tcl.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dom...@gm...                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+ *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
  *   oyv...@zy...                                               *
  *                                                                         *
  *   Copyright (C) 2009 SoftPLC Corporation                                *
@@ -176,9 +176,10 @@ static int Jim_Command_drscan(Jim_Interp *interp, int argc, Jim_Obj *const *args
 		str = Jim_GetString(args[i + 1], &len);
 
 		fields[field_count].num_bits = bits;
-		fields[field_count].out_value = malloc(DIV_ROUND_UP(bits, 8));
-		str_to_buf(str, len, fields[field_count].out_value, bits, 0);
-		fields[field_count].in_value = fields[field_count].out_value;
+		void * t = malloc(DIV_ROUND_UP(bits, 8));
+		fields[field_count].out_value = t;
+		str_to_buf(str, len, t, bits, 0);
+		fields[field_count].in_value = t;
 		field_count++;
 	}
 
@@ -200,7 +201,7 @@ static int Jim_Command_drscan(Jim_Interp *interp, int argc, Jim_Obj *const *args
 
 		Jim_GetLong(interp, args[i], &bits);
 		str = buf_to_str(fields[field_count].in_value, bits, 16);
-		free(fields[field_count].out_value);
+		free((void *)fields[field_count].out_value);
 
 		Jim_ListAppendElement(interp, list, Jim_NewStringObj(interp, str, strlen(str)));
 		free(str);
@@ -1511,7 +1512,7 @@ COMMAND_HANDLER(handle_irscan_command)
 		{
 			int j;
 			for (j = 0; j < i; j++)
-				free(fields[j].out_value);
+				free((void *)fields[j].out_value);
                         free(fields);
 			command_print(CMD_CTX, "Tap: %s unknown", CMD_ARGV[i*2]);
 
@@ -1525,7 +1526,7 @@ COMMAND_HANDLER(handle_irscan_command)
 		retval = parse_u32(CMD_ARGV[i * 2 + 1], &value);
 		if (ERROR_OK != retval)
 			goto error_return;
-		buf_set_u32(fields[i].out_value, 0, field_size, value);
+		buf_set_u32((void *)fields[i].out_value, 0, field_size, value);
 		fields[i].in_value = NULL;
 	}
 
@@ -1538,7 +1539,7 @@ error_return:
 	for (i = 0; i < num_fields; i++)
 	{
 		if (NULL != fields[i].out_value)
-			free(fields[i].out_value);
+			free((void *)fields[i].out_value);
 	}
 
 	free (fields);
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 59cd562..69f3a76 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dom...@gm...                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008,2009 Øyvind Harboe                            *
+ *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
  *   oyv...@zy...                                               *
  *                                                                         *
  *   Copyright (C) 2008 by Spencer Oliver                                  *
@@ -357,7 +357,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	/* bits 36:32 -- register */
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	fields[1].out_value[0] = reg_addr;
+	field1_out[0] = reg_addr;
 	fields[1].in_value = NULL;
 	fields[1].check_value = NULL;
 	fields[1].check_mask = NULL;
@@ -365,7 +365,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	/* bit 37 -- 0/read */
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	fields[2].out_value[0] = 0;
+	field2_out[0] = 0;
 	fields[2].in_value = NULL;
 	fields[2].check_value = NULL;
 	fields[2].check_mask = NULL;
@@ -382,7 +382,7 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	 * EICE_COMMS_DATA would read the register twice
 	 * reading the control register is safe
 	 */
-	fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
+	field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
 	/* traverse Update-DR, reading but with no other side effects */
 	jtag_add_dr_scan_check(ice_reg->jtag_info->tap, 3, fields, TAP_IDLE);
@@ -413,12 +413,12 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+	field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 	fields[1].in_value = NULL;
 
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	fields[2].out_value[0] = 0;
+	field2_out[0] = 0;
 	fields[2].in_value = NULL;
 
 	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
@@ -429,7 +429,7 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 		 * to avoid reading additional data from the DCC data reg
 		 */
 		if (size == 1)
-			fields[1].out_value[0] = eice_regs[EICE_COMMS_CTRL].addr;
+			field1_out[0] = eice_regs[EICE_COMMS_CTRL].addr;
 
 		fields[0].in_value = (uint8_t *)data;
 		jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
@@ -529,18 +529,18 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+	field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 	fields[1].in_value = NULL;
 
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	fields[2].out_value[0] = 1;
+	field2_out[0] = 1;
 
 	fields[2].in_value = NULL;
 
 	while (size > 0)
 	{
-		buf_set_u32(fields[0].out_value, 0, 32, *data);
+		buf_set_u32(field0_out, 0, 32, *data);
 		jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 
 		data++;
@@ -581,12 +581,12 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 
 	fields[1].num_bits = 5;
 	fields[1].out_value = field1_out;
-	fields[1].out_value[0] = eice_regs[EICE_COMMS_DATA].addr;
+	field1_out[0] = eice_regs[EICE_COMMS_DATA].addr;
 	fields[1].in_value = NULL;
 
 	fields[2].num_bits = 1;
 	fields[2].out_value = field2_out;
-	fields[2].out_value[0] = 0;
+	field2_out[0] = 0;
 	fields[2].in_value = NULL;
 
 	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
diff --git a/src/target/etb.c b/src/target/etb.c
index 3280874..ba47c39 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -55,14 +55,15 @@ static int etb_set_instr(struct etb *etb, uint32_t new_instr)
 		struct scan_field field;
 
 		field.num_bits = tap->ir_length;
-		field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
-		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
+		void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
+		field.out_value = t;
+		buf_set_u32(t, 0, field.num_bits, new_instr);
 
 		field.in_value = NULL;
 
 		jtag_add_ir_scan(tap, &field, TAP_IDLE);
 
-		free(field.out_value);
+		free(t);
 	}
 
 	return ERROR_OK;
@@ -75,8 +76,9 @@ static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
 		struct scan_field field;
 
 		field.num_bits = 5;
-		field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
-		buf_set_u32(field.out_value, 0, field.num_bits, new_scan_chain);
+		void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
+		field.out_value = t;
+		buf_set_u32(t, 0, field.num_bits, new_scan_chain);
 
 		field.in_value = NULL;
 
@@ -86,7 +88,7 @@ static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
 
 		etb->cur_scan_chain = new_scan_chain;
 
-		free(field.out_value);
+		free(t);
 	}
 
 	return ERROR_OK;
@@ -181,13 +183,15 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
 	fields[0].in_value = NULL;
 
 	fields[1].num_bits = 7;
-	fields[1].out_value = malloc(1);
-	buf_set_u32(fields[1].out_value, 0, 7, 4);
+	uint8_t temp1;
+	fields[1].out_value = &temp1;
+	buf_set_u32(&temp1, 0, 7, 4);
 	fields[1].in_value = NULL;
 
 	fields[2].num_bits = 1;
-	fields[2].out_value = malloc(1);
-	buf_set_u32(fields[2].out_value, 0, 1, 0);
+	uint8_t temp2;
+	fields[2].out_value = &temp2;
+	buf_set_u32(&temp2, 0, 1, 0);
 	fields[2].in_value = NULL;
 
 	jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
@@ -195,13 +199,13 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
 	for (i = 0; i < num_frames; i++)
 	{
 		/* ensure nR/W reamins set to read */
-		buf_set_u32(fields[2].out_value, 0, 1, 0);
+		buf_set_u32(&temp2, 0, 1, 0);
 
 		/* address remains set to 0x4 (RAM data) until we read the last frame */
 		if (i < num_frames - 1)
-			buf_set_u32(fields[1].out_value, 0, 7, 4);
+			buf_set_u32(&temp1, 0, 7, 4);
 		else
-			buf_set_u32(fields[1].out_value, 0, 7, 0);
+			buf_set_u32(&temp1, 0, 7, 0);
 
 		fields[0].in_value = (uint8_t *)(data + i);
 		jtag_add_dr_scan(etb->tap, 3, fields, TAP_IDLE);
@@ -211,9 +215,6 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
 
 	jtag_execute_queue();
 
-	free(fields[1].out_value);
-	free(fields[2].out_value);
-
 	return ERROR_OK;
 }
 
@@ -236,15 +237,17 @@ static int etb_read_reg_w_check(struct reg *reg,
 	fields[0].check_mask = NULL;
 
 	fields[1].num_bits = 7;
-	fields[1].out_value = malloc(1);
-	buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
+	uint8_t temp1;
+	fields[1].out_value = &temp1;
+	buf_set_u32(&temp1, 0, 7, reg_addr);
 	fields[1].in_value = NULL;
 	fields[1].check_value = NULL;
 	fields[1].check_mask = NULL;
 
 	fields[2].num_bits = 1;
-	fields[2].out_value = malloc(1);
-	buf_set_u32(fields[2].out_value, 0, 1, 0);
+	uint8_t temp2;
+	fields[2].out_value = &temp2;
+	buf_set_u32(&temp2, 0, 1, 0);
 	fields[2].in_value = NULL;
 	fields[2].check_value = NULL;
 	fields[2].check_mask = NULL;
@@ -254,16 +257,13 @@ static int etb_read_reg_w_check(struct reg *reg,
 	/* read the identification register in the second run, to make sure we
 	 * don't read the ETB data register twice, skipping every second entry
 	 */
-	buf_set_u32(fields[1].out_value, 0, 7, 0x0);
+	buf_set_u32(&temp1, 0, 7, 0x0);
 	fields[0].in_value = reg->value;
 	fields[0].check_value = check_value;
 	fields[0].check_mask = check_mask;
 
 	jtag_add_dr_scan_check(etb_reg->etb->tap, 3, fields, TAP_IDLE);
 
-	free(fields[1].out_value);
-	free(fields[2].out_value);
-
 	return ERROR_OK;
 }
 
@@ -312,25 +312,23 @@ static int etb_write_reg(struct reg *reg, uint32_t value)
 	etb_set_instr(etb_reg->etb, 0xc);
 
 	fields[0].num_bits = 32;
-	fields[0].out_value = malloc(4);
-	buf_set_u32(fields[0].out_value, 0, 32, value);
+	uint8_t temp0[4];
+	fields[0].out_value = temp0;
+	buf_set_u32(&temp0, 0, 32, value);
 	fields[0].in_value = NULL;
 
 	fields[1].num_bits = 7;
-	fields[1].out_value = malloc(1);
-	buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
+	uint8_t temp1;
+	fields[1].out_value = &temp1;
+	buf_set_u32(&temp1, 0, 7, reg_addr);
 	fields[1].in_value = NULL;
 
 	fields[2].num_bits = 1;
-	fields[2].out_value = malloc(1);
-	buf_set_u32(fields[2].out_value, 0, 1, 1);
+	uint8_t temp2;
+	fields[2].out_value = &temp2;
+	buf_set_u32(&temp2, 0, 1, 1);
 
 	fields[2].in_value = NULL;
-
-	free(fields[0].out_value);
-	free(fields[1].out_value);
-	free(fields[2].out_value);
-
 	return ERROR_OK;
 }
 
diff --git a/src/target/etm.c b/src/target/etm.c
index 3850ced..4f4bf9a 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -514,15 +514,17 @@ static int etm_read_reg_w_check(struct reg *reg,
 	fields[0].check_mask = NULL;
 
 	fields[1].num_bits = 7;
-	fields[1].out_value = malloc(1);
-	buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
+	uint8_t temp1;
+	fields[1].out_value = &temp1;
+	buf_set_u32(&temp1, 0, 7, reg_addr);
 	fields[1].in_value = NULL;
 	fields[1].check_value = NULL;
 	fields[1].check_mask = NULL;
 
 	fields[2].num_bits = 1;
-	fields[2].out_value = malloc(1);
-	buf_set_u32(fields[2].out_value, 0, 1, 0);
+	uint8_t temp2;
+	fields[2].out_value = &temp2;
+	buf_set_u32(&temp2, 0, 1, 0);
 	fields[2].in_value = NULL;
 	fields[2].check_value = NULL;
 	fields[2].check_mask = NULL;
@@ -535,9 +537,6 @@ static int etm_read_reg_w_check(struct reg *reg,
 
 	jtag_add_dr_scan_check(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);
 
-	free(fields[1].out_value);
-	free(fields[2].out_value);
-
 	return ERROR_OK;
 }
 
@@ -592,19 +591,19 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
 	fields[0].num_bits = 32;
 	uint8_t tmp1[4];
 	fields[0].out_value = tmp1;
-	buf_set_u32(fields[0].out_value, 0, 32, value);
+	buf_set_u32(tmp1, 0, 32, value);
 	fields[0].in_value = NULL;
 
 	fields[1].num_bits = 7;
 	uint8_t tmp2;
 	fields[1].out_value = &tmp2;
-	buf_set_u32(fields[1].out_value, 0, 7, reg_addr);
+	buf_set_u32(&tmp2, 0, 7, reg_addr);
 	fields[1].in_value = NULL;
 
 	fields[2].num_bits = 1;
 	uint8_t tmp3;
 	fields[2].out_value = &tmp3;
-	buf_set_u32(fields[2].out_value, 0, 1, 1);
+	buf_set_u32(&tmp3, 0, 1, 1);
 	fields[2].in_value = NULL;
 
 	jtag_add_dr_scan(etm_reg->jtag_info->tap, 3, fields, TAP_IDLE);

commit 96949890ee29ab4b3ca15802302c5d93358b69e1
Author: Øyvind Harboe <oyv...@zy...>
Date:   Fri Mar 19 22:04:45 2010 +0100

    jtag: move towards making out_value const
    
    These were relatively straightforward fixes which are
    backwards compatible.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c
index 732226f..a93b6a2 100644
--- a/src/flash/nor/str9xpec.c
+++ b/src/flash/nor/str9xpec.c
@@ -44,13 +44,14 @@ int str9xpec_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end
 		struct scan_field field;
 
 		field.num_bits = tap->ir_length;
-		field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
-		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
+		void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
+		field.out_value = t;
+		buf_set_u32(t, 0, field.num_bits, new_instr);
 		field.in_value = NULL;
 
 		jtag_add_ir_scan(tap, &field, end_state);
 
-		free(field.out_value);
+		free(t);
 	}
 
 	return ERROR_OK;
diff --git a/src/pld/virtex2.c b/src/pld/virtex2.c
index b2833fa..1963736 100644
--- a/src/pld/virtex2.c
+++ b/src/pld/virtex2.c
@@ -36,13 +36,14 @@ static int virtex2_set_instr(struct jtag_tap *tap, uint32_t new_instr)
 		struct scan_field field;
 
 		field.num_bits = tap->ir_length;
-		field.out_value = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
-		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
+		void * t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
+		field.out_value = t;
+		buf_set_u32(t, 0, field.num_bits, new_instr);
 		field.in_value = NULL;
 
 		jtag_add_ir_scan(tap, &field, TAP_IDLE);
 
-		free(field.out_value);
+		free(t);
 	}
 
 	return ERROR_OK;
diff --git a/src/target/arm_jtag.c b/src/target/arm_jtag.c
index f8b5f4f..8cc4428 100644
--- a/src/target/arm_jtag.c
+++ b/src/target/arm_jtag.c
@@ -40,7 +40,7 @@ int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr,  vo
 
 	field.num_bits = tap->ir_length;
 	field.out_value = t;
-	buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
+	buf_set_u32(t, 0, field.num_bits, new_instr);
 	field.in_value = NULL;
 
 	if (no_verify_capture == NULL)
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 37e1f09..98b27f0 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -43,7 +43,7 @@ int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
 
 		field.num_bits = tap->ir_length;
 		field.out_value = t;
-		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
+		buf_set_u32(t, 0, field.num_bits, new_instr);
 		field.in_value = NULL;
 
 		jtag_add_ir_scan(tap, &field, TAP_IDLE);
@@ -105,7 +105,7 @@ int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
 
 	field.num_bits = 32;
 	field.out_value = t;
-	buf_set_u32(field.out_value, 0, field.num_bits, *data);
+	buf_set_u32(t, 0, field.num_bits, *data);
 	field.in_value = r;
 
 	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
@@ -136,7 +136,7 @@ int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
 
 	field.num_bits = 8;
 	field.out_value = t;
-	buf_set_u32(field.out_value, 0, field.num_bits, *data);
+	buf_set_u32(t, 0, field.num_bits, *data);
 	field.in_value = r;
 
 	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
diff --git a/src/target/xscale.c b/src/target/xscale.c
index f0e2311..0f1953d 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -171,7 +171,7 @@ static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_s
 		memset(&field, 0, sizeof field);
 		field.num_bits = tap->ir_length;
 		field.out_value = scratch;
-		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
+		buf_set_u32(scratch, 0, field.num_bits, new_instr);
 
 		jtag_add_ir_scan(tap, &field, end_state);
 	}

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/str9xpec.c |    7 +++--
 src/jtag/jtag.h          |    4 +-
 src/jtag/tcl.c           |   17 ++++++-----
 src/pld/virtex2.c        |    7 +++--
 src/target/arm_jtag.c    |    2 +-
 src/target/embeddedice.c |   24 ++++++++--------
 src/target/etb.c         |   68 ++++++++++++++++++++++-----------------------
 src/target/etm.c         |   19 ++++++-------
 src/target/mips_ejtag.c  |    6 ++--
 src/target/xscale.c      |    2 +-
 10 files changed, 78 insertions(+), 78 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-121-g3b310db

[David B. <dbr...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  3b310dbac5ae1db7fb768aa0789bbe101137c7e1 (commit)
      from  7373d1c342ff0ef5c0663fcee2f688eb5eb4ef65 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 3b310dbac5ae1db7fb768aa0789bbe101137c7e1
Author: David Brownell <dbr...@us...>
Date:   Fri Mar 19 10:31:44 2010 -0700

    FT2232 comment tweaks
    
    Note that the FT4232 chips have four channels not two, and
    Elaborate on uses of the additional channels.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/jtag/drivers/ft2232.c b/src/jtag/drivers/ft2232.c
index b45e8a4..8e835c5 100644
--- a/src/jtag/drivers/ft2232.c
+++ b/src/jtag/drivers/ft2232.c
@@ -32,12 +32,24 @@
  * JTAG adapters based on the FT2232 full and high speed USB parts are
  * popular low cost JTAG debug solutions.  Many FT2232 based JTAG adapters
  * are discrete, but development boards may integrate them as alternatives
- * to more capable (and expensive) third party JTAG pods.  Since JTAG uses
- * only one of the two ports on these devices, on integrated boards the
- * second port often serves as a USB-to-serial adapter for the target's
- * console UART even when the JTAG port is not in use.  (Systems which
- * support ARM's SWD in addition to JTAG, or instead of it, may use that
- * second port for reading SWV trace data.)
+ * to more capable (and expensive) third party JTAG pods.
+ *
+ * JTAG uses only one of the two communications channels ("MPSSE engines")
+ * on these devices.  Adapters based on FT4232 parts have four ports/channels
+ * (A/B/C/D), instead of just two (A/B).
+ *
+ * Especially on development boards integrating one of these chips (as
+ * opposed to discrete pods/dongles), the additional channels can be used
+ * for a variety of purposes, but OpenOCD only uses one channel at a time.
+ *
+ *  - As a USB-to-serial adapter for the target's console UART ...
+ *    which may be able to support ROM boot loaders that load initial
+ *    firmware images to flash (or SRAM).
+ *
+ *  - On systems which support ARM's SWD in addition to JTAG, or instead
+ *    of it, that second port can be used for reading SWV/SWO trace data.
+ *
+ *  - Additional JTAG links, e.g. to a CPLD or * FPGA.
  *
  * FT2232 based JTAG adapters are "dumb" not "smart", because most JTAG
  * request/response interactions involve round trips over the USB link.

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/ft2232.c |   24 ++++++++++++++++++------
 1 files changed, 18 insertions(+), 6 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-120-g7373d1c

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  7373d1c342ff0ef5c0663fcee2f688eb5eb4ef65 (commit)
      from  03359b16800c618ea4489d086bac9cd26a8d4547 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 7373d1c342ff0ef5c0663fcee2f688eb5eb4ef65
Author: Øyvind Harboe <oyv...@zy...>
Date:   Fri Mar 19 14:47:01 2010 +0100

    zy1000: clean up jtag_add_xx_scan fn's
    
    The implementation is now more straightforward as the
    scan_fields have been greatly simplified over time.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index a844dc3..6f75e59 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -492,103 +492,93 @@ static void shiftValueInnerFlip(const tap_state_t state, const tap_state_t endSt
 }
 #endif
 
-static void gotoEndState(tap_state_t end_state)
+// here we shuffle N bits out/in
+static __inline void scanBits(const uint8_t *out_value, uint8_t *in_value, int num_bits, bool pause, tap_state_t shiftState, tap_state_t end_state)
 {
-	setCurrentState(end_state);
-}
-
-static __inline void scanFields(int num_fields, const struct scan_field *fields, tap_state_t shiftState, int pause)
-{
-	int i;
-	int j;
-	int k;
-
-	for (i = 0; i < num_fields; i++)
+	tap_state_t pause_state = shiftState;
+	for (int j = 0; j < num_bits; j += 32)
 	{
-		cyg_uint32 value;
-
-		uint8_t *inBuffer = NULL;
-
-
-		// figure out where to store the input data
-		int num_bits = fields[i].num_bits;
-		if (fields[i].in_value != NULL)
+		int k = num_bits - j;
+		if (k > 32)
 		{
-			inBuffer = fields[i].in_value;
+			k = 32;
+			/* we have more to shift out */
+		} else if (pause)
+		{
+			/* this was the last to shift out this time */
+			pause_state = end_state;
 		}
 
-		// here we shuffle N bits out/in
-		j = 0;
-		while (j < num_bits)
+		// we have (num_bits + 7)/8 bytes of bits to toggle out.
+		// bits are pushed out LSB to MSB
+		cyg_uint32 value;
+		value = 0;
+		if (out_value != NULL)
 		{
-			tap_state_t pause_state;
-			int l;
-			k = num_bits-j;
-			pause_state = (shiftState == TAP_DRSHIFT)?TAP_DRSHIFT:TAP_IRSHIFT;
-			if (k > 32)
-			{
-				k = 32;
-				/* we have more to shift out */
-			} else if (pause&&(i == num_fields-1))
+			for (int l = 0; l < k; l += 8)
 			{
-				/* this was the last to shift out this time */
-				pause_state = (shiftState==TAP_DRSHIFT)?TAP_DRPAUSE:TAP_IRPAUSE;
+				value|=out_value[(j + l)/8]<<l;
 			}
+		}
+		/* mask away unused bits for easier debugging */
+		if (k < 32)
+		{
+			value&=~(((uint32_t)0xffffffff) << k);
+		} else
+		{
+			/* Shifting by >= 32 is not defined by the C standard
+			 * and will in fact shift by &0x1f bits on nios */
+		}
 
-			// we have (num_bits + 7)/8 bytes of bits to toggle out.
-			// bits are pushed out LSB to MSB
-			value = 0;
-			if (fields[i].out_value != NULL)
-			{
-				for (l = 0; l < k; l += 8)
-				{
-					value|=fields[i].out_value[(j + l)/8]<<l;
-				}
-			}
-			/* mask away unused bits for easier debugging */
-			if (k < 32)
-			{
-				value&=~(((uint32_t)0xffffffff) << k);
-			} else
-			{
-				/* Shifting by >= 32 is not defined by the C standard
-				 * and will in fact shift by &0x1f bits on nios */
-			}
+		shiftValueInner(shiftState, pause_state, k, value);
 
-			shiftValueInner(shiftState, pause_state, k, value);
+		if (in_value != NULL)
+		{
+			// data in, LSB to MSB
+			value = getShiftValue();
+			// we're shifting in data to MSB, shift data to be aligned for returning the value
+			value >>= 32-k;
 
-			if (inBuffer != NULL)
+			for (int l = 0; l < k; l += 8)
 			{
-				// data in, LSB to MSB
-				value = getShiftValue();
-				// we're shifting in data to MSB, shift data to be aligned for returning the value
-				value >>= 32-k;
-
-				for (l = 0; l < k; l += 8)
-				{
-					inBuffer[(j + l)/8]=(value >> l)&0xff;
-				}
+				in_value[(j + l)/8]=(value >> l)&0xff;
 			}
-			j += k;
 		}
 	}
 }
 
+static __inline void scanFields(int num_fields, const struct scan_field *fields, tap_state_t shiftState, tap_state_t end_state)
+{
+	for (int i = 0; i < num_fields; i++)
+	{
+		scanBits(fields[i].out_value,
+				fields[i].in_value,
+				fields[i].num_bits,
+				(i == num_fields-1),
+				shiftState,
+				end_state);
+	}
+}
+
 int interface_jtag_add_ir_scan(struct jtag_tap *active, const struct scan_field *fields, tap_state_t state)
 {
 	int scan_size = 0;
 	struct jtag_tap *tap, *nextTap;
+	tap_state_t pause_state = TAP_IRSHIFT;
 
 	for (tap = jtag_tap_next_enabled(NULL); tap!= NULL; tap = nextTap)
 	{
 		nextTap = jtag_tap_next_enabled(tap);
-		bool pause = (nextTap==NULL);
+		if (nextTap==NULL)
+		{
+			pause_state = state;
+		}
 		scan_size = tap->ir_length;
 
 		/* search the list */
 		if (tap == active)
 		{
-			scanFields(1, fields, TAP_IRSHIFT, pause);
+			scanFields(1, fields, TAP_IRSHIFT, pause_state);
 			/* update device information */
 			buf_cpy(fields[0].out_value, tap->cur_instr, scan_size);
 
@@ -597,12 +587,11 @@ int interface_jtag_add_ir_scan(struct jtag_tap *active, const struct scan_field
 		{
 			/* if a device isn't listed, set it to BYPASS */
 			assert(scan_size <= 32);
-			shiftValueInner(TAP_IRSHIFT, pause?TAP_IRPAUSE:TAP_IRSHIFT, scan_size, 0xffffffff);
+			shiftValueInner(TAP_IRSHIFT, pause_state, scan_size, 0xffffffff);
 
 			tap->bypass = 1;
 		}
 	}
-	gotoEndState(state);
 
 	return ERROR_OK;
 }
@@ -613,51 +602,41 @@ int interface_jtag_add_ir_scan(struct jtag_tap *active, const struct scan_field
 
 int interface_jtag_add_plain_ir_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, tap_state_t state)
 {
-	struct scan_field field;
-	field.num_bits	= num_bits;
-	field.out_value	= out_bits;
-	field.in_value	= in_bits;
-
-	scanFields(1, &field, TAP_IRSHIFT, 1);
-	gotoEndState(state);
-
+	scanBits(out_bits, in_bits, num_bits, true, TAP_IRSHIFT, state);
 	return ERROR_OK;
 }
 
 int interface_jtag_add_dr_scan(struct jtag_tap *active, int num_fields, const struct scan_field *fields, tap_state_t state)
 {
 	struct jtag_tap *tap, *nextTap;
+	tap_state_t pause_state = TAP_DRSHIFT;
 	for (tap = jtag_tap_next_enabled(NULL); tap!= NULL; tap = nextTap)
 	{
 		nextTap = jtag_tap_next_enabled(tap);
-		bool pause = (nextTap==NULL);
+		if (nextTap==NULL)
+		{
+			pause_state = state;
+		}
 
 		/* Find a range of fields to write to this tap */
 		if (tap == active)
 		{
 			assert(!tap->bypass);
 
-			scanFields(num_fields, fields, TAP_DRSHIFT, pause);
+			scanFields(num_fields, fields, TAP_DRSHIFT, pause_state);
 		} else
 		{
 			/* Shift out a 0 for disabled tap's */
 			assert(tap->bypass);
-			shiftValueInner(TAP_DRSHIFT, pause?TAP_DRPAUSE:TAP_DRSHIFT, 1, 0);
+			shiftValueInner(TAP_DRSHIFT, pause_state, 1, 0);
 		}
 	}
-	gotoEndState(state);
 	return ERROR_OK;
 }
 
 int interface_jtag_add_plain_dr_scan(int num_bits, const uint8_t *out_bits, uint8_t *in_bits, tap_state_t state)
 {
-	struct scan_field field;
-	field.num_bits	= num_bits;
-	field.out_value	= out_bits;
-	field.in_value	= in_bits;
-
-	scanFields(1, &field, TAP_DRSHIFT, 1);
-	gotoEndState(state);
+	scanBits(out_bits, in_bits, num_bits, true, TAP_DRSHIFT, state);
 	return ERROR_OK;
 }
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/zy1000/zy1000.c |  155 ++++++++++++++++++++--------------------------
 1 files changed, 67 insertions(+), 88 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-119-g03359b1

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  03359b16800c618ea4489d086bac9cd26a8d4547 (commit)
      from  7f6bab0c4c36d7a64f933904e5add9bc6b36d78c (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 03359b16800c618ea4489d086bac9cd26a8d4547
Author: Øyvind Harboe <oyv...@zy...>
Date:   Fri Mar 19 14:27:19 2010 +0100

    zy1000: fix bug in end state of DCC writes
    
    Introduced in latest commits, found by code inspection &
    GCC warning.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index 9b8b480..a844dc3 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -775,7 +775,7 @@ int interface_jtag_add_pathmove(int num_states, const tap_state_t *path)
 
 	uint8_t seq[16];
 	memset(seq, 0, sizeof(seq));
-	assert(num_states < (sizeof(seq) * 8));
+	assert(num_states < (int)((sizeof(seq) * 8)));
 
 	while (num_states)
 	{
@@ -850,7 +850,7 @@ void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer,
 	} else
 	{
 		tap_state_t end_state = TAP_IDLE;
-		tap_state_t shift_end_state;
+		tap_state_t shift_end_state = TAP_DRSHIFT;
 		if (post_bits == 0)
 			shift_end_state = end_state;
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/zy1000/zy1000.c |    4 ++--
 1 files changed, 2 insertions(+), 2 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-118-g7f6bab0

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  7f6bab0c4c36d7a64f933904e5add9bc6b36d78c (commit)
       via  15ff2aeca9b302419aed62fc3cc73dedacdd62cb (commit)
       via  1911c8ec8d286840c6a0d6a57c423072766d3386 (commit)
       via  729845238228f577bc3d6369d83667e5e2df1aee (commit)
       via  8ce828dd382c907db4c6bd38e5b54996e50327fd (commit)
      from  8d411d0d249dda7ceb951c4f8c8a509f4fd1dfb0 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 7f6bab0c4c36d7a64f933904e5add9bc6b36d78c
Author: Øyvind Harboe <oyv...@zy...>
Date:   Thu Mar 18 18:53:39 2010 +0100

    jtag: retire jtag_get/set_end_state()
    
    Voila! This get rids of mysteries about what what
    state the TAP is in.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/core.c b/src/jtag/core.c
index a09472a..65ca824 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -86,7 +86,6 @@ static struct jtag_tap *__jtag_all_taps = NULL;
 static unsigned jtag_num_taps = 0;
 
 static enum reset_types jtag_reset_config = RESET_NONE;
-static tap_state_t cmd_queue_end_state = TAP_RESET;
 tap_state_t cmd_queue_cur_state = TAP_RESET;
 
 static bool jtag_verify_capture_ir = true;
@@ -717,7 +716,6 @@ void jtag_add_reset(int req_tlr_or_trst, int req_srst)
 	 */
 	if (trst_with_tlr) {
 		LOG_DEBUG("JTAG reset with TLR instead of TRST");
-		jtag_set_end_state(TAP_RESET);
 		jtag_add_tlr();
 
 	} else if (jtag_trst != new_trst) {
@@ -743,24 +741,6 @@ void jtag_add_reset(int req_tlr_or_trst, int req_srst)
 	}
 }
 
-/* DEPRECATED! store such global state outside JTAG layer */
-void jtag_set_end_state(tap_state_t state)
-{
-	if ((state == TAP_DRSHIFT)||(state == TAP_IRSHIFT))
-	{
-		LOG_ERROR("BUG: TAP_DRSHIFT/IRSHIFT can't be end state. Calling code should use a larger scan field");
-	}
-
-	if (state != TAP_INVALID)
-		cmd_queue_end_state = state;
-}
-
-/* DEPRECATED! store such global state outside JTAG layer */
-tap_state_t jtag_get_end_state(void)
-{
-	return cmd_queue_end_state;
-}
-
 void jtag_add_sleep(uint32_t us)
 {
 	/// @todo Here, keep_alive() appears to be a layering violation!!!
diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index a92c986..a6d16e9 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -550,26 +550,6 @@ void jtag_add_runtest(int num_cycles, tap_state_t endstate);
  */
 void jtag_add_reset(int req_tlr_or_trst, int srst);
 
-
-/**
- * DEPRECATED! store such global state outside JTAG layer
- *
- * Function jtag_set_end_state
- *
- * Set a global variable to \a state if \a state != TAP_INVALID.
- *
- */
-void jtag_set_end_state(tap_state_t state);
-
-/**
- * DEPRECATED! store such global state outside JTAG layer
- * 
- * Function jtag_get_end_state
- *
- * Return the value of the global variable for end state
- */
-tap_state_t jtag_get_end_state(void);
-
 void jtag_add_sleep(uint32_t us);
 
 int jtag_add_tms_seq(unsigned nbits, const uint8_t *seq, enum tap_state t);
diff --git a/src/pld/virtex2.c b/src/pld/virtex2.c
index 93509de..b2833fa 100644
--- a/src/pld/virtex2.c
+++ b/src/pld/virtex2.c
@@ -141,7 +141,6 @@ static int virtex2_load(struct pld_device *pld_device, const char *filename)
 	if ((retval = xilinx_read_bit_file(&bit_file, filename)) != ERROR_OK)
 		return retval;
 
-	jtag_set_end_state(TAP_IDLE);
 	virtex2_set_instr(virtex2_info->tap, 0xb); /* JPROG_B */
 	jtag_execute_queue();
 	jtag_add_sleep(1000);
@@ -160,7 +159,6 @@ static int virtex2_load(struct pld_device *pld_device, const char *filename)
 
 	jtag_add_tlr();
 
-	jtag_set_end_state(TAP_IDLE);
 	virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
 	jtag_add_runtest(13, TAP_IDLE);
 	virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index d59465b..0d795fb 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -87,7 +87,6 @@ int adi_jtag_dp_scan(struct adiv5_dap *dap,
 	struct scan_field fields[2];
 	uint8_t out_addr_buf;
 
-	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
 
 	/* Scan out a read or write operation using some DP or AP register.
@@ -331,7 +330,6 @@ static int jtag_idcode_q_read(struct adiv5_dap *dap,
 	struct scan_field fields[1];
 
 	/* This is a standard JTAG operation -- no DAP tweakage */
-	jtag_set_end_state(TAP_IDLE);
 	retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL, TAP_IDLE);
 	if (retval != ERROR_OK)
 		return retval;
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 6e72c7a..0093360 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -54,7 +54,6 @@ static int arm720t_scan_cp15(struct target *target,
 
 	buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 
-	jtag_set_end_state(TAP_DRPAUSE);
 	if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 4c8d83d..8f63f3c 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -687,7 +687,6 @@ int arm7_9_execute_sys_speed(struct target *target)
 	struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
 	/* set RESTART instruction */
-	jtag_set_end_state(TAP_IDLE);
 	if (arm7_9->need_bypass_before_restart) {
 		arm7_9->need_bypass_before_restart = 0;
 		arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
@@ -740,7 +739,6 @@ int arm7_9_execute_fast_sys_speed(struct target *target)
 	struct reg *dbg_stat = &arm7_9->eice_cache->reg_list[EICE_DBG_STAT];
 
 	/* set RESTART instruction */
-	jtag_set_end_state(TAP_IDLE);
 	if (arm7_9->need_bypass_before_restart) {
 		arm7_9->need_bypass_before_restart = 0;
 		arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
@@ -1743,7 +1741,6 @@ int arm7_9_restart_core(struct target *target)
 	struct arm_jtag *jtag_info = &arm7_9->jtag_info;
 
 	/* set RESTART instruction */
-	jtag_set_end_state(TAP_IDLE);
 	if (arm7_9->need_bypass_before_restart) {
 		arm7_9->need_bypass_before_restart = 0;
 		arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index f145275..541adc8 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -56,8 +56,6 @@ static int arm7tdmi_examine_debug_reason(struct target *target)
 		uint8_t databus[4];
 		uint8_t breakpoint;
 
-		jtag_set_end_state(TAP_DRPAUSE);
-
 		fields[0].num_bits = 1;
 		fields[0].out_value = NULL;
 		fields[0].in_value = &breakpoint;
@@ -119,7 +117,6 @@ static __inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_
 static __inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info,
 		uint32_t out, uint32_t *deprecated, int breakpoint)
 {
-	jtag_set_end_state(TAP_DRPAUSE);
 	arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 
@@ -132,7 +129,6 @@ static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
 	int retval = ERROR_OK;
 	struct scan_field fields[2];
 
-	jtag_set_end_state(TAP_DRPAUSE);
 	if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
@@ -217,7 +213,6 @@ static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
 	int retval = ERROR_OK;
 	struct scan_field fields[2];
 
-	jtag_set_end_state(TAP_DRPAUSE);
 	if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 2e7c72d..4916de1 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -91,7 +91,6 @@ static int arm920t_read_cp15_physical(struct target *target,
 
 	jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
@@ -142,7 +141,6 @@ static int arm920t_write_cp15_physical(struct target *target,
 
 	buf_set_u32(value_buf, 0, 32, value);
 
-	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
@@ -192,7 +190,6 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 
 	jtag_info = &arm920t->arm7_9_common.jtag_info;
 
-	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index c45d984..ff18bae 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -63,7 +63,6 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
 
 	buf_set_u32(address_buf, 0, 14, address);
 
-	jtag_set_end_state(TAP_IDLE);
 	if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
 	{
 		return retval;
@@ -152,7 +151,6 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
 	buf_set_u32(address_buf, 0, 14, address);
 	buf_set_u32(value_buf, 0, 32, value);
 
-	jtag_set_end_state(TAP_IDLE);
 	if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
 	{
 		return retval;
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index c1e8058..b4207c8 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -84,7 +84,6 @@ static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
 	uint8_t reg_addr_buf = reg_addr & 0x3f;
 	uint8_t nr_w_buf = 0;
 
-	jtag_set_end_state(TAP_IDLE);
 	if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
 	{
 		return retval;
@@ -139,7 +138,6 @@ int arm966e_write_cp15(struct target *target, int reg_addr, uint32_t value)
 
 	buf_set_u32(value_buf, 0, 32, value);
 
-	jtag_set_end_state(TAP_IDLE);
 	if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
 	{
 		return retval;
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index 4f28599..744ee76 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -87,8 +87,6 @@ int arm9tdmi_examine_debug_reason(struct target *target)
 		uint8_t instructionbus[4];
 		uint8_t debug_reason;
 
-		jtag_set_end_state(TAP_DRPAUSE);
-
 		fields[0].num_bits = 32;
 		fields[0].out_value = NULL;
 		fields[0].in_value = databus;
@@ -154,7 +152,6 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr,
 	if (sysspeed)
 		buf_set_u32(&sysspeed_buf, 2, 1, 1);
 
-	jtag_set_end_state(TAP_DRPAUSE);
 	if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
@@ -213,7 +210,6 @@ int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
 	int retval = ERROR_OK;;
 	struct scan_field fields[3];
 
-	jtag_set_end_state(TAP_DRPAUSE);
 	if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
@@ -280,7 +276,6 @@ int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
 	int retval = ERROR_OK;
 	struct scan_field fields[3];
 
-	jtag_set_end_state(TAP_DRPAUSE);
 	if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 9272f66..59cd562 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -343,7 +343,6 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	uint8_t field1_out[1];
 	uint8_t field2_out[1];
 
-	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 
 	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
@@ -405,7 +404,6 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 	uint8_t field1_out[1];
 	uint8_t field2_out[1];
 
-	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
@@ -490,7 +488,6 @@ void embeddedice_write_reg(struct reg *reg, uint32_t value)
 
 	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
 
-	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 
 	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
@@ -523,7 +520,6 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 	uint8_t field1_out[1];
 	uint8_t field2_out[1];
 
-	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
@@ -576,7 +572,6 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 	else
 		return ERROR_INVALID_ARGUMENTS;
 
-	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
diff --git a/src/target/etb.c b/src/target/etb.c
index 96a6e0d..3280874 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -173,7 +173,6 @@ static int etb_read_ram(struct etb *etb, uint32_t *data, int num_frames)
 	struct scan_field fields[3];
 	int i;
 
-	jtag_set_end_state(TAP_IDLE);
 	etb_scann(etb, 0x0);
 	etb_set_instr(etb, 0xc);
 
@@ -227,7 +226,6 @@ static int etb_read_reg_w_check(struct reg *reg,
 
 	LOG_DEBUG("%i", (int)(etb_reg->addr));
 
-	jtag_set_end_state(TAP_IDLE);
 	etb_scann(etb_reg->etb, 0x0);
 	etb_set_instr(etb_reg->etb, 0xc);
 
@@ -310,7 +308,6 @@ static int etb_write_reg(struct reg *reg, uint32_t value)
 
 	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
 
-	jtag_set_end_state(TAP_IDLE);
 	etb_scann(etb_reg->etb, 0x0);
 	etb_set_instr(etb_reg->etb, 0xc);
 
diff --git a/src/target/etm.c b/src/target/etm.c
index 3c25f4e..3850ced 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -504,7 +504,6 @@ static int etm_read_reg_w_check(struct reg *reg,
 
 	LOG_DEBUG("%s (%u)", r->name, reg_addr);
 
-	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
 	arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 
@@ -587,7 +586,6 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
 
 	LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 
-	jtag_set_end_state(TAP_IDLE);
 	arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
 	arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 405c50c..efd3040 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -84,7 +84,6 @@ int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
 
 	buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 
-	jtag_set_end_state(TAP_DRPAUSE);
 	arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
 
 	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index d79c58d..37e1f09 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -56,8 +56,6 @@ int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
 {
 	struct scan_field field;
 
-	jtag_set_end_state(TAP_IDLE);
-
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
 
 	field.num_bits = 32;
@@ -78,8 +76,6 @@ int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
 {
 	struct scan_field field;
 
-	jtag_set_end_state(TAP_IDLE);
-
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
 
 	field.num_bits = 32;
@@ -209,7 +205,6 @@ int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step)
 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
 {
 	uint32_t ejtag_ctrl;
-	jtag_set_end_state(TAP_IDLE);
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 
 	/* set debug break bit */
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 5919f5b..5604b6a 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -112,7 +112,6 @@ int mips_m4k_poll(struct target *target)
 	uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl;
 
 	/* read ejtag control reg */
-	jtag_set_end_state(TAP_IDLE);
 	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -122,7 +121,6 @@ int mips_m4k_poll(struct target *target)
 	{
 		/* we have detected a reset, clear flag
 		 * otherwise ejtag will not work */
-		jtag_set_end_state(TAP_IDLE);
 		ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
@@ -135,7 +133,6 @@ int mips_m4k_poll(struct target *target)
 	{
 		if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 		{
-			jtag_set_end_state(TAP_IDLE);
 			mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 
 			target->state = TARGET_HALTED;
@@ -227,12 +224,10 @@ int mips_m4k_assert_reset(struct target *target)
 	if (target->reset_halt)
 	{
 		/* use hardware to catch reset */
-		jtag_set_end_state(TAP_IDLE);
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
 	}
 	else
 	{
-		jtag_set_end_state(TAP_IDLE);
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 	}
 
diff --git a/src/target/xscale.c b/src/target/xscale.c
index f22513a..f0e2311 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -191,7 +191,6 @@ static int xscale_read_dcsr(struct target *target)
 	uint8_t field2_check_value = 0x0;
 	uint8_t field2_check_mask = 0x1;
 
-	jtag_set_end_state(TAP_DRPAUSE);
 	xscale_jtag_set_instr(target->tap,
 		XSCALE_SELDCSR << xscale->xscale_variant,
 		TAP_DRPAUSE);
@@ -235,8 +234,6 @@ static int xscale_read_dcsr(struct target *target)
 	fields[1].out_value = xscale->reg_cache->reg_list[XSCALE_DCSR].value;
 	fields[1].in_value = NULL;
 
-	jtag_set_end_state(TAP_IDLE);
-
 	jtag_add_dr_scan(target->tap, 3, fields, TAP_DRPAUSE);
 
 	/* DANGER!!! this must be here. It will make sure that the arguments
@@ -286,7 +283,6 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words
 	fields[2].check_value = &field2_check_value;
 	fields[2].check_mask = &field2_check_mask;
 
-	jtag_set_end_state(TAP_IDLE);
 	xscale_jtag_set_instr(target->tap,
 		XSCALE_DBGTX << xscale->xscale_variant,
 		TAP_IDLE);
@@ -369,8 +365,6 @@ static int xscale_read_tx(struct target *target, int consume)
 	uint8_t field2_check_value = 0x0;
 	uint8_t field2_check_mask = 0x1;
 
-	jtag_set_end_state(TAP_IDLE);
-
 	xscale_jtag_set_instr(target->tap,
 		XSCALE_DBGTX << xscale->xscale_variant,
 		TAP_IDLE);
@@ -466,8 +460,6 @@ static int xscale_write_rx(struct target *target)
 	uint8_t field2_check_value = 0x0;
 	uint8_t field2_check_mask = 0x1;
 
-	jtag_set_end_state(TAP_IDLE);
-
 	xscale_jtag_set_instr(target->tap,
 		XSCALE_DBGRX << xscale->xscale_variant,
 		TAP_IDLE);
@@ -545,8 +537,6 @@ static int xscale_send(struct target *target, uint8_t *buffer, int count, int si
 	int retval;
 	int done_count = 0;
 
-	jtag_set_end_state(TAP_IDLE);
-
 	xscale_jtag_set_instr(target->tap,
 		XSCALE_DBGRX << xscale->xscale_variant,
 		TAP_IDLE);
@@ -629,7 +619,6 @@ static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_br
 	if (ext_dbg_brk != -1)
 		xscale->external_debug_break = ext_dbg_brk;
 
-	jtag_set_end_state(TAP_IDLE);
 	xscale_jtag_set_instr(target->tap,
 		XSCALE_SELDCSR << xscale->xscale_variant,
 		TAP_IDLE);
@@ -692,7 +681,6 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8]
 	LOG_DEBUG("loading miniIC at 0x%8.8" PRIx32 "", va);
 
 	/* LDIC into IR */
-	jtag_set_end_state(TAP_IDLE);
 	xscale_jtag_set_instr(target->tap,
 		XSCALE_LDIC << xscale->xscale_variant,
 		TAP_IDLE);
@@ -744,7 +732,6 @@ static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
 	uint8_t cmd;
 	struct scan_field fields[2];
 
-	jtag_set_end_state(TAP_IDLE);
 	xscale_jtag_set_instr(target->tap,
 		XSCALE_LDIC << xscale->xscale_variant,
 		TAP_IDLE);
@@ -1484,7 +1471,6 @@ static int xscale_assert_reset(struct target *target)
 	/* select DCSR instruction (set endstate to R-T-I to ensure we don't
 	 * end up in T-L-R, which would reset JTAG
 	 */
-	jtag_set_end_state(TAP_IDLE);
 	xscale_jtag_set_instr(target->tap,
 		XSCALE_SELDCSR << xscale->xscale_variant,
 		TAP_IDLE);

commit 15ff2aeca9b302419aed62fc3cc73dedacdd62cb
Author: Øyvind Harboe <oyv...@zy...>
Date:   Thu Mar 18 18:41:43 2010 +0100

    jtag: remove jtag_get_end_state() usage
    
    Code inspection indicated what constant end states to
    use.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 3ea23d4..d79c58d 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -46,7 +46,7 @@ int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
 		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
 		field.in_value = NULL;
 
-		jtag_add_ir_scan(tap, &field, jtag_get_end_state());
+		jtag_add_ir_scan(tap, &field, TAP_IDLE);
 	}
 
 	return ERROR_OK;
@@ -112,7 +112,7 @@ int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
 	buf_set_u32(field.out_value, 0, field.num_bits, *data);
 	field.in_value = r;
 
-	jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
+	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
@@ -143,7 +143,7 @@ int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
 	buf_set_u32(field.out_value, 0, field.num_bits, *data);
 	field.in_value = r;
 
-	jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
+	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 	{
@@ -339,7 +339,7 @@ int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t
 		fields[1].in_value = (uint8_t *) data;
 	}
 
-	jtag_add_dr_scan(tap, 2, fields, jtag_get_end_state());
+	jtag_add_dr_scan(tap, 2, fields, TAP_IDLE);
 	keep_alive();
 
 	return ERROR_OK;

commit 1911c8ec8d286840c6a0d6a57c423072766d3386
Author: Øyvind Harboe <oyv...@zy...>
Date:   Thu Mar 18 18:37:23 2010 +0100

    jtag: get rid of unecessary jtag_get_end_state()
    
    By code inspection.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/xscale.c b/src/target/xscale.c
index 55323ae..f22513a 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -158,7 +158,7 @@ static int xscale_verify_pointer(struct command_context *cmd_ctx,
 	return ERROR_OK;
 }
 
-static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr)
+static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
 {
 	if (tap == NULL)
 		return ERROR_FAIL;
@@ -173,7 +173,7 @@ static int xscale_jtag_set_instr(struct jtag_tap *tap, uint32_t new_instr)
 		field.out_value = scratch;
 		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
 
-		jtag_add_ir_scan(tap, &field, jtag_get_end_state());
+		jtag_add_ir_scan(tap, &field, end_state);
 	}
 
 	return ERROR_OK;
@@ -193,7 +193,8 @@ static int xscale_read_dcsr(struct target *target)
 
 	jtag_set_end_state(TAP_DRPAUSE);
 	xscale_jtag_set_instr(target->tap,
-		XSCALE_SELDCSR << xscale->xscale_variant);
+		XSCALE_SELDCSR << xscale->xscale_variant,
+		TAP_DRPAUSE);
 
 	buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 	buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
@@ -287,7 +288,8 @@ static int xscale_receive(struct target *target, uint32_t *buffer, int num_words
 
 	jtag_set_end_state(TAP_IDLE);
 	xscale_jtag_set_instr(target->tap,
-		XSCALE_DBGTX << xscale->xscale_variant);
+		XSCALE_DBGTX << xscale->xscale_variant,
+		TAP_IDLE);
 	jtag_add_runtest(1, TAP_IDLE); /* ensures that we're in the TAP_IDLE state as the above could be a no-op */
 
 	/* repeat until all words have been collected */
@@ -370,7 +372,8 @@ static int xscale_read_tx(struct target *target, int consume)
 	jtag_set_end_state(TAP_IDLE);
 
 	xscale_jtag_set_instr(target->tap,
-		XSCALE_DBGTX << xscale->xscale_variant);
+		XSCALE_DBGTX << xscale->xscale_variant,
+		TAP_IDLE);
 
 	path[0] = TAP_DRSELECT;
 	path[1] = TAP_DRCAPTURE;
@@ -466,7 +469,8 @@ static int xscale_write_rx(struct target *target)
 	jtag_set_end_state(TAP_IDLE);
 
 	xscale_jtag_set_instr(target->tap,
-		XSCALE_DBGRX << xscale->xscale_variant);
+		XSCALE_DBGRX << xscale->xscale_variant,
+		TAP_IDLE);
 
 	memset(&fields, 0, sizeof fields);
 
@@ -544,7 +548,8 @@ static int xscale_send(struct target *target, uint8_t *buffer, int count, int si
 	jtag_set_end_state(TAP_IDLE);
 
 	xscale_jtag_set_instr(target->tap,
-		XSCALE_DBGRX << xscale->xscale_variant);
+		XSCALE_DBGRX << xscale->xscale_variant,
+		TAP_IDLE);
 
 	bits[0]=3;
 	t[0]=0;
@@ -626,7 +631,8 @@ static int xscale_write_dcsr(struct target *target, int hold_rst, int ext_dbg_br
 
 	jtag_set_end_state(TAP_IDLE);
 	xscale_jtag_set_instr(target->tap,
-		XSCALE_SELDCSR << xscale->xscale_variant);
+		XSCALE_SELDCSR << xscale->xscale_variant,
+		TAP_IDLE);
 
 	buf_set_u32(&field0, 1, 1, xscale->hold_rst);
 	buf_set_u32(&field0, 2, 1, xscale->external_debug_break);
@@ -688,7 +694,8 @@ static int xscale_load_ic(struct target *target, uint32_t va, uint32_t buffer[8]
 	/* LDIC into IR */
 	jtag_set_end_state(TAP_IDLE);
 	xscale_jtag_set_instr(target->tap,
-		XSCALE_LDIC << xscale->xscale_variant);
+		XSCALE_LDIC << xscale->xscale_variant,
+		TAP_IDLE);
 
 	/* CMD is b011 to load a cacheline into the Mini ICache.
 	 * Loading into the main ICache is deprecated, and unused.
@@ -739,7 +746,8 @@ static int xscale_invalidate_ic_line(struct target *target, uint32_t va)
 
 	jtag_set_end_state(TAP_IDLE);
 	xscale_jtag_set_instr(target->tap,
-		XSCALE_LDIC << xscale->xscale_variant);
+		XSCALE_LDIC << xscale->xscale_variant,
+		TAP_IDLE);
 
 	/* CMD for invalidate IC line b000, bits [6:4] b000 */
 	buf_set_u32(&cmd, 0, 6, 0x0);
@@ -1478,7 +1486,8 @@ static int xscale_assert_reset(struct target *target)
 	 */
 	jtag_set_end_state(TAP_IDLE);
 	xscale_jtag_set_instr(target->tap,
-		XSCALE_SELDCSR << xscale->xscale_variant);
+		XSCALE_SELDCSR << xscale->xscale_variant,
+		TAP_IDLE);
 
 	/* set Hold reset, Halt mode and Trap Reset */
 	buf_set_u32(xscale->reg_cache->reg_list[XSCALE_DCSR].value, 30, 1, 0x1);
@@ -1486,7 +1495,7 @@ static int xscale_assert_reset(struct target *target)
 	xscale_write_dcsr(target, 1, 0);
 
 	/* select BYPASS, because having DCSR selected caused problems on the PXA27x */
-	xscale_jtag_set_instr(target->tap, ~0);
+	xscale_jtag_set_instr(target->tap, ~0, TAP_IDLE);
 	jtag_execute_queue();
 
 	/* assert reset */

commit 729845238228f577bc3d6369d83667e5e2df1aee
Author: Øyvind Harboe <oyv...@zy...>
Date:   Thu Mar 18 18:34:34 2010 +0100

    jtag: remove unecessary usage of jtag_get_end_state().
    
    By code inspection.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/etb.c b/src/target/etb.c
index 9971070..96a6e0d 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -60,7 +60,7 @@ static int etb_set_instr(struct etb *etb, uint32_t new_instr)
 
 		field.in_value = NULL;
 
-		jtag_add_ir_scan(tap, &field, jtag_get_end_state());
+		jtag_add_ir_scan(tap, &field, TAP_IDLE);
 
 		free(field.out_value);
 	}
@@ -82,7 +82,7 @@ static int etb_scann(struct etb *etb, uint32_t new_scan_chain)
 
 		/* select INTEST instruction */
 		etb_set_instr(etb, 0x2);
-		jtag_add_dr_scan(etb->tap, 1, &field, jtag_get_end_state());
+		jtag_add_dr_scan(etb->tap, 1, &field, TAP_IDLE);
 
 		etb->cur_scan_chain = new_scan_chain;
 

commit 8ce828dd382c907db4c6bd38e5b54996e50327fd
Author: Øyvind Harboe <oyv...@zy...>
Date:   Thu Mar 18 18:31:58 2010 +0100

    jtag: remove jtag_get_end_state()'s that should be unecessary
    
    By a bit of code inspection it seems like all of these
    instances of jtag_get_end_state() can be unambigously
    replaced by constants.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/jtag/zy1000/zy1000.c b/src/jtag/zy1000/zy1000.c
index 177d286..9b8b480 100644
--- a/src/jtag/zy1000/zy1000.c
+++ b/src/jtag/zy1000/zy1000.c
@@ -849,7 +849,7 @@ void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer,
 		}
 	} else
 	{
-		tap_state_t end_state = jtag_get_end_state();
+		tap_state_t end_state = TAP_IDLE;
 		tap_state_t shift_end_state;
 		if (post_bits == 0)
 			shift_end_state = end_state;
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 85c6816..4c8d83d 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -995,7 +995,7 @@ int arm7_9_assert_reset(struct target *target)
 			 * certain ARM9 cores (maybe more) - AT91SAM9260
 			 * and STR9
 			 */
-			jtag_add_runtest(1, jtag_get_end_state());
+			jtag_add_runtest(1, TAP_IDLE);
 		}
 		else
 		{
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 25151ff..f145275 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -104,9 +104,9 @@ static __inline int arm7tdmi_clock_out_inner(struct arm_jtag *jtag_info, uint32_
 			2,
 			arm7tdmi_num_bits,
 			values,
-			jtag_get_end_state());
+			TAP_DRPAUSE);
 
-	jtag_add_runtest(0, jtag_get_end_state());
+	jtag_add_runtest(0, TAP_DRPAUSE);
 
 	return ERROR_OK;
 }
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index b4b6f04..4f28599 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -186,7 +186,7 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr,
 		jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE);
 	}
 
-	jtag_add_runtest(0, jtag_get_end_state());
+	jtag_add_runtest(0, TAP_DRPAUSE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	{
diff --git a/src/target/embeddedice.h b/src/target/embeddedice.h
index cd48ce6..d278115 100644
--- a/src/target/embeddedice.h
+++ b/src/target/embeddedice.h
@@ -128,7 +128,7 @@ static __inline__ void embeddedice_write_reg_inner(struct jtag_tap *tap, int reg
 			2,
 			embeddedice_num_bits,
 			values,
-			jtag_get_end_state());
+			TAP_IDLE);
 }
 
 void embeddedice_write_dcc(struct jtag_tap *tap, int reg_addr, uint8_t *buffer, int little, int count);

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/core.c            |   20 ------------------
 src/jtag/jtag.h            |   20 ------------------
 src/jtag/zy1000/zy1000.c   |    2 +-
 src/pld/virtex2.c          |    2 -
 src/target/adi_v5_jtag.c   |    2 -
 src/target/arm720t.c       |    1 -
 src/target/arm7_9_common.c |    5 +---
 src/target/arm7tdmi.c      |    9 +------
 src/target/arm920t.c       |    3 --
 src/target/arm926ejs.c     |    2 -
 src/target/arm966e.c       |    2 -
 src/target/arm9tdmi.c      |    7 +-----
 src/target/embeddedice.c   |    5 ----
 src/target/embeddedice.h   |    2 +-
 src/target/etb.c           |    7 +----
 src/target/etm.c           |    2 -
 src/target/feroceon.c      |    1 -
 src/target/mips_ejtag.c    |   13 +++--------
 src/target/mips_m4k.c      |    5 ----
 src/target/xscale.c        |   47 +++++++++++++++++++------------------------
 20 files changed, 33 insertions(+), 124 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-113-g8d411d0

[David B. <dbr...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  8d411d0d249dda7ceb951c4f8c8a509f4fd1dfb0 (commit)
      from  fc9de56a251a7cfc2610cc1904a69fc7b9fd3011 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 8d411d0d249dda7ceb951c4f8c8a509f4fd1dfb0
Author: Mike Dunn <mik...@ne...>
Date:   Thu Mar 18 21:34:13 2010 -0700

    Fix underlying problem with xscale icache and dcache commands
    
    Fix problem with the xscale icache and dcache commands.  Both commands were
    enabling or disabling the mmu, not the caches
    
    I didn't look any further after my earlier patch fixed the trivial problem
    with command argument parsing.  Turns out the underlying code was broken.
    
    The resolution is straightforward when you look at the arguments to
    xscale_enable_mmu_caches() and xscale_disable_mmu_caches().  I finally
    took a deeper look after dumping the cp15 control register (XSCALE_CTRL)
    and seeing that the cache bits weren't changing, but the mmu bit was
    (which caused all manner of grief, as you can imagine).  This has been
    tested and works OK now.
    
     src/target/xscale.c |   17 +++++++++++------
     1 files changed, 11 insertions(+), 6 deletions(-)
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/xscale.c b/src/target/xscale.c
index f5aada5..55323ae 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -3204,14 +3204,19 @@ COMMAND_HANDLER(xscale_handle_idcache_command)
 	{
 		bool enable;
 		COMMAND_PARSE_ENABLE(CMD_ARGV[0], enable);
-		if (enable)
-			xscale_enable_mmu_caches(target, 1, 0, 0);
-		else
-			xscale_disable_mmu_caches(target, 1, 0, 0);
-		if (icache)
+		if (icache) {
 			xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled = enable;
-		else
+			if (enable)
+				xscale_enable_mmu_caches(target, 0, 0, 1);
+			else
+				xscale_disable_mmu_caches(target, 0, 0, 1);
+		} else {
 			xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled = enable;
+			if (enable)
+				xscale_enable_mmu_caches(target, 0, 1, 0);
+			else
+				xscale_disable_mmu_caches(target, 0, 1, 0);
+		}
 	}
 
 	bool enabled = icache ?

-----------------------------------------------------------------------

Summary of changes:
 src/target/xscale.c |   17 +++++++++++------
 1 files changed, 11 insertions(+), 6 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-111-gc09035e

[David B. <dbr...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  c09035ea2cb24dee300476a3502919d23d90d1f5 (commit)
       via  52a788e008ecf0ca6156f02de08a0f062d49a236 (commit)
      from  ec108ff59e23ec32abf1223488ad96dd26205a5b (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit c09035ea2cb24dee300476a3502919d23d90d1f5
Merge: 52a788e ec108ff
Author: David Brownell <dbr...@us...>
Date:   Thu Mar 18 12:11:58 2010 -0700

    Merge branch 'master' of ssh://dbr...@op.../gitroot/openocd/openocd


commit 52a788e008ecf0ca6156f02de08a0f062d49a236
Author: David Brownell <dbr...@us...>
Date:   Thu Mar 18 11:56:17 2010 -0700

    remove more duplication
    
    Not sure how the original "move code to adi_v5_swd.c" patch left
    some code in the "arm_adi_v5.c" file, but a recent patch was only
    a partial fix -- it didn't remove all the duplication.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 4afd50c..01c274b 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1572,28 +1572,3 @@ const struct command_registration dap_command_handlers[] = {
 };
 
 
-/*
- * This represents the bits which must be sent out on TMS/SWDIO to
- * switch a DAP implemented using an SWJ-DP module into SWD mode.
- * These bits are stored (and transmitted) LSB-first.
- *
- * See the DAP-Lite specification, section 2.2.5 for information
- * about making the debug link select SWD or JTAG.  (Similar info
- * is in a few other ARM documents.)
- */
-static const uint8_t jtag2swd_bitseq[] = {
-	/* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
-	 * putting both JTAG and SWD logic into reset state.
-	 */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	/* Switching sequence enables SWD and disables JTAG
-	 * NOTE: bits in the DP's IDCODE may expose the need for
-	 * an old/deprecated sequence (0xb6 0xed).
-	 */
-	0x9e, 0xe7,
-	/* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
-	 * putting both JTAG and SWD logic into reset state.
-	 */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-};
-

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c |   25 -------------------------
 1 files changed, 0 insertions(+), 25 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-112-gfc9de56

[David B. <dbr...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  fc9de56a251a7cfc2610cc1904a69fc7b9fd3011 (commit)
      from  c09035ea2cb24dee300476a3502919d23d90d1f5 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit fc9de56a251a7cfc2610cc1904a69fc7b9fd3011
Author: David Brownell <dbr...@us...>
Date:   Thu Mar 18 12:32:35 2010 -0700

    ADI_v5 - it's not always an "SWJ-DP"
    
    So don't use the name "swjdp" for all DAPs; rename to
    plain old "dap", which *is* always correct.
    
    Signed-off-by: David Brownell <dbr...@us...>

diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 41443ff..d59465b 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -66,7 +66,7 @@
  * will be needed to collect the data which was read; the "invalue" collects
  * the posted result of a preceding operation, not the current one.
  *
- * @param swjdp the DAP
+ * @param dap the DAP
  * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
  * @param reg_addr two significant bits; A[3:2]; for APACC access, the
  *	SELECT register has more addressing bits.
@@ -79,11 +79,11 @@
 /* FIXME don't export ... this is a temporary workaround for the
  * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
  */
-int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
+int adi_jtag_dp_scan(struct adiv5_dap *dap,
 		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 		uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
 {
-	struct arm_jtag *jtag_info = swjdp->jtag_info;
+	struct arm_jtag *jtag_info = dap->jtag_info;
 	struct scan_field fields[2];
 	uint8_t out_addr_buf;
 
@@ -117,8 +117,8 @@ int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
 	if ((instr == JTAG_DP_APACC)
 			&& ((reg_addr == AP_REG_DRW)
 				|| ((reg_addr & 0xF0) == AP_REG_BD0))
-			&& (swjdp->memaccess_tck != 0))
-		jtag_add_runtest(swjdp->memaccess_tck,
+			&& (dap->memaccess_tck != 0))
+		jtag_add_runtest(dap->memaccess_tck,
 				TAP_IDLE);
 
 	return jtag_get_error();
@@ -130,7 +130,7 @@ int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
  * conversions are performed (so the types of invalue and outvalue
  * must be different).
  */
-static int adi_jtag_dp_scan_u32(struct adiv5_dap *swjdp,
+static int adi_jtag_dp_scan_u32(struct adiv5_dap *dap,
 		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 		uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
 {
@@ -139,7 +139,7 @@ static int adi_jtag_dp_scan_u32(struct adiv5_dap *swjdp,
 
 	buf_set_u32(out_value_buf, 0, 32, outvalue);
 
-	retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
+	retval = adi_jtag_dp_scan(dap, instr, reg_addr, RnW,
 			out_value_buf, (uint8_t *)invalue, ack);
 	if (retval != ERROR_OK)
 		return retval;
@@ -161,14 +161,14 @@ static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
 			outvalue, NULL, NULL);
 }
 
-static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *swjdp,
+static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *dap,
 		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 		uint32_t outvalue, uint32_t *invalue)
 {
 	int retval;
 
 	/* Issue the read or write */
-	retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
+	retval = adi_jtag_dp_scan_u32(dap, instr, reg_addr,
 			RnW, outvalue, NULL, NULL);
 	if (retval != ERROR_OK)
 		return retval;
@@ -177,12 +177,12 @@ static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *swjdp,
 	 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
 	 */
 	if ((RnW == DPAP_READ) && (invalue != NULL))
-		retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
-				DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
+		retval = adi_jtag_dp_scan_u32(dap, JTAG_DP_DPACC,
+				DP_RDBUFF, DPAP_READ, 0, invalue, &dap->ack);
 	return retval;
 }
 
-static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
+static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
 {
 	int retval;
 	uint32_t ctrlstat;
@@ -191,7 +191,7 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
 
 #if 0
 	/* Danger!!!! BROKEN!!!! */
-	adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+	adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 			DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 	/* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
 	R956 introduced the check on return value here and now Michael Schwingen reports
@@ -209,21 +209,21 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
 	/* Post CTRL/STAT read; discard any previous posted read value
 	 * but collect its ACK status.
 	 */
-	adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+	adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 			DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
 		return retval;
 
-	swjdp->ack = swjdp->ack & 0x7;
+	dap->ack = dap->ack & 0x7;
 
 	/* common code path avoids calling timeval_ms() */
-	if (swjdp->ack != JTAG_ACK_OK_FAULT)
+	if (dap->ack != JTAG_ACK_OK_FAULT)
 	{
 		long long then = timeval_ms();
 
-		while (swjdp->ack != JTAG_ACK_OK_FAULT)
+		while (dap->ack != JTAG_ACK_OK_FAULT)
 		{
-			if (swjdp->ack == JTAG_ACK_WAIT)
+			if (dap->ack == JTAG_ACK_WAIT)
 			{
 				if ((timeval_ms()-then) > 1000)
 				{
@@ -240,15 +240,15 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
 			{
 				LOG_WARNING("Invalid ACK %#x "
 						"in JTAG-DP transaction",
-						swjdp->ack);
+						dap->ack);
 				return ERROR_JTAG_DEVICE_ERROR;
 			}
 
-			adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+			adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
-			if ((retval = dap_run(swjdp)) != ERROR_OK)
+			if ((retval = dap_run(dap)) != ERROR_OK)
 				return retval;
-			swjdp->ack = swjdp->ack & 0x7;
+			dap->ack = dap->ack & 0x7;
 		}
 	}
 
@@ -260,7 +260,7 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
 		LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
 		/* Check power to debug regions */
 		if ((ctrlstat & 0xf0000000) != 0xf0000000)
-			 ahbap_debugport_init(swjdp);
+			 ahbap_debugport_init(dap);
 		else
 		{
 			uint32_t mem_ap_csw, mem_ap_tar;
@@ -269,14 +269,14 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
 			 * MEM-AP access; but not if autoincrementing.
 			 * *Real* CSW and TAR values are always shown.
 			 */
-			if (swjdp->ap_tar_value != (uint32_t) -1)
+			if (dap->ap_tar_value != (uint32_t) -1)
 				LOG_DEBUG("MEM-AP Cached values: "
 					"ap_bank 0x%" PRIx32
 					", ap_csw 0x%" PRIx32
 					", ap_tar 0x%" PRIx32,
-					swjdp->ap_bank_value,
-					swjdp->ap_csw_value,
-					swjdp->ap_tar_value);
+					dap->ap_bank_value,
+					dap->ap_csw_value,
+					dap->ap_tar_value);
 
 			if (ctrlstat & SSTICKYORUN)
 				LOG_ERROR("JTAG-DP OVERRUN - check clock, "
@@ -286,34 +286,34 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
 				LOG_ERROR("JTAG-DP STICKY ERROR");
 
 			/* Clear Sticky Error Bits */
-			adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+			adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 					DP_CTRL_STAT, DPAP_WRITE,
-					swjdp->dp_ctrl_stat | SSTICKYORUN
+					dap->dp_ctrl_stat | SSTICKYORUN
 						| SSTICKYERR, NULL);
-			adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+			adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
 					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
-			if ((retval = dap_run(swjdp)) != ERROR_OK)
+			if ((retval = dap_run(dap)) != ERROR_OK)
 				return retval;
 
 			LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
 
-			retval = dap_queue_ap_read(swjdp,
+			retval = dap_queue_ap_read(dap,
 					AP_REG_CSW, &mem_ap_csw);
 			if (retval != ERROR_OK)
 				return retval;
 
-			retval = dap_queue_ap_read(swjdp,
+			retval = dap_queue_ap_read(dap,
 					AP_REG_TAR, &mem_ap_tar);
 			if (retval != ERROR_OK)
 				return retval;
 
-			if ((retval = dap_run(swjdp)) != ERROR_OK)
+			if ((retval = dap_run(dap)) != ERROR_OK)
 				return retval;
 			LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
 					PRIx32, mem_ap_csw, mem_ap_tar);
 
 		}
-		if ((retval = dap_run(swjdp)) != ERROR_OK)
+		if ((retval = dap_run(dap)) != ERROR_OK)
 			return retval;
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 01c274b..1b97e33 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -96,23 +96,23 @@ static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address
  * selection is implicitly used with future AP transactions.
  * This is a NOP if the specified AP is already selected.
  *
- * @param swjdp The DAP
+ * @param dap The DAP
  * @param apsel Number of the AP to (implicitly) use with further
  *	transactions.  This normally identifies a MEM-AP.
  */
-void dap_ap_select(struct adiv5_dap *swjdp,uint8_t apsel)
+void dap_ap_select(struct adiv5_dap *dap,uint8_t apsel)
 {
 	uint32_t select = (apsel << 24) & 0xFF000000;
 
-	if (select != swjdp->apsel)
+	if (select != dap->apsel)
 	{
-		swjdp->apsel = select;
+		dap->apsel = select;
 		/* Switching AP invalidates cached values.
 		 * Values MUST BE UPDATED BEFORE AP ACCESS.
 		 */
-		swjdp->ap_bank_value = -1;
-		swjdp->ap_csw_value = -1;
-		swjdp->ap_tar_value = -1;
+		dap->ap_bank_value = -1;
+		dap->ap_csw_value = -1;
+		dap->ap_tar_value = -1;
 	}
 }
 
@@ -127,7 +127,7 @@ void dap_ap_select(struct adiv5_dap *swjdp,uint8_t apsel)
  *
  * @todo Rename to reflect it being specifically a MEM-AP function.
  *
- * @param swjdp The DAP connected to the MEM-AP.
+ * @param dap The DAP connected to the MEM-AP.
  * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
  *	matches the cached value, the register is not changed.
  * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
@@ -135,37 +135,37 @@ void dap_ap_select(struct adiv5_dap *swjdp,uint8_t apsel)
  *
  * @return ERROR_OK if the transaction was properly queued, else a fault code.
  */
-int dap_setup_accessport(struct adiv5_dap *swjdp, uint32_t csw, uint32_t tar)
+int dap_setup_accessport(struct adiv5_dap *dap, uint32_t csw, uint32_t tar)
 {
 	int retval;
 
 	csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
-	if (csw != swjdp->ap_csw_value)
+	if (csw != dap->ap_csw_value)
 	{
 		/* LOG_DEBUG("DAP: Set CSW %x",csw); */
-		retval = dap_queue_ap_write(swjdp, AP_REG_CSW, csw);
+		retval = dap_queue_ap_write(dap, AP_REG_CSW, csw);
 		if (retval != ERROR_OK)
 			return retval;
-		swjdp->ap_csw_value = csw;
+		dap->ap_csw_value = csw;
 	}
-	if (tar != swjdp->ap_tar_value)
+	if (tar != dap->ap_tar_value)
 	{
 		/* LOG_DEBUG("DAP: Set TAR %x",tar); */
-		retval = dap_queue_ap_write(swjdp, AP_REG_TAR, tar);
+		retval = dap_queue_ap_write(dap, AP_REG_TAR, tar);
 		if (retval != ERROR_OK)
 			return retval;
-		swjdp->ap_tar_value = tar;
+		dap->ap_tar_value = tar;
 	}
 	/* Disable TAR cache when autoincrementing */
 	if (csw & CSW_ADDRINC_MASK)
-		swjdp->ap_tar_value = -1;
+		dap->ap_tar_value = -1;
 	return ERROR_OK;
 }
 
 /**
  * Asynchronous (queued) read of a word from memory or a system register.
  *
- * @param swjdp The DAP connected to the MEM-AP performing the read.
+ * @param dap The DAP connected to the MEM-AP performing the read.
  * @param address Address of the 32-bit word to read; it must be
  *	readable by the currently selected MEM-AP.
  * @param value points to where the word will be stored when the
@@ -173,7 +173,7 @@ int dap_setup_accessport(struct adiv5_dap *swjdp, uint32_t csw, uint32_t tar)
  *
  * @return ERROR_OK for success.  Otherwise a fault code.
  */
-int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address,
+int mem_ap_read_u32(struct adiv5_dap *dap, uint32_t address,
 		uint32_t *value)
 {
 	int retval;
@@ -181,19 +181,19 @@ int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address,
 	/* Use banked addressing (REG_BDx) to avoid some link traffic
 	 * (updating TAR) when reading several consecutive addresses.
 	 */
-	retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
+	retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 			address & 0xFFFFFFF0);
 	if (retval != ERROR_OK)
 		return retval;
 
-	return dap_queue_ap_read(swjdp, AP_REG_BD0 | (address & 0xC), value);
+	return dap_queue_ap_read(dap, AP_REG_BD0 | (address & 0xC), value);
 }
 
 /**
  * Synchronous read of a word from memory or a system register.
  * As a side effect, this flushes any queued transactions.
  *
- * @param swjdp The DAP connected to the MEM-AP performing the read.
+ * @param dap The DAP connected to the MEM-AP performing the read.
  * @param address Address of the 32-bit word to read; it must be
  *	readable by the currently selected MEM-AP.
  * @param value points to where the result will be stored.
@@ -201,22 +201,22 @@ int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address,
  * @return ERROR_OK for success; *value holds the result.
  * Otherwise a fault code.
  */
-int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
+int mem_ap_read_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 		uint32_t *value)
 {
 	int retval;
 
-	retval = mem_ap_read_u32(swjdp, address, value);
+	retval = mem_ap_read_u32(dap, address, value);
 	if (retval != ERROR_OK)
 		return retval;
 
-	return dap_run(swjdp);
+	return dap_run(dap);
 }
 
 /**
  * Asynchronous (queued) write of a word to memory or a system register.
  *
- * @param swjdp The DAP connected to the MEM-AP.
+ * @param dap The DAP connected to the MEM-AP.
  * @param address Address to be written; it must be writable by
  *	the currently selected MEM-AP.
  * @param value Word that will be written to the address when transaction
@@ -224,7 +224,7 @@ int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
  *
  * @return ERROR_OK for success.  Otherwise a fault code.
  */
-int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address,
+int mem_ap_write_u32(struct adiv5_dap *dap, uint32_t address,
 		uint32_t value)
 {
 	int retval;
@@ -232,12 +232,12 @@ int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address,
 	/* Use banked addressing (REG_BDx) to avoid some link traffic
 	 * (updating TAR) when writing several consecutive addresses.
 	 */
-	retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
+	retval = dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_OFF,
 			address & 0xFFFFFFF0);
 	if (retval != ERROR_OK)
 		return retval;
 
-	return dap_queue_ap_write(swjdp, AP_REG_BD0 | (address & 0xC),
+	return dap_queue_ap_write(dap, AP_REG_BD0 | (address & 0xC),
 			value);
 }
 
@@ -245,32 +245,32 @@ int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address,
  * Synchronous write of a word to memory or a system register.
  * As a side effect, this flushes any queued transactions.
  *
- * @param swjdp The DAP connected to the MEM-AP.
+ * @param dap The DAP connected to the MEM-AP.
  * @param address Address to be written; it must be writable by
  *	the currently selected MEM-AP.
  * @param value Word that will be written.
  *
  * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
  */
-int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
+int mem_ap_write_atomic_u32(struct adiv5_dap *dap, uint32_t address,
 		uint32_t value)
 {
-	int retval = mem_ap_write_u32(swjdp, address, value);
+	int retval = mem_ap_write_u32(dap, address, value);
 
 	if (retval != ERROR_OK)
 		return retval;
 
-	return dap_run(swjdp);
+	return dap_run(dap);
 }
 
 /*****************************************************************************
 *                                                                            *
-* mem_ap_write_buf(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address) *
+* mem_ap_write_buf(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address) *
 *                                                                            *
 * Write a buffer in target order (little endian)                             *
 *                                                                            *
 *****************************************************************************/
-int mem_ap_write_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u32(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 {
 	int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
 	uint32_t adr = address;
@@ -301,7 +301,7 @@ int mem_ap_write_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer, int count, ui
 	while (wcount > 0)
 	{
 		/* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
-		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+		blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 		if (wcount < blocksize)
 			blocksize = wcount;
 
@@ -309,17 +309,17 @@ int mem_ap_write_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer, int count, ui
 		if (blocksize == 0)
 			blocksize = 1;
 
-		dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+		dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
 
 		for (writecount = 0; writecount < blocksize; writecount++)
 		{
-			retval = dap_queue_ap_write(swjdp, AP_REG_DRW,
+			retval = dap_queue_ap_write(dap, AP_REG_DRW,
 				*(uint32_t *) (buffer + 4 * writecount));
 			if (retval != ERROR_OK)
 				break;
 		}
 
-		if (dap_run(swjdp) == ERROR_OK)
+		if (dap_run(dap) == ERROR_OK)
 		{
 			wcount = wcount - blocksize;
 			address = address + 4 * blocksize;
@@ -341,7 +341,7 @@ int mem_ap_write_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer, int count, ui
 	return retval;
 }
 
-static int mem_ap_write_buf_packed_u16(struct adiv5_dap *swjdp,
+static int mem_ap_write_buf_packed_u16(struct adiv5_dap *dap,
 		uint8_t *buffer, int count, uint32_t address)
 {
 	int retval = ERROR_OK;
@@ -354,7 +354,7 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *swjdp,
 		int nbytes;
 
 		/* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
-		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+		blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 
 		if (wcount < blocksize)
 			blocksize = wcount;
@@ -363,7 +363,7 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *swjdp,
 		if (blocksize == 0)
 			blocksize = 1;
 
-		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+		dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 		writecount = blocksize;
 
 		do
@@ -372,7 +372,7 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *swjdp,
 
 			if (nbytes < 4)
 			{
-				if (mem_ap_write_buf_u16(swjdp, buffer,
+				if (mem_ap_write_buf_u16(dap, buffer,
 						nbytes, address) != ERROR_OK)
 				{
 					LOG_WARNING("Block write error address "
@@ -396,12 +396,12 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *swjdp,
 				}
 
 				memcpy(&outvalue, buffer, sizeof(uint32_t));
-				retval = dap_queue_ap_write(swjdp,
+				retval = dap_queue_ap_write(dap,
 						AP_REG_DRW, outvalue);
 				if (retval != ERROR_OK)
 					break;
 
-				if (dap_run(swjdp) != ERROR_OK)
+				if (dap_run(dap) != ERROR_OK)
 				{
 					LOG_WARNING("Block write error address "
 						"0x%" PRIx32 ", count 0x%x",
@@ -421,24 +421,24 @@ static int mem_ap_write_buf_packed_u16(struct adiv5_dap *swjdp,
 	return retval;
 }
 
-int mem_ap_write_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u16(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 {
 	int retval = ERROR_OK;
 
 	if (count >= 4)
-		return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
+		return mem_ap_write_buf_packed_u16(dap, buffer, count, address);
 
 	while (count > 0)
 	{
-		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+		dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
 		uint16_t svalue;
 		memcpy(&svalue, buffer, sizeof(uint16_t));
 		uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
-		retval = dap_queue_ap_write(swjdp, AP_REG_DRW, outvalue);
+		retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 		if (retval != ERROR_OK)
 			break;
 
-		retval = dap_run(swjdp);
+		retval = dap_run(dap);
 		if (retval != ERROR_OK)
 			break;
 
@@ -450,7 +450,7 @@ int mem_ap_write_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer, int count, ui
 	return retval;
 }
 
-static int mem_ap_write_buf_packed_u8(struct adiv5_dap *swjdp,
+static int mem_ap_write_buf_packed_u8(struct adiv5_dap *dap,
 		uint8_t *buffer, int count, uint32_t address)
 {
 	int retval = ERROR_OK;
@@ -463,12 +463,12 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *swjdp,
 		int nbytes;
 
 		/* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
-		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+		blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 
 		if (wcount < blocksize)
 			blocksize = wcount;
 
-		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+		dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 		writecount = blocksize;
 
 		do
@@ -477,7 +477,7 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *swjdp,
 
 			if (nbytes < 4)
 			{
-				if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
+				if (mem_ap_write_buf_u8(dap, buffer, nbytes, address) != ERROR_OK)
 				{
 					LOG_WARNING("Block write error address "
 						"0x%" PRIx32 ", count 0x%x",
@@ -500,12 +500,12 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *swjdp,
 				}
 
 				memcpy(&outvalue, buffer, sizeof(uint32_t));
-				retval = dap_queue_ap_write(swjdp,
+				retval = dap_queue_ap_write(dap,
 						AP_REG_DRW, outvalue);
 				if (retval != ERROR_OK)
 					break;
 
-				if (dap_run(swjdp) != ERROR_OK)
+				if (dap_run(dap) != ERROR_OK)
 				{
 					LOG_WARNING("Block write error address "
 						"0x%" PRIx32 ", count 0x%x",
@@ -525,22 +525,22 @@ static int mem_ap_write_buf_packed_u8(struct adiv5_dap *swjdp,
 	return retval;
 }
 
-int mem_ap_write_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
+int mem_ap_write_buf_u8(struct adiv5_dap *dap, uint8_t *buffer, int count, uint32_t address)
 {
 	int retval = ERROR_OK;
 
 	if (count >= 4)
-		return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
+		return mem_ap_write_buf_packed_u8(dap, buffer, count, address);
 
 	while (count > 0)
 	{
-		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+		dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
 		uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
-		retval = dap_queue_ap_write(swjdp, AP_REG_DRW, outvalue);
+		retval = dap_queue_ap_write(dap, AP_REG_DRW, outvalue);
 		if (retval != ERROR_OK)
 			break;
 
-		retval = dap_run(swjdp);
+		retval = dap_run(dap);
 		if (retval != ERROR_OK)
 			break;
 
@@ -555,19 +555,19 @@ int mem_ap_write_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uin
 /* FIXME don't import ... this is a temporary workaround for the
  * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
  */
-extern int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
+extern int adi_jtag_dp_scan(struct adiv5_dap *dap,
 		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
 		uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
 
 /**
  * Synchronously read a block of 32-bit words into a buffer
- * @param swjdp The DAP connected to the MEM-AP.
+ * @param dap The DAP connected to the MEM-AP.
  * @param buffer where the words will be stored (in host byte order).
  * @param count How many words to read.
  * @param address Memory address from which to read words; all the
  *	words must be readable by the currently selected MEM-AP.
  */
-int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer,
+int mem_ap_read_buf_u32(struct adiv5_dap *dap, uint8_t *buffer,
 		int count, uint32_t address)
 {
 	int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
@@ -583,7 +583,7 @@ int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer,
 		 * TAR autoincrement size (at least 2^10).  Autoincrement
 		 * mode avoids an extra per-word roundtrip to update TAR.
 		 */
-		blocksize = max_tar_block_size(swjdp->tar_autoincr_block,
+		blocksize = max_tar_block_size(dap->tar_autoincr_block,
 				address);
 		if (wcount < blocksize)
 			blocksize = wcount;
@@ -592,7 +592,7 @@ int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer,
 		if (blocksize == 0)
 			blocksize = 1;
 
-		dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE,
+		dap_setup_accessport(dap, CSW_32BIT | CSW_ADDRINC_SINGLE,
 				address);
 
 		/* FIXME remove these three calls to adi_jtag_dp_scan(),
@@ -603,7 +603,7 @@ int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer,
 		 */
 
 		/* Scan out first read */
-		adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
+		adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 				DPAP_READ, 0, NULL, NULL);
 		for (readcount = 0; readcount < blocksize - 1; readcount++)
 		{
@@ -611,18 +611,18 @@ int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer,
 			 * previous one.  Assumes read is acked "OK/FAULT",
 			 * and CTRL_STAT says that meant "OK".
 			 */
-			adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
+			adi_jtag_dp_scan(dap, JTAG_DP_APACC, AP_REG_DRW,
 					DPAP_READ, 0, buffer + 4 * readcount,
-					&swjdp->ack);
+					&dap->ack);
 		}
 
 		/* Scan in last posted value; RDBUFF has no other effect,
 		 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
 		 */
-		adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
+		adi_jtag_dp_scan(dap, JTAG_DP_DPACC, DP_RDBUFF,
 				DPAP_READ, 0, buffer + 4 * readcount,
-				&swjdp->ack);
-		if (dap_run(swjdp) == ERROR_OK)
+				&dap->ack);
+		if (dap_run(dap) == ERROR_OK)
 		{
 			wcount = wcount - blocksize;
 			address += 4 * blocksize;
@@ -664,7 +664,7 @@ int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer,
 	return retval;
 }
 
-static int mem_ap_read_buf_packed_u16(struct adiv5_dap *swjdp,
+static int mem_ap_read_buf_packed_u16(struct adiv5_dap *dap,
 		uint8_t *buffer, int count, uint32_t address)
 {
 	uint32_t invalue;
@@ -678,11 +678,11 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *swjdp,
 		int nbytes;
 
 		/* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
-		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+		blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 		if (wcount < blocksize)
 			blocksize = wcount;
 
-		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+		dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_PACKED, address);
 
 		/* handle unaligned data at 4k boundary */
 		if (blocksize == 0)
@@ -691,8 +691,8 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *swjdp,
 
 		do
 		{
-			retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
-			if (dap_run(swjdp) != ERROR_OK)
+			retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+			if (dap_run(dap) != ERROR_OK)
 			{
 				LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 				/* REVISIT return the *actual* fault code */
@@ -718,29 +718,29 @@ static int mem_ap_read_buf_packed_u16(struct adiv5_dap *swjdp,
 
 /**
  * Synchronously read a block of 16-bit halfwords into a buffer
- * @param swjdp The DAP connected to the MEM-AP.
+ * @param dap The DAP connected to the MEM-AP.
  * @param buffer where the halfwords will be stored (in host byte order).
  * @param count How many halfwords to read.
  * @param address Memory address from which to read words; all the
  *	words must be readable by the currently selected MEM-AP.
  */
-int mem_ap_read_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer,
+int mem_ap_read_buf_u16(struct adiv5_dap *dap, uint8_t *buffer,
 		int count, uint32_t address)
 {
 	uint32_t invalue, i;
 	int retval = ERROR_OK;
 
 	if (count >= 4)
-		return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
+		return mem_ap_read_buf_packed_u16(dap, buffer, count, address);
 
 	while (count > 0)
 	{
-		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
-		retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
+		dap_setup_accessport(dap, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+		retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
 		if (retval != ERROR_OK)
 			break;
 
-		retval = dap_run(swjdp);
+		retval = dap_run(dap);
 		if (retval != ERROR_OK)
 			break;
 
@@ -772,7 +772,7 @@ int mem_ap_read_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer,
  * The solution is to arrange for a large out/in scan in this loop and
  * and convert data afterwards.
  */
-static int mem_ap_read_buf_packed_u8(struct adiv5_dap *swjdp,
+static int mem_ap_read_buf_packed_u8(struct adiv5_dap *dap,
 		uint8_t *buffer, int count, uint32_t address)
 {
 	uint32_t invalue;
@@ -786,18 +786,18 @@ static int mem_ap_read_buf_packed_u8(struct adiv5_dap *swjdp,
 		int nbytes;
 
 		/* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
-		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+		blocksize = max_tar_block_size(dap->tar_autoincr_block, address);
 
 		if (wcount < blocksize)
 			blocksize = wcount;
 
-		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+		dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_PACKED, address);
 		readcount = blocksize;
 
 		do
 		{
-			retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
-			if (dap_run(swjdp) != ERROR_OK)
+			retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+			if (dap_run(dap) != ERROR_OK)
 			{
 				LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
 				/* REVISIT return the *actual* fault code */
@@ -823,26 +823,26 @@ static int mem_ap_read_buf_packed_u8(struct adiv5_dap *swjdp,
 
 /**
  * Synchronously read a block of bytes into a buffer
- * @param swjdp The DAP connected to the MEM-AP.
+ * @param dap The DAP connected to the MEM-AP.
  * @param buffer where the bytes will be stored.
  * @param count How many bytes to read.
  * @param address Memory address from which to read data; all the
  *	data must be readable by the currently selected MEM-AP.
  */
-int mem_ap_read_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer,
+int mem_ap_read_buf_u8(struct adiv5_dap *dap, uint8_t *buffer,
 		int count, uint32_t address)
 {
 	uint32_t invalue;
 	int retval = ERROR_OK;
 
 	if (count >= 4)
-		return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
+		return mem_ap_read_buf_packed_u8(dap, buffer, count, address);
 
 	while (count > 0)
 	{
-		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
-		retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
-		retval = dap_run(swjdp);
+		dap_setup_accessport(dap, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+		retval = dap_queue_ap_read(dap, AP_REG_DRW, &invalue);
+		retval = dap_run(dap);
 		if (retval != ERROR_OK)
 			break;
 
@@ -870,14 +870,14 @@ extern const struct dap_ops jtag_dp_ops;
  * for further use, and arranges to use AP #0 for all AP operations
  * until dap_ap-select() changes that policy.
  *
- * @param swjdp The DAP being initialized.
+ * @param dap The DAP being initialized.
  *
  * @todo Rename this.  We also need an initialization scheme which account
  * for SWD transports not just JTAG; that will need to address differences
  * in layering.  (JTAG is useful without any debug target; but not SWD.)
  * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
  */
-int ahbap_debugport_init(struct adiv5_dap *swjdp)
+int ahbap_debugport_init(struct adiv5_dap *dap)
 {
 	uint32_t idreg, romaddr, dummy;
 	uint32_t ctrlstat;
@@ -887,7 +887,7 @@ int ahbap_debugport_init(struct adiv5_dap *swjdp)
 	LOG_DEBUG(" ");
 
 	/* JTAG-DP or SWJ-DP, in JTAG mode */
-	swjdp->ops = &jtag_dp_ops;
+	dap->ops = &jtag_dp_ops;
 
 	/* Default MEM-AP setup.
 	 *
@@ -895,42 +895,42 @@ int ahbap_debugport_init(struct adiv5_dap *swjdp)
 	 * Should we probe, or take a hint from the caller?
 	 * Presumably we can ignore the possibility of multiple APs.
 	 */
-	swjdp->apsel = !0;
-	dap_ap_select(swjdp, 0);
+	dap->apsel = !0;
+	dap_ap_select(dap, 0);
 
 	/* DP initialization */
 
-	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
+	retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, SSTICKYERR);
+	retval = dap_queue_dp_write(dap, DP_CTRL_STAT, SSTICKYERR);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
+	retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 	if (retval != ERROR_OK)
 		return retval;
 
-	swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
-	retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
+	dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
+	retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 	if (retval != ERROR_OK)
 		return retval;
 
-	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
+	retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 	if (retval != ERROR_OK)
 		return retval;
-	if ((retval = dap_run(swjdp)) != ERROR_OK)
+	if ((retval = dap_run(dap)) != ERROR_OK)
 		return retval;
 
 	/* Check that we have debug power domains activated */
 	while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
 	{
 		LOG_DEBUG("DAP: wait CDBGPWRUPACK");
-		retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
+		retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 		if (retval != ERROR_OK)
 			return retval;
-		if ((retval = dap_run(swjdp)) != ERROR_OK)
+		if ((retval = dap_run(dap)) != ERROR_OK)
 			return retval;
 		alive_sleep(10);
 	}
@@ -938,23 +938,23 @@ int ahbap_debugport_init(struct adiv5_dap *swjdp)
 	while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
 	{
 		LOG_DEBUG("DAP: wait CSYSPWRUPACK");
-		retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
+		retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &ctrlstat);
 		if (retval != ERROR_OK)
 			return retval;
-		if ((retval = dap_run(swjdp)) != ERROR_OK)
+		if ((retval = dap_run(dap)) != ERROR_OK)
 			return retval;
 		alive_sleep(10);
 	}
 
-	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
+	retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 	if (retval != ERROR_OK)
 		return retval;
 	/* With debug power on we can activate OVERRUN checking */
-	swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
-	retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
+	dap->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
+	retval = dap_queue_dp_write(dap, DP_CTRL_STAT, dap->dp_ctrl_stat);
 	if (retval != ERROR_OK)
 		return retval;
-	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
+	retval = dap_queue_dp_read(dap, DP_CTRL_STAT, &dummy);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -964,12 +964,12 @@ int ahbap_debugport_init(struct adiv5_dap *swjdp)
 	 * Should it?  If the ROM address is valid, is this the right
 	 * place to scan the table and do any topology detection?
 	 */
-	retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &idreg);
-	retval = dap_queue_ap_read(swjdp, AP_REG_BASE, &romaddr);
+	retval = dap_queue_ap_read(dap, AP_REG_IDR, &idreg);
+	retval = dap_queue_ap_read(dap, AP_REG_BASE, &romaddr);
 
 	LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
 		", Debug ROM Address 0x%" PRIx32,
-		swjdp->apsel, idreg, romaddr);
+		dap->apsel, idreg, romaddr);
 
 	return ERROR_OK;
 }
@@ -993,7 +993,7 @@ is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
 }
 
 static int dap_info_command(struct command_context *cmd_ctx,
-		struct adiv5_dap *swjdp, int apsel)
+		struct adiv5_dap *dap, int apsel)
 {
 	int retval;
 	uint32_t dbgbase, apid;
@@ -1005,11 +1005,11 @@ static int dap_info_command(struct command_context *cmd_ctx,
 	if (apsel >= 256)
 		return ERROR_INVALID_ARGUMENTS;
 
-	apselold = swjdp->apsel;
-	dap_ap_select(swjdp, apsel);
-	retval = dap_queue_ap_read(swjdp, AP_REG_BASE, &dbgbase);
-	retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &apid);
-	retval = dap_run(swjdp);
+	apselold = dap->apsel;
+	dap_ap_select(dap, apsel);
+	retval = dap_queue_ap_read(dap, AP_REG_BASE, &dbgbase);
+	retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
+	retval = dap_run(dap);
 	if (retval != ERROR_OK)
 		return retval;
 
@@ -1059,12 +1059,12 @@ static int dap_info_command(struct command_context *cmd_ctx,
 			command_print(cmd_ctx, "\tROM table in legacy format");
 
 		/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
-		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
-		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
-		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
-		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
-		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
-		retval = dap_run(swjdp);
+		mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
+		mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
+		mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
+		mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
+		mem_ap_read_u32(dap, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
+		retval = dap_run(dap);
 		if (retval != ERROR_OK)
 			return retval;
 
@@ -1084,7 +1084,7 @@ static int dap_info_command(struct command_context *cmd_ctx,
 		entry_offset = 0;
 		do
 		{
-			mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
+			mem_ap_read_atomic_u32(dap, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
 			command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
 			if (romentry&0x01)
 			{
@@ -1096,23 +1096,23 @@ static int dap_info_command(struct command_context *cmd_ctx,
 
 				component_base = (uint32_t)((dbgbase & 0xFFFFF000)
 						+ (int)(romentry & 0xFFFFF000));
-				mem_ap_read_atomic_u32(swjdp,
+				mem_ap_read_atomic_u32(dap,
 						(component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
-				mem_ap_read_atomic_u32(swjdp,
+				mem_ap_read_atomic_u32(dap,
 						(component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
-				mem_ap_read_atomic_u32(swjdp,
+				mem_ap_read_atomic_u32(dap,
 						(component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
-				mem_ap_read_atomic_u32(swjdp,
+				mem_ap_read_atomic_u32(dap,
 						(component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
-				mem_ap_read_atomic_u32(swjdp,
+				mem_ap_read_atomic_u32(dap,
 						(component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
-				mem_ap_read_atomic_u32(swjdp,
+				mem_ap_read_atomic_u32(dap,
 						(component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
-				mem_ap_read_atomic_u32(swjdp,
+				mem_ap_read_atomic_u32(dap,
 						(component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
-				mem_ap_read_atomic_u32(swjdp,
+				mem_ap_read_atomic_u32(dap,
 						(component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
-				mem_ap_read_atomic_u32(swjdp,
+				mem_ap_read_atomic_u32(dap,
 						(component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
 				component_start = component_base - 0x1000*(c_pid4 >> 4);
 
@@ -1130,7 +1130,7 @@ static int dap_info_command(struct command_context *cmd_ctx,
 					unsigned minor;
 					char *major = "Reserved", *subtype = "Reserved";
 
-					mem_ap_read_atomic_u32(swjdp,
+					mem_ap_read_atomic_u32(dap,
 							(component_base & 0xfffff000) | 0xfcc,
 							&devtype);
 					minor = (devtype >> 4) & 0x0f;
@@ -1346,7 +1346,7 @@ static int dap_info_command(struct command_context *cmd_ctx,
 	{
 		command_print(cmd_ctx, "\tNo ROM table present");
 	}
-	dap_ap_select(swjdp, apselold);
+	dap_ap_select(dap, apselold);
 
 	return ERROR_OK;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/adi_v5_jtag.c |   70 ++++++------
 src/target/arm_adi_v5.c  |  280 +++++++++++++++++++++++-----------------------
 2 files changed, 175 insertions(+), 175 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-109-gec108ff

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  ec108ff59e23ec32abf1223488ad96dd26205a5b (commit)
      from  46f92878da6c65eac275d1783e4e4019ec3c9af9 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit ec108ff59e23ec32abf1223488ad96dd26205a5b
Author: Øyvind Harboe <oyv...@zy...>
Date:   Thu Mar 18 12:07:41 2010 +0100

    jtag: retire one instance of jtag_get_end_state() usage
    
    Less global variables....
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index 091b77a..41443ff 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -88,7 +88,7 @@ int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
 	uint8_t out_addr_buf;
 
 	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, instr, NULL);
+	arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
 
 	/* Scan out a read or write operation using some DP or AP register.
 	 * For APACC access with any sticky error flag set, this is discarded.
@@ -330,10 +330,9 @@ static int jtag_idcode_q_read(struct adiv5_dap *dap,
 	int retval;
 	struct scan_field fields[1];
 
-	jtag_set_end_state(TAP_IDLE);
-
 	/* This is a standard JTAG operation -- no DAP tweakage */
-	retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL);
+	jtag_set_end_state(TAP_IDLE);
+	retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL, TAP_IDLE);
 	if (retval != ERROR_OK)
 		return retval;
 
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 71d4a01..6e72c7a 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -55,11 +55,11 @@ static int arm720t_scan_cp15(struct target *target,
 	buf_set_u32(out_buf, 0, 32, flip_u32(out, 32));
 
 	jtag_set_end_state(TAP_DRPAUSE);
-	if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
 	}
-	if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL)) != ERROR_OK)
+	if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
 	}
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index c6a08cf..85c6816 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -690,9 +690,9 @@ int arm7_9_execute_sys_speed(struct target *target)
 	jtag_set_end_state(TAP_IDLE);
 	if (arm7_9->need_bypass_before_restart) {
 		arm7_9->need_bypass_before_restart = 0;
-		arm_jtag_set_instr(jtag_info, 0xf, NULL);
+		arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
 	}
-	arm_jtag_set_instr(jtag_info, 0x4, NULL);
+	arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
 
 	long long then = timeval_ms();
 	int timeout;
@@ -743,9 +743,9 @@ int arm7_9_execute_fast_sys_speed(struct target *target)
 	jtag_set_end_state(TAP_IDLE);
 	if (arm7_9->need_bypass_before_restart) {
 		arm7_9->need_bypass_before_restart = 0;
-		arm_jtag_set_instr(jtag_info, 0xf, NULL);
+		arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
 	}
-	arm_jtag_set_instr(jtag_info, 0x4, NULL);
+	arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
 
 	if (!set)
 	{
@@ -1746,9 +1746,9 @@ int arm7_9_restart_core(struct target *target)
 	jtag_set_end_state(TAP_IDLE);
 	if (arm7_9->need_bypass_before_restart) {
 		arm7_9->need_bypass_before_restart = 0;
-		arm_jtag_set_instr(jtag_info, 0xf, NULL);
+		arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
 	}
-	arm_jtag_set_instr(jtag_info, 0x4, NULL);
+	arm_jtag_set_instr(jtag_info, 0x4, NULL, TAP_IDLE);
 
 	jtag_add_runtest(1, TAP_IDLE);
 	return jtag_execute_queue();
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index 2d6d68f..25151ff 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -66,11 +66,11 @@ static int arm7tdmi_examine_debug_reason(struct target *target)
 		fields[1].out_value = NULL;
 		fields[1].in_value = databus;
 
-		if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
+		if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
 		{
 			return retval;
 		}
-		arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
+		arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
 
 		jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE);
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -120,8 +120,8 @@ static __inline int arm7tdmi_clock_out(struct arm_jtag *jtag_info,
 		uint32_t out, uint32_t *deprecated, int breakpoint)
 {
 	jtag_set_end_state(TAP_DRPAUSE);
-	arm_jtag_scann(jtag_info, 0x1);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 
 	return arm7tdmi_clock_out_inner(jtag_info, out, breakpoint);
 }
@@ -133,11 +133,11 @@ static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
 	struct scan_field fields[2];
 
 	jtag_set_end_state(TAP_DRPAUSE);
-	if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
 	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 
 	fields[0].num_bits = 1;
 	fields[0].out_value = NULL;
@@ -218,11 +218,11 @@ static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
 	struct scan_field fields[2];
 
 	jtag_set_end_state(TAP_DRPAUSE);
-	if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
 	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 
 	fields[0].num_bits = 1;
 	fields[0].out_value = NULL;
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 68d3997..2e7c72d 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -92,8 +92,8 @@ static int arm920t_read_cp15_physical(struct target *target,
 	jtag_info = &arm920t->arm7_9_common.jtag_info;
 
 	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(jtag_info, 0xf);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	fields[0].num_bits = 1;
 	fields[0].out_value = &access_type_buf;
@@ -143,8 +143,8 @@ static int arm920t_write_cp15_physical(struct target *target,
 	buf_set_u32(value_buf, 0, 32, value);
 
 	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(jtag_info, 0xf);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	fields[0].num_bits = 1;
 	fields[0].out_value = &access_type_buf;
@@ -193,8 +193,8 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 	jtag_info = &arm920t->arm7_9_common.jtag_info;
 
 	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(jtag_info, 0xf);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_scann(jtag_info, 0xf, TAP_IDLE);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	buf_set_u32(cp15_opcode_buf, 0, 32, cp15_opcode);
 
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index ea951e5..c45d984 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -64,11 +64,11 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
 	buf_set_u32(address_buf, 0, 14, address);
 
 	jtag_set_end_state(TAP_IDLE);
-	if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
 	{
 		return retval;
 	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
@@ -121,7 +121,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
 	LOG_DEBUG("addr: 0x%x value: %8.8x", address, *value);
 #endif
 
-	arm_jtag_set_instr(jtag_info, 0xc, NULL);
+	arm_jtag_set_instr(jtag_info, 0xc, NULL, TAP_IDLE);
 
 	return ERROR_OK;
 }
@@ -153,11 +153,11 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
 	buf_set_u32(value_buf, 0, 32, value);
 
 	jtag_set_end_state(TAP_IDLE);
-	if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
 	{
 		return retval;
 	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = value_buf;
@@ -207,7 +207,7 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
 	LOG_DEBUG("addr: 0x%x value: %8.8x", address, value);
 #endif
 
-	arm_jtag_set_instr(jtag_info, 0xf, NULL);
+	arm_jtag_set_instr(jtag_info, 0xf, NULL, TAP_IDLE);
 
 	return ERROR_OK;
 }
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index 67678c1..c1e8058 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -85,11 +85,11 @@ static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
 	uint8_t nr_w_buf = 0;
 
 	jtag_set_end_state(TAP_IDLE);
-	if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
 	{
 		return retval;
 	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	fields[0].num_bits = 32;
 	/* REVISIT: table 7-2 shows that bits 31-31 need to be
@@ -140,11 +140,11 @@ int arm966e_write_cp15(struct target *target, int reg_addr, uint32_t value)
 	buf_set_u32(value_buf, 0, 32, value);
 
 	jtag_set_end_state(TAP_IDLE);
-	if ((retval = arm_jtag_scann(jtag_info, 0xf)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0xf, TAP_IDLE)) != ERROR_OK)
 	{
 		return retval;
 	}
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = value_buf;
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index f091188..b4b6f04 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -101,11 +101,11 @@ int arm9tdmi_examine_debug_reason(struct target *target)
 		fields[2].out_value = NULL;
 		fields[2].in_value = instructionbus;
 
-		if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1)) != ERROR_OK)
+		if ((retval = arm_jtag_scann(&arm7_9->jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
 		{
 			return retval;
 		}
-		arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
+		arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL, TAP_DRPAUSE);
 
 		jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, TAP_DRPAUSE);
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -155,12 +155,12 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr,
 		buf_set_u32(&sysspeed_buf, 2, 1, 1);
 
 	jtag_set_end_state(TAP_DRPAUSE);
-	if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
 	}
 
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = out_buf;
@@ -214,12 +214,12 @@ int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
 	struct scan_field fields[3];
 
 	jtag_set_end_state(TAP_DRPAUSE);
-	if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
 	}
 
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
@@ -281,12 +281,12 @@ int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
 	struct scan_field fields[3];
 
 	jtag_set_end_state(TAP_DRPAUSE);
-	if ((retval = arm_jtag_scann(jtag_info, 0x1)) != ERROR_OK)
+	if ((retval = arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE)) != ERROR_OK)
 	{
 		return retval;
 	}
 
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
diff --git a/src/target/arm_jtag.c b/src/target/arm_jtag.c
index 5ed104c..f8b5f4f 100644
--- a/src/target/arm_jtag.c
+++ b/src/target/arm_jtag.c
@@ -31,7 +31,7 @@
 #define _ARM_JTAG_SCAN_N_CHECK_
 #endif
 
-int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr,  void *no_verify_capture)
+int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr,  void *no_verify_capture, tap_state_t end_state)
 {
 	struct jtag_tap *tap;
 	tap = jtag_info->tap;
@@ -45,19 +45,19 @@ int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr,  vo
 
 	if (no_verify_capture == NULL)
 	{
-		jtag_add_ir_scan(tap, &field, jtag_get_end_state());
+		jtag_add_ir_scan(tap, &field, end_state);
 	} else
 	{
 		/* FIX!!!! this is a kludge!!! arm926ejs.c should reimplement this arm_jtag_set_instr to
 		 * have special verification code.
 		 */
-		jtag_add_ir_scan_noverify(tap, &field, jtag_get_end_state());
+		jtag_add_ir_scan_noverify(tap, &field, end_state);
 	}
 
 	return ERROR_OK;
 }
 
-int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain)
+int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain, tap_state_t end_state)
 {
 	int retval = ERROR_OK;
 	uint32_t values[1];
@@ -66,7 +66,7 @@ int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain)
 	values[0]=new_scan_chain;
 	num_bits[0]=jtag_info->scann_size;
 
-	if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->scann_instr, NULL)) != ERROR_OK)
+	if ((retval = arm_jtag_set_instr(jtag_info, jtag_info->scann_instr, NULL, end_state)) != ERROR_OK)
 	{
 		return retval;
 	}
@@ -75,7 +75,7 @@ int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain)
 			1,
 			num_bits,
 			values,
-			jtag_get_end_state());
+			end_state);
 
 	jtag_info->cur_scan_chain = new_scan_chain;
 
diff --git a/src/target/arm_jtag.h b/src/target/arm_jtag.h
index cf230b4..37c228f 100644
--- a/src/target/arm_jtag.h
+++ b/src/target/arm_jtag.h
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dom...@gm...                                                   *
  *                                                                         *
- *   Copyright (C) 2007,2008 Øyvind Harboe                                 *
+ *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
  *   oyv...@zy...                                               *
  *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
@@ -36,9 +36,11 @@ struct arm_jtag
 	uint32_t intest_instr;
 };
 
-int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr,  void *no_verify_capture);
+int arm_jtag_set_instr_inner(struct arm_jtag *jtag_info, uint32_t new_instr,
+		void *no_verify_capture,
+		tap_state_t end_state);
 static inline int arm_jtag_set_instr(struct arm_jtag *jtag_info,
-		uint32_t new_instr, void *no_verify_capture)
+		uint32_t new_instr, void *no_verify_capture, tap_state_t end_state)
 {
 	/* inline most common code path */
 	struct jtag_tap *tap;
@@ -48,7 +50,7 @@ static inline int arm_jtag_set_instr(struct arm_jtag *jtag_info,
 
 	if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr)
 	{
-		return arm_jtag_set_instr_inner(jtag_info, new_instr, no_verify_capture);
+		return arm_jtag_set_instr_inner(jtag_info, new_instr, no_verify_capture, end_state);
 	}
 
 	return ERROR_OK;
@@ -56,14 +58,14 @@ static inline int arm_jtag_set_instr(struct arm_jtag *jtag_info,
 }
 
 
-int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain);
-static inline int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain)
+int arm_jtag_scann_inner(struct arm_jtag *jtag_info, uint32_t new_scan_chain, tap_state_t end_state);
+static inline int arm_jtag_scann(struct arm_jtag *jtag_info, uint32_t new_scan_chain, tap_state_t end_state)
 {
 	/* inline most common code path */
 	int retval = ERROR_OK;
 	if (jtag_info->cur_scan_chain != new_scan_chain)
 	{
-		return arm_jtag_scann_inner(jtag_info, new_scan_chain);
+		return arm_jtag_scann_inner(jtag_info, new_scan_chain, end_state);
 	}
 
 	return retval;
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index fe266d6..9272f66 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -344,9 +344,9 @@ int embeddedice_read_reg_w_check(struct reg *reg,
 	uint8_t field2_out[1];
 
 	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(ice_reg->jtag_info, 0x2);
+	arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 
-	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	/* bits 31:0 -- data (ignored here) */
 	fields[0].num_bits = 32;
@@ -406,8 +406,8 @@ int embeddedice_receive(struct arm_jtag *jtag_info, uint32_t *data, uint32_t siz
 	uint8_t field2_out[1];
 
 	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(jtag_info, 0x2);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
@@ -491,9 +491,9 @@ void embeddedice_write_reg(struct reg *reg, uint32_t value)
 	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
 
 	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(ice_reg->jtag_info, 0x2);
+	arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 
-	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(ice_reg->jtag_info, ice_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	uint8_t reg_addr = ice_reg->addr & 0x1f;
 	embeddedice_write_reg_inner(ice_reg->jtag_info->tap, reg_addr, value);
@@ -524,8 +524,8 @@ int embeddedice_send(struct arm_jtag *jtag_info, uint32_t *data, uint32_t size)
 	uint8_t field2_out[1];
 
 	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(jtag_info, 0x2);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = field0_out;
@@ -577,8 +577,8 @@ int embeddedice_handshake(struct arm_jtag *jtag_info, int hsbit, uint32_t timeou
 		return ERROR_INVALID_ARGUMENTS;
 
 	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(jtag_info, 0x2);
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_scann(jtag_info, 0x2, TAP_IDLE);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = NULL;
diff --git a/src/target/etm.c b/src/target/etm.c
index a1c77b0..3c25f4e 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -505,8 +505,8 @@ static int etm_read_reg_w_check(struct reg *reg,
 	LOG_DEBUG("%s (%u)", r->name, reg_addr);
 
 	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(etm_reg->jtag_info, 0x6);
-	arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
+	arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
+	arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = reg->value;
@@ -588,8 +588,8 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
 	LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
 
 	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_scann(etm_reg->jtag_info, 0x6);
-	arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL);
+	arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
+	arm_jtag_set_instr(etm_reg->jtag_info, etm_reg->jtag_info->intest_instr, NULL, TAP_IDLE);
 
 	fields[0].num_bits = 32;
 	uint8_t tmp1[4];
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 22ddb55..405c50c 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -85,9 +85,9 @@ int feroceon_dummy_clock_out(struct arm_jtag *jtag_info, uint32_t instr)
 	buf_set_u32(instr_buf, 0, 32, flip_u32(instr, 32));
 
 	jtag_set_end_state(TAP_DRPAUSE);
-	arm_jtag_scann(jtag_info, 0x1);
+	arm_jtag_scann(jtag_info, 0x1, TAP_DRPAUSE);
 
-	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL);
+	arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, NULL, TAP_DRPAUSE);
 
 	fields[0].num_bits = 32;
 	fields[0].out_value = out_buf;

-----------------------------------------------------------------------

Summary of changes:
 src/target/adi_v5_jtag.c   |    7 +++----
 src/target/arm720t.c       |    4 ++--
 src/target/arm7_9_common.c |   12 ++++++------
 src/target/arm7tdmi.c      |   16 ++++++++--------
 src/target/arm920t.c       |   12 ++++++------
 src/target/arm926ejs.c     |   12 ++++++------
 src/target/arm966e.c       |    8 ++++----
 src/target/arm9tdmi.c      |   16 ++++++++--------
 src/target/arm_jtag.c      |   12 ++++++------
 src/target/arm_jtag.h      |   16 +++++++++-------
 src/target/embeddedice.c   |   20 ++++++++++----------
 src/target/etm.c           |    8 ++++----
 src/target/feroceon.c      |    4 ++--
 13 files changed, 74 insertions(+), 73 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-107-gd37ed90

[Spencer O. <nt...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  d37ed9094a62ec144b9d9fdc214d8c7723caadec (commit)
       via  ae1c64706a6fa421b60884e23561f39016950f54 (commit)
       via  b48a94f05da3a887f1978da01db77b79513d4aa9 (commit)
      from  36df240cea04990e8c18aa0b90bd63374f22dbd3 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit d37ed9094a62ec144b9d9fdc214d8c7723caadec
Author: Spencer Oliver <nt...@us...>
Date:   Thu Mar 18 09:18:53 2010 +0000

    DOCS: update flash bank examples
    
     - include the $_FLASHNAME in all flash bank examples.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index da2782b..83a6369 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4180,8 +4180,8 @@ To configure two adjacent banks of 16 MBytes each, both sixteen bits (two bytes)
 wide on a sixteen bit bus:
 
 @example
-flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
-flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
+flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
+flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
 @end example
 
 To configure one bank of 32 MBytes
@@ -4189,7 +4189,7 @@ built from two sixteen bit (two byte) wide parts wired in parallel
 to create a thirty-two bit (four byte) bus with doubled throughput:
 
 @example
-flash bank cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
+flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
 @end example
 
 @c "cfi part_id" disabled
@@ -4205,7 +4205,7 @@ The setup command only requires the @var{target} argument
 since all devices in this family have the same memory layout.
 
 @example
-flash bank aduc702x 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME aduc702x 0 0 0 0 $_TARGETNAME
 @end example
 @end deffn
 
@@ -4226,9 +4226,9 @@ the following fixed locations:
 
 @example
 # Flash bank 0 - all chips
-flash bank at91sam3 0x00080000 0 1 1 $_TARGETNAME
+flash bank $_FLASHNAME at91sam3 0x00080000 0 1 1 $_TARGETNAME
 # Flash bank 1 - only 256K chips
-flash bank at91sam3 0x00100000 0 1 1 $_TARGETNAME
+flash bank $_FLASHNAME at91sam3 0x00100000 0 1 1 $_TARGETNAME
 @end example
 
 Internally, the AT91SAM3 flash memory is organized as follows.
@@ -4280,7 +4280,7 @@ recognizes a number of these chips using the chip identification
 register, and autoconfigures itself.
 
 @example
-flash bank at91sam7 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME at91sam7 0 0 0 0 $_TARGETNAME
 @end example
 
 For chips which are not recognized by the controller driver, you must
@@ -4367,7 +4367,7 @@ with most tool chains @command{verify_image} will fail.
 LPC flashes don't require the chip and bus width to be specified.
 
 @example
-flash bank lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
+flash bank $_FLASHNAME lpc2000 0x0 0x7d000 0 0 $_TARGETNAME \
       lpc2000_v2 14765 calc_checksum
 @end example
 
@@ -4385,7 +4385,7 @@ the programming clock rate in Hz.
 LPC flashes don't require the chip and bus width to be specified.
 
 @example
-flash bank lpc288x 0 0 0 0 $_TARGETNAME 12000000
+flash bank $_FLASHNAME lpc288x 0 0 0 0 $_TARGETNAME 12000000
 @end example
 @end deffn
 
@@ -4418,7 +4418,7 @@ and not by the standard @code{flash protect} command.
 
 Example for a 125 MHz clock frequency:
 @example
-flash bank lpc2900 0 0 0 0 $_TARGETNAME 125000
+flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME 125000
 @end example
 
 Some @code{lpc2900}-specific commands are defined. In the following command list,
@@ -4516,7 +4516,7 @@ lpc2900 secure_jtag 0
 @emph{No idea what this is, other than using some arm7/arm9 core.}
 
 @example
-flash bank ocl 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME ocl 0 0 0 0 $_TARGETNAME
 @end example
 @end deffn
 
@@ -4525,8 +4525,8 @@ The PIC32MX microcontrollers are based on the MIPS 4K cores,
 and integrate flash memory.
 
 @example
-flash bank pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
-flash bank pix32mx 0x1d000000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME pix32mx 0x1d000000 0 0 0 $_TARGETNAME
 @end example
 
 @comment numerous *disabled* commands are defined:
@@ -4555,7 +4555,7 @@ That seems pointless since the same effect can be had using the
 standard @command{flash erase_address} command.}
 
 @example
-flash bank stellaris 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stellaris 0 0 0 0 $_TARGETNAME
 @end example
 @end deffn
 
@@ -4581,7 +4581,7 @@ The driver automatically recognizes a number of these chips using
 the chip identification register, and autoconfigures itself.
 
 @example
-flash bank stm32x 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stm32x 0 0 0 0 $_TARGETNAME
 @end example
 
 Some stm32x-specific commands
@@ -4619,7 +4619,7 @@ The @var{str7x} driver defines one mandatory parameter, @var{variant},
 which is either @code{STR71x}, @code{STR73x} or @code{STR75x}.
 
 @example
-flash bank str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
+flash bank $_FLASHNAME str7x 0x40000000 0x00040000 0 0 $_TARGETNAME STR71x
 @end example
 
 @deffn Command {str7x disable_jtag} bank
@@ -4635,7 +4635,7 @@ The str9 needs the flash controller to be configured using
 the @command{str9x flash_config} command prior to Flash programming.
 
 @example
-flash bank str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
+flash bank $_FLASHNAME str9x 0x40000000 0x00040000 0 0 $_TARGETNAME
 str9x flash_config 0 4 2 0 0x80000
 @end example
 
@@ -4785,13 +4785,13 @@ Currently, the mflash driver supports s3c2440 and pxa270.
 Example for s3c2440 mflash where @var{RST pin} is GPIO B1:
 
 @example
-mflash bank s3c2440 0x10000000 1b 0
+mflash bank $_FLASHNAME s3c2440 0x10000000 1b 0
 @end example
 
 Example for pxa270 mflash where @var{RST pin} is GPIO 43:
 
 @example
-mflash bank pxa270 0x08000000 43 0
+mflash bank $_FLASHNAME pxa270 0x08000000 43 0
 @end example
 @end deffn
 
@@ -7406,8 +7406,8 @@ has closed the connection to OpenOCD. This might be a GDB issue.
 
 @item @b{LPC2000 Flash} In the configuration file in the section where flash device configurations
 are described, there is a parameter for specifying the clock frequency
-for LPC2000 internal flash devices (e.g.  @option{flash bank lpc2000
-0x0 0x40000 0 0 0 lpc2000_v1 14746 calc_checksum}), which must be
+for LPC2000 internal flash devices (e.g.  @option{flash bank $_FLASHNAME lpc2000
+0x0 0x40000 0 0 $_TARGETNAME lpc2000_v1 14746 calc_checksum}), which must be
 specified in kilohertz. However, I do have a quartz crystal of a
 frequency that contains fractions of kilohertz (e.g. 14,745,600 Hz,
 i.e. 14,745.600 kHz).  Is it possible to specify real numbers for the

commit ae1c64706a6fa421b60884e23561f39016950f54
Author: Spencer Oliver <nt...@us...>
Date:   Thu Mar 18 09:35:45 2010 +0000

    PIC32MX: add unlock cmd
    
    'unlock' performs a full unlock/erase of the device, removing any
    code protection.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 98fc690..da2782b 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -4523,10 +4523,10 @@ flash bank ocl 0 0 0 0 $_TARGETNAME
 @deffn {Flash Driver} pic32mx
 The PIC32MX microcontrollers are based on the MIPS 4K cores,
 and integrate flash memory.
-@emph{The current implementation is incomplete.}
 
 @example
-flash bank pix32mx 0 0 0 0 $_TARGETNAME
+flash bank pix32mx 0x1fc00000 0 0 0 $_TARGETNAME
+flash bank pix32mx 0x1d000000 0 0 0 $_TARGETNAME
 @end example
 
 @comment numerous *disabled* commands are defined:
@@ -4538,6 +4538,10 @@ Some pic32mx-specific commands are defined:
 Programs the specified 32-bit @var{value} at the given @var{address}
 in the specified chip @var{bank}.
 @end deffn
+@deffn Command {pic32mx unlock} bank
+Unlock and erase specified chip @var{bank}.
+This will remove any Code Protection.
+@end deffn
 @end deffn
 
 @deffn {Flash Driver} stellaris
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index c46264c..36744e6 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -31,6 +31,7 @@
 #include "pic32mx.h"
 #include <target/algorithm.h>
 #include <target/mips32.h>
+#include <target/mips_m4k.h>
 
 static const struct pic32mx_devs_s {
 	uint8_t	devid;
@@ -664,6 +665,73 @@ COMMAND_HANDLER(pic32mx_handle_pgm_word_command)
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(pic32mx_handle_unlock_command)
+{
+	uint32_t mchip_cmd;
+	struct target *target = NULL;
+	struct mips_m4k_common *mips_m4k;
+	struct mips_ejtag *ejtag_info;
+	int timeout = 10;
+
+	if (CMD_ARGC < 1)
+	{
+		command_print(CMD_CTX, "pic32mx unlock <bank>");
+		return ERROR_OK;
+	}
+
+	struct flash_bank *bank;
+	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+	if (ERROR_OK != retval)
+		return retval;
+
+	target = bank->target;
+	mips_m4k = target_to_m4k(target);
+	ejtag_info = &mips_m4k->mips32.ejtag_info;
+
+	/* we have to use the MTAP to perform a full erase */
+	mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
+	mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
+
+	/* first check status of device */
+	mchip_cmd = MCHP_STATUS;
+	mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+	if (mchip_cmd & (1 << 7))
+	{
+		/* device is not locked */
+		command_print(CMD_CTX, "pic32mx is already unlocked, erasing anyway");
+	}
+
+	/* unlock/erase device */
+	mchip_cmd = MCHP_ASERT_RST;
+	mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+
+	mchip_cmd = MCHP_ERASE;
+	mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+
+	do {
+		mchip_cmd = MCHP_STATUS;
+		mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+		if (timeout-- == 0)
+		{
+			LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx32 "", mchip_cmd);
+			break;
+		}
+		alive_sleep(1);
+	} while ((mchip_cmd & (1 << 2)) || (!(mchip_cmd & (1 << 3))));
+
+	mchip_cmd = MCHP_DE_ASSERT_RST;
+	mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+
+	/* select ejtag tap */
+	mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
+
+	command_print(CMD_CTX, "pic32mx unlocked.\n"
+			"INFO: a reset or power cycle is required "
+			"for the new settings to take effect.");
+
+	return ERROR_OK;
+}
+
 static const struct command_registration pic32mx_exec_command_handlers[] = {
 	{
 		.name = "pgm_word",
@@ -671,6 +739,13 @@ static const struct command_registration pic32mx_exec_command_handlers[] = {
 		.mode = COMMAND_EXEC,
 		.help = "program a word",
 	},
+	{
+		.name = "unlock",
+		.handler = pic32mx_handle_unlock_command,
+		.mode = COMMAND_EXEC,
+		.usage = "[bank_id]",
+		.help = "Unlock/Erase entire device.",
+	},
 	COMMAND_REGISTRATION_DONE
 };
 
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index 164edd0..f302a70 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -48,6 +48,8 @@
 /* microchip specific cmds */
 #define MCHP_ASERT_RST			0xd1
 #define MCHP_DE_ASSERT_RST		0xd0
+#define MCHP_ERASE				0xfc
+#define MCHP_STATUS				0x00
 
 /* ejtag control register bits ECR */
 #define EJTAG_CTRL_TOF			(1 << 1)

commit b48a94f05da3a887f1978da01db77b79513d4aa9
Author: Spencer Oliver <nt...@us...>
Date:   Wed Mar 17 17:24:22 2010 +0000

    MIPS: remove unused arg from mips_ejtag_set_instr
    
    This arg was never used and was just taken from the arm jtag code.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/src/target/mips32_dmaacc.c b/src/target/mips32_dmaacc.c
index aa36d2c..7d3c2da 100644
--- a/src/target/mips32_dmaacc.c
+++ b/src/target/mips32_dmaacc.c
@@ -49,11 +49,11 @@ begin_ejtag_dma_read:
 
 	/* Setup Address */
 	v = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Initiate DMA Read & set DSTRT */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -64,11 +64,11 @@ begin_ejtag_dma_read:
 	} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	/* Read Data */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ejtag_info, data);
 
 	/* Clear DMA & Check DERR */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
@@ -95,11 +95,11 @@ begin_ejtag_dma_read_h:
 
 	/* Setup Address */
 	v = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Initiate DMA Read & set DSTRT */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -110,11 +110,11 @@ begin_ejtag_dma_read_h:
 	} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	/* Read Data */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Clear DMA & Check DERR */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
@@ -147,11 +147,11 @@ begin_ejtag_dma_read_b:
 
 	/* Setup Address */
 	v = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Initiate DMA Read & set DSTRT */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DRWN | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -162,11 +162,11 @@ begin_ejtag_dma_read_b:
 	} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	/* Read Data */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Clear DMA & Check DERR */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
@@ -209,16 +209,16 @@ begin_ejtag_dma_write:
 
 	/* Setup Address */
 	v = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Setup Data */
 	v = data;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Initiate DMA Write & set DSTRT */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_WORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -229,7 +229,7 @@ begin_ejtag_dma_write:
 	} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	/* Clear DMA & Check DERR */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
@@ -260,16 +260,16 @@ begin_ejtag_dma_write_h:
 
 	/* Setup Address */
 	v = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Setup Data */
 	v = data;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Initiate DMA Write & set DSTRT */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_HALFWORD | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -280,7 +280,7 @@ begin_ejtag_dma_write_h:
 	} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	/* Clear DMA & Check DERR */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl  & EJTAG_CTRL_DERR)
@@ -312,16 +312,16 @@ begin_ejtag_dma_write_b:
 
 	/*  Setup Address*/
 	v = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Setup Data */
 	v = data;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ejtag_info, &v);
 
 	/* Initiate DMA Write & set DSTRT */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = EJTAG_CTRL_DMAACC | EJTAG_CTRL_DMA_BYTE | EJTAG_CTRL_DSTRT | ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
@@ -332,7 +332,7 @@ begin_ejtag_dma_write_b:
 	} while (ejtag_ctrl & EJTAG_CTRL_DSTRT);
 
 	/* Clear DMA & Check DERR */
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	ejtag_ctrl = ejtag_info->ejtag_ctrl;
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	if (ejtag_ctrl & EJTAG_CTRL_DERR)
diff --git a/src/target/mips32_pracc.c b/src/target/mips32_pracc.c
index bcba0f1..19ba886 100644
--- a/src/target/mips32_pracc.c
+++ b/src/target/mips32_pracc.c
@@ -96,7 +96,7 @@ static int wait_for_pracc_rw(struct mips_ejtag *ejtag_info, uint32_t *ctrl)
 
 	while (1)
 	{
-		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 		ejtag_ctrl = ejtag_info->ejtag_ctrl;
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 		if (ejtag_ctrl & EJTAG_CTRL_PRACC)
@@ -149,12 +149,12 @@ static int mips32_pracc_exec_read(struct mips32_pracc_context *ctx, uint32_t add
 	}
 
 	/* Send the data out */
-	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ctx->ejtag_info, &data);
 
 	/* Clear the access pending bit (let the processor eat!) */
 	ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
-	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL);
 	mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
 
 	jtag_add_clocks(5);
@@ -169,12 +169,12 @@ static int mips32_pracc_exec_write(struct mips32_pracc_context *ctx, uint32_t ad
 	int offset;
 	struct mips_ejtag *ejtag_info = ctx->ejtag_info;
 
-	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA, NULL);
+	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_DATA);
 	mips_ejtag_drscan_32(ctx->ejtag_info, &data);
 
 	/* Clear access pending bit */
 	ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
-	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ctx->ejtag_info, EJTAG_INST_CONTROL);
 	mips_ejtag_drscan_32(ctx->ejtag_info, &ejtag_ctrl);
 
 	jtag_add_clocks(5);
@@ -230,7 +230,7 @@ int mips32_pracc_exec(struct mips_ejtag *ejtag_info, int code_len, const uint32_
 			return retval;
 
 		address = data = 0;
-		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 		mips_ejtag_drscan_32(ejtag_info, &address);
 
 		/* Check for read or write */
@@ -979,12 +979,12 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
 		if ((retval = wait_for_pracc_rw(ejtag_info, &ejtag_ctrl)) != ERROR_OK)
 			return retval;
 
-		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA, NULL);
+		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_DATA);
 		mips_ejtag_drscan_32(ejtag_info, &jmp_code[i]);
 
 		/* Clear the access pending bit (let the processor eat!) */
 		ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_PRACC;
-		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 	}
 
@@ -993,7 +993,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
 
 	/* next fetch to dmseg should be in FASTDATA_AREA, check */
 	address = 0;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &address);
 
 	if (address != MIPS32_PRACC_FASTDATA_AREA)
@@ -1001,12 +1001,12 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
 
 	/* Send the load start address */
 	val = addr;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
 	mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
 
 	/* Send the load end address */
 	val = addr + (count - 1) * 4;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_FASTDATA);
 	mips_ejtag_fastdata_scan(ejtag_info, 1, &val);
 
 	for (i = 0; i < count; i++)
@@ -1026,7 +1026,7 @@ int mips32_pracc_fastdata_xfer(struct mips_ejtag *ejtag_info, struct working_are
 		return retval;
 
 	address = 0;
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_ADDRESS);
 	mips_ejtag_drscan_32(ejtag_info, &address);
 
 	if (address != MIPS32_PRACC_TEXT)
diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 974c836..3ea23d4 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -28,7 +28,7 @@
 #include "mips32.h"
 #include "mips_ejtag.h"
 
-int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr, void *delete_me_and_submit_patch)
+int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, int new_instr)
 {
 	struct jtag_tap *tap;
 
@@ -58,7 +58,7 @@ int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode)
 
 	jtag_set_end_state(TAP_IDLE);
 
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IDCODE);
 
 	field.num_bits = 32;
 	field.out_value = NULL;
@@ -80,7 +80,7 @@ int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode)
 
 	jtag_set_end_state(TAP_IDLE);
 
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_IMPCODE);
 
 	field.num_bits = 32;
 	field.out_value = NULL;
@@ -210,7 +210,7 @@ int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info)
 {
 	uint32_t ejtag_ctrl;
 	jtag_set_end_state(TAP_IDLE);
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 
 	/* set debug break bit */
 	ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_JTAGBRK;
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index a086cd5..164edd0 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -129,7 +129,7 @@ struct mips_ejtag
 };
 
 int mips_ejtag_set_instr(struct mips_ejtag *ejtag_info,
-		int new_instr, void *delete_me_and_submit_patch);
+		int new_instr);
 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
 int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode);
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index d1b4589..5919f5b 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -113,7 +113,7 @@ int mips_m4k_poll(struct target *target)
 
 	/* read ejtag control reg */
 	jtag_set_end_state(TAP_IDLE);
-	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+	mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 	mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 
 	/* clear this bit before handling polling
@@ -125,7 +125,7 @@ int mips_m4k_poll(struct target *target)
 		jtag_set_end_state(TAP_IDLE);
 		ejtag_ctrl = ejtag_info->ejtag_ctrl & ~EJTAG_CTRL_ROCC;
 
-		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 		LOG_DEBUG("Reset Detected");
 	}
@@ -136,7 +136,7 @@ int mips_m4k_poll(struct target *target)
 		if ((target->state == TARGET_RUNNING) || (target->state == TARGET_RESET))
 		{
 			jtag_set_end_state(TAP_IDLE);
-			mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
+			mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 
 			target->state = TARGET_HALTED;
 
@@ -228,12 +228,12 @@ int mips_m4k_assert_reset(struct target *target)
 	{
 		/* use hardware to catch reset */
 		jtag_set_end_state(TAP_IDLE);
-		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT, NULL);
+		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_EJTAGBOOT);
 	}
 	else
 	{
 		jtag_set_end_state(TAP_IDLE);
-		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
+		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT);
 	}
 
 	if (assert_srst)
@@ -257,21 +257,21 @@ int mips_m4k_assert_reset(struct target *target)
 			LOG_DEBUG("Using MTAP reset to reset processor...");
 
 			/* use microchip specific MTAP reset */
-			mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP, NULL);
-			mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND, NULL);
+			mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP);
+			mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND);
 
 			mchip_cmd = MCHP_ASERT_RST;
 			mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
 			mchip_cmd = MCHP_DE_ASSERT_RST;
 			mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
-			mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL);
+			mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
 		}
 		else
 		{
 			/* use ejtag reset - not supported by all cores */
 			uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 			LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
-			mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+			mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL);
 			mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
 		}
 	}
@@ -933,7 +933,7 @@ int mips_m4k_examine(struct target *target)
 		{
 			/* we are using a pic32mx so select ejtag port
 			 * as it is not selected by default */
-			mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL);
+			mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP);
 			LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
 			mips_m4k->is_pic32mx = true;
 		}

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi           |   46 ++++++++++++++------------
 src/flash/nor/pic32mx.c    |   75 ++++++++++++++++++++++++++++++++++++++++++++
 src/target/mips32_dmaacc.c |   48 ++++++++++++++--------------
 src/target/mips32_pracc.c  |   24 +++++++-------
 src/target/mips_ejtag.c    |    8 ++--
 src/target/mips_ejtag.h    |    4 ++-
 src/target/mips_m4k.c      |   20 ++++++------
 7 files changed, 153 insertions(+), 72 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-108-g46f9287

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  46f92878da6c65eac275d1783e4e4019ec3c9af9 (commit)
      from  d37ed9094a62ec144b9d9fdc214d8c7723caadec (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 46f92878da6c65eac275d1783e4e4019ec3c9af9
Author: Øyvind Harboe <oyv...@zy...>
Date:   Thu Mar 18 12:06:07 2010 +0100

    oops: committed and pushed two temp files....
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/arm_adi_v5.c.orig b/src/target/arm_adi_v5.c.orig
deleted file mode 100644
index 708e858..0000000
--- a/src/target/arm_adi_v5.c.orig
+++ /dev/null
@@ -1,1981 +0,0 @@
-/***************************************************************************
- *   Copyright (C) 2006 by Magnus Lundin                                   *
- *   lu...@ml...                                                    *
- *                                                                         *
- *   Copyright (C) 2008 by Spencer Oliver                                  *
- *   sp...@sp...                                                  *
- *                                                                         *
- *   Copyright (C) 2009 by Oyvind Harboe                                   *
- *   oyv...@zy...                                               *
- *                                                                         *
- *   Copyright (C) 2009-2010 by David Brownell                             *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
- ***************************************************************************/
-
-/**
- * @file
- * This file implements support for the ARM Debug Interface version 5 (ADIv5)
- * debugging architecture.  Compared with previous versions, this includes
- * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
- * transport, and focusses on memory mapped resources as defined by the
- * CoreSight architecture.
- *
- * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
- * basic components:  a Debug Port (DP) transporting messages to and from a
- * debugger, and an Access Port (AP) accessing resources.  Three types of DP
- * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
- * One uses only SWD for communication, and is called SW-DP.  The third can
- * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
- * is used to access memory mapped resources and is called a MEM-AP.  Also a
- * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
- *
- * This programming interface allows DAP pipelined operations through a
- * transaction queue.  This primarily affects AP operations (such as using
- * a MEM-AP to access memory or registers).  If the current transaction has
- * not finished by the time the next one must begin, and the ORUNDETECT bit
- * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
- * further AP operations will fail.  There are two basic methods to avoid
- * such overrun errors.  One involves polling for status instead of using
- * transaction piplining.  The other involves adding delays to ensure the
- * AP has enough time to complete one operation before starting the next
- * one.  (For JTAG these delays are controlled by memaccess_tck.)
- */
-
-/*
- * Relevant specifications from ARM include:
- *
- * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
- * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
- *
- * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
- * Cortex-M3(tm) TRM, ARM DDI 0337G
- */
-
-#ifdef HAVE_CONFIG_H
-#include "config.h"
-#endif
-
-#include "arm.h"
-#include "arm_adi_v5.h"
-#include <helper/time_support.h>
-
-
-/* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
-
-/*
-	uint32_t tar_block_size(uint32_t address)
-	Return the largest block starting at address that does not cross a tar block size alignment boundary
-*/
-static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
-{
-	return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
-}
-
-/***************************************************************************
- *                                                                         *
-<<<<<<< HEAD:src/target/arm_adi_v5.c
-=======
- * DPACC and APACC scanchain access through JTAG-DP                        *
- *                                                                         *
-***************************************************************************/
-
-/**
- * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
- * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
- * discusses operations which access these registers.
- *
- * Note that only one scan is performed.  If RnW is set, a separate scan
- * will be needed to collect the data which was read; the "invalue" collects
- * the posted result of a preceding operation, not the current one.
- *
- * @param swjdp the DAP
- * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
- * @param reg_addr two significant bits; A[3:2]; for APACC access, the
- *	SELECT register has more addressing bits.
- * @param RnW false iff outvalue will be written to the DP or AP
- * @param outvalue points to a 32-bit (little-endian) integer
- * @param invalue NULL, or points to a 32-bit (little-endian) integer
- * @param ack points to where the three bit JTAG_ACK_* code will be stored
- */
-static int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
-		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
-		uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
-{
-	struct arm_jtag *jtag_info = swjdp->jtag_info;
-	struct scan_field fields[2];
-	uint8_t out_addr_buf;
-
-	jtag_set_end_state(TAP_IDLE);
-	arm_jtag_set_instr(jtag_info, instr, NULL);
-
-	/* Scan out a read or write operation using some DP or AP register.
-	 * For APACC access with any sticky error flag set, this is discarded.
-	 */
-	fields[0].num_bits = 3;
-	buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
-	fields[0].out_value = &out_addr_buf;
-	fields[0].in_value = ack;
-
-	/* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
-	 * complete; data we write is discarded, data we read is unpredictable.
-	 * When overrun detect is active, STICKYORUN is set.
-	 */
-
-	fields[1].num_bits = 32;
-	fields[1].out_value = outvalue;
-	fields[1].in_value = invalue;
-
-	jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE);
-
-	/* Add specified number of tck clocks after starting memory bus
-	 * access, giving the hardware time to complete the access.
-	 * They provide more time for the (MEM) AP to complete the read ...
-	 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
-	 */
-	if ((instr == JTAG_DP_APACC)
-			&& ((reg_addr == AP_REG_DRW)
-				|| ((reg_addr & 0xF0) == AP_REG_BD0))
-			&& (swjdp->memaccess_tck != 0))
-		jtag_add_runtest(swjdp->memaccess_tck,
-				TAP_IDLE);
-
-	return jtag_get_error();
-}
-
-/**
- * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
- * This is exactly like adi_jtag_dp_scan(), except that endianness
- * conversions are performed (so the types of invalue and outvalue
- * must be different).
- */
-static int adi_jtag_dp_scan_u32(struct adiv5_dap *swjdp,
-		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
-		uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
-{
-	uint8_t out_value_buf[4];
-	int retval;
-
-	buf_set_u32(out_value_buf, 0, 32, outvalue);
-
-	retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
-			out_value_buf, (uint8_t *)invalue, ack);
-	if (retval != ERROR_OK)
-		return retval;
-
-	if (invalue)
-		jtag_add_callback(arm_le_to_h_u32,
-				(jtag_callback_data_t) invalue);
-
-	return retval;
-}
-
-/**
- * Utility to write AP registers.
- */
-static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
-		uint8_t reg_addr, uint8_t *outvalue)
-{
-	return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
-			outvalue, NULL, NULL);
-}
-
-static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *swjdp,
-		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
-		uint32_t outvalue, uint32_t *invalue)
-{
-	int retval;
-
-	/* Issue the read or write */
-	retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
-			RnW, outvalue, NULL, NULL);
-	if (retval != ERROR_OK)
-		return retval;
-
-	/* For reads,  collect posted value; RDBUFF has no other effect.
-	 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
-	 */
-	if ((RnW == DPAP_READ) && (invalue != NULL))
-		retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
-				DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
-	return retval;
-}
-
-static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
-{
-	int retval;
-	uint32_t ctrlstat;
-
-	/* too expensive to call keep_alive() here */
-
-#if 0
-	/* Danger!!!! BROKEN!!!! */
-	adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
-			DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
-	/* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
-	R956 introduced the check on return value here and now Michael Schwingen reports
-	that this code no longer works....
-
-	https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
-	*/
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
-	{
-		LOG_ERROR("BUG: Why does this fail the first time????");
-	}
-	/* Why??? second time it works??? */
-#endif
-
-	/* Post CTRL/STAT read; discard any previous posted read value
-	 * but collect its ACK status.
-	 */
-	adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
-			DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
-	if ((retval = jtag_execute_queue()) != ERROR_OK)
-		return retval;
-
-	swjdp->ack = swjdp->ack & 0x7;
-
-	/* common code path avoids calling timeval_ms() */
-	if (swjdp->ack != JTAG_ACK_OK_FAULT)
-	{
-		long long then = timeval_ms();
-
-		while (swjdp->ack != JTAG_ACK_OK_FAULT)
-		{
-			if (swjdp->ack == JTAG_ACK_WAIT)
-			{
-				if ((timeval_ms()-then) > 1000)
-				{
-					/* NOTE:  this would be a good spot
-					 * to use JTAG_DP_ABORT.
-					 */
-					LOG_WARNING("Timeout (1000ms) waiting "
-						"for ACK=OK/FAULT "
-						"in JTAG-DP transaction");
-					return ERROR_JTAG_DEVICE_ERROR;
-				}
-			}
-			else
-			{
-				LOG_WARNING("Invalid ACK %#x "
-						"in JTAG-DP transaction",
-						swjdp->ack);
-				return ERROR_JTAG_DEVICE_ERROR;
-			}
-
-			adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
-					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
-			if ((retval = dap_run(swjdp)) != ERROR_OK)
-				return retval;
-			swjdp->ack = swjdp->ack & 0x7;
-		}
-	}
-
-	/* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
-
-	/* Check for STICKYERR and STICKYORUN */
-	if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
-	{
-		LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
-		/* Check power to debug regions */
-		if ((ctrlstat & 0xf0000000) != 0xf0000000)
-			 ahbap_debugport_init(swjdp);
-		else
-		{
-			uint32_t mem_ap_csw, mem_ap_tar;
-
-			/* Maybe print information about last intended
-			 * MEM-AP access; but not if autoincrementing.
-			 * *Real* CSW and TAR values are always shown.
-			 */
-			if (swjdp->ap_tar_value != (uint32_t) -1)
-				LOG_DEBUG("MEM-AP Cached values: "
-					"ap_bank 0x%" PRIx32
-					", ap_csw 0x%" PRIx32
-					", ap_tar 0x%" PRIx32,
-					swjdp->ap_bank_value,
-					swjdp->ap_csw_value,
-					swjdp->ap_tar_value);
-
-			if (ctrlstat & SSTICKYORUN)
-				LOG_ERROR("JTAG-DP OVERRUN - check clock, "
-					"memaccess, or reduce jtag speed");
-
-			if (ctrlstat & SSTICKYERR)
-				LOG_ERROR("JTAG-DP STICKY ERROR");
-
-			/* Clear Sticky Error Bits */
-			adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
-					DP_CTRL_STAT, DPAP_WRITE,
-					swjdp->dp_ctrl_stat | SSTICKYORUN
-						| SSTICKYERR, NULL);
-			adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
-					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
-			if ((retval = dap_run(swjdp)) != ERROR_OK)
-				return retval;
-
-			LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
-
-			retval = dap_queue_ap_read(swjdp,
-					AP_REG_CSW, &mem_ap_csw);
-			if (retval != ERROR_OK)
-				return retval;
-
-			retval = dap_queue_ap_read(swjdp,
-					AP_REG_TAR, &mem_ap_tar);
-			if (retval != ERROR_OK)
-				return retval;
-
-			if ((retval = dap_run(swjdp)) != ERROR_OK)
-				return retval;
-			LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
-					PRIx32, mem_ap_csw, mem_ap_tar);
-
-		}
-		if ((retval = dap_run(swjdp)) != ERROR_OK)
-			return retval;
-		return ERROR_JTAG_DEVICE_ERROR;
-	}
-
-	return ERROR_OK;
-}
-
-/***************************************************************************
- *                                                                         *
->>>>>>> jtag: cut down on usage of unintended modification of global end state:src/target/arm_adi_v5.c
- * DP and MEM-AP  register access  through APACC and DPACC                 *
- *                                                                         *
-***************************************************************************/
-
-/**
- * Select one of the APs connected to the specified DAP.  The
- * selection is implicitly used with future AP transactions.
- * This is a NOP if the specified AP is already selected.
- *
- * @param swjdp The DAP
- * @param apsel Number of the AP to (implicitly) use with further
- *	transactions.  This normally identifies a MEM-AP.
- */
-void dap_ap_select(struct adiv5_dap *swjdp,uint8_t apsel)
-{
-	uint32_t select = (apsel << 24) & 0xFF000000;
-
-	if (select != swjdp->apsel)
-	{
-		swjdp->apsel = select;
-		/* Switching AP invalidates cached values.
-		 * Values MUST BE UPDATED BEFORE AP ACCESS.
-		 */
-		swjdp->ap_bank_value = -1;
-		swjdp->ap_csw_value = -1;
-		swjdp->ap_tar_value = -1;
-	}
-}
-
-/**
- * Queue transactions setting up transfer parameters for the
- * currently selected MEM-AP.
- *
- * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
- * initiate data reads or writes using memory or peripheral addresses.
- * If the CSW is configured for it, the TAR may be automatically
- * incremented after each transfer.
- *
- * @todo Rename to reflect it being specifically a MEM-AP function.
- *
- * @param swjdp The DAP connected to the MEM-AP.
- * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
- *	matches the cached value, the register is not changed.
- * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
- *	matches the cached address, the register is not changed.
- *
- * @return ERROR_OK if the transaction was properly queued, else a fault code.
- */
-int dap_setup_accessport(struct adiv5_dap *swjdp, uint32_t csw, uint32_t tar)
-{
-	int retval;
-
-	csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
-	if (csw != swjdp->ap_csw_value)
-	{
-		/* LOG_DEBUG("DAP: Set CSW %x",csw); */
-		retval = dap_queue_ap_write(swjdp, AP_REG_CSW, csw);
-		if (retval != ERROR_OK)
-			return retval;
-		swjdp->ap_csw_value = csw;
-	}
-	if (tar != swjdp->ap_tar_value)
-	{
-		/* LOG_DEBUG("DAP: Set TAR %x",tar); */
-		retval = dap_queue_ap_write(swjdp, AP_REG_TAR, tar);
-		if (retval != ERROR_OK)
-			return retval;
-		swjdp->ap_tar_value = tar;
-	}
-	/* Disable TAR cache when autoincrementing */
-	if (csw & CSW_ADDRINC_MASK)
-		swjdp->ap_tar_value = -1;
-	return ERROR_OK;
-}
-
-/**
- * Asynchronous (queued) read of a word from memory or a system register.
- *
- * @param swjdp The DAP connected to the MEM-AP performing the read.
- * @param address Address of the 32-bit word to read; it must be
- *	readable by the currently selected MEM-AP.
- * @param value points to where the word will be stored when the
- *	transaction queue is flushed (assuming no errors).
- *
- * @return ERROR_OK for success.  Otherwise a fault code.
- */
-int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address,
-		uint32_t *value)
-{
-	int retval;
-
-	/* Use banked addressing (REG_BDx) to avoid some link traffic
-	 * (updating TAR) when reading several consecutive addresses.
-	 */
-	retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
-			address & 0xFFFFFFF0);
-	if (retval != ERROR_OK)
-		return retval;
-
-	return dap_queue_ap_read(swjdp, AP_REG_BD0 | (address & 0xC), value);
-}
-
-/**
- * Synchronous read of a word from memory or a system register.
- * As a side effect, this flushes any queued transactions.
- *
- * @param swjdp The DAP connected to the MEM-AP performing the read.
- * @param address Address of the 32-bit word to read; it must be
- *	readable by the currently selected MEM-AP.
- * @param value points to where the result will be stored.
- *
- * @return ERROR_OK for success; *value holds the result.
- * Otherwise a fault code.
- */
-int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
-		uint32_t *value)
-{
-	int retval;
-
-	retval = mem_ap_read_u32(swjdp, address, value);
-	if (retval != ERROR_OK)
-		return retval;
-
-	return dap_run(swjdp);
-}
-
-/**
- * Asynchronous (queued) write of a word to memory or a system register.
- *
- * @param swjdp The DAP connected to the MEM-AP.
- * @param address Address to be written; it must be writable by
- *	the currently selected MEM-AP.
- * @param value Word that will be written to the address when transaction
- *	queue is flushed (assuming no errors).
- *
- * @return ERROR_OK for success.  Otherwise a fault code.
- */
-int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address,
-		uint32_t value)
-{
-	int retval;
-
-	/* Use banked addressing (REG_BDx) to avoid some link traffic
-	 * (updating TAR) when writing several consecutive addresses.
-	 */
-	retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
-			address & 0xFFFFFFF0);
-	if (retval != ERROR_OK)
-		return retval;
-
-	return dap_queue_ap_write(swjdp, AP_REG_BD0 | (address & 0xC),
-			value);
-}
-
-/**
- * Synchronous write of a word to memory or a system register.
- * As a side effect, this flushes any queued transactions.
- *
- * @param swjdp The DAP connected to the MEM-AP.
- * @param address Address to be written; it must be writable by
- *	the currently selected MEM-AP.
- * @param value Word that will be written.
- *
- * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
- */
-int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
-		uint32_t value)
-{
-	int retval = mem_ap_write_u32(swjdp, address, value);
-
-	if (retval != ERROR_OK)
-		return retval;
-
-	return dap_run(swjdp);
-}
-
-/*****************************************************************************
-*                                                                            *
-* mem_ap_write_buf(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address) *
-*                                                                            *
-* Write a buffer in target order (little endian)                             *
-*                                                                            *
-*****************************************************************************/
-int mem_ap_write_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
-{
-	int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
-	uint32_t adr = address;
-	uint8_t* pBuffer = buffer;
-
-	count >>= 2;
-	wcount = count;
-
-	/* if we have an unaligned access - reorder data */
-	if (adr & 0x3u)
-	{
-		for (writecount = 0; writecount < count; writecount++)
-		{
-			int i;
-			uint32_t outvalue;
-			memcpy(&outvalue, pBuffer, sizeof(uint32_t));
-
-			for (i = 0; i < 4; i++)
-			{
-				*((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
-				outvalue >>= 8;
-				adr++;
-			}
-			pBuffer += sizeof(uint32_t);
-		}
-	}
-
-	while (wcount > 0)
-	{
-		/* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
-		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
-		if (wcount < blocksize)
-			blocksize = wcount;
-
-		/* handle unaligned data at 4k boundary */
-		if (blocksize == 0)
-			blocksize = 1;
-
-		dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
-
-		for (writecount = 0; writecount < blocksize; writecount++)
-		{
-			retval = dap_queue_ap_write(swjdp, AP_REG_DRW,
-				*(uint32_t *) (buffer + 4 * writecount));
-			if (retval != ERROR_OK)
-				break;
-		}
-
-		if (dap_run(swjdp) == ERROR_OK)
-		{
-			wcount = wcount - blocksize;
-			address = address + 4 * blocksize;
-			buffer = buffer + 4 * blocksize;
-		}
-		else
-		{
-			errorcount++;
-		}
-
-		if (errorcount > 1)
-		{
-			LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
-			/* REVISIT return the *actual* fault code */
-			return ERROR_JTAG_DEVICE_ERROR;
-		}
-	}
-
-	return retval;
-}
-
-static int mem_ap_write_buf_packed_u16(struct adiv5_dap *swjdp,
-		uint8_t *buffer, int count, uint32_t address)
-{
-	int retval = ERROR_OK;
-	int wcount, blocksize, writecount, i;
-
-	wcount = count >> 1;
-
-	while (wcount > 0)
-	{
-		int nbytes;
-
-		/* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
-		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
-
-		if (wcount < blocksize)
-			blocksize = wcount;
-
-		/* handle unaligned data at 4k boundary */
-		if (blocksize == 0)
-			blocksize = 1;
-
-		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
-		writecount = blocksize;
-
-		do
-		{
-			nbytes = MIN((writecount << 1), 4);
-
-			if (nbytes < 4)
-			{
-				if (mem_ap_write_buf_u16(swjdp, buffer,
-						nbytes, address) != ERROR_OK)
-				{
-					LOG_WARNING("Block write error address "
-						"0x%" PRIx32 ", count 0x%x",
-						address, count);
-					return ERROR_JTAG_DEVICE_ERROR;
-				}
-
-				address += nbytes >> 1;
-			}
-			else
-			{
-				uint32_t outvalue;
-				memcpy(&outvalue, buffer, sizeof(uint32_t));
-
-				for (i = 0; i < nbytes; i++)
-				{
-					*((uint8_t*)buffer + (address & 0x3)) = outvalue;
-					outvalue >>= 8;
-					address++;
-				}
-
-				memcpy(&outvalue, buffer, sizeof(uint32_t));
-				retval = dap_queue_ap_write(swjdp,
-						AP_REG_DRW, outvalue);
-				if (retval != ERROR_OK)
-					break;
-
-				if (dap_run(swjdp) != ERROR_OK)
-				{
-					LOG_WARNING("Block write error address "
-						"0x%" PRIx32 ", count 0x%x",
-						address, count);
-					/* REVISIT return *actual* fault code */
-					return ERROR_JTAG_DEVICE_ERROR;
-				}
-			}
-
-			buffer += nbytes >> 1;
-			writecount -= nbytes >> 1;
-
-		} while (writecount);
-		wcount -= blocksize;
-	}
-
-	return retval;
-}
-
-int mem_ap_write_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
-{
-	int retval = ERROR_OK;
-
-	if (count >= 4)
-		return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
-
-	while (count > 0)
-	{
-		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
-		uint16_t svalue;
-		memcpy(&svalue, buffer, sizeof(uint16_t));
-		uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
-		retval = dap_queue_ap_write(swjdp, AP_REG_DRW, outvalue);
-		if (retval != ERROR_OK)
-			break;
-
-		retval = dap_run(swjdp);
-		if (retval != ERROR_OK)
-			break;
-
-		count -= 2;
-		address += 2;
-		buffer += 2;
-	}
-
-	return retval;
-}
-
-static int mem_ap_write_buf_packed_u8(struct adiv5_dap *swjdp,
-		uint8_t *buffer, int count, uint32_t address)
-{
-	int retval = ERROR_OK;
-	int wcount, blocksize, writecount, i;
-
-	wcount = count;
-
-	while (wcount > 0)
-	{
-		int nbytes;
-
-		/* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
-		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
-
-		if (wcount < blocksize)
-			blocksize = wcount;
-
-		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
-		writecount = blocksize;
-
-		do
-		{
-			nbytes = MIN(writecount, 4);
-
-			if (nbytes < 4)
-			{
-				if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
-				{
-					LOG_WARNING("Block write error address "
-						"0x%" PRIx32 ", count 0x%x",
-						address, count);
-					return ERROR_JTAG_DEVICE_ERROR;
-				}
-
-				address += nbytes;
-			}
-			else
-			{
-				uint32_t outvalue;
-				memcpy(&outvalue, buffer, sizeof(uint32_t));
-
-				for (i = 0; i < nbytes; i++)
-				{
-					*((uint8_t*)buffer + (address & 0x3)) = outvalue;
-					outvalue >>= 8;
-					address++;
-				}
-
-				memcpy(&outvalue, buffer, sizeof(uint32_t));
-				retval = dap_queue_ap_write(swjdp,
-						AP_REG_DRW, outvalue);
-				if (retval != ERROR_OK)
-					break;
-
-				if (dap_run(swjdp) != ERROR_OK)
-				{
-					LOG_WARNING("Block write error address "
-						"0x%" PRIx32 ", count 0x%x",
-						address, count);
-					/* REVISIT return *actual* fault code */
-					return ERROR_JTAG_DEVICE_ERROR;
-				}
-			}
-
-			buffer += nbytes;
-			writecount -= nbytes;
-
-		} while (writecount);
-		wcount -= blocksize;
-	}
-
-	return retval;
-}
-
-int mem_ap_write_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
-{
-	int retval = ERROR_OK;
-
-	if (count >= 4)
-		return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
-
-	while (count > 0)
-	{
-		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
-		uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
-		retval = dap_queue_ap_write(swjdp, AP_REG_DRW, outvalue);
-		if (retval != ERROR_OK)
-			break;
-
-		retval = dap_run(swjdp);
-		if (retval != ERROR_OK)
-			break;
-
-		count--;
-		address++;
-		buffer++;
-	}
-
-	return retval;
-}
-
-/* FIXME don't import ... this is a temporary workaround for the
- * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
- */
-extern int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
-		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
-		uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
-
-/**
- * Synchronously read a block of 32-bit words into a buffer
- * @param swjdp The DAP connected to the MEM-AP.
- * @param buffer where the words will be stored (in host byte order).
- * @param count How many words to read.
- * @param address Memory address from which to read words; all the
- *	words must be readable by the currently selected MEM-AP.
- */
-int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer,
-		int count, uint32_t address)
-{
-	int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
-	uint32_t adr = address;
-	uint8_t* pBuffer = buffer;
-
-	count >>= 2;
-	wcount = count;
-
-	while (wcount > 0)
-	{
-		/* Adjust to read blocks within boundaries aligned to the
-		 * TAR autoincrement size (at least 2^10).  Autoincrement
-		 * mode avoids an extra per-word roundtrip to update TAR.
-		 */
-		blocksize = max_tar_block_size(swjdp->tar_autoincr_block,
-				address);
-		if (wcount < blocksize)
-			blocksize = wcount;
-
-		/* handle unaligned data at 4k boundary */
-		if (blocksize == 0)
-			blocksize = 1;
-
-		dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE,
-				address);
-
-		/* FIXME remove these three calls to adi_jtag_dp_scan(),
-		 * so this routine becomes transport-neutral.  Be careful
-		 * not to cause performance problems with JTAG; would it
-		 * suffice to loop over dap_queue_ap_read(), or would that
-		 * be slower when JTAG is the chosen transport?
-		 */
-
-		/* Scan out first read */
-		adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
-				DPAP_READ, 0, NULL, NULL);
-		for (readcount = 0; readcount < blocksize - 1; readcount++)
-		{
-			/* Scan out next read; scan in posted value for the
-			 * previous one.  Assumes read is acked "OK/FAULT",
-			 * and CTRL_STAT says that meant "OK".
-			 */
-			adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
-					DPAP_READ, 0, buffer + 4 * readcount,
-					&swjdp->ack);
-		}
-
-		/* Scan in last posted value; RDBUFF has no other effect,
-		 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
-		 */
-		adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
-				DPAP_READ, 0, buffer + 4 * readcount,
-				&swjdp->ack);
-		if (dap_run(swjdp) == ERROR_OK)
-		{
-			wcount = wcount - blocksize;
-			address += 4 * blocksize;
-			buffer += 4 * blocksize;
-		}
-		else
-		{
-			errorcount++;
-		}
-
-		if (errorcount > 1)
-		{
-			LOG_WARNING("Block read error address 0x%" PRIx32
-				", count 0x%x", address, count);
-			/* REVISIT return the *actual* fault code */
-			return ERROR_JTAG_DEVICE_ERROR;
-		}
-	}
-
-	/* if we have an unaligned access - reorder data */
-	if (adr & 0x3u)
-	{
-		for (readcount = 0; readcount < count; readcount++)
-		{
-			int i;
-			uint32_t data;
-			memcpy(&data, pBuffer, sizeof(uint32_t));
-
-			for (i = 0; i < 4; i++)
-			{
-				*((uint8_t*)pBuffer) =
-						(data >> 8 * (adr & 0x3));
-				pBuffer++;
-				adr++;
-			}
-		}
-	}
-
-	return retval;
-}
-
-static int mem_ap_read_buf_packed_u16(struct adiv5_dap *swjdp,
-		uint8_t *buffer, int count, uint32_t address)
-{
-	uint32_t invalue;
-	int retval = ERROR_OK;
-	int wcount, blocksize, readcount, i;
-
-	wcount = count >> 1;
-
-	while (wcount > 0)
-	{
-		int nbytes;
-
-		/* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
-		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
-		if (wcount < blocksize)
-			blocksize = wcount;
-
-		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
-
-		/* handle unaligned data at 4k boundary */
-		if (blocksize == 0)
-			blocksize = 1;
-		readcount = blocksize;
-
-		do
-		{
-			retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
-			if (dap_run(swjdp) != ERROR_OK)
-			{
-				LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
-				/* REVISIT return the *actual* fault code */
-				return ERROR_JTAG_DEVICE_ERROR;
-			}
-
-			nbytes = MIN((readcount << 1), 4);
-
-			for (i = 0; i < nbytes; i++)
-			{
-				*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
-				buffer++;
-				address++;
-			}
-
-			readcount -= (nbytes >> 1);
-		} while (readcount);
-		wcount -= blocksize;
-	}
-
-	return retval;
-}
-
-/**
- * Synchronously read a block of 16-bit halfwords into a buffer
- * @param swjdp The DAP connected to the MEM-AP.
- * @param buffer where the halfwords will be stored (in host byte order).
- * @param count How many halfwords to read.
- * @param address Memory address from which to read words; all the
- *	words must be readable by the currently selected MEM-AP.
- */
-int mem_ap_read_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer,
-		int count, uint32_t address)
-{
-	uint32_t invalue, i;
-	int retval = ERROR_OK;
-
-	if (count >= 4)
-		return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
-
-	while (count > 0)
-	{
-		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
-		retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
-		if (retval != ERROR_OK)
-			break;
-
-		retval = dap_run(swjdp);
-		if (retval != ERROR_OK)
-			break;
-
-		if (address & 0x1)
-		{
-			for (i = 0; i < 2; i++)
-			{
-				*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
-				buffer++;
-				address++;
-			}
-		}
-		else
-		{
-			uint16_t svalue = (invalue >> 8 * (address & 0x3));
-			memcpy(buffer, &svalue, sizeof(uint16_t));
-			address += 2;
-			buffer += 2;
-		}
-		count -= 2;
-	}
-
-	return retval;
-}
-
-/* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
- * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
- *
- * The solution is to arrange for a large out/in scan in this loop and
- * and convert data afterwards.
- */
-static int mem_ap_read_buf_packed_u8(struct adiv5_dap *swjdp,
-		uint8_t *buffer, int count, uint32_t address)
-{
-	uint32_t invalue;
-	int retval = ERROR_OK;
-	int wcount, blocksize, readcount, i;
-
-	wcount = count;
-
-	while (wcount > 0)
-	{
-		int nbytes;
-
-		/* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
-		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
-
-		if (wcount < blocksize)
-			blocksize = wcount;
-
-		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
-		readcount = blocksize;
-
-		do
-		{
-			retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
-			if (dap_run(swjdp) != ERROR_OK)
-			{
-				LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
-				/* REVISIT return the *actual* fault code */
-				return ERROR_JTAG_DEVICE_ERROR;
-			}
-
-			nbytes = MIN(readcount, 4);
-
-			for (i = 0; i < nbytes; i++)
-			{
-				*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
-				buffer++;
-				address++;
-			}
-
-			readcount -= nbytes;
-		} while (readcount);
-		wcount -= blocksize;
-	}
-
-	return retval;
-}
-
-/**
- * Synchronously read a block of bytes into a buffer
- * @param swjdp The DAP connected to the MEM-AP.
- * @param buffer where the bytes will be stored.
- * @param count How many bytes to read.
- * @param address Memory address from which to read data; all the
- *	data must be readable by the currently selected MEM-AP.
- */
-int mem_ap_read_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer,
-		int count, uint32_t address)
-{
-	uint32_t invalue;
-	int retval = ERROR_OK;
-
-	if (count >= 4)
-		return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
-
-	while (count > 0)
-	{
-		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
-		retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
-		retval = dap_run(swjdp);
-		if (retval != ERROR_OK)
-			break;
-
-		*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
-		count--;
-		address++;
-		buffer++;
-	}
-
-	return retval;
-}
-
-/*--------------------------------------------------------------------------*/
-
-<<<<<<< HEAD:src/target/arm_adi_v5.c
-=======
-static int jtag_idcode_q_read(struct adiv5_dap *dap,
-		uint8_t *ack, uint32_t *data)
-{
-	struct arm_jtag *jtag_info = dap->jtag_info;
-	int retval;
-	struct scan_field fields[1];
-
-	jtag_set_end_state(TAP_IDLE);
-
-	/* This is a standard JTAG operation -- no DAP tweakage */
-	retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL);
-	if (retval != ERROR_OK)
-		return retval;
-
-	fields[0].num_bits = 32;
-	fields[0].out_value = NULL;
-	fields[0].in_value = (void *) data;
-
-	jtag_add_dr_scan(jtag_info->tap, 1, fields, TAP_IDLE);
-	retval = jtag_get_error();
-	if (retval != ERROR_OK)
-		return retval;
-
-	jtag_add_callback(arm_le_to_h_u32,
-			(jtag_callback_data_t) data);
-
-	return retval;
-}
-
-static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
-		uint32_t *data)
-{
-	return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
-			reg, DPAP_READ, 0, data);
-}
-
-static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
-		uint32_t data)
-{
-	return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
-			reg, DPAP_WRITE, data, NULL);
-}
-
-/** Select the AP register bank matching bits 7:4 of reg. */
-static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
-{
-	uint32_t select = reg & 0x000000F0;
-
-	if (select == dap->ap_bank_value)
-		return ERROR_OK;
-	dap->ap_bank_value = select;
-
-	select |= dap->apsel;
-
-	return jtag_dp_q_write(dap, DP_SELECT, select);
-}
-
-static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
-		uint32_t *data)
-{
-	int retval = jtag_ap_q_bankselect(dap, reg);
-
-	if (retval != ERROR_OK)
-		return retval;
-
-	return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
-			DPAP_READ, 0, data);
-}
-
-static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
-		uint32_t data)
-{
-	uint8_t out_value_buf[4];
-
-	int retval = jtag_ap_q_bankselect(dap, reg);
-	if (retval != ERROR_OK)
-		return retval;
->>>>>>> jtag: cut down on usage of unintended modification of global end state:src/target/arm_adi_v5.c
-
-/* FIXME don't import ... just initialize as
- * part of DAP transport setup
-*/
-extern const struct dap_ops jtag_dp_ops;
-
-/*--------------------------------------------------------------------------*/
-
-/**
- * Initialize a DAP.  This sets up the power domains, prepares the DP
- * for further use, and arranges to use AP #0 for all AP operations
- * until dap_ap-select() changes that policy.
- *
- * @param swjdp The DAP being initialized.
- *
- * @todo Rename this.  We also need an initialization scheme which account
- * for SWD transports not just JTAG; that will need to address differences
- * in layering.  (JTAG is useful without any debug target; but not SWD.)
- * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
- */
-int ahbap_debugport_init(struct adiv5_dap *swjdp)
-{
-	uint32_t idreg, romaddr, dummy;
-	uint32_t ctrlstat;
-	int cnt = 0;
-	int retval;
-
-	LOG_DEBUG(" ");
-
-	/* JTAG-DP or SWJ-DP, in JTAG mode */
-	swjdp->ops = &jtag_dp_ops;
-
-	/* Default MEM-AP setup.
-	 *
-	 * REVISIT AP #0 may be an inappropriate default for this.
-	 * Should we probe, or take a hint from the caller?
-	 * Presumably we can ignore the possibility of multiple APs.
-	 */
-	swjdp->apsel = !0;
-	dap_ap_select(swjdp, 0);
-
-	/* DP initialization */
-
-	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
-	if (retval != ERROR_OK)
-		return retval;
-
-	retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, SSTICKYERR);
-	if (retval != ERROR_OK)
-		return retval;
-
-	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
-	if (retval != ERROR_OK)
-		return retval;
-
-	swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
-	retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
-	if (retval != ERROR_OK)
-		return retval;
-
-	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
-	if (retval != ERROR_OK)
-		return retval;
-	if ((retval = dap_run(swjdp)) != ERROR_OK)
-		return retval;
-
-	/* Check that we have debug power domains activated */
-	while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
-	{
-		LOG_DEBUG("DAP: wait CDBGPWRUPACK");
-		retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
-		if (retval != ERROR_OK)
-			return retval;
-		if ((retval = dap_run(swjdp)) != ERROR_OK)
-			return retval;
-		alive_sleep(10);
-	}
-
-	while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
-	{
-		LOG_DEBUG("DAP: wait CSYSPWRUPACK");
-		retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
-		if (retval != ERROR_OK)
-			return retval;
-		if ((retval = dap_run(swjdp)) != ERROR_OK)
-			return retval;
-		alive_sleep(10);
-	}
-
-	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
-	if (retval != ERROR_OK)
-		return retval;
-	/* With debug power on we can activate OVERRUN checking */
-	swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
-	retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
-	if (retval != ERROR_OK)
-		return retval;
-	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
-	if (retval != ERROR_OK)
-		return retval;
-
-	/*
-	 * REVISIT this isn't actually *initializing* anything in an AP,
-	 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
-	 * Should it?  If the ROM address is valid, is this the right
-	 * place to scan the table and do any topology detection?
-	 */
-	retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &idreg);
-	retval = dap_queue_ap_read(swjdp, AP_REG_BASE, &romaddr);
-
-	LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
-		", Debug ROM Address 0x%" PRIx32,
-		swjdp->apsel, idreg, romaddr);
-
-	return ERROR_OK;
-}
-
-/* CID interpretation -- see ARM IHI 0029B section 3
- * and ARM IHI 0031A table 13-3.
- */
-static const char *class_description[16] ={
-	"Reserved", "ROM table", "Reserved", "Reserved",
-	"Reserved", "Reserved", "Reserved", "Reserved",
-	"Reserved", "CoreSight component", "Reserved", "Peripheral Test Block",
-	"Reserved", "OptimoDE DESS",
-		"Generic IP component", "PrimeCell or System component"
-};
-
-static bool
-is_dap_cid_ok(uint32_t cid3, uint32_t cid2, uint32_t cid1, uint32_t cid0)
-{
-	return cid3 == 0xb1 && cid2 == 0x05
-			&& ((cid1 & 0x0f) == 0) && cid0 == 0x0d;
-}
-
-static int dap_info_command(struct command_context *cmd_ctx,
-		struct adiv5_dap *swjdp, int apsel)
-{
-	int retval;
-	uint32_t dbgbase, apid;
-	int romtable_present = 0;
-	uint8_t mem_ap;
-	uint32_t apselold;
-
-	/* AP address is in bits 31:24 of DP_SELECT */
-	if (apsel >= 256)
-		return ERROR_INVALID_ARGUMENTS;
-
-	apselold = swjdp->apsel;
-	dap_ap_select(swjdp, apsel);
-	retval = dap_queue_ap_read(swjdp, AP_REG_BASE, &dbgbase);
-	retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &apid);
-	retval = dap_run(swjdp);
-	if (retval != ERROR_OK)
-		return retval;
-
-	/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
-	mem_ap = ((apid&0x10000) && ((apid&0x0F) != 0));
-	command_print(cmd_ctx, "AP ID register 0x%8.8" PRIx32, apid);
-	if (apid)
-	{
-		switch (apid&0x0F)
-		{
-			case 0:
-				command_print(cmd_ctx, "\tType is JTAG-AP");
-				break;
-			case 1:
-				command_print(cmd_ctx, "\tType is MEM-AP AHB");
-				break;
-			case 2:
-				command_print(cmd_ctx, "\tType is MEM-AP APB");
-				break;
-			default:
-				command_print(cmd_ctx, "\tUnknown AP type");
-				break;
-		}
-
-		/* NOTE: a MEM-AP may have a single CoreSight component that's
-		 * not a ROM table ... or have no such components at all.
-		 */
-		if (mem_ap)
-			command_print(cmd_ctx, "AP BASE 0x%8.8" PRIx32,
-					dbgbase);
-	}
-	else
-	{
-		command_print(cmd_ctx, "No AP found at this apsel 0x%x", apsel);
-	}
-
-	romtable_present = ((mem_ap) && (dbgbase != 0xFFFFFFFF));
-	if (romtable_present)
-	{
-		uint32_t cid0,cid1,cid2,cid3,memtype,romentry;
-		uint16_t entry_offset;
-
-		/* bit 16 of apid indicates a memory access port */
-		if (dbgbase & 0x02)
-			command_print(cmd_ctx, "\tValid ROM table present");
-		else
-			command_print(cmd_ctx, "\tROM table in legacy format");
-
-		/* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
-		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF0, &cid0);
-		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF4, &cid1);
-		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFF8, &cid2);
-		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFFC, &cid3);
-		mem_ap_read_u32(swjdp, (dbgbase&0xFFFFF000) | 0xFCC, &memtype);
-		retval = dap_run(swjdp);
-		if (retval != ERROR_OK)
-			return retval;
-
-		if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
-			command_print(cmd_ctx, "\tCID3 0x%2.2" PRIx32
-					", CID2 0x%2.2" PRIx32
-					", CID1 0x%2.2" PRIx32
-					", CID0 0x%2.2" PRIx32,
-					cid3, cid2, cid1, cid0);
-		if (memtype & 0x01)
-			command_print(cmd_ctx, "\tMEMTYPE system memory present on bus");
-		else
-			command_print(cmd_ctx, "\tMEMTYPE System memory not present. "
-					"Dedicated debug bus.");
-
-		/* Now we read ROM table entries from dbgbase&0xFFFFF000) | 0x000 until we get 0x00000000 */
-		entry_offset = 0;
-		do
-		{
-			mem_ap_read_atomic_u32(swjdp, (dbgbase&0xFFFFF000) | entry_offset, &romentry);
-			command_print(cmd_ctx, "\tROMTABLE[0x%x] = 0x%" PRIx32 "",entry_offset,romentry);
-			if (romentry&0x01)
-			{
-				uint32_t c_cid0, c_cid1, c_cid2, c_cid3;
-				uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4;
-				uint32_t component_start, component_base;
-				unsigned part_num;
-				char *type, *full;
-
-				component_base = (uint32_t)((dbgbase & 0xFFFFF000)
-						+ (int)(romentry & 0xFFFFF000));
-				mem_ap_read_atomic_u32(swjdp,
-						(component_base & 0xFFFFF000) | 0xFE0, &c_pid0);
-				mem_ap_read_atomic_u32(swjdp,
-						(component_base & 0xFFFFF000) | 0xFE4, &c_pid1);
-				mem_ap_read_atomic_u32(swjdp,
-						(component_base & 0xFFFFF000) | 0xFE8, &c_pid2);
-				mem_ap_read_atomic_u32(swjdp,
-						(component_base & 0xFFFFF000) | 0xFEC, &c_pid3);
-				mem_ap_read_atomic_u32(swjdp,
-						(component_base & 0xFFFFF000) | 0xFD0, &c_pid4);
-				mem_ap_read_atomic_u32(swjdp,
-						(component_base & 0xFFFFF000) | 0xFF0, &c_cid0);
-				mem_ap_read_atomic_u32(swjdp,
-						(component_base & 0xFFFFF000) | 0xFF4, &c_cid1);
-				mem_ap_read_atomic_u32(swjdp,
-						(component_base & 0xFFFFF000) | 0xFF8, &c_cid2);
-				mem_ap_read_atomic_u32(swjdp,
-						(component_base & 0xFFFFF000) | 0xFFC, &c_cid3);
-				component_start = component_base - 0x1000*(c_pid4 >> 4);
-
-				command_print(cmd_ctx, "\t\tComponent base address 0x%" PRIx32
-						", start address 0x%" PRIx32,
-						component_base, component_start);
-				command_print(cmd_ctx, "\t\tComponent class is 0x%x, %s",
-						(int) (c_cid1 >> 4) & 0xf,
-						/* See ARM IHI 0029B Table 3-3 */
-						class_description[(c_cid1 >> 4) & 0xf]);
-
-				/* CoreSight component? */
-				if (((c_cid1 >> 4) & 0x0f) == 9) {
-					uint32_t devtype;
-					unsigned minor;
-					char *major = "Reserved", *subtype = "Reserved";
-
-					mem_ap_read_atomic_u32(swjdp,
-							(component_base & 0xfffff000) | 0xfcc,
-							&devtype);
-					minor = (devtype >> 4) & 0x0f;
-					switch (devtype & 0x0f) {
-					case 0:
-						major = "Miscellaneous";
-						switch (minor) {
-						case 0:
-							subtype = "other";
-							break;
-						case 4:
-							subtype = "Validation component";
-							break;
-						}
-						break;
-					case 1:
-						major = "Trace Sink";
-						switch (minor) {
-						case 0:
-							subtype = "other";
-							break;
-						case 1:
-							subtype = "Port";
-							break;
-						case 2:
-							subtype = "Buffer";
-							break;
-						}
-						break;
-					case 2:
-						major = "Trace Link";
-						switch (minor) {
-						case 0:
-							subtype = "other";
-							break;
-						case 1:
-							subtype = "Funnel, router";
-							break;
-						case 2:
-							subtype = "Filter";
-							break;
-						case 3:
-							subtype = "FIFO, buffer";
-							break;
-						}
-						break;
-					case 3:
-						major = "Trace Source";
-						switch (minor) {
-						case 0:
-							subtype = "other";
-							break;
-						case 1:
-							subtype = "Processor";
-							break;
-						case 2:
-							subtype = "DSP";
-							break;
-						case 3:
-							subtype = "Engine/Coprocessor";
-							break;
-						case 4:
-							subtype = "Bus";
-							break;
-						}
-						break;
-					case 4:
-						major = "Debug Control";
-						switch (minor) {
-						case 0:
-							subtype = "other";
-							break;
-						case 1:
-							subtype = "Trigger Matrix";
-							break;
-						case 2:
-							subtype = "Debug Auth";
-							break;
-						}
-						break;
-					case 5:
-						major = "Debug Logic";
-						switch (minor) {
-						case 0:
-							subtype = "other";
-							break;
-						case 1:
-							subtype = "Processor";
-							break;
-						case 2:
-							subtype = "DSP";
-							break;
-						case 3:
-							subtype = "Engine/Coprocessor";
-							break;
-						}
-						break;
-					}
-					command_print(cmd_ctx, "\t\tType is 0x%2.2x, %s, %s",
-							(unsigned) (devtype & 0xff),
-							major, subtype);
-					/* REVISIT also show 0xfc8 DevId */
-				}
-
-				if (!is_dap_cid_ok(cid3, cid2, cid1, cid0))
-					command_print(cmd_ctx, "\t\tCID3 0x%2.2" PRIx32
-							", CID2 0x%2.2" PRIx32
-							", CID1 0x%2.2" PRIx32
-							", CID0 0x%2.2" PRIx32,
-							c_cid3, c_cid2, c_cid1, c_cid0);
-				command_print(cmd_ctx, "\t\tPeripheral ID[4..0] = hex "
-						"%2.2x %2.2x %2.2x %2.2x %2.2x",
-						(int) c_pid4,
-						(int) c_pid3, (int) c_pid2,
-						(int) c_pid1, (int) c_pid0);
-
-				/* Part number interpretations are from Cortex
-				 * core specs, the CoreSight components TRM
-				 * (ARM DDI 0314H), and ETM specs; also from
-				 * chip observation (e.g. TI SDTI).
-				 */
-				part_num = c_pid0 & 0xff;
-				part_num |= (c_pid1 & 0x0f) << 8;
-				switch (part_num) {
-				case 0x000:
-					type = "Cortex-M3 NVIC";
-					full = "(Interrupt Controller)";
-					break;
-				case 0x001:
-					type = "Cortex-M3 ITM";
-					full = "(Instrumentation Trace Module)";
-					break;
-				case 0x002:
-					type = "Cortex-M3 DWT";
-					full = "(Data Watchpoint and Trace)";
-					break;
-				case 0x003:
-					type = "Cortex-M3 FBP";
-					full = "(Flash Patch and Breakpoint)";
-					break;
-				case 0x00d:
-					type = "CoreSight ETM11";
-					full = "(Embedded Trace)";
-					break;
-				// case 0x113: what?
-				case 0x120:		/* from OMAP3 memmap */
-					type = "TI SDTI";
-					full = "(System Debug Trace Interface)";
-					break;
-				case 0x343:		/* from OMAP3 memmap */
-					type = "TI DAPCTL";
-					full = "";
-					break;
-				case 0x906:
-					type = "Coresight CTI";
-					full = "(Cross Trigger)";
-					break;
-				case 0x907:
-					type = "Coresight ETB";
-					full = "(Trace Buffer)";
-					break;
-				case 0x908:
-					type = "Coresight CSTF";
-					full = "(Trace Funnel)";
-					break;
-				case 0x910:
-					type = "CoreSight ETM9";
-					full = "(Embedded Trace)";
-					break;
-				case 0x912:
-					type = "Coresight TPIU";
-					full = "(Trace Port Interface Unit)";
-					break;
-				case 0x921:
-					type = "Cortex-A8 ETM";
-					full = "(Embedded Trace)";
-					break;
-				case 0x922:
-					type = "Cortex-A8 CTI";
-					full = "(Cross Trigger)";
-					break;
-				case 0x923:
-					type = "Cortex-M3 TPIU";
-					full = "(Trace Port Interface Unit)";
-					break;
-				case 0x924:
-					type = "Cortex-M3 ETM";
-					full = "(Embedded Trace)";
-					break;
-				case 0xc08:
-					type = "Cortex-A8 Debug";
-					full = "(Debug Unit)";
-					break;
-				default:
-					type = "-*- unrecognized -*-";
-					full = "";
-					break;
-				}
-				command_print(cmd_ctx, "\t\tPart is %s %s",
-						type, full);
-			}
-			else
-			{
-				if (romentry)
-					command_print(cmd_ctx, "\t\tComponent not present");
-				else
-					command_print(cmd_ctx, "\t\tEnd of ROM table");
-			}
-			entry_offset += 4;
-		} while (romentry > 0);
-	}
-	else
-	{
-		command_print(cmd_ctx, "\tNo ROM table present");
-	}
-	dap_ap_select(swjdp, apselold);
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(handle_dap_info_command)
-{
-	struct target *target = get_current_target(CMD_CTX);
-	struct arm *arm = target_to_arm(target);
-	struct adiv5_dap *dap = arm->dap;
-	uint32_t apsel;
-
-	switch (CMD_ARGC) {
-	case 0:
-		apsel = dap->apsel;
-		break;
-	case 1:
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
-		break;
-	default:
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	return dap_info_command(CMD_CTX, dap, apsel);
-}
-
-COMMAND_HANDLER(dap_baseaddr_command)
-{
-	struct target *target = get_current_target(CMD_CTX);
-	struct arm *arm = target_to_arm(target);
-	struct adiv5_dap *dap = arm->dap;
-
-	uint32_t apsel, apselsave, baseaddr;
-	int retval;
-
-	apselsave = dap->apsel;
-	switch (CMD_ARGC) {
-	case 0:
-		apsel = dap->apsel;
-		break;
-	case 1:
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
-		/* AP address is in bits 31:24 of DP_SELECT */
-		if (apsel >= 256)
-			return ERROR_INVALID_ARGUMENTS;
-		break;
-	default:
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	if (apselsave != apsel)
-		dap_ap_select(dap, apsel);
-
-	/* NOTE:  assumes we're talking to a MEM-AP, which
-	 * has a base address.  There are other kinds of AP,
-	 * though they're not common for now.  This should
-	 * use the ID register to verify it's a MEM-AP.
-	 */
-	retval = dap_queue_ap_read(dap, AP_REG_BASE, &baseaddr);
-	retval = dap_run(dap);
-	if (retval != ERROR_OK)
-		return retval;
-
-	command_print(CMD_CTX, "0x%8.8" PRIx32, baseaddr);
-
-	if (apselsave != apsel)
-		dap_ap_select(dap, apselsave);
-
-	return retval;
-}
-
-COMMAND_HANDLER(dap_memaccess_command)
-{
-	struct target *target = get_current_target(CMD_CTX);
-	struct arm *arm = target_to_arm(target);
-	struct adiv5_dap *dap = arm->dap;
-
-	uint32_t memaccess_tck;
-
-	switch (CMD_ARGC) {
-	case 0:
-		memaccess_tck = dap->memaccess_tck;
-		break;
-	case 1:
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], memaccess_tck);
-		break;
-	default:
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-	dap->memaccess_tck = memaccess_tck;
-
-	command_print(CMD_CTX, "memory bus access delay set to %" PRIi32 " tck",
-			dap->memaccess_tck);
-
-	return ERROR_OK;
-}
-
-COMMAND_HANDLER(dap_apsel_command)
-{
-	struct target *target = get_current_target(CMD_CTX);
-	struct arm *arm = target_to_arm(target);
-	struct adiv5_dap *dap = arm->dap;
-
-	uint32_t apsel, apid;
-	int retval;
-
-	switch (CMD_ARGC) {
-	case 0:
-		apsel = 0;
-		break;
-	case 1:
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
-		/* AP address is in bits 31:24 of DP_SELECT */
-		if (apsel >= 256)
-			return ERROR_INVALID_ARGUMENTS;
-		break;
-	default:
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	dap_ap_select(dap, apsel);
-	retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
-	retval = dap_run(dap);
-	if (retval != ERROR_OK)
-		return retval;
-
-	command_print(CMD_CTX, "ap %" PRIi32 " selected, identification register 0x%8.8" PRIx32,
-			apsel, apid);
-
-	return retval;
-}
-
-COMMAND_HANDLER(dap_apid_command)
-{
-	struct target *target = get_current_target(CMD_CTX);
-	struct arm *arm = target_to_arm(target);
-	struct adiv5_dap *dap = arm->dap;
-
-	uint32_t apsel, apselsave, apid;
-	int retval;
-
-	apselsave = dap->apsel;
-	switch (CMD_ARGC) {
-	case 0:
-		apsel = dap->apsel;
-		break;
-	case 1:
-		COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], apsel);
-		/* AP address is in bits 31:24 of DP_SELECT */
-		if (apsel >= 256)
-			return ERROR_INVALID_ARGUMENTS;
-		break;
-	default:
-		return ERROR_COMMAND_SYNTAX_ERROR;
-	}
-
-	if (apselsave != apsel)
-		dap_ap_select(dap, apsel);
-
-	retval = dap_queue_ap_read(dap, AP_REG_IDR, &apid);
-	retval = dap_run(dap);
-	if (retval != ERROR_OK)
-		return retval;
-
-	command_print(CMD_CTX, "0x%8.8" PRIx32, apid);
-	if (apselsave != apsel)
-		dap_ap_select(dap, apselsave);
-
-	return retval;
-}
-
-static const struct command_registration dap_commands[] = {
-	{
-		.name = "info",
-		.handler = handle_dap_info_command,
-		.mode = COMMAND_EXEC,
-		.help = "display ROM table for MEM-AP "
-			"(default currently selected AP)",
-		.usage = "[ap_num]",
-	},
-	{
-		.name = "apsel",
-		.handler = dap_apsel_command,
-		.mode = COMMAND_EXEC,
-		.help = "Set the currently selected AP (default 0) "
-			"and display the result",
-		.usage = "[ap_num]",
-	},
-	{
-		.name = "apid",
-		.handler = dap_apid_command,
-		.mode = COMMAND_EXEC,
-		.help = "return ID register from AP "
-			"(default currently selected AP)",
-		.usage = "[ap_num]",
-	},
-	{
-		.name = "baseaddr",
-		.handler = dap_baseaddr_command,
-		.mode = COMMAND_EXEC,
-		.help = "return debug base address from MEM-AP "
-			"(default currently selected AP)",
-		.usage = "[ap_num]",
-	},
-	{
-		.name = "memaccess",
-		.handler = dap_memaccess_command,
-		.mode = COMMAND_EXEC,
-		.help = "set/get number of extra tck for MEM-AP memory "
-			"bus access [0-255]",
-		.usage = "[cycles]",
-	},
-	COMMAND_REGISTRATION_DONE
-};
-
-const struct command_registration dap_command_handlers[] = {
-	{
-		.name = "dap",
-		.mode = COMMAND_EXEC,
-		.help = "DAP command group",
-		.chain = dap_commands,
-	},
-	COMMAND_REGISTRATION_DONE
-};
-
-
-/*
- * This represents the bits which must be sent out on TMS/SWDIO to
- * switch a DAP implemented using an SWJ-DP module into SWD mode.
- * These bits are stored (and transmitted) LSB-first.
- *
- * See the DAP-Lite specification, section 2.2.5 for information
- * about making the debug link select SWD or JTAG.  (Similar info
- * is in a few other ARM documents.)
- */
-static const uint8_t jtag2swd_bitseq[] = {
-	/* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
-	 * putting both JTAG and SWD logic into reset state.
-	 */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-	/* Switching sequence enables SWD and disables JTAG
-	 * NOTE: bits in the DP's IDCODE may expose the need for
-	 * an old/deprecated sequence (0xb6 0xed).
-	 */
-	0x9e, 0xe7,
-	/* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
-	 * putting both JTAG and SWD logic into reset state.
-	 */
-	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
-};
-
-/**
- * Put the debug link into SWD mode, if the target supports it.
- * The link's initial mode may be either JTAG (for example,
- * with SWJ-DP after reset) or SWD.
- *
- * @param target Enters SWD mode (if possible).
- *
- * Note that targets using the JTAG-DP do not support SWD, and that
- * some targets which could otherwise support it may have have been
- * configured to disable SWD signaling
- *
- * @return ERROR_OK or else a fault code.
- */
-int dap_to_swd(struct target *target)
-{
-	int retval;
-
-	LOG_DEBUG("Enter SWD mode");
-
-	/* REVISIT it's nasty to need to make calls to a "jtag"
-	 * subsystem if the link isn't in JTAG mode...
-	 */
-
-	retval =  jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
-			jtag2swd_bitseq, TAP_INVALID);
-	if (retval == ERROR_OK)
-		retval = jtag_execute_queue();
-
-	/* REVISIT set up the DAP's ops vector for SWD mode. */
-
-	return retval;
-}
-
diff --git a/src/target/arm_adi_v5.c~ b/src/target/arm_adi_v5.c~
deleted file mode 100644
index 708e858..0000000
--- a/src/target/arm_adi_v5.c~
+++ /dev/null
@@ -1,1981 +0,0 @@
-/***************************************************************************
- *   Copyright (C) 2006 by Magnus Lundin                                   *
- *   lu...@ml...                                                    *
- *                                                                         *
- *   Copyright (C) 2008 by Spencer Oliver                                  *
- *   sp...@sp...                                                  *
- *                                                                         *
- *   Copyright (C) 2009 by Oyvind Harboe                                   *
- *   oyv...@zy...                                               *
- *                                                                         *
- *   Copyright (C) 2009-2010 by David Brownell                             *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program; if not, write to the                         *
- *   Free Software Foundation, Inc.,                                       *
- *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
- ***************************************************************************/
-
-/**
- * @file
- * This file implements support for the ARM Debug Interface version 5 (ADIv5)
- * debugging architecture.  Compared with previous versions, this includes
- * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for messag...
 
[truncated message content]

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-104-g36df240

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  36df240cea04990e8c18aa0b90bd63374f22dbd3 (commit)
      from  fccdfc1cd78ddfb687e0d1fc630c3fa10af2b5f9 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 36df240cea04990e8c18aa0b90bd63374f22dbd3
Author: Øyvind Harboe <oyv...@zy...>
Date:   Tue Mar 16 14:13:03 2010 +0100

    jtag: cut down on usage of unintended modification of global end state
    
    jtag_get/set_end_state() is now deprecated.
    
    There were lots of places in the code where the end state was
    unintentionally modified.
    
    The big Q is whether there were any places where the intention
    was to modify the end state. 0.5 is a long way off, so we'll
    get a fair amount of testing.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c
index 35fe806..732226f 100644
--- a/src/flash/nor/str9xpec.c
+++ b/src/flash/nor/str9xpec.c
@@ -69,7 +69,7 @@ static uint8_t str9xpec_isc_status(struct jtag_tap *tap)
 	field.in_value = &status;
 
 
-	jtag_add_dr_scan(tap, 1, &field, jtag_set_end_state(TAP_IDLE));
+	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 	jtag_execute_queue();
 
 	LOG_DEBUG("status: 0x%2.2x", status);
@@ -156,7 +156,7 @@ static int str9xpec_read_config(struct flash_bank *bank)
 	field.in_value = str9xpec_info->options;
 
 
-	jtag_add_dr_scan(tap, 1, &field, jtag_set_end_state(TAP_IDLE));
+	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 	jtag_execute_queue();
 
 	status = str9xpec_isc_status(tap);
@@ -302,7 +302,7 @@ static int str9xpec_blank_check(struct flash_bank *bank, int first, int last)
 	field.out_value = buffer;
 	field.in_value = NULL;
 
-	jtag_add_dr_scan(tap, 1, &field, jtag_set_end_state(TAP_IDLE));
+	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 	jtag_add_sleep(40000);
 
 	/* read blank check result */
@@ -406,7 +406,7 @@ static int str9xpec_erase_area(struct flash_bank *bank, int first, int last)
 	field.out_value = buffer;
 	field.in_value = NULL;
 
-	jtag_add_dr_scan(tap, 1, &field, jtag_set_end_state(TAP_IDLE));
+	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 	jtag_execute_queue();
 
 	jtag_add_sleep(10);
@@ -466,7 +466,7 @@ static int str9xpec_lock_device(struct flash_bank *bank)
 		field.out_value = NULL;
 		field.in_value = &status;
 
-		jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
+		jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 		jtag_execute_queue();
 
 	} while (!(status & ISC_STATUS_BUSY));
@@ -546,7 +546,7 @@ static int str9xpec_set_address(struct flash_bank *bank, uint8_t sector)
 	field.out_value = &sector;
 	field.in_value = NULL;
 
-	jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
+	jtag_add_dr_scan(tap, 1, &field, TAP_IRPAUSE);
 
 	return ERROR_OK;
 }
@@ -631,7 +631,7 @@ static int str9xpec_write(struct flash_bank *bank, uint8_t *buffer,
 			field.out_value = (buffer + bytes_written);
 			field.in_value = NULL;
 
-			jtag_add_dr_scan(tap, 1, &field, jtag_set_end_state(TAP_IDLE));
+			jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 
 			/* small delay before polling */
 			jtag_add_sleep(50);
@@ -643,7 +643,7 @@ static int str9xpec_write(struct flash_bank *bank, uint8_t *buffer,
 				field.out_value = NULL;
 				field.in_value = scanbuf;
 
-				jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
+				jtag_add_dr_scan(tap, 1, &field, TAP_IRPAUSE);
 				jtag_execute_queue();
 
 				status = buf_get_u32(scanbuf, 0, 8);
@@ -679,7 +679,7 @@ static int str9xpec_write(struct flash_bank *bank, uint8_t *buffer,
 		field.out_value = last_dword;
 		field.in_value = NULL;
 
-		jtag_add_dr_scan(tap, 1, &field, jtag_set_end_state(TAP_IDLE));
+		jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 
 		/* small delay before polling */
 		jtag_add_sleep(50);
@@ -691,7 +691,7 @@ static int str9xpec_write(struct flash_bank *bank, uint8_t *buffer,
 			field.out_value = NULL;
 			field.in_value = scanbuf;
 
-			jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
+			jtag_add_dr_scan(tap, 1, &field, TAP_IRPAUSE);
 			jtag_execute_queue();
 
 			status = buf_get_u32(scanbuf, 0, 8);
@@ -744,7 +744,7 @@ COMMAND_HANDLER(str9xpec_handle_part_id_command)
 	field.out_value = NULL;
 	field.in_value = buffer;
 
-	jtag_add_dr_scan(tap, 1, &field, jtag_set_end_state(TAP_IDLE));
+	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 	jtag_execute_queue();
 
 	idcode = buf_get_u32(buffer, 0, 32);
@@ -860,7 +860,7 @@ static int str9xpec_write_options(struct flash_bank *bank)
 	field.out_value = str9xpec_info->options;
 	field.in_value = NULL;
 
-	jtag_add_dr_scan(tap, 1, &field, jtag_set_end_state(TAP_IDLE));
+	jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
 
 	/* small delay before polling */
 	jtag_add_sleep(50);
@@ -872,7 +872,7 @@ static int str9xpec_write_options(struct flash_bank *bank)
 		field.out_value = NULL;
 		field.in_value = &status;
 
-		jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
+		jtag_add_dr_scan(tap, 1, &field, TAP_IRPAUSE);
 		jtag_execute_queue();
 
 	} while (!(status & ISC_STATUS_BUSY));
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 9792280..a09472a 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -743,7 +743,8 @@ void jtag_add_reset(int req_tlr_or_trst, int req_srst)
 	}
 }
 
-tap_state_t jtag_set_end_state(tap_state_t state)
+/* DEPRECATED! store such global state outside JTAG layer */
+void jtag_set_end_state(tap_state_t state)
 {
 	if ((state == TAP_DRSHIFT)||(state == TAP_IRSHIFT))
 	{
@@ -752,9 +753,9 @@ tap_state_t jtag_set_end_state(tap_state_t state)
 
 	if (state != TAP_INVALID)
 		cmd_queue_end_state = state;
-	return cmd_queue_end_state;
 }
 
+/* DEPRECATED! store such global state outside JTAG layer */
 tap_state_t jtag_get_end_state(void)
 {
 	return cmd_queue_end_state;
diff --git a/src/jtag/jtag.h b/src/jtag/jtag.h
index 0bbea5f..a92c986 100644
--- a/src/jtag/jtag.h
+++ b/src/jtag/jtag.h
@@ -552,15 +552,18 @@ void jtag_add_reset(int req_tlr_or_trst, int srst);
 
 
 /**
+ * DEPRECATED! store such global state outside JTAG layer
+ *
  * Function jtag_set_end_state
  *
  * Set a global variable to \a state if \a state != TAP_INVALID.
  *
- * Return the value of the global variable.
  */
-tap_state_t jtag_set_end_state(tap_state_t state);
+void jtag_set_end_state(tap_state_t state);
 
 /**
+ * DEPRECATED! store such global state outside JTAG layer
+ * 
  * Function jtag_get_end_state
  *
  * Return the value of the global variable for end state
diff --git a/src/pld/virtex2.c b/src/pld/virtex2.c
index 976535b..93509de 100644
--- a/src/pld/virtex2.c
+++ b/src/pld/virtex2.c
@@ -40,7 +40,7 @@ static int virtex2_set_instr(struct jtag_tap *tap, uint32_t new_instr)
 		buf_set_u32(field.out_value, 0, field.num_bits, new_instr);
 		field.in_value = NULL;
 
-		jtag_add_ir_scan(tap, &field, jtag_set_end_state(TAP_IDLE));
+		jtag_add_ir_scan(tap, &field, TAP_IDLE);
 
 		free(field.out_value);
 	}
@@ -67,7 +67,7 @@ static int virtex2_send_32(struct pld_device *pld_device,
 
 	virtex2_set_instr(virtex2_info->tap, 0x5); /* CFG_IN */
 
-	jtag_add_dr_scan(virtex2_info->tap, 1, &scan_field, jtag_set_end_state(TAP_DRPAUSE));
+	jtag_add_dr_scan(virtex2_info->tap, 1, &scan_field, TAP_DRPAUSE);
 
 	free(values);
 
@@ -96,7 +96,7 @@ static int virtex2_receive_32(struct pld_device *pld_device,
 	{
 		scan_field.in_value = (uint8_t *)words;
 
-		jtag_add_dr_scan(virtex2_info->tap, 1, &scan_field, jtag_set_end_state(TAP_DRPAUSE));
+		jtag_add_dr_scan(virtex2_info->tap, 1, &scan_field, TAP_DRPAUSE);
 
 		jtag_add_callback(virtexflip32, (jtag_callback_data_t)words);
 
@@ -155,18 +155,18 @@ static int virtex2_load(struct pld_device *pld_device, const char *filename)
 	field.num_bits = bit_file.length * 8;
 	field.out_value = bit_file.data;
 
-	jtag_add_dr_scan(virtex2_info->tap, 1, &field, jtag_set_end_state(TAP_DRPAUSE));
+	jtag_add_dr_scan(virtex2_info->tap, 1, &field, TAP_DRPAUSE);
 	jtag_execute_queue();
 
 	jtag_add_tlr();
 
 	jtag_set_end_state(TAP_IDLE);
 	virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
-	jtag_add_runtest(13, jtag_set_end_state(TAP_IDLE));
+	jtag_add_runtest(13, TAP_IDLE);
 	virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
 	virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
 	virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */
-	jtag_add_runtest(13, jtag_set_end_state(TAP_IDLE));
+	jtag_add_runtest(13, TAP_IDLE);
 	virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */
 	jtag_execute_queue();
 
diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index eac83b7..091b77a 100644
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -107,7 +107,7 @@ int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
 	fields[1].out_value = outvalue;
 	fields[1].in_value = invalue;
 
-	jtag_add_dr_scan(jtag_info->tap, 2, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE);
 
 	/* Add specified number of tck clocks after starting memory bus
 	 * access, giving the hardware time to complete the access.
@@ -119,7 +119,7 @@ int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
 				|| ((reg_addr & 0xF0) == AP_REG_BD0))
 			&& (swjdp->memaccess_tck != 0))
 		jtag_add_runtest(swjdp->memaccess_tck,
-				jtag_set_end_state(TAP_IDLE));
+				TAP_IDLE);
 
 	return jtag_get_error();
 }
@@ -341,7 +341,7 @@ static int jtag_idcode_q_read(struct adiv5_dap *dap,
 	fields[0].out_value = NULL;
 	fields[0].in_value = (void *) data;
 
-	jtag_add_dr_scan(jtag_info->tap, 1, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 1, fields, TAP_IDLE);
 	retval = jtag_get_error();
 	if (retval != ERROR_OK)
 		return retval;
diff --git a/src/target/arm11_dbgtap.c b/src/target/arm11_dbgtap.c
index 2b7b4e4..18bf255 100644
--- a/src/target/arm11_dbgtap.c
+++ b/src/target/arm11_dbgtap.c
@@ -482,7 +482,7 @@ int arm11_run_instr_data_to_core(struct arm11_common * arm11, uint32_t opcode, u
 		{
 			Data	    = *data;
 
-			arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, jtag_set_end_state(TAP_IDLE));
+			arm11_add_dr_scan_vc(arm11->arm.target->tap, ARRAY_SIZE(chain5_fields), chain5_fields, TAP_IDLE);
 
 			CHECK_RETVAL(jtag_execute_queue());
 
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 79eb79b..71d4a01 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -75,15 +75,15 @@ static int arm720t_scan_cp15(struct target *target,
 	if (in)
 	{
 		fields[1].in_value = (uint8_t *)in;
-		jtag_add_dr_scan(jtag_info->tap, 2, fields, jtag_get_end_state());
+		jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
 		jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
 	} else
 	{
-		jtag_add_dr_scan(jtag_info->tap, 2, fields, jtag_get_end_state());
+		jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
 	}
 
 	if (clock)
-		jtag_add_runtest(0, jtag_get_end_state());
+		jtag_add_runtest(0, TAP_DRPAUSE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index d1e7a93..c6a08cf 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1750,7 +1750,7 @@ int arm7_9_restart_core(struct target *target)
 	}
 	arm_jtag_set_instr(jtag_info, 0x4, NULL);
 
-	jtag_add_runtest(1, jtag_set_end_state(TAP_IDLE));
+	jtag_add_runtest(1, TAP_IDLE);
 	return jtag_execute_queue();
 }
 
diff --git a/src/target/arm7tdmi.c b/src/target/arm7tdmi.c
index ab8a3e5..2d6d68f 100644
--- a/src/target/arm7tdmi.c
+++ b/src/target/arm7tdmi.c
@@ -72,7 +72,7 @@ static int arm7tdmi_examine_debug_reason(struct target *target)
 		}
 		arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 
-		jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, jtag_set_end_state(TAP_DRPAUSE));
+		jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE);
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
@@ -83,7 +83,7 @@ static int arm7tdmi_examine_debug_reason(struct target *target)
 		fields[1].in_value = NULL;
 		fields[1].out_value = databus;
 
-		jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, jtag_set_end_state(TAP_DRPAUSE));
+		jtag_add_dr_scan(arm7_9->jtag_info.tap, 2, fields, TAP_DRPAUSE);
 
 		if (breakpoint & 1)
 			target->debug_reason = DBG_REASON_WATCHPOINT;
@@ -147,11 +147,11 @@ static int arm7tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
 	fields[1].out_value = NULL;
 	fields[1].in_value = (uint8_t *)in;
 
-	jtag_add_dr_scan(jtag_info->tap, 2, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
 
 	jtag_add_callback(arm7flip32, (jtag_callback_data_t)in);
 
-	jtag_add_runtest(0, jtag_get_end_state());
+	jtag_add_runtest(0, TAP_DRPAUSE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -232,11 +232,11 @@ static int arm7tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
 	fields[1].out_value = NULL;
 	jtag_alloc_in_value32(&fields[1]);
 
-	jtag_add_dr_scan(jtag_info->tap, 2, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_DRPAUSE);
 
 	jtag_add_callback4(arm7endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[1].in_value);
 
-	jtag_add_runtest(0, jtag_get_end_state());
+	jtag_add_runtest(0, TAP_DRPAUSE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 {
diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index a7816fd..68d3997 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -111,11 +111,11 @@ static int arm920t_read_cp15_physical(struct target *target,
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-	jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
 	fields[1].in_value = (uint8_t *)value;
 
-	jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
 	jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
 
@@ -162,7 +162,7 @@ static int arm920t_write_cp15_physical(struct target *target,
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-	jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
@@ -214,7 +214,7 @@ static int arm920t_execute_cp15(struct target *target, uint32_t cp15_opcode,
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-	jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
 	arm9tdmi_clock_out(jtag_info, arm_opcode, 0, NULL, 0);
 	arm9tdmi_clock_out(jtag_info, ARMV4_5_NOP, 0, NULL, 1);
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index f4c4774..ea951e5 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -86,7 +86,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-	jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
 	long long then = timeval_ms();
 
@@ -95,7 +95,7 @@ static int arm926ejs_cp15_read(struct target *target, uint32_t op1, uint32_t op2
 		/* rescan with NOP, to wait for the access to complete */
 		access = 0;
 		nr_w_buf = 0;
-		jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
+		jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
 		jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
 
@@ -175,7 +175,7 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
 	fields[3].out_value = &nr_w_buf;
 	fields[3].in_value = NULL;
 
-	jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 
 	long long then = timeval_ms();
 
@@ -184,7 +184,7 @@ static int arm926ejs_cp15_write(struct target *target, uint32_t op1, uint32_t op
 		/* rescan with NOP, to wait for the access to complete */
 		access = 0;
 		nr_w_buf = 0;
-		jtag_add_dr_scan(jtag_info->tap, 4, fields, jtag_get_end_state());
+		jtag_add_dr_scan(jtag_info->tap, 4, fields, TAP_IDLE);
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
diff --git a/src/target/arm966e.c b/src/target/arm966e.c
index 4f47644..67678c1 100644
--- a/src/target/arm966e.c
+++ b/src/target/arm966e.c
@@ -106,11 +106,11 @@ static int arm966e_read_cp15(struct target *target, int reg_addr, uint32_t *valu
 	fields[2].out_value = &nr_w_buf;
 	fields[2].in_value = NULL;
 
-	jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 
 	fields[1].in_value = (uint8_t *)value;
 
-	jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 
 	jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)value);
 
@@ -158,7 +158,7 @@ int arm966e_write_cp15(struct target *target, int reg_addr, uint32_t value)
 	fields[2].out_value = &nr_w_buf;
 	fields[2].in_value = NULL;
 
-	jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_IDLE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	LOG_DEBUG("addr: 0x%x value: %8.8x", reg_addr, value);
diff --git a/src/target/arm9tdmi.c b/src/target/arm9tdmi.c
index f3935a3..f091188 100644
--- a/src/target/arm9tdmi.c
+++ b/src/target/arm9tdmi.c
@@ -107,7 +107,7 @@ int arm9tdmi_examine_debug_reason(struct target *target)
 		}
 		arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, NULL);
 
-		jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, jtag_set_end_state(TAP_DRPAUSE));
+		jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, TAP_DRPAUSE);
 		if ((retval = jtag_execute_queue()) != ERROR_OK)
 		{
 			return retval;
@@ -120,7 +120,7 @@ int arm9tdmi_examine_debug_reason(struct target *target)
 		fields[2].in_value = NULL;
 		fields[2].out_value = instructionbus;
 
-		jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, jtag_set_end_state(TAP_DRPAUSE));
+		jtag_add_dr_scan(arm7_9->jtag_info.tap, 3, fields, TAP_DRPAUSE);
 
 		if (debug_reason & 0x4)
 			if (debug_reason & 0x2)
@@ -177,13 +177,13 @@ int arm9tdmi_clock_out(struct arm_jtag *jtag_info, uint32_t instr,
 	if (in)
 	{
 		fields[0].in_value = (uint8_t *)in;
-		jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
+		jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE);
 
 		jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
 	}
 	else
 	{
-		jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
+		jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE);
 	}
 
 	jtag_add_runtest(0, jtag_get_end_state());
@@ -233,11 +233,11 @@ int arm9tdmi_clock_data_in(struct arm_jtag *jtag_info, uint32_t *in)
 	fields[2].out_value = NULL;
 	fields[2].in_value = NULL;
 
-	jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE);
 
 	jtag_add_callback(arm_le_to_h_u32, (jtag_callback_data_t)in);
 
-	jtag_add_runtest(0, jtag_get_end_state());
+	jtag_add_runtest(0, TAP_DRPAUSE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	{
@@ -300,11 +300,11 @@ int arm9tdmi_clock_data_in_endianness(struct arm_jtag *jtag_info,
 	fields[2].out_value = NULL;
 	fields[2].in_value = NULL;
 
-	jtag_add_dr_scan(jtag_info->tap, 3, fields, jtag_get_end_state());
+	jtag_add_dr_scan(jtag_info->tap, 3, fields, TAP_DRPAUSE);
 
 	jtag_add_callback4(arm9endianness, (jtag_callback_data_t)in, (jtag_callback_data_t)size, (jtag_callback_data_t)be, (jtag_callback_data_t)fields[0].in_value);
 
-	jtag_add_runtest(0, jtag_get_end_state());
+	jtag_add_runtest(0, TAP_DRPAUSE);
 
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
 	{
diff --git a/src/target/arm_adi_v5.c.orig b/src/target/arm_adi_v5.c.orig
new file mode 100644
index 0000000..708e858
--- /dev/null
+++ b/src/target/arm_adi_v5.c.orig
@@ -0,0 +1,1981 @@
+/***************************************************************************
+ *   Copyright (C) 2006 by Magnus Lundin                                   *
+ *   lu...@ml...                                                    *
+ *                                                                         *
+ *   Copyright (C) 2008 by Spencer Oliver                                  *
+ *   sp...@sp...                                                  *
+ *                                                                         *
+ *   Copyright (C) 2009 by Oyvind Harboe                                   *
+ *   oyv...@zy...                                               *
+ *                                                                         *
+ *   Copyright (C) 2009-2010 by David Brownell                             *
+ *                                                                         *
+ *   This program is free software; you can redistribute it and/or modify  *
+ *   it under the terms of the GNU General Public License as published by  *
+ *   the Free Software Foundation; either version 2 of the License, or     *
+ *   (at your option) any later version.                                   *
+ *                                                                         *
+ *   This program is distributed in the hope that it will be useful,       *
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
+ *   GNU General Public License for more details.                          *
+ *                                                                         *
+ *   You should have received a copy of the GNU General Public License     *
+ *   along with this program; if not, write to the                         *
+ *   Free Software Foundation, Inc.,                                       *
+ *   59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.             *
+ ***************************************************************************/
+
+/**
+ * @file
+ * This file implements support for the ARM Debug Interface version 5 (ADIv5)
+ * debugging architecture.  Compared with previous versions, this includes
+ * a low pin-count Serial Wire Debug (SWD) alternative to JTAG for message
+ * transport, and focusses on memory mapped resources as defined by the
+ * CoreSight architecture.
+ *
+ * A key concept in ADIv5 is the Debug Access Port, or DAP.  A DAP has two
+ * basic components:  a Debug Port (DP) transporting messages to and from a
+ * debugger, and an Access Port (AP) accessing resources.  Three types of DP
+ * are defined.  One uses only JTAG for communication, and is called JTAG-DP.
+ * One uses only SWD for communication, and is called SW-DP.  The third can
+ * use either SWD or JTAG, and is called SWJ-DP.  The most common type of AP
+ * is used to access memory mapped resources and is called a MEM-AP.  Also a
+ * JTAG-AP is also defined, bridging to JTAG resources; those are uncommon.
+ *
+ * This programming interface allows DAP pipelined operations through a
+ * transaction queue.  This primarily affects AP operations (such as using
+ * a MEM-AP to access memory or registers).  If the current transaction has
+ * not finished by the time the next one must begin, and the ORUNDETECT bit
+ * is set in the DP_CTRL_STAT register, the SSTICKYORUN status is set and
+ * further AP operations will fail.  There are two basic methods to avoid
+ * such overrun errors.  One involves polling for status instead of using
+ * transaction piplining.  The other involves adding delays to ensure the
+ * AP has enough time to complete one operation before starting the next
+ * one.  (For JTAG these delays are controlled by memaccess_tck.)
+ */
+
+/*
+ * Relevant specifications from ARM include:
+ *
+ * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031A
+ * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
+ *
+ * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D
+ * Cortex-M3(tm) TRM, ARM DDI 0337G
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "arm.h"
+#include "arm_adi_v5.h"
+#include <helper/time_support.h>
+
+
+/* ARM ADI Specification requires at least 10 bits used for TAR autoincrement  */
+
+/*
+	uint32_t tar_block_size(uint32_t address)
+	Return the largest block starting at address that does not cross a tar block size alignment boundary
+*/
+static uint32_t max_tar_block_size(uint32_t tar_autoincr_block, uint32_t address)
+{
+	return (tar_autoincr_block - ((tar_autoincr_block - 1) & address)) >> 2;
+}
+
+/***************************************************************************
+ *                                                                         *
+<<<<<<< HEAD:src/target/arm_adi_v5.c
+=======
+ * DPACC and APACC scanchain access through JTAG-DP                        *
+ *                                                                         *
+***************************************************************************/
+
+/**
+ * Scan DPACC or APACC using target ordered uint8_t buffers.  No endianness
+ * conversions are performed.  See section 4.4.3 of the ADIv5 spec, which
+ * discusses operations which access these registers.
+ *
+ * Note that only one scan is performed.  If RnW is set, a separate scan
+ * will be needed to collect the data which was read; the "invalue" collects
+ * the posted result of a preceding operation, not the current one.
+ *
+ * @param swjdp the DAP
+ * @param instr JTAG_DP_APACC (AP access) or JTAG_DP_DPACC (DP access)
+ * @param reg_addr two significant bits; A[3:2]; for APACC access, the
+ *	SELECT register has more addressing bits.
+ * @param RnW false iff outvalue will be written to the DP or AP
+ * @param outvalue points to a 32-bit (little-endian) integer
+ * @param invalue NULL, or points to a 32-bit (little-endian) integer
+ * @param ack points to where the three bit JTAG_ACK_* code will be stored
+ */
+static int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
+		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
+		uint8_t *outvalue, uint8_t *invalue, uint8_t *ack)
+{
+	struct arm_jtag *jtag_info = swjdp->jtag_info;
+	struct scan_field fields[2];
+	uint8_t out_addr_buf;
+
+	jtag_set_end_state(TAP_IDLE);
+	arm_jtag_set_instr(jtag_info, instr, NULL);
+
+	/* Scan out a read or write operation using some DP or AP register.
+	 * For APACC access with any sticky error flag set, this is discarded.
+	 */
+	fields[0].num_bits = 3;
+	buf_set_u32(&out_addr_buf, 0, 3, ((reg_addr >> 1) & 0x6) | (RnW & 0x1));
+	fields[0].out_value = &out_addr_buf;
+	fields[0].in_value = ack;
+
+	/* NOTE: if we receive JTAG_ACK_WAIT, the previous operation did not
+	 * complete; data we write is discarded, data we read is unpredictable.
+	 * When overrun detect is active, STICKYORUN is set.
+	 */
+
+	fields[1].num_bits = 32;
+	fields[1].out_value = outvalue;
+	fields[1].in_value = invalue;
+
+	jtag_add_dr_scan(jtag_info->tap, 2, fields, TAP_IDLE);
+
+	/* Add specified number of tck clocks after starting memory bus
+	 * access, giving the hardware time to complete the access.
+	 * They provide more time for the (MEM) AP to complete the read ...
+	 * See "Minimum Response Time" for JTAG-DP, in the ADIv5 spec.
+	 */
+	if ((instr == JTAG_DP_APACC)
+			&& ((reg_addr == AP_REG_DRW)
+				|| ((reg_addr & 0xF0) == AP_REG_BD0))
+			&& (swjdp->memaccess_tck != 0))
+		jtag_add_runtest(swjdp->memaccess_tck,
+				TAP_IDLE);
+
+	return jtag_get_error();
+}
+
+/**
+ * Scan DPACC or APACC out and in from host ordered uint32_t buffers.
+ * This is exactly like adi_jtag_dp_scan(), except that endianness
+ * conversions are performed (so the types of invalue and outvalue
+ * must be different).
+ */
+static int adi_jtag_dp_scan_u32(struct adiv5_dap *swjdp,
+		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
+		uint32_t outvalue, uint32_t *invalue, uint8_t *ack)
+{
+	uint8_t out_value_buf[4];
+	int retval;
+
+	buf_set_u32(out_value_buf, 0, 32, outvalue);
+
+	retval = adi_jtag_dp_scan(swjdp, instr, reg_addr, RnW,
+			out_value_buf, (uint8_t *)invalue, ack);
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (invalue)
+		jtag_add_callback(arm_le_to_h_u32,
+				(jtag_callback_data_t) invalue);
+
+	return retval;
+}
+
+/**
+ * Utility to write AP registers.
+ */
+static inline int adi_jtag_ap_write_check(struct adiv5_dap *dap,
+		uint8_t reg_addr, uint8_t *outvalue)
+{
+	return adi_jtag_dp_scan(dap, JTAG_DP_APACC, reg_addr, DPAP_WRITE,
+			outvalue, NULL, NULL);
+}
+
+static int adi_jtag_scan_inout_check_u32(struct adiv5_dap *swjdp,
+		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
+		uint32_t outvalue, uint32_t *invalue)
+{
+	int retval;
+
+	/* Issue the read or write */
+	retval = adi_jtag_dp_scan_u32(swjdp, instr, reg_addr,
+			RnW, outvalue, NULL, NULL);
+	if (retval != ERROR_OK)
+		return retval;
+
+	/* For reads,  collect posted value; RDBUFF has no other effect.
+	 * Assumes read gets acked with OK/FAULT, and CTRL_STAT says "OK".
+	 */
+	if ((RnW == DPAP_READ) && (invalue != NULL))
+		retval = adi_jtag_dp_scan_u32(swjdp, JTAG_DP_DPACC,
+				DP_RDBUFF, DPAP_READ, 0, invalue, &swjdp->ack);
+	return retval;
+}
+
+static int jtagdp_transaction_endcheck(struct adiv5_dap *swjdp)
+{
+	int retval;
+	uint32_t ctrlstat;
+
+	/* too expensive to call keep_alive() here */
+
+#if 0
+	/* Danger!!!! BROKEN!!!! */
+	adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+			DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+	/* Danger!!!! BROKEN!!!! Why will jtag_execute_queue() fail here????
+	R956 introduced the check on return value here and now Michael Schwingen reports
+	that this code no longer works....
+
+	https://lists.berlios.de/pipermail/openocd-development/2008-September/003107.html
+	*/
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		LOG_ERROR("BUG: Why does this fail the first time????");
+	}
+	/* Why??? second time it works??? */
+#endif
+
+	/* Post CTRL/STAT read; discard any previous posted read value
+	 * but collect its ACK status.
+	 */
+	adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+			DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
+		return retval;
+
+	swjdp->ack = swjdp->ack & 0x7;
+
+	/* common code path avoids calling timeval_ms() */
+	if (swjdp->ack != JTAG_ACK_OK_FAULT)
+	{
+		long long then = timeval_ms();
+
+		while (swjdp->ack != JTAG_ACK_OK_FAULT)
+		{
+			if (swjdp->ack == JTAG_ACK_WAIT)
+			{
+				if ((timeval_ms()-then) > 1000)
+				{
+					/* NOTE:  this would be a good spot
+					 * to use JTAG_DP_ABORT.
+					 */
+					LOG_WARNING("Timeout (1000ms) waiting "
+						"for ACK=OK/FAULT "
+						"in JTAG-DP transaction");
+					return ERROR_JTAG_DEVICE_ERROR;
+				}
+			}
+			else
+			{
+				LOG_WARNING("Invalid ACK %#x "
+						"in JTAG-DP transaction",
+						swjdp->ack);
+				return ERROR_JTAG_DEVICE_ERROR;
+			}
+
+			adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+			if ((retval = dap_run(swjdp)) != ERROR_OK)
+				return retval;
+			swjdp->ack = swjdp->ack & 0x7;
+		}
+	}
+
+	/* REVISIT also STICKYCMP, for pushed comparisons (nyet used) */
+
+	/* Check for STICKYERR and STICKYORUN */
+	if (ctrlstat & (SSTICKYORUN | SSTICKYERR))
+	{
+		LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
+		/* Check power to debug regions */
+		if ((ctrlstat & 0xf0000000) != 0xf0000000)
+			 ahbap_debugport_init(swjdp);
+		else
+		{
+			uint32_t mem_ap_csw, mem_ap_tar;
+
+			/* Maybe print information about last intended
+			 * MEM-AP access; but not if autoincrementing.
+			 * *Real* CSW and TAR values are always shown.
+			 */
+			if (swjdp->ap_tar_value != (uint32_t) -1)
+				LOG_DEBUG("MEM-AP Cached values: "
+					"ap_bank 0x%" PRIx32
+					", ap_csw 0x%" PRIx32
+					", ap_tar 0x%" PRIx32,
+					swjdp->ap_bank_value,
+					swjdp->ap_csw_value,
+					swjdp->ap_tar_value);
+
+			if (ctrlstat & SSTICKYORUN)
+				LOG_ERROR("JTAG-DP OVERRUN - check clock, "
+					"memaccess, or reduce jtag speed");
+
+			if (ctrlstat & SSTICKYERR)
+				LOG_ERROR("JTAG-DP STICKY ERROR");
+
+			/* Clear Sticky Error Bits */
+			adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+					DP_CTRL_STAT, DPAP_WRITE,
+					swjdp->dp_ctrl_stat | SSTICKYORUN
+						| SSTICKYERR, NULL);
+			adi_jtag_scan_inout_check_u32(swjdp, JTAG_DP_DPACC,
+					DP_CTRL_STAT, DPAP_READ, 0, &ctrlstat);
+			if ((retval = dap_run(swjdp)) != ERROR_OK)
+				return retval;
+
+			LOG_DEBUG("jtag-dp: CTRL/STAT 0x%" PRIx32, ctrlstat);
+
+			retval = dap_queue_ap_read(swjdp,
+					AP_REG_CSW, &mem_ap_csw);
+			if (retval != ERROR_OK)
+				return retval;
+
+			retval = dap_queue_ap_read(swjdp,
+					AP_REG_TAR, &mem_ap_tar);
+			if (retval != ERROR_OK)
+				return retval;
+
+			if ((retval = dap_run(swjdp)) != ERROR_OK)
+				return retval;
+			LOG_ERROR("MEM_AP_CSW 0x%" PRIx32 ", MEM_AP_TAR 0x%"
+					PRIx32, mem_ap_csw, mem_ap_tar);
+
+		}
+		if ((retval = dap_run(swjdp)) != ERROR_OK)
+			return retval;
+		return ERROR_JTAG_DEVICE_ERROR;
+	}
+
+	return ERROR_OK;
+}
+
+/***************************************************************************
+ *                                                                         *
+>>>>>>> jtag: cut down on usage of unintended modification of global end state:src/target/arm_adi_v5.c
+ * DP and MEM-AP  register access  through APACC and DPACC                 *
+ *                                                                         *
+***************************************************************************/
+
+/**
+ * Select one of the APs connected to the specified DAP.  The
+ * selection is implicitly used with future AP transactions.
+ * This is a NOP if the specified AP is already selected.
+ *
+ * @param swjdp The DAP
+ * @param apsel Number of the AP to (implicitly) use with further
+ *	transactions.  This normally identifies a MEM-AP.
+ */
+void dap_ap_select(struct adiv5_dap *swjdp,uint8_t apsel)
+{
+	uint32_t select = (apsel << 24) & 0xFF000000;
+
+	if (select != swjdp->apsel)
+	{
+		swjdp->apsel = select;
+		/* Switching AP invalidates cached values.
+		 * Values MUST BE UPDATED BEFORE AP ACCESS.
+		 */
+		swjdp->ap_bank_value = -1;
+		swjdp->ap_csw_value = -1;
+		swjdp->ap_tar_value = -1;
+	}
+}
+
+/**
+ * Queue transactions setting up transfer parameters for the
+ * currently selected MEM-AP.
+ *
+ * Subsequent transfers using registers like AP_REG_DRW or AP_REG_BD2
+ * initiate data reads or writes using memory or peripheral addresses.
+ * If the CSW is configured for it, the TAR may be automatically
+ * incremented after each transfer.
+ *
+ * @todo Rename to reflect it being specifically a MEM-AP function.
+ *
+ * @param swjdp The DAP connected to the MEM-AP.
+ * @param csw MEM-AP Control/Status Word (CSW) register to assign.  If this
+ *	matches the cached value, the register is not changed.
+ * @param tar MEM-AP Transfer Address Register (TAR) to assign.  If this
+ *	matches the cached address, the register is not changed.
+ *
+ * @return ERROR_OK if the transaction was properly queued, else a fault code.
+ */
+int dap_setup_accessport(struct adiv5_dap *swjdp, uint32_t csw, uint32_t tar)
+{
+	int retval;
+
+	csw = csw | CSW_DBGSWENABLE | CSW_MASTER_DEBUG | CSW_HPROT;
+	if (csw != swjdp->ap_csw_value)
+	{
+		/* LOG_DEBUG("DAP: Set CSW %x",csw); */
+		retval = dap_queue_ap_write(swjdp, AP_REG_CSW, csw);
+		if (retval != ERROR_OK)
+			return retval;
+		swjdp->ap_csw_value = csw;
+	}
+	if (tar != swjdp->ap_tar_value)
+	{
+		/* LOG_DEBUG("DAP: Set TAR %x",tar); */
+		retval = dap_queue_ap_write(swjdp, AP_REG_TAR, tar);
+		if (retval != ERROR_OK)
+			return retval;
+		swjdp->ap_tar_value = tar;
+	}
+	/* Disable TAR cache when autoincrementing */
+	if (csw & CSW_ADDRINC_MASK)
+		swjdp->ap_tar_value = -1;
+	return ERROR_OK;
+}
+
+/**
+ * Asynchronous (queued) read of a word from memory or a system register.
+ *
+ * @param swjdp The DAP connected to the MEM-AP performing the read.
+ * @param address Address of the 32-bit word to read; it must be
+ *	readable by the currently selected MEM-AP.
+ * @param value points to where the word will be stored when the
+ *	transaction queue is flushed (assuming no errors).
+ *
+ * @return ERROR_OK for success.  Otherwise a fault code.
+ */
+int mem_ap_read_u32(struct adiv5_dap *swjdp, uint32_t address,
+		uint32_t *value)
+{
+	int retval;
+
+	/* Use banked addressing (REG_BDx) to avoid some link traffic
+	 * (updating TAR) when reading several consecutive addresses.
+	 */
+	retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
+			address & 0xFFFFFFF0);
+	if (retval != ERROR_OK)
+		return retval;
+
+	return dap_queue_ap_read(swjdp, AP_REG_BD0 | (address & 0xC), value);
+}
+
+/**
+ * Synchronous read of a word from memory or a system register.
+ * As a side effect, this flushes any queued transactions.
+ *
+ * @param swjdp The DAP connected to the MEM-AP performing the read.
+ * @param address Address of the 32-bit word to read; it must be
+ *	readable by the currently selected MEM-AP.
+ * @param value points to where the result will be stored.
+ *
+ * @return ERROR_OK for success; *value holds the result.
+ * Otherwise a fault code.
+ */
+int mem_ap_read_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
+		uint32_t *value)
+{
+	int retval;
+
+	retval = mem_ap_read_u32(swjdp, address, value);
+	if (retval != ERROR_OK)
+		return retval;
+
+	return dap_run(swjdp);
+}
+
+/**
+ * Asynchronous (queued) write of a word to memory or a system register.
+ *
+ * @param swjdp The DAP connected to the MEM-AP.
+ * @param address Address to be written; it must be writable by
+ *	the currently selected MEM-AP.
+ * @param value Word that will be written to the address when transaction
+ *	queue is flushed (assuming no errors).
+ *
+ * @return ERROR_OK for success.  Otherwise a fault code.
+ */
+int mem_ap_write_u32(struct adiv5_dap *swjdp, uint32_t address,
+		uint32_t value)
+{
+	int retval;
+
+	/* Use banked addressing (REG_BDx) to avoid some link traffic
+	 * (updating TAR) when writing several consecutive addresses.
+	 */
+	retval = dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_OFF,
+			address & 0xFFFFFFF0);
+	if (retval != ERROR_OK)
+		return retval;
+
+	return dap_queue_ap_write(swjdp, AP_REG_BD0 | (address & 0xC),
+			value);
+}
+
+/**
+ * Synchronous write of a word to memory or a system register.
+ * As a side effect, this flushes any queued transactions.
+ *
+ * @param swjdp The DAP connected to the MEM-AP.
+ * @param address Address to be written; it must be writable by
+ *	the currently selected MEM-AP.
+ * @param value Word that will be written.
+ *
+ * @return ERROR_OK for success; the data was written.  Otherwise a fault code.
+ */
+int mem_ap_write_atomic_u32(struct adiv5_dap *swjdp, uint32_t address,
+		uint32_t value)
+{
+	int retval = mem_ap_write_u32(swjdp, address, value);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	return dap_run(swjdp);
+}
+
+/*****************************************************************************
+*                                                                            *
+* mem_ap_write_buf(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address) *
+*                                                                            *
+* Write a buffer in target order (little endian)                             *
+*                                                                            *
+*****************************************************************************/
+int mem_ap_write_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
+{
+	int wcount, blocksize, writecount, errorcount = 0, retval = ERROR_OK;
+	uint32_t adr = address;
+	uint8_t* pBuffer = buffer;
+
+	count >>= 2;
+	wcount = count;
+
+	/* if we have an unaligned access - reorder data */
+	if (adr & 0x3u)
+	{
+		for (writecount = 0; writecount < count; writecount++)
+		{
+			int i;
+			uint32_t outvalue;
+			memcpy(&outvalue, pBuffer, sizeof(uint32_t));
+
+			for (i = 0; i < 4; i++)
+			{
+				*((uint8_t*)pBuffer + (adr & 0x3)) = outvalue;
+				outvalue >>= 8;
+				adr++;
+			}
+			pBuffer += sizeof(uint32_t);
+		}
+	}
+
+	while (wcount > 0)
+	{
+		/* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
+		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+		if (wcount < blocksize)
+			blocksize = wcount;
+
+		/* handle unaligned data at 4k boundary */
+		if (blocksize == 0)
+			blocksize = 1;
+
+		dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE, address);
+
+		for (writecount = 0; writecount < blocksize; writecount++)
+		{
+			retval = dap_queue_ap_write(swjdp, AP_REG_DRW,
+				*(uint32_t *) (buffer + 4 * writecount));
+			if (retval != ERROR_OK)
+				break;
+		}
+
+		if (dap_run(swjdp) == ERROR_OK)
+		{
+			wcount = wcount - blocksize;
+			address = address + 4 * blocksize;
+			buffer = buffer + 4 * blocksize;
+		}
+		else
+		{
+			errorcount++;
+		}
+
+		if (errorcount > 1)
+		{
+			LOG_WARNING("Block write error address 0x%" PRIx32 ", wcount 0x%x", address, wcount);
+			/* REVISIT return the *actual* fault code */
+			return ERROR_JTAG_DEVICE_ERROR;
+		}
+	}
+
+	return retval;
+}
+
+static int mem_ap_write_buf_packed_u16(struct adiv5_dap *swjdp,
+		uint8_t *buffer, int count, uint32_t address)
+{
+	int retval = ERROR_OK;
+	int wcount, blocksize, writecount, i;
+
+	wcount = count >> 1;
+
+	while (wcount > 0)
+	{
+		int nbytes;
+
+		/* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
+		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+
+		if (wcount < blocksize)
+			blocksize = wcount;
+
+		/* handle unaligned data at 4k boundary */
+		if (blocksize == 0)
+			blocksize = 1;
+
+		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+		writecount = blocksize;
+
+		do
+		{
+			nbytes = MIN((writecount << 1), 4);
+
+			if (nbytes < 4)
+			{
+				if (mem_ap_write_buf_u16(swjdp, buffer,
+						nbytes, address) != ERROR_OK)
+				{
+					LOG_WARNING("Block write error address "
+						"0x%" PRIx32 ", count 0x%x",
+						address, count);
+					return ERROR_JTAG_DEVICE_ERROR;
+				}
+
+				address += nbytes >> 1;
+			}
+			else
+			{
+				uint32_t outvalue;
+				memcpy(&outvalue, buffer, sizeof(uint32_t));
+
+				for (i = 0; i < nbytes; i++)
+				{
+					*((uint8_t*)buffer + (address & 0x3)) = outvalue;
+					outvalue >>= 8;
+					address++;
+				}
+
+				memcpy(&outvalue, buffer, sizeof(uint32_t));
+				retval = dap_queue_ap_write(swjdp,
+						AP_REG_DRW, outvalue);
+				if (retval != ERROR_OK)
+					break;
+
+				if (dap_run(swjdp) != ERROR_OK)
+				{
+					LOG_WARNING("Block write error address "
+						"0x%" PRIx32 ", count 0x%x",
+						address, count);
+					/* REVISIT return *actual* fault code */
+					return ERROR_JTAG_DEVICE_ERROR;
+				}
+			}
+
+			buffer += nbytes >> 1;
+			writecount -= nbytes >> 1;
+
+		} while (writecount);
+		wcount -= blocksize;
+	}
+
+	return retval;
+}
+
+int mem_ap_write_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
+{
+	int retval = ERROR_OK;
+
+	if (count >= 4)
+		return mem_ap_write_buf_packed_u16(swjdp, buffer, count, address);
+
+	while (count > 0)
+	{
+		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+		uint16_t svalue;
+		memcpy(&svalue, buffer, sizeof(uint16_t));
+		uint32_t outvalue = (uint32_t)svalue << 8 * (address & 0x3);
+		retval = dap_queue_ap_write(swjdp, AP_REG_DRW, outvalue);
+		if (retval != ERROR_OK)
+			break;
+
+		retval = dap_run(swjdp);
+		if (retval != ERROR_OK)
+			break;
+
+		count -= 2;
+		address += 2;
+		buffer += 2;
+	}
+
+	return retval;
+}
+
+static int mem_ap_write_buf_packed_u8(struct adiv5_dap *swjdp,
+		uint8_t *buffer, int count, uint32_t address)
+{
+	int retval = ERROR_OK;
+	int wcount, blocksize, writecount, i;
+
+	wcount = count;
+
+	while (wcount > 0)
+	{
+		int nbytes;
+
+		/* Adjust to write blocks within boundaries aligned to the TAR autoincremnent size*/
+		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+
+		if (wcount < blocksize)
+			blocksize = wcount;
+
+		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+		writecount = blocksize;
+
+		do
+		{
+			nbytes = MIN(writecount, 4);
+
+			if (nbytes < 4)
+			{
+				if (mem_ap_write_buf_u8(swjdp, buffer, nbytes, address) != ERROR_OK)
+				{
+					LOG_WARNING("Block write error address "
+						"0x%" PRIx32 ", count 0x%x",
+						address, count);
+					return ERROR_JTAG_DEVICE_ERROR;
+				}
+
+				address += nbytes;
+			}
+			else
+			{
+				uint32_t outvalue;
+				memcpy(&outvalue, buffer, sizeof(uint32_t));
+
+				for (i = 0; i < nbytes; i++)
+				{
+					*((uint8_t*)buffer + (address & 0x3)) = outvalue;
+					outvalue >>= 8;
+					address++;
+				}
+
+				memcpy(&outvalue, buffer, sizeof(uint32_t));
+				retval = dap_queue_ap_write(swjdp,
+						AP_REG_DRW, outvalue);
+				if (retval != ERROR_OK)
+					break;
+
+				if (dap_run(swjdp) != ERROR_OK)
+				{
+					LOG_WARNING("Block write error address "
+						"0x%" PRIx32 ", count 0x%x",
+						address, count);
+					/* REVISIT return *actual* fault code */
+					return ERROR_JTAG_DEVICE_ERROR;
+				}
+			}
+
+			buffer += nbytes;
+			writecount -= nbytes;
+
+		} while (writecount);
+		wcount -= blocksize;
+	}
+
+	return retval;
+}
+
+int mem_ap_write_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer, int count, uint32_t address)
+{
+	int retval = ERROR_OK;
+
+	if (count >= 4)
+		return mem_ap_write_buf_packed_u8(swjdp, buffer, count, address);
+
+	while (count > 0)
+	{
+		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+		uint32_t outvalue = (uint32_t)*buffer << 8 * (address & 0x3);
+		retval = dap_queue_ap_write(swjdp, AP_REG_DRW, outvalue);
+		if (retval != ERROR_OK)
+			break;
+
+		retval = dap_run(swjdp);
+		if (retval != ERROR_OK)
+			break;
+
+		count--;
+		address++;
+		buffer++;
+	}
+
+	return retval;
+}
+
+/* FIXME don't import ... this is a temporary workaround for the
+ * mem_ap_read_buf_u32() mess, until it's no longer JTAG-specific.
+ */
+extern int adi_jtag_dp_scan(struct adiv5_dap *swjdp,
+		uint8_t instr, uint8_t reg_addr, uint8_t RnW,
+		uint8_t *outvalue, uint8_t *invalue, uint8_t *ack);
+
+/**
+ * Synchronously read a block of 32-bit words into a buffer
+ * @param swjdp The DAP connected to the MEM-AP.
+ * @param buffer where the words will be stored (in host byte order).
+ * @param count How many words to read.
+ * @param address Memory address from which to read words; all the
+ *	words must be readable by the currently selected MEM-AP.
+ */
+int mem_ap_read_buf_u32(struct adiv5_dap *swjdp, uint8_t *buffer,
+		int count, uint32_t address)
+{
+	int wcount, blocksize, readcount, errorcount = 0, retval = ERROR_OK;
+	uint32_t adr = address;
+	uint8_t* pBuffer = buffer;
+
+	count >>= 2;
+	wcount = count;
+
+	while (wcount > 0)
+	{
+		/* Adjust to read blocks within boundaries aligned to the
+		 * TAR autoincrement size (at least 2^10).  Autoincrement
+		 * mode avoids an extra per-word roundtrip to update TAR.
+		 */
+		blocksize = max_tar_block_size(swjdp->tar_autoincr_block,
+				address);
+		if (wcount < blocksize)
+			blocksize = wcount;
+
+		/* handle unaligned data at 4k boundary */
+		if (blocksize == 0)
+			blocksize = 1;
+
+		dap_setup_accessport(swjdp, CSW_32BIT | CSW_ADDRINC_SINGLE,
+				address);
+
+		/* FIXME remove these three calls to adi_jtag_dp_scan(),
+		 * so this routine becomes transport-neutral.  Be careful
+		 * not to cause performance problems with JTAG; would it
+		 * suffice to loop over dap_queue_ap_read(), or would that
+		 * be slower when JTAG is the chosen transport?
+		 */
+
+		/* Scan out first read */
+		adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
+				DPAP_READ, 0, NULL, NULL);
+		for (readcount = 0; readcount < blocksize - 1; readcount++)
+		{
+			/* Scan out next read; scan in posted value for the
+			 * previous one.  Assumes read is acked "OK/FAULT",
+			 * and CTRL_STAT says that meant "OK".
+			 */
+			adi_jtag_dp_scan(swjdp, JTAG_DP_APACC, AP_REG_DRW,
+					DPAP_READ, 0, buffer + 4 * readcount,
+					&swjdp->ack);
+		}
+
+		/* Scan in last posted value; RDBUFF has no other effect,
+		 * assuming ack is OK/FAULT and CTRL_STAT says "OK".
+		 */
+		adi_jtag_dp_scan(swjdp, JTAG_DP_DPACC, DP_RDBUFF,
+				DPAP_READ, 0, buffer + 4 * readcount,
+				&swjdp->ack);
+		if (dap_run(swjdp) == ERROR_OK)
+		{
+			wcount = wcount - blocksize;
+			address += 4 * blocksize;
+			buffer += 4 * blocksize;
+		}
+		else
+		{
+			errorcount++;
+		}
+
+		if (errorcount > 1)
+		{
+			LOG_WARNING("Block read error address 0x%" PRIx32
+				", count 0x%x", address, count);
+			/* REVISIT return the *actual* fault code */
+			return ERROR_JTAG_DEVICE_ERROR;
+		}
+	}
+
+	/* if we have an unaligned access - reorder data */
+	if (adr & 0x3u)
+	{
+		for (readcount = 0; readcount < count; readcount++)
+		{
+			int i;
+			uint32_t data;
+			memcpy(&data, pBuffer, sizeof(uint32_t));
+
+			for (i = 0; i < 4; i++)
+			{
+				*((uint8_t*)pBuffer) =
+						(data >> 8 * (adr & 0x3));
+				pBuffer++;
+				adr++;
+			}
+		}
+	}
+
+	return retval;
+}
+
+static int mem_ap_read_buf_packed_u16(struct adiv5_dap *swjdp,
+		uint8_t *buffer, int count, uint32_t address)
+{
+	uint32_t invalue;
+	int retval = ERROR_OK;
+	int wcount, blocksize, readcount, i;
+
+	wcount = count >> 1;
+
+	while (wcount > 0)
+	{
+		int nbytes;
+
+		/* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
+		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+		if (wcount < blocksize)
+			blocksize = wcount;
+
+		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_PACKED, address);
+
+		/* handle unaligned data at 4k boundary */
+		if (blocksize == 0)
+			blocksize = 1;
+		readcount = blocksize;
+
+		do
+		{
+			retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
+			if (dap_run(swjdp) != ERROR_OK)
+			{
+				LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+				/* REVISIT return the *actual* fault code */
+				return ERROR_JTAG_DEVICE_ERROR;
+			}
+
+			nbytes = MIN((readcount << 1), 4);
+
+			for (i = 0; i < nbytes; i++)
+			{
+				*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
+				buffer++;
+				address++;
+			}
+
+			readcount -= (nbytes >> 1);
+		} while (readcount);
+		wcount -= blocksize;
+	}
+
+	return retval;
+}
+
+/**
+ * Synchronously read a block of 16-bit halfwords into a buffer
+ * @param swjdp The DAP connected to the MEM-AP.
+ * @param buffer where the halfwords will be stored (in host byte order).
+ * @param count How many halfwords to read.
+ * @param address Memory address from which to read words; all the
+ *	words must be readable by the currently selected MEM-AP.
+ */
+int mem_ap_read_buf_u16(struct adiv5_dap *swjdp, uint8_t *buffer,
+		int count, uint32_t address)
+{
+	uint32_t invalue, i;
+	int retval = ERROR_OK;
+
+	if (count >= 4)
+		return mem_ap_read_buf_packed_u16(swjdp, buffer, count, address);
+
+	while (count > 0)
+	{
+		dap_setup_accessport(swjdp, CSW_16BIT | CSW_ADDRINC_SINGLE, address);
+		retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
+		if (retval != ERROR_OK)
+			break;
+
+		retval = dap_run(swjdp);
+		if (retval != ERROR_OK)
+			break;
+
+		if (address & 0x1)
+		{
+			for (i = 0; i < 2; i++)
+			{
+				*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
+				buffer++;
+				address++;
+			}
+		}
+		else
+		{
+			uint16_t svalue = (invalue >> 8 * (address & 0x3));
+			memcpy(buffer, &svalue, sizeof(uint16_t));
+			address += 2;
+			buffer += 2;
+		}
+		count -= 2;
+	}
+
+	return retval;
+}
+
+/* FIX!!! is this a potential performance bottleneck w.r.t. requiring too many
+ * roundtrips when jtag_execute_queue() has a large overhead(e.g. for USB)s?
+ *
+ * The solution is to arrange for a large out/in scan in this loop and
+ * and convert data afterwards.
+ */
+static int mem_ap_read_buf_packed_u8(struct adiv5_dap *swjdp,
+		uint8_t *buffer, int count, uint32_t address)
+{
+	uint32_t invalue;
+	int retval = ERROR_OK;
+	int wcount, blocksize, readcount, i;
+
+	wcount = count;
+
+	while (wcount > 0)
+	{
+		int nbytes;
+
+		/* Adjust to read blocks within boundaries aligned to the TAR autoincremnent size*/
+		blocksize = max_tar_block_size(swjdp->tar_autoincr_block, address);
+
+		if (wcount < blocksize)
+			blocksize = wcount;
+
+		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_PACKED, address);
+		readcount = blocksize;
+
+		do
+		{
+			retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
+			if (dap_run(swjdp) != ERROR_OK)
+			{
+				LOG_WARNING("Block read error address 0x%" PRIx32 ", count 0x%x", address, count);
+				/* REVISIT return the *actual* fault code */
+				return ERROR_JTAG_DEVICE_ERROR;
+			}
+
+			nbytes = MIN(readcount, 4);
+
+			for (i = 0; i < nbytes; i++)
+			{
+				*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
+				buffer++;
+				address++;
+			}
+
+			readcount -= nbytes;
+		} while (readcount);
+		wcount -= blocksize;
+	}
+
+	return retval;
+}
+
+/**
+ * Synchronously read a block of bytes into a buffer
+ * @param swjdp The DAP connected to the MEM-AP.
+ * @param buffer where the bytes will be stored.
+ * @param count How many bytes to read.
+ * @param address Memory address from which to read data; all the
+ *	data must be readable by the currently selected MEM-AP.
+ */
+int mem_ap_read_buf_u8(struct adiv5_dap *swjdp, uint8_t *buffer,
+		int count, uint32_t address)
+{
+	uint32_t invalue;
+	int retval = ERROR_OK;
+
+	if (count >= 4)
+		return mem_ap_read_buf_packed_u8(swjdp, buffer, count, address);
+
+	while (count > 0)
+	{
+		dap_setup_accessport(swjdp, CSW_8BIT | CSW_ADDRINC_SINGLE, address);
+		retval = dap_queue_ap_read(swjdp, AP_REG_DRW, &invalue);
+		retval = dap_run(swjdp);
+		if (retval != ERROR_OK)
+			break;
+
+		*((uint8_t*)buffer) = (invalue >> 8 * (address & 0x3));
+		count--;
+		address++;
+		buffer++;
+	}
+
+	return retval;
+}
+
+/*--------------------------------------------------------------------------*/
+
+<<<<<<< HEAD:src/target/arm_adi_v5.c
+=======
+static int jtag_idcode_q_read(struct adiv5_dap *dap,
+		uint8_t *ack, uint32_t *data)
+{
+	struct arm_jtag *jtag_info = dap->jtag_info;
+	int retval;
+	struct scan_field fields[1];
+
+	jtag_set_end_state(TAP_IDLE);
+
+	/* This is a standard JTAG operation -- no DAP tweakage */
+	retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL);
+	if (retval != ERROR_OK)
+		return retval;
+
+	fields[0].num_bits = 32;
+	fields[0].out_value = NULL;
+	fields[0].in_value = (void *) data;
+
+	jtag_add_dr_scan(jtag_info->tap, 1, fields, TAP_IDLE);
+	retval = jtag_get_error();
+	if (retval != ERROR_OK)
+		return retval;
+
+	jtag_add_callback(arm_le_to_h_u32,
+			(jtag_callback_data_t) data);
+
+	return retval;
+}
+
+static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
+		uint32_t *data)
+{
+	return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+			reg, DPAP_READ, 0, data);
+}
+
+static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
+		uint32_t data)
+{
+	return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_DPACC,
+			reg, DPAP_WRITE, data, NULL);
+}
+
+/** Select the AP register bank matching bits 7:4 of reg. */
+static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
+{
+	uint32_t select = reg & 0x000000F0;
+
+	if (select == dap->ap_bank_value)
+		return ERROR_OK;
+	dap->ap_bank_value = select;
+
+	select |= dap->apsel;
+
+	return jtag_dp_q_write(dap, DP_SELECT, select);
+}
+
+static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
+		uint32_t *data)
+{
+	int retval = jtag_ap_q_bankselect(dap, reg);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	return adi_jtag_scan_inout_check_u32(dap, JTAG_DP_APACC, reg,
+			DPAP_READ, 0, data);
+}
+
+static int jtag_ap_q_write(struct adiv5_dap *dap, unsigned reg,
+		uint32_t data)
+{
+	uint8_t out_value_buf[4];
+
+	int retval = jtag_ap_q_bankselect(dap, reg);
+	if (retval != ERROR_OK)
+		return retval;
+>>>>>>> jtag: cut down on usage of unintended modification of global end state:src/target/arm_adi_v5.c
+
+/* FIXME don't import ... just initialize as
+ * part of DAP transport setup
+*/
+extern const struct dap_ops jtag_dp_ops;
+
+/*--------------------------------------------------------------------------*/
+
+/**
+ * Initialize a DAP.  This sets up the power domains, prepares the DP
+ * for further use, and arranges to use AP #0 for all AP operations
+ * until dap_ap-select() changes that policy.
+ *
+ * @param swjdp The DAP being initialized.
+ *
+ * @todo Rename this.  We also need an initialization scheme which account
+ * for SWD transports not just JTAG; that will need to address differences
+ * in layering.  (JTAG is useful without any debug target; but not SWD.)
+ * And this may not even use an AHB-AP ... e.g. DAP-Lite uses an APB-AP.
+ */
+int ahbap_debugport_init(struct adiv5_dap *swjdp)
+{
+	uint32_t idreg, romaddr, dummy;
+	uint32_t ctrlstat;
+	int cnt = 0;
+	int retval;
+
+	LOG_DEBUG(" ");
+
+	/* JTAG-DP or SWJ-DP, in JTAG mode */
+	swjdp->ops = &jtag_dp_ops;
+
+	/* Default MEM-AP setup.
+	 *
+	 * REVISIT AP #0 may be an inappropriate default for this.
+	 * Should we probe, or take a hint from the caller?
+	 * Presumably we can ignore the possibility of multiple APs.
+	 */
+	swjdp->apsel = !0;
+	dap_ap_select(swjdp, 0);
+
+	/* DP initialization */
+
+	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, SSTICKYERR);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
+	if (retval != ERROR_OK)
+		return retval;
+
+	swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ;
+	retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
+	if (retval != ERROR_OK)
+		return retval;
+	if ((retval = dap_run(swjdp)) != ERROR_OK)
+		return retval;
+
+	/* Check that we have debug power domains activated */
+	while (!(ctrlstat & CDBGPWRUPACK) && (cnt++ < 10))
+	{
+		LOG_DEBUG("DAP: wait CDBGPWRUPACK");
+		retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
+		if (retval != ERROR_OK)
+			return retval;
+		if ((retval = dap_run(swjdp)) != ERROR_OK)
+			return retval;
+		alive_sleep(10);
+	}
+
+	while (!(ctrlstat & CSYSPWRUPACK) && (cnt++ < 10))
+	{
+		LOG_DEBUG("DAP: wait CSYSPWRUPACK");
+		retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &ctrlstat);
+		if (retval != ERROR_OK)
+			return retval;
+		if ((retval = dap_run(swjdp)) != ERROR_OK)
+			return retval;
+		alive_sleep(10);
+	}
+
+	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
+	if (retval != ERROR_OK)
+		return retval;
+	/* With debug power on we can activate OVERRUN checking */
+	swjdp->dp_ctrl_stat = CDBGPWRUPREQ | CSYSPWRUPREQ | CORUNDETECT;
+	retval = dap_queue_dp_write(swjdp, DP_CTRL_STAT, swjdp->dp_ctrl_stat);
+	if (retval != ERROR_OK)
+		return retval;
+	retval = dap_queue_dp_read(swjdp, DP_CTRL_STAT, &dummy);
+	if (retval != ERROR_OK)
+		return retval;
+
+	/*
+	 * REVISIT this isn't actually *initializing* anything in an AP,
+	 * and doesn't care if it's a MEM-AP at all (much less AHB-AP).
+	 * Should it?  If the ROM address is valid, is this the right
+	 * place to scan the table and do any topology detection?
+	 */
+	retval = dap_queue_ap_read(swjdp, AP_REG_IDR, &idreg);
+	retval = dap_queue_ap_read(swjdp, AP_REG_BASE, &romaddr);
+
+	LOG_DEBUG("MEM-AP #%d ID Register 0x%" PRIx32
+		", Debug ROM Address 0x%" PRIx32,
+		swjdp->apsel, idreg, romaddr);
+
+	return ERROR_OK;
+}
+
+/* CID interpretation -- see ARM IHI 0029B section 3
+ * and ARM IHI 0031A table 13-3.
+ */
+static const char *class_description[16] ={
+	"Reserved", "ROM table", "Reserved", "Reserved",
+	"Reserved", "Reserved", "Reserved", "Reserved",
+	"Reserved", "CoreSight component", "Re...
 
[truncated message content]

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-103-gfccdfc1

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  fccdfc1cd78ddfb687e0d1fc630c3fa10af2b5f9 (commit)
      from  0529431fe740fbf04b41129d84e2d8633b13fabe (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit fccdfc1cd78ddfb687e0d1fc630c3fa10af2b5f9
Author: Øyvind Harboe <oyv...@zy...>
Date:   Wed Mar 17 21:50:23 2010 +0100

    linker error: fix problem with duplicate fn
    
    A fn was copied instead of moved to a new file. The linker
    can discard exact copies of fn's without warning.
    
    This is a C++'ism.
    
    However on my Ubuntu 9.10 machine, it fails.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index dcad0fb..4afd50c 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1597,36 +1597,3 @@ static const uint8_t jtag2swd_bitseq[] = {
 	0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
 };
 
-/**
- * Put the debug link into SWD mode, if the target supports it.
- * The link's initial mode may be either JTAG (for example,
- * with SWJ-DP after reset) or SWD.
- *
- * @param target Enters SWD mode (if possible).
- *
- * Note that targets using the JTAG-DP do not support SWD, and that
- * some targets which could otherwise support it may have have been
- * configured to disable SWD signaling
- *
- * @return ERROR_OK or else a fault code.
- */
-int dap_to_swd(struct target *target)
-{
-	int retval;
-
-	LOG_DEBUG("Enter SWD mode");
-
-	/* REVISIT it's nasty to need to make calls to a "jtag"
-	 * subsystem if the link isn't in JTAG mode...
-	 */
-
-	retval =  jtag_add_tms_seq(8 * sizeof(jtag2swd_bitseq),
-			jtag2swd_bitseq, TAP_INVALID);
-	if (retval == ERROR_OK)
-		retval = jtag_execute_queue();
-
-	/* REVISIT set up the DAP's ops vector for SWD mode. */
-
-	return retval;
-}
-

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c |   33 ---------------------------------
 1 files changed, 0 insertions(+), 33 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-102-g0529431

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  0529431fe740fbf04b41129d84e2d8633b13fabe (commit)
      from  cc197c808625d9afa5e4c316122d59b71fe8ee44 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 0529431fe740fbf04b41129d84e2d8633b13fabe
Author: Øyvind Harboe <oyv...@zy...>
Date:   Wed Mar 17 21:34:43 2010 +0100

    mips: fix warning
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index cea8fa8..42dc6e0 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -135,7 +135,7 @@ int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
 	if (tap == NULL)
 		return ERROR_FAIL;
 	struct scan_field field;
-	uint8_t t[4], r[4];
+	uint8_t t[4] = {0, 0, 0, 0}, r[4];
 	int retval;
 
 	field.num_bits = 8;

-----------------------------------------------------------------------

Summary of changes:
 src/target/mips_ejtag.c |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-101-gcc197c8

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  cc197c808625d9afa5e4c316122d59b71fe8ee44 (commit)
      from  bf71e34cbf874fcf568742283cfa96360a9c75e1 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit cc197c808625d9afa5e4c316122d59b71fe8ee44
Author: Øyvind Harboe <oyv...@zy...>
Date:   Wed Mar 17 12:59:33 2010 +0100

    gdb: long running "monitor mww" now works w/gdb
    
    invoke keep_alive() to make sure that the default 2000ms
    timeout does not trigger.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/target.c b/src/target/target.c
index 91fe787..2c88a6f 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -2355,6 +2355,8 @@ static int target_fill_mem(struct target *target,
 		{
 			break;
 		}
+		/* avoid GDB timeouts */
+		keep_alive();
 	}
 	free(target_buf);
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.c |    2 ++
 1 files changed, 2 insertions(+), 0 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-100-gbf71e34

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  bf71e34cbf874fcf568742283cfa96360a9c75e1 (commit)
      from  099ffc754ab22cb9b8e3e6af04e21284de12d885 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit bf71e34cbf874fcf568742283cfa96360a9c75e1
Author: Øyvind Harboe <oyv...@zy...>
Date:   Tue Mar 16 18:02:58 2010 +0100

    target: faster mww operations
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/target.c b/src/target/target.c
index b6813fd..91fe787 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -2,7 +2,7 @@
  *   Copyright (C) 2005 by Dominic Rath                                    *
  *   Dom...@gm...                                                   *
  *                                                                         *
- *   Copyright (C) 2007-2009 Øyvind Harboe                                 *
+ *   Copyright (C) 2007-2010 Øyvind Harboe                                 *
  *   oyv...@zy...                                               *
  *                                                                         *
  *   Copyright (C) 2008, Duane Ellis                                       *
@@ -2294,6 +2294,74 @@ COMMAND_HANDLER(handle_md_command)
 	return retval;
 }
 
+typedef int (*target_write_fn)(struct target *target,
+		uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+
+static int target_write_memory_fast(struct target *target,
+		uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer)
+{
+	return target_write_buffer(target, address, size * count, buffer);
+}
+
+static int target_fill_mem(struct target *target,
+		uint32_t address,
+		target_write_fn fn,
+		unsigned data_size,
+		/* value */
+		uint32_t b,
+		/* count */
+		unsigned c)
+{
+	/* We have to write in reasonably large chunks to be able
+	 * to fill large memory areas with any sane speed */
+	const unsigned chunk_size = 16384;
+	uint8_t *target_buf = malloc(chunk_size * data_size);
+	if (target_buf == NULL)
+	{
+		LOG_ERROR("Out of memory");
+		return ERROR_FAIL;
+	}
+
+	for (unsigned i = 0; i < chunk_size; i ++)
+	{
+		switch (data_size)
+		{
+		case 4:
+			target_buffer_set_u32(target, target_buf + i*data_size, b);
+			break;
+		case 2:
+			target_buffer_set_u16(target, target_buf + i*data_size, b);
+			break;
+		case 1:
+			target_buffer_set_u8(target, target_buf + i*data_size, b);
+			break;
+		default:
+			exit(-1);
+		}
+	}
+
+	int retval = ERROR_OK;
+
+	for (unsigned x = 0; x < c; x += chunk_size)
+	{
+		unsigned current;
+		current = c - x;
+		if (current > chunk_size)
+		{
+			current = chunk_size;
+		}
+		int retval = fn(target, address + x * data_size, data_size, current, target_buf);
+		if (retval != ERROR_OK)
+		{
+			break;
+		}
+	}
+	free(target_buf);
+
+	return retval;
+}
+
+
 COMMAND_HANDLER(handle_mw_command)
 {
 	if (CMD_ARGC < 2)
@@ -2301,8 +2369,7 @@ COMMAND_HANDLER(handle_mw_command)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 	bool physical=strcmp(CMD_ARGV[0], "phys")==0;
-	int (*fn)(struct target *target,
-			uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+	target_write_fn fn;
 	if (physical)
 	{
 		CMD_ARGC--;
@@ -2310,7 +2377,7 @@ COMMAND_HANDLER(handle_mw_command)
 		fn=target_write_phys_memory;
 	} else
 	{
-		fn=target_write_memory;
+		fn = target_write_memory_fast;
 	}
 	if ((CMD_ARGC < 2) || (CMD_ARGC > 3))
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -2327,35 +2394,22 @@ COMMAND_HANDLER(handle_mw_command)
 
 	struct target *target = get_current_target(CMD_CTX);
 	unsigned wordsize;
-	uint8_t value_buf[4];
 	switch (CMD_NAME[2])
 	{
 		case 'w':
 			wordsize = 4;
-			target_buffer_set_u32(target, value_buf, value);
 			break;
 		case 'h':
 			wordsize = 2;
-			target_buffer_set_u16(target, value_buf, value);
 			break;
 		case 'b':
 			wordsize = 1;
-			value_buf[0] = value;
 			break;
 		default:
 			return ERROR_COMMAND_SYNTAX_ERROR;
 	}
-	for (unsigned i = 0; i < count; i++)
-	{
-		int retval = fn(target,
-				address + i * wordsize, wordsize, 1, value_buf);
-		if (ERROR_OK != retval)
-			return retval;
-		keep_alive();
-	}
-
-	return ERROR_OK;
 
+	return target_fill_mem(target, address, fn, wordsize, value, count);
 }
 
 static COMMAND_HELPER(parse_load_image_command_CMD_ARGV, struct image *image,
@@ -3909,36 +3963,21 @@ static int jim_target_mw(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	}
 
 	struct target *target = Jim_CmdPrivData(goi.interp);
-	uint8_t  target_buf[32];
+	unsigned data_size;
 	if (strcasecmp(cmd_name, "mww") == 0) {
-		target_buffer_set_u32(target, target_buf, b);
-		b = 4;
+		data_size = 4;
 	}
 	else if (strcasecmp(cmd_name, "mwh") == 0) {
-		target_buffer_set_u16(target, target_buf, b);
-		b = 2;
+		data_size = 2;
 	}
 	else if (strcasecmp(cmd_name, "mwb") == 0) {
-		target_buffer_set_u8(target, target_buf, b);
-		b = 1;
+		data_size = 1;
 	} else {
 		LOG_ERROR("command '%s' unknown: ", cmd_name);
 		return JIM_ERR;
 	}
 
-	for (jim_wide x = 0; x < c; x++)
-	{
-		e = target_write_memory(target, a, b, 1, target_buf);
-		if (e != ERROR_OK)
-		{
-			Jim_SetResult_sprintf(interp,
-					"Error writing @ 0x%08x: %d\n", (int)(a), e);
-			return JIM_ERR;
-		}
-		/* b = width */
-		a = a + b;
-	}
-	return JIM_OK;
+	return (target_fill_mem(target, a, target_write_memory_fast, data_size, b, c) == ERROR_OK) ? JIM_OK : JIM_ERR;
 }
 
 static int jim_target_md(Jim_Interp *interp, int argc, Jim_Obj *const *argv)

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.c |  115 ++++++++++++++++++++++++++++++++++-----------------
 1 files changed, 77 insertions(+), 38 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-99-g099ffc7

[Øyvind H. <go...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  099ffc754ab22cb9b8e3e6af04e21284de12d885 (commit)
      from  3ad171cd537f8fc1bac649f24513ebfafd95baf2 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 099ffc754ab22cb9b8e3e6af04e21284de12d885
Author: Øyvind Harboe <oyv...@zy...>
Date:   Wed Mar 17 12:43:47 2010 +0100

    target: mdX/mwX on target were badly broken
    
    - incorrect parsing of arguments
    - mdX didn't display arguments correctly
    
    I don't think anyone ever used that code path :-)
    
    Did you know that "target mdw" and mdw are very different?
    
    for {set i 0} {$i < 256} {set i [expr $i+1]} {mwb [expr 0x2000000+$i] $i}
    
     mdw 0x2000000 0x10
    0x02000000: 03020100 07060504 0b0a0908 0f0e0d0c 13121110 17161514 1b1a1918 1f1e1d1c
    0x02000020: 23222120 27262524 2b2a2928 2f2e2d2c 33323130 37363534 3b3a3938 3f3e3d3c
    
    > zy1000.cpu mdb 0x2000000 0x20
    0x02000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f ................
    0x02000010 10 11 12 13 14 15 16 17 18 19 1a 1b 1c 1d 1e 1f ................
    > zy1000.cpu mdh 0x2000000 0x20
    0x02000000 0100 0302 0504 0706 0908 0b0a 0d0c 0f0e ................
    0x02000010 1110 1312 1514 1716 1918 1b1a 1d1c 1f1e ................
    0x02000020 2120 2322 2524 2726 2928 2b2a 2d2c 2f2e  !"#$%&'()*+,-./
    0x02000030 3130 3332 3534 3736 3938 3b3a 3d3c 3f3e 0123456789:;<=>?
    > zy1000.cpu mdw 0x2000000 0x20
    0x02000000 03020100 07060504 0b0a0908 0f0e0d0c ................
    0x02000010 13121110 17161514 1b1a1918 1f1e1d1c ................
    0x02000020 23222120 27262524 2b2a2928 2f2e2d2c  !"#$%&'()*+,-./
    0x02000030 33323130 37363534 3b3a3938 3f3e3d3c 0123456789:;<=>?
    0x02000040 43424140 47464544 4b4a4948 4f4e4d4c @ABCDEFGHIJKLMNO
    0x02000050 53525150 57565554 5b5a5958 5f5e5d5c PQRSTUVWXYZ[\]^_
    0x02000060 63626160 67666564 6b6a6968 6f6e6d6c `abcdefghijklmno
    0x02000070 73727170 77767574 7b7a7978 7f7e7d7c pqrstuvwxyz{|}~.
    
    Signed-off-by: Øyvind Harboe <oyv...@zy...>

diff --git a/src/target/target.c b/src/target/target.c
index 1eb1435..b6813fd 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -3879,13 +3879,17 @@ static int jim_target_mw(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	Jim_GetOptInfo goi;
 	Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
 
-	if (goi.argc != 2 && goi.argc != 3)
+	/* danger! goi.argc will be modified below! */
+	argc = goi.argc;
+
+	if (argc != 2 && argc != 3)
 	{
 		Jim_SetResult_sprintf(goi.interp,
 				"usage: %s <address> <data> [<count>]", cmd_name);
 		return JIM_ERR;
 	}
 
+
 	jim_wide a;
 	int e = Jim_GetOpt_Wide(&goi, &a);
 	if (e != JIM_OK)
@@ -3897,7 +3901,7 @@ static int jim_target_mw(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 		return e;
 
 	jim_wide c = 1;
-	if (goi.argc == 3)
+	if (argc == 3)
 	{
 		e = Jim_GetOpt_Wide(&goi, &c);
 		if (e != JIM_OK)
@@ -3944,7 +3948,10 @@ static int jim_target_md(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 	Jim_GetOptInfo goi;
 	Jim_GetOpt_Setup(&goi, interp, argc - 1, argv + 1);
 
-	if ((goi.argc == 2) || (goi.argc == 3))
+	/* danger! goi.argc will be modified below! */
+	argc = goi.argc;
+
+	if ((argc != 1) && (argc != 2))
 	{
 		Jim_SetResult_sprintf(goi.interp,
 				"usage: %s <address> [<count>]", cmd_name);
@@ -3957,7 +3964,7 @@ static int jim_target_md(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 		return JIM_ERR;
 	}
 	jim_wide c;
-	if (goi.argc) {
+	if (argc == 2) {
 		e = Jim_GetOpt_Wide(&goi, &c);
 		if (e != JIM_OK) {
 			return JIM_ERR;
@@ -3999,7 +4006,7 @@ static int jim_target_md(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 		case 4:
 			for (x = 0; x < 16 && x < y; x += 4)
 			{
-				z = target_buffer_get_u32(target, &(target_buf[ x * 4 ]));
+				z = target_buffer_get_u32(target, &(target_buf[ x ]));
 				Jim_fprintf(interp, interp->cookie_stdout, "%08x ", (int)(z));
 			}
 			for (; (x < 16) ; x += 4) {
@@ -4009,7 +4016,7 @@ static int jim_target_md(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 		case 2:
 			for (x = 0; x < 16 && x < y; x += 2)
 			{
-				z = target_buffer_get_u16(target, &(target_buf[ x * 2 ]));
+				z = target_buffer_get_u16(target, &(target_buf[ x ]));
 				Jim_fprintf(interp, interp->cookie_stdout, "%04x ", (int)(z));
 			}
 			for (; (x < 16) ; x += 2) {
@@ -4019,7 +4026,7 @@ static int jim_target_md(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
 		case 1:
 		default:
 			for (x = 0 ; (x < 16) && (x < y) ; x += 1) {
-				z = target_buffer_get_u8(target, &(target_buf[ x * 4 ]));
+				z = target_buffer_get_u8(target, &(target_buf[ x ]));
 				Jim_fprintf(interp, interp->cookie_stdout, "%02x ", (int)(z));
 			}
 			for (; (x < 16) ; x += 1) {

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.c |   21 ++++++++++++++-------
 1 files changed, 14 insertions(+), 7 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[openocd-svn] Main OpenOCD repository branch, master, updated. v0.4.0-98-g3ad171c

[Spencer O. <nt...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  3ad171cd537f8fc1bac649f24513ebfafd95baf2 (commit)
       via  e7e9bfde47768b22be8b15c30c027dc8fb67c778 (commit)
       via  79ca05b106ef92915c4e9288cbf34d5db1cf4cd2 (commit)
      from  051e2c99ab8111f6bffdb412b40ceef333530ae6 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 3ad171cd537f8fc1bac649f24513ebfafd95baf2
Author: Spencer Oliver <nt...@us...>
Date:   Wed Mar 17 09:57:44 2010 +0000

    SCRIPT: add add_script_search_dir cmd
    
    Add a add_script_search_dir cmd so that adding search
    dir's can be added to cfg scripts.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/NEWS b/NEWS
index cc2560b..0b9a6a4 100644
--- a/NEWS
+++ b/NEWS
@@ -16,6 +16,11 @@ JTAG Layer:
 Boundary Scan:
 
 Target Layer:
+	MIPS:
+		- "ejtag_srst" variant removed. The same functionality is
+		  obtained by using "reset_config none".
+		- added PIC32MX software reset support, this means srst is not
+		  required to be connected anymore.
 
 Flash Layer:
 	New "stellaris recover" command, implements the procedure
@@ -23,12 +28,15 @@ Flash Layer:
 		state to the factory defaults, including erasing
 		the flash and its protection bits, and possibly
 		re-enabling hardware debugging).
-
+	PIC32MX now uses algorithm for flash programming, this
+		has increased the performance by approx 96%.
 
 Board, Target, and Interface Configuration Scripts:
 	Support IAR LPC1768 kickstart board (by Olimex)
 
 Core Jim/TCL Scripting:
+	New "add_script_search_dir" command, behaviour is the same
+		as the "-s" cmd line option.
 
 Documentation:
 
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 780cd4d..98fc690 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -590,6 +590,7 @@ Configuration files and scripts are searched for in
 @enumerate
 @item the current directory,
 @item any search dir specified on the command line using the @option{-s} option,
+@item any search dir specified using the @command{add_script_search_dir} command,
 @item @file{$HOME/.openocd} (not on Windows),
 @item the site wide script library @file{$pkgdatadir/site} and
 @item the OpenOCD-supplied script library @file{$pkgdatadir/scripts}.
@@ -5396,6 +5397,10 @@ Redirect logging to @var{filename};
 the initial log output channel is stderr.
 @end deffn
 
+@deffn Command add_script_search_dir [directory]
+Add @var{directory} to the file/script search path.
+@end deffn
+
 @anchor{Target State handling}
 @section Target State handling
 @cindex reset
diff --git a/src/openocd.c b/src/openocd.c
index d376f5f..54c454d 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -159,6 +159,16 @@ COMMAND_HANDLER(handle_init_command)
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(handle_add_script_search_dir_command)
+{
+	if (CMD_ARGC != 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	add_script_search_dir(CMD_ARGV[0]);
+
+	return ERROR_OK;
+}
+
 static const struct command_registration openocd_command_handlers[] = {
 	{
 		.name = "version",
@@ -182,6 +192,13 @@ static const struct command_registration openocd_command_handlers[] = {
 			"called automatically at the end of startup.",
 
 	},
+	{
+		.name = "add_script_search_dir",
+		.handler = &handle_add_script_search_dir_command,
+		.mode = COMMAND_ANY,
+		.help = "dir to search for config files and scripts",
+
+	},
 	COMMAND_REGISTRATION_DONE
 };
 

commit e7e9bfde47768b22be8b15c30c027dc8fb67c778
Author: Spencer Oliver <nt...@us...>
Date:   Tue Mar 16 12:54:08 2010 +0000

    PIC32: add software reset support
    
    The PIC32MX does not support the ejtag software reset - it is
    optional in the ejtag spec.
    
    We perform the equivalent using the microchip specific MTAP cmd's.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c
index 984b535..cea8fa8 100644
--- a/src/target/mips_ejtag.c
+++ b/src/target/mips_ejtag.c
@@ -127,6 +127,37 @@ int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data)
 	return ERROR_OK;
 }
 
+int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data)
+{
+	struct jtag_tap *tap;
+	tap  = ejtag_info->tap;
+
+	if (tap == NULL)
+		return ERROR_FAIL;
+	struct scan_field field;
+	uint8_t t[4], r[4];
+	int retval;
+
+	field.num_bits = 8;
+	field.out_value = t;
+	buf_set_u32(field.out_value, 0, field.num_bits, *data);
+	field.in_value = r;
+
+	jtag_add_dr_scan(tap, 1, &field, jtag_get_end_state());
+
+	if ((retval = jtag_execute_queue()) != ERROR_OK)
+	{
+		LOG_ERROR("register read failed");
+		return retval;
+	}
+
+	*data = buf_get_u32(field.in_value, 0, 32);
+
+	keep_alive();
+
+	return ERROR_OK;
+}
+
 int mips_ejtag_step_enable(struct mips_ejtag *ejtag_info)
 {
 	static const uint32_t code[] = {
diff --git a/src/target/mips_ejtag.h b/src/target/mips_ejtag.h
index 5c1f245..a086cd5 100644
--- a/src/target/mips_ejtag.h
+++ b/src/target/mips_ejtag.h
@@ -43,6 +43,11 @@
 /* microchip PIC32MX specific instructions */
 #define MTAP_SW_MTAP			0x04
 #define MTAP_SW_ETAP			0x05
+#define MTAP_COMMAND			0x07
+
+/* microchip specific cmds */
+#define MCHP_ASERT_RST			0xd1
+#define MCHP_DE_ASSERT_RST		0xd0
 
 /* ejtag control register bits ECR */
 #define EJTAG_CTRL_TOF			(1 << 1)
@@ -130,6 +135,7 @@ int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
 int mips_ejtag_get_impcode(struct mips_ejtag *ejtag_info, uint32_t *impcode);
 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info, uint32_t *idcode);
 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
+int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint32_t *data);
 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write, uint32_t *data);
 
 int mips_ejtag_init(struct mips_ejtag *ejtag_info);
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index d3536d8..d1b4589 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -250,11 +250,30 @@ int mips_m4k_assert_reset(struct target *target)
 	}
 	else
 	{
+		if (mips_m4k->is_pic32mx)
+		{
+			uint32_t mchip_cmd;
+
+			LOG_DEBUG("Using MTAP reset to reset processor...");
+
+			/* use microchip specific MTAP reset */
+			mips_ejtag_set_instr(ejtag_info, MTAP_SW_MTAP, NULL);
+			mips_ejtag_set_instr(ejtag_info, MTAP_COMMAND, NULL);
+
+			mchip_cmd = MCHP_ASERT_RST;
+			mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+			mchip_cmd = MCHP_DE_ASSERT_RST;
+			mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
+			mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL);
+		}
+		else
+		{
 			/* use ejtag reset - not supported by all cores */
 			uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
 			LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
 			mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
 			mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+		}
 	}
 
 	target->state = TARGET_RESET;
@@ -878,7 +897,7 @@ int mips_m4k_init_target(struct command_context *cmd_ctx, struct target *target)
 int mips_m4k_init_arch_info(struct target *target, struct mips_m4k_common *mips_m4k,
 		struct jtag_tap *tap)
 {
-	struct mips32_common *mips32 = &mips_m4k->mips32_common;
+	struct mips32_common *mips32 = &mips_m4k->mips32;
 
 	mips_m4k->common_magic = MIPSM4K_COMMON_MAGIC;
 
@@ -901,8 +920,8 @@ int mips_m4k_target_create(struct target *target, Jim_Interp *interp)
 int mips_m4k_examine(struct target *target)
 {
 	int retval;
-	struct mips32_common *mips32 = target_to_mips32(target);
-	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+	struct mips_m4k_common *mips_m4k = target_to_m4k(target);
+	struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
 	uint32_t idcode = 0;
 
 	if (!target_was_examined(target))
@@ -916,6 +935,7 @@ int mips_m4k_examine(struct target *target)
 			 * as it is not selected by default */
 			mips_ejtag_set_instr(ejtag_info, MTAP_SW_ETAP, NULL);
 			LOG_DEBUG("PIC32MX Detected - using EJTAG Interface");
+			mips_m4k->is_pic32mx = true;
 		}
 	}
 
diff --git a/src/target/mips_m4k.h b/src/target/mips_m4k.h
index 9b33020..5eb2029 100644
--- a/src/target/mips_m4k.h
+++ b/src/target/mips_m4k.h
@@ -32,6 +32,7 @@ struct target;
 struct mips_m4k_common
 {
 	int common_magic;
+	bool is_pic32mx;
 	struct mips32_common mips32;
 };
 

commit 79ca05b106ef92915c4e9288cbf34d5db1cf4cd2
Author: Spencer Oliver <nt...@us...>
Date:   Tue Mar 16 12:48:53 2010 +0000

    MIPS: remove ejtag_srst variant
    
    The mips_m4k_assert_reset has now been restructured
    so the variant ejtag_srst is not required anymore.
    The ejtag software reset will be used if the target does not
    have srst connected.
    
    Remove ejtag_srst from docs.
    
    Signed-off-by: Spencer Oliver <nt...@us...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index e1bb2b7..780cd4d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3453,14 +3453,6 @@ be detected and the normal reset behaviour used.
 @item @code{fa526} -- resembles arm920 (w/o Thumb)
 @item @code{feroceon} -- resembles arm926
 @item @code{mips_m4k} -- a MIPS core.  This supports one variant:
-@itemize @minus
-@item @code{ejtag_srst} ... Use this when debugging targets that do not
-provide a functional SRST line on the EJTAG connector.  This causes
-OpenOCD to instead use an EJTAG software reset command to reset the
-processor.
-You still need to enable @option{srst} on the @command{reset_config}
-command to enable OpenOCD hardware reset functionality.
-@end itemize
 @item @code{xscale} -- this is actually an architecture,
 not a CPU type.  It is based on the ARMv5 architecture.
 There are several variants defined:
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 389daf9..d3536d8 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -212,18 +212,17 @@ int mips_m4k_halt(struct target *target)
 
 int mips_m4k_assert_reset(struct target *target)
 {
-	struct mips32_common *mips32 = target_to_mips32(target);
-	struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
+	struct mips_m4k_common *mips_m4k = target_to_m4k(target);
+	struct mips_ejtag *ejtag_info = &mips_m4k->mips32.ejtag_info;
+	int assert_srst = 1;
 
 	LOG_DEBUG("target->state: %s",
 		target_state_name(target));
 
 	enum reset_types jtag_reset_config = jtag_get_reset_config();
+
 	if (!(jtag_reset_config & RESET_HAS_SRST))
-	{
-		LOG_ERROR("Can't assert SRST");
-		return ERROR_FAIL;
-	}
+		assert_srst = 0;
 
 	if (target->reset_halt)
 	{
@@ -237,14 +236,7 @@ int mips_m4k_assert_reset(struct target *target)
 		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_NORMALBOOT, NULL);
 	}
 
-	if (strcmp(target->variant, "ejtag_srst") == 0)
-	{
-		uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
-		LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
-		mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
-		mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
-	}
-	else
+	if (assert_srst)
 	{
 		/* here we should issue a srst only, but we may have to assert trst as well */
 		if (jtag_reset_config & RESET_SRST_PULLS_TRST)
@@ -256,11 +248,19 @@ int mips_m4k_assert_reset(struct target *target)
 			jtag_add_reset(0, 1);
 		}
 	}
+	else
+	{
+			/* use ejtag reset - not supported by all cores */
+			uint32_t ejtag_ctrl = ejtag_info->ejtag_ctrl | EJTAG_CTRL_PRRST | EJTAG_CTRL_PERRST;
+			LOG_DEBUG("Using EJTAG reset (PRRST) to reset processor...");
+			mips_ejtag_set_instr(ejtag_info, EJTAG_INST_CONTROL, NULL);
+			mips_ejtag_drscan_32(ejtag_info, &ejtag_ctrl);
+	}
 
 	target->state = TARGET_RESET;
 	jtag_add_sleep(50000);
 
-	register_cache_invalidate(mips32->core_cache);
+	register_cache_invalidate(mips_m4k->mips32.core_cache);
 
 	if (target->reset_halt)
 	{
diff --git a/src/target/mips_m4k.h b/src/target/mips_m4k.h
index 4fe14a0..9b33020 100644
--- a/src/target/mips_m4k.h
+++ b/src/target/mips_m4k.h
@@ -32,14 +32,14 @@ struct target;
 struct mips_m4k_common
 {
 	int common_magic;
-	struct mips32_common mips32_common;
+	struct mips32_common mips32;
 };
 
 static inline struct mips_m4k_common *
 target_to_m4k(struct target *target)
 {
 	return container_of(target->arch_info,
-			struct mips_m4k_common, mips32_common);
+			struct mips_m4k_common, mips32);
 }
 
 int mips_m4k_bulk_write_memory(struct target *target,

-----------------------------------------------------------------------

Summary of changes:
 NEWS                    |   10 +++++++-
 doc/openocd.texi        |   13 ++++------
 src/openocd.c           |   17 ++++++++++++++
 src/target/mips_ejtag.c |   31 ++++++++++++++++++++++++++
 src/target/mips_ejtag.h |    6 +++++
 src/target/mips_m4k.c   |   56 +++++++++++++++++++++++++++++++---------------
 src/target/mips_m4k.h   |    5 ++-
 7 files changed, 109 insertions(+), 29 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository