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|
From: openocd-gerrit <ope...@us...> - 2025-03-09 13:27:20
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c81cb4aa2d2b85a513f58d2ddbc492f606473c77 (commit)
from 8a6f89ca170ce69835f03805aa60106801da61a8 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit c81cb4aa2d2b85a513f58d2ddbc492f606473c77
Author: Nishanth Menon <nm...@ti...>
Date: Thu Sep 28 03:37:03 2023 -0500
tcl/target: Add support for TI MSPM0
Add basic support for Texas Instruments MSPM0L, C and G family of
Cortex-M0 based micro-controllers.
Change-Id: If2b5b1eca001f74d501ede67ec621c7497548a85
Co-developed-by: Henry Nguyen <h-n...@ti...>
Signed-off-by: Henry Nguyen <h-n...@ti...>
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8385
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
Reviewed-by: zapb <de...@za...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 68c7a825b..386528a9d 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -7438,6 +7438,7 @@ flash bank $_FLASHNAME mspm0 0 0 0 0 $_TARGETNAME
halt
flash erase_sector 0 0 last
flash write_image MAIN.bin 0x0
+mspm0_board_reset
@end example
@item @b{To erase and program the NONMAIN region:}
@@ -7445,10 +7446,29 @@ flash write_image MAIN.bin 0x0
halt
flash erase_sector 1 0 last
flash write_image NONMAIN.bin 0x41C00000
+mspm0_board_reset
@end example
@end itemize
+@deffn {TCL proc} {mspm0_board_reset}
+Performs an nRST toggle on the device.
+@end deffn
+
+@deffn {TCL proc} {mspm0_mass_erase}
+Sends the mass erase command to the SEC-AP mailbox and then performs
+an nRST toggle. Once the command has been fully processed by the ROM,
+all MAIN memory will be erased. NOTE: This command is not supported
+on MSPM0C* family of devices.
+@end deffn
+
+@deffn {TCL proc} {mspm0_factory_reset}
+Sends the factory reset command to the SEC-AP mailbox and then performs
+an nRST toggle. Once the command has been fully processed by the ROM,
+all MAIN memory will be erased and NONMAIN will be reset to its default
+values.
+@end deffn
+
@end deffn
@deffn {Flash Driver} {niietcm4}
diff --git a/tcl/target/ti_mspm0.cfg b/tcl/target/ti_mspm0.cfg
new file mode 100644
index 000000000..4e9b89c1f
--- /dev/null
+++ b/tcl/target/ti_mspm0.cfg
@@ -0,0 +1,199 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/
+#
+# Texas Instruments MSPM0L/G - ARM Cortex-M0 @ 32MHz
+# https://www.ti.com/microcontrollers-mcus-processors/arm-based-microcontrollers/arm-cortex-m0-mcus/overview.html
+#
+
+source [find bitsbytes.tcl]
+
+if { [info exists CHIPNAME] } {
+ set _CHIPNAME $CHIPNAME
+} else {
+ # Meant to work with MSPM0L and MSPM0G class of devices.
+ set _CHIPNAME mspm0x
+}
+
+if { [info exists CPUTAPID] } {
+ set _DAP_TAPID $CPUTAPID
+} else {
+ set _DAP_TAPID 0x4ba00477
+}
+
+if { [info exists DAP_SWD_ID] } {
+ set _DAP_SWD_ID $DAP_SWD_ID
+} else {
+ set _DAP_SWD_ID 0x2ba01477
+}
+
+source [find target/swj-dp.tcl]
+
+# MSPM0 only supports swd, so set it here and save a line for custom boards
+transport select swd
+
+set _DAP_ID $_DAP_SWD_ID
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_DAP_ID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+if { [info exists WORKAREABASE] } {
+ set _WORKAREABASE $WORKAREABASE
+} else {
+ set _WORKAREABASE 0x20000000
+}
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ # Smallest SRAM size is 1K SRAM.
+ set _WORKAREASIZE 0x400
+}
+
+#
+# MSPM0 Debug SubSystem Mailbox (DSSM) Communication helpers
+#
+
+proc _mspm0_wait_for_dssm_response {command} {
+ # Wait for SECAP::RCR rx_valid to be set
+ set timeout 1000
+ while { [expr { [$::_CHIPNAME.dap apreg 2 0xc] & 0x1}] != 0x1 } {
+ sleep 1
+ set timeout [expr {$timeout - 1}]
+ if { $timeout == 0 } {
+ set rcr [$::_CHIPNAME.dap apreg 2 0xc]
+ return -code error [format "MSPM0 SECAP RCR=0x%08x timeout rx_valid" $rcr]
+ }
+ }
+
+ # Read SECAP::RXD to clear the RX_VALID bit
+ set rxd [$::_CHIPNAME.dap apreg 2 0x8]
+ # Read SECAP::RCR
+ set rcr [$::_CHIPNAME.dap apreg 2 0xc]
+
+ # Check if we got successful response. This is denoted as:
+ # 8 LSBits of $command should matchup with SECAP::RCR
+ # and
+ # SECAP::RXD should be 0x10003
+ if { ([expr { $command & 0xff}] == $rcr) && ($rxd == 0x10003) } {
+ return 0
+ }
+
+ # Provide some debug log for users to report back if CMD fails.
+ return -code error [format "MSPM0 SECAP CMD FAIL! RXD: 0x%08X RCR: 0x%08X" $rxd $rcr]
+}
+
+proc _mspm0_dssm_command {command} {
+ # SECAP::TCR = command
+ $::_CHIPNAME.dap apreg 2 0x4 $command
+ # SECAP::TDR = 0x0
+ $::_CHIPNAME.dap apreg 2 0x0 0x0
+ # Read SECAP::RCR and RXD to clear up any prev pending reads
+ set rxd [$::_CHIPNAME.dap apreg 2 0x8]
+ set rcr [$::_CHIPNAME.dap apreg 2 0xc]
+ # Make sure everything is synced
+ sleep 1000
+ # Trigger nRST
+ mspm0_board_reset
+
+ # Wait for ROM to do it's magic and respond back
+ set res [_mspm0_wait_for_dssm_response $command]
+ if { $res } {
+ return $res
+ }
+ # Paranoid.. make sure ROM does what it is meant to do
+ # RX valid should have been cleared after the operation is
+ # complete
+ sleep 1000
+
+ # Trigger nRST to get back to sane system
+ mspm0_board_reset
+ sleep 1000
+
+ return 0
+}
+
+# NOTE: Password authentication scheme is NOT supported atm.
+# mspm0_factory_reset: Factory reset the board
+proc mspm0_factory_reset {} {
+ set res [_mspm0_dssm_command 0x020a]
+ if { $res } {
+ echo "Factory Reset failed!"
+ } else {
+ echo "Factory reset success! Halting processor"
+ # We need to halt the processor else the WDT fires!
+ halt
+ }
+ return $res
+}
+
+add_help_text mspm0_factory_reset "Force Factory reset to recover 'bricked' board"
+
+# NOTE: Password authentication scheme is NOT supported atm.
+# mspm0_mass_erase: Mass erase flash
+proc mspm0_mass_erase {} {
+ set res [_mspm0_dssm_command 0x020c]
+ if { $res } {
+ echo "Mass Erase failed!"
+ } else {
+ echo "Mass Erase success! Halting Processor"
+ # We need to halt the processor else the WDT fires!
+ halt
+ }
+ return $res
+}
+
+add_help_text mspm0_mass_erase "Mass erase flash"
+
+# mspm0_start_bootloader: Ask explicitly for bootloader startup
+proc mspm0_start_bootloader {} {
+ set res [_mspm0_dssm_command 0x0108]
+ if { $res } {
+ echo "Start BL failed!"
+ }
+ return $res
+}
+
+add_help_text mspm0_start_bootloader "Ask explicitly for bootloader startup"
+
+# MSPM0 requires board level NRST reset to be toggled for
+# Factory reset operations to function.
+# However this cannot be the default configuration as this
+# prevents reset init reset halt to function properly
+# since the Debug Subsystem (debugss) logic or coresight
+# seems impacted by nRST.
+# This can be overridden in board file as required.
+#
+# mspm0_board_reset: Board level reset
+proc mspm0_board_reset {} {
+ set user_reset_config [reset_config]
+ reset_config srst_only
+ set errno [catch {reset}]
+ eval reset_config $user_reset_config
+ if {$errno} {error}
+}
+
+add_help_text mspm0_board_reset "Request a board level reset"
+
+# If the flash is empty or the device is already in low-power state, then
+# debug access is not available. to handle this, explicitly control power ap
+# to provide access. Refer to Technical Reference Manual for further info.
+proc _mspm0_enable_low_power_mode { } {
+ # PWR_AP::DPREC <= FRCACT(3)=1, RST_CTL(14:16)=1, IHIB_SLP(20)=1
+ $::_CHIPNAME.dap apreg 4 0x00 0x104008
+ # PWR_AP::SPREC <= SYSRST=1
+ $::_CHIPNAME.dap apreg 4 0xF0 0x01
+ # PWR_AP::DPREC <= FRCACT(3)=1, IHIB_SLP(20)=1
+ $::_CHIPNAME.dap apreg 4 0x00 0x100008
+}
+
+$_TARGETNAME configure -event examine-start { _mspm0_enable_low_power_mode }
+$_TARGETNAME configure -work-area-phys $_WORKAREABASE -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME.main mspm0 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME.nonmain mspm0 0x41c00000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME.data mspm0 0x41d00000 0 0 0 $_TARGETNAME
+
+cortex_m reset_config sysresetreq
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 20 +++++
tcl/target/ti_mspm0.cfg | 199 ++++++++++++++++++++++++++++++++++++++++++++++++
2 files changed, 219 insertions(+)
create mode 100644 tcl/target/ti_mspm0.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-03-09 13:26:45
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 8a6f89ca170ce69835f03805aa60106801da61a8 (commit)
from b6b5edf13b5d3500c94a5afc7adda132768cd568 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 8a6f89ca170ce69835f03805aa60106801da61a8
Author: Nishanth Menon <nm...@ti...>
Date: Thu Sep 28 03:37:03 2023 -0500
flash/nor: Add basic support for TI's MSPM0L/G family
Add basic flashing support for Texas Instruments MSPM0L, C and G
family of Cortex-M0 based micro-controllers.
This initial basic flashing support allows for controlling protection,
erase, write and read of non-main flash region.
This has been tested with:
* Valgrind (3.22.0):
valgrind --leak-check=full --show-leak-kinds=all \
--track-origins=yes --verbose
* Ubuntu clang version 20.0.0
(++20241014053649+ed77df56f272-1~exp1~20241014053827.1987)
Valgrind-clean, no new Clang analyzer or sparse warnings have been
introduced.
Change-Id: I29b8055ea6da9c38c5b7b91bea1ec7581c5bc8ff
Co-developed-by: Henry Nguyen <h-n...@ti...>
Signed-off-by: Henry Nguyen <h-n...@ti...>
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8384
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: zapb <de...@za...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 2ec49a4c0..68c7a825b 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -7401,6 +7401,56 @@ msp432 bsl lock
@end deffn
@end deffn
+@deffn {Flash Driver} {mspm0}
+
+All Arm Cortex-M0+ MSPM0 microcontroller versions from Texas Instruments
+include internal flash. The mspm0 flash driver automatically recognizes the
+specific version's flash parameters and autoconfigures itself. The main
+program flash starts at address 0x0. Non-main flash starts at 0x41c00000.
+If present on the device, the optional region called "Data" starts at
+0x41d00000.
+
+@b{Warning}:
+
+@itemize @bullet
+@item @b{Reset while MCU operation:} When erasing all of MAIN memory, if the
+MCU is still executing from MAIN memory do not reset the device as it could
+cause a double hard-fault due to the missing interrupt vector table at the
+start of memory. To recover from such scenario reset or power-cycle the MCU.
+
+@item @b{No explicit protection support:} MSPM0 flash controller auto-protect
+themselves after every flash operation. As a result of this, OpenOCD does not
+explicitly provide any protection function and automatically un-protects
+required sections as flash operations are requested.
+@end itemize
+
+@b{Examples}:
+
+@itemize @bullet
+
+@item @b{Flash bank description:}
+@example
+flash bank $_FLASHNAME mspm0 0 0 0 0 $_TARGETNAME
+@end example
+
+@item @b{To erase and program the MAIN region:}
+@example
+halt
+flash erase_sector 0 0 last
+flash write_image MAIN.bin 0x0
+@end example
+
+@item @b{To erase and program the NONMAIN region:}
+@example
+halt
+flash erase_sector 1 0 last
+flash write_image NONMAIN.bin 0x41C00000
+@end example
+
+@end itemize
+
+@end deffn
+
@deffn {Flash Driver} {niietcm4}
This drivers handles the integrated NOR flash on NIIET Cortex-M4
based controllers. Flash size and sector layout are auto-configured by the driver.
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index 829687761..147807fba 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -45,6 +45,7 @@ NOR_DRIVERS = \
%D%/max32xxx.c \
%D%/mdr.c \
%D%/msp432.c \
+ %D%/mspm0.c \
%D%/mrvlqspi.c \
%D%/niietcm4.c \
%D%/non_cfi.c \
diff --git a/src/flash/nor/driver.h b/src/flash/nor/driver.h
index 852a55a11..794566f12 100644
--- a/src/flash/nor/driver.h
+++ b/src/flash/nor/driver.h
@@ -274,6 +274,7 @@ extern const struct flash_driver max32xxx_flash;
extern const struct flash_driver mdr_flash;
extern const struct flash_driver mrvlqspi_flash;
extern const struct flash_driver msp432_flash;
+extern const struct flash_driver mspm0_flash;
extern const struct flash_driver niietcm4_flash;
extern const struct flash_driver npcx_flash;
extern const struct flash_driver nrf51_flash;
diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c
index ce97b8150..67d86243b 100644
--- a/src/flash/nor/drivers.c
+++ b/src/flash/nor/drivers.c
@@ -51,6 +51,7 @@ static const struct flash_driver * const flash_drivers[] = {
&mdr_flash,
&mrvlqspi_flash,
&msp432_flash,
+ &mspm0_flash,
&niietcm4_flash,
&npcx_flash,
&nrf5_flash,
diff --git a/src/flash/nor/mspm0.c b/src/flash/nor/mspm0.c
new file mode 100644
index 000000000..4731c89cc
--- /dev/null
+++ b/src/flash/nor/mspm0.c
@@ -0,0 +1,1131 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/***************************************************************************
+ * Copyright (C) 2023-2025 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ * NOR flash driver for MSPM0L and MSPM0G class of uC from Texas Instruments.
+ *
+ * See:
+ * https://www.ti.com/microcontrollers-mcus-processors/arm-based-microcontrollers/arm-cortex-m0-mcus/overview.html
+ ***************************************************************************/
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <helper/bits.h>
+#include <helper/time_support.h>
+
+/* MSPM0 Region memory map */
+#define MSPM0_FLASH_BASE_NONMAIN 0x41C00000
+#define MSPM0_FLASH_END_NONMAIN 0x41C00400
+#define MSPM0_FLASH_BASE_MAIN 0x0
+#define MSPM0_FLASH_BASE_DATA 0x41D00000
+
+/* MSPM0 FACTORYREGION registers */
+#define MSPM0_FACTORYREGION 0x41C40000
+#define MSPM0_TRACEID (MSPM0_FACTORYREGION + 0x000)
+#define MSPM0_DID (MSPM0_FACTORYREGION + 0x004)
+#define MSPM0_USERID (MSPM0_FACTORYREGION + 0x008)
+#define MSPM0_SRAMFLASH (MSPM0_FACTORYREGION + 0x018)
+
+/* MSPM0 FCTL registers */
+#define FLASH_CONTROL_BASE 0x400CD000
+#define FCTL_REG_DESC (FLASH_CONTROL_BASE + 0x10FC)
+#define FCTL_REG_CMDEXEC (FLASH_CONTROL_BASE + 0x1100)
+#define FCTL_REG_CMDTYPE (FLASH_CONTROL_BASE + 0x1104)
+#define FCTL_REG_CMDADDR (FLASH_CONTROL_BASE + 0x1120)
+#define FCTL_REG_CMDBYTEN (FLASH_CONTROL_BASE + 0x1124)
+#define FCTL_REG_CMDDATA0 (FLASH_CONTROL_BASE + 0x1130)
+#define FCTL_REG_CMDWEPROTA (FLASH_CONTROL_BASE + 0x11D0)
+#define FCTL_REG_CMDWEPROTB (FLASH_CONTROL_BASE + 0x11D4)
+#define FCTL_REG_CMDWEPROTNM (FLASH_CONTROL_BASE + 0x1210)
+#define FCTL_REG_STATCMD (FLASH_CONTROL_BASE + 0x13D0)
+
+/* FCTL_STATCMD[CMDDONE] Bits */
+#define FCTL_STATCMD_CMDDONE_MASK 0x00000001
+#define FCTL_STATCMD_CMDDONE_STATDONE 0x00000001
+
+/* FCTL_STATCMD[CMDPASS] Bits */
+#define FCTL_STATCMD_CMDPASS_MASK 0x00000002
+#define FCTL_STATCMD_CMDPASS_STATPASS 0x00000002
+
+/*
+ * FCTL_CMDEXEC Bits
+ * FCTL_CMDEXEC[VAL] Bits
+ */
+#define FCTL_CMDEXEC_VAL_EXECUTE 0x00000001
+
+/* FCTL_CMDTYPE[COMMAND] Bits */
+#define FCTL_CMDTYPE_COMMAND_PROGRAM 0x00000001
+#define FCTL_CMDTYPE_COMMAND_ERASE 0x00000002
+
+/* FCTL_CMDTYPE[SIZE] Bits */
+#define FCTL_CMDTYPE_SIZE_ONEWORD 0x00000000
+#define FCTL_CMDTYPE_SIZE_SECTOR 0x00000040
+
+/* FCTL_FEATURE_VER_B minimum */
+#define FCTL_FEATURE_VER_B 0xA
+
+#define MSPM0_MAX_PROTREGS 3
+
+#define MSPM0_FLASH_TIMEOUT_MS 8000
+#define ERR_STRING_MAX 255
+
+/* SYSCTL BASE */
+#define SYSCTL_BASE 0x400AF000
+#define SYSCTL_SECCFG_SECSTATUS (SYSCTL_BASE + 0x00003048)
+
+/* TI manufacturer ID */
+#define TI_MANUFACTURER_ID 0x17
+
+/* Defines for probe status */
+#define MSPM0_NO_ID_FOUND 0
+#define MSPM0_DEV_ID_FOUND 1
+#define MSPM0_DEV_PART_ID_FOUND 2
+
+struct mspm0_flash_bank {
+ /* chip id register */
+ uint32_t did;
+ /* Device Unique ID register */
+ uint32_t traceid;
+ unsigned char version;
+
+ const char *name;
+
+ /* Decoded flash information */
+ unsigned int data_flash_size_kb;
+ unsigned int main_flash_size_kb;
+ unsigned int main_flash_num_banks;
+ unsigned int sector_size;
+ /* Decoded SRAM information */
+ unsigned int sram_size_kb;
+
+ /* Flash word size: 64 bit = 8, 128bit = 16 bytes */
+ unsigned char flash_word_size_bytes;
+
+ /* Protection register stuff */
+ unsigned int protect_reg_base;
+ unsigned int protect_reg_count;
+
+ /* Flashctl version: A - CMDWEPROTA/B, B- CMDWEPROTB */
+ unsigned char flash_version;
+};
+
+struct mspm0_part_info {
+ const char *part_name;
+ unsigned short part;
+ unsigned char variant;
+};
+
+struct mspm0_family_info {
+ const char *family_name;
+ unsigned short part_num;
+ unsigned char part_count;
+ const struct mspm0_part_info *part_info;
+};
+
+/* https://www.ti.com/lit/ds/symlink/mspm0l1346.pdf Table 8-13 and so on */
+static const struct mspm0_part_info mspm0l_parts[] = {
+ { "MSPM0L1105TDGS20R", 0x51DB, 0x16 },
+ { "MSPM0L1105TDGS28R", 0x51DB, 0x83 },
+ { "MSPM0L1105TDYYR", 0x51DB, 0x54 },
+ { "MSPM0L1105TRGER", 0x51DB, 0x86 },
+ { "MSPM0L1105TRHBR", 0x51DB, 0x68 },
+ { "MSPM0L1106TDGS20R", 0x5552, 0x4B },
+ { "MSPM0L1106TDGS28R", 0x5552, 0x98 },
+ { "MSPM0L1106TDYYR", 0x5552, 0x9D },
+ { "MSPM0L1106TRGER", 0x5552, 0x90 },
+ { "MSPM0L1106TRHBR", 0x5552, 0x53 },
+ { "MSPM0L1303SRGER", 0xef0, 0x17 },
+ { "MSPM0L1303TRGER", 0xef0, 0xe2 },
+ { "MSPM0L1304QDGS20R", 0xd717, 0x91 },
+ { "MSPM0L1304QDGS28R", 0xd717, 0xb6 },
+ { "MSPM0L1304QDYYR", 0xd717, 0xa0 },
+ { "MSPM0L1304QRHBR", 0xd717, 0xa9 },
+ { "MSPM0L1304SDGS20R", 0xd717, 0xfa },
+ { "MSPM0L1304SDGS28R", 0xd717, 0x73 },
+ { "MSPM0L1304SDYYR", 0xd717, 0xb7 },
+ { "MSPM0L1304SRGER", 0xd717, 0x26 },
+ { "MSPM0L1304SRHBR", 0xd717, 0xe4 },
+ { "MSPM0L1304TDGS20R", 0xd717, 0x33 },
+ { "MSPM0L1304TDGS28R", 0xd717, 0xa8 },
+ { "MSPM0L1304TDYYR", 0xd717, 0xf9 },
+ { "MSPM0L1304TRGER", 0xd717, 0xb7 },
+ { "MSPM0L1304TRHBR", 0xd717, 0x5a },
+ { "MSPM0L1305QDGS20R", 0x4d03, 0xb7 },
+ { "MSPM0L1305QDGS28R", 0x4d03, 0x74 },
+ { "MSPM0L1305QDYYR", 0x4d03, 0xec },
+ { "MSPM0L1305QRHBR", 0x4d03, 0x78 },
+ { "MSPM0L1305SDGS20R", 0x4d03, 0xc7 },
+ { "MSPM0L1305SDGS28R", 0x4d03, 0x64 },
+ { "MSPM0L1305SDYYR", 0x4d03, 0x91 },
+ { "MSPM0L1305SRGER", 0x4d03, 0x73 },
+ { "MSPM0L1305SRHBR", 0x4d03, 0x2d },
+ { "MSPM0L1305TDGS20R", 0x4d03, 0xa0 },
+ { "MSPM0L1305TDGS28R", 0x4d03, 0xfb },
+ { "MSPM0L1305TDYYR", 0x4d03, 0xde },
+ { "MSPM0L1305TRGER", 0x4d03, 0xea },
+ { "MSPM0L1305TRHBR", 0x4d03, 0x85 },
+ { "MSPM0L1306QDGS20R", 0xbb70, 0x59 },
+ { "MSPM0L1306QDGS28R", 0xbb70, 0xf7 },
+ { "MSPM0L1306QDYYR", 0xbb70, 0x9f },
+ { "MSPM0L1306QRHBR", 0xbb70, 0xc2 },
+ { "MSPM0L1306SDGS20R", 0xbb70, 0xf4 },
+ { "MSPM0L1306SDGS28R", 0xbb70, 0x5 },
+ { "MSPM0L1306SDYYR", 0xbb70, 0xe },
+ { "MSPM0L1306SRGER", 0xbb70, 0x7f },
+ { "MSPM0L1306SRHBR", 0xbb70, 0x3c },
+ { "MSPM0L1306TDGS20R", 0xbb70, 0xa },
+ { "MSPM0L1306TDGS28R", 0xbb70, 0x63 },
+ { "MSPM0L1306TDYYR", 0xbb70, 0x35 },
+ { "MSPM0L1306TRGER", 0xbb70, 0xaa },
+ { "MSPM0L1306TRHBR", 0xbb70, 0x52 },
+ { "MSPM0L1343TDGS20R", 0xb231, 0x2e },
+ { "MSPM0L1344TDGS20R", 0x40b0, 0xd0 },
+ { "MSPM0L1345TDGS28R", 0x98b4, 0x74 },
+ { "MSPM0L1346TDGS28R", 0xf2b5, 0xef },
+};
+
+/* https://www.ti.com/lit/ds/symlink/mspm0g3506.pdf Table 8-20 */
+static const struct mspm0_part_info mspm0g_parts[] = {
+ { "MSPM0G1105TPTR", 0x8934, 0xD },
+ { "MSPM0G1105TRGZR", 0x8934, 0xFE },
+ { "MSPM0G1106TPMR", 0x477B, 0xD4 },
+ { "MSPM0G1106TPTR", 0x477B, 0x71 },
+ { "MSPM0G1106TRGZR", 0x477B, 0xBB },
+ { "MSPM0G1106TRHBR", 0x477B, 0x0 },
+ { "MSPM0G1107TDGS28R", 0x807B, 0x82 },
+ { "MSPM0G1107TPMR", 0x807B, 0xB3 },
+ { "MSPM0G1107TPTR", 0x807B, 0x32 },
+ { "MSPM0G1107TRGER", 0x807B, 0x79 },
+ { "MSPM0G1107TRGZR", 0x807B, 0x20 },
+ { "MSPM0G1107TRHBR", 0x807B, 0xBC },
+ { "MSPM0G1505SDGS28R", 0x13C4, 0x73 },
+ { "MSPM0G1505SPMR", 0x13C4, 0x53 },
+ { "MSPM0G1505SPTR", 0x13C4, 0x3E },
+ { "MSPM0G1505SRGER", 0x13C4, 0x47 },
+ { "MSPM0G1505SRGZR", 0x13C4, 0x34 },
+ { "MSPM0G1505SRHBR", 0x13C4, 0x30 },
+ { "MSPM0G1506SDGS28R", 0x5AE0, 0x3A },
+ { "MSPM0G1506SPMR", 0x5AE0, 0xF6 },
+ { "MSPM0G1506SRGER", 0x5AE0, 0x67 },
+ { "MSPM0G1506SRGZR", 0x5AE0, 0x75 },
+ { "MSPM0G1506SRHBR", 0x5AE0, 0x57 },
+ { "MSPM0G1507SDGS28R", 0x2655, 0x6D },
+ { "MSPM0G1507SPMR", 0x2655, 0x97 },
+ { "MSPM0G1507SRGER", 0x2655, 0x83 },
+ { "MSPM0G1507SRGZR", 0x2655, 0xD3 },
+ { "MSPM0G1507SRHBR", 0x2655, 0x4D },
+ { "MSPM0G3105SDGS20R", 0x4749, 0x21 },
+ { "MSPM0G3105SDGS28R", 0x4749, 0xDD },
+ { "MSPM0G3105SRHBR", 0x4749, 0xBE },
+ { "MSPM0G3106SDGS20R", 0x54C7, 0xD2 },
+ { "MSPM0G3106SDGS28R", 0x54C7, 0xB9 },
+ { "MSPM0G3106SRHBR", 0x54C7, 0x67 },
+ { "MSPM0G3107SDGS20R", 0xAB39, 0x5C },
+ { "MSPM0G3107SDGS28R", 0xAB39, 0xCC },
+ { "MSPM0G3107SRHBR", 0xAB39, 0xB7 },
+ { "MSPM0G3505SDGS28R", 0xc504, 0x8e },
+ { "MSPM0G3505SPMR", 0xc504, 0x1d },
+ { "MSPM0G3505SPTR", 0xc504, 0x93 },
+ { "MSPM0G3505SRGZR", 0xc504, 0xc7 },
+ { "MSPM0G3505SRHBR", 0xc504, 0xe7 },
+ { "MSPM0G3505TDGS28R", 0xc504, 0xdf },
+ { "MSPM0G3506SDGS28R", 0x151f, 0x8 },
+ { "MSPM0G3506SPMR", 0x151f, 0xd4 },
+ { "MSPM0G3506SPTR", 0x151f, 0x39 },
+ { "MSPM0G3506SRGZR", 0x151f, 0xfe },
+ { "MSPM0G3506SRHBR", 0x151f, 0xb5 },
+ { "MSPM0G3507SDGS28R", 0xae2d, 0xca },
+ { "MSPM0G3507SPMR", 0xae2d, 0xc7 },
+ { "MSPM0G3507SPTR", 0xae2d, 0x3f },
+ { "MSPM0G3507SRGZR", 0xae2d, 0xf7 },
+ { "MSPM0G3507SRHBR", 0xae2d, 0x4c },
+ { "M0G3107QPMRQ1", 0x4e2f, 0x51 },
+ { "M0G3107QPTRQ1", 0x4e2f, 0xc7},
+ { "M0G3107QRGZRQ1", 0x4e2f, 0x8a },
+ { "M0G3107QRHBRQ1", 0x4e2f, 0x9a},
+ { "M0G3107QDGS28RQ1", 0x4e2f, 0xd5},
+ { "M0G3107QDGS28RQ1", 0x4e2f, 0x67},
+ { "M0G3107QDGS20RQ1", 0x4e2f, 0xfd},
+ { "M0G3106QPMRQ1", 0x54C7, 0x08},
+ { "M0G3105QDGS32RQ1", 0x1349, 0x08},
+ { "M0G3106QPTRQ1", 0x54C7, 0x3F},
+ { "M0G3105QDGS28RQ1", 0x1349, 0x1B},
+ { "M0G3106QRGZRQ1", 0x94AD, 0xE6},
+ { "M0G3105QDGS20RQ1", 0x1349, 0xFB},
+ { "M0G3106QRHBRQ1", 0x94AD, 0x20},
+ { "M0G3106QDGS32RQ1", 0x94AD, 0x8D},
+ { "M0G3106QDGS28RQ1", 0x94AD, 0x03},
+ { "M0G3106QDGS20RQ1", 0x94AD, 0x6F},
+ { "M0G3105QPMRQ1", 0x1349, 0xD0},
+ { "M0G3105QPTRQ1", 0x1349, 0xEF},
+ { "M0G3105QRGZRQ1", 0x1349, 0x70},
+ { "M0G3105QRHBRQ1", 0x1349, 0x01},
+};
+
+/* https://www.ti.com/lit/gpn/mspm0c1104 Table 8-12 and so on */
+static const struct mspm0_part_info mspm0c_parts[] = {
+ { "MSPS003F4SPW20R", 0x57b3, 0x70},
+ { "MSPM0C1104SDGS20R", 0x57b3, 0x71},
+ { "MSPM0C1104SRUKR", 0x57b3, 0x73},
+ { "MSPM0C1104SDYYR", 0x57b3, 0x75},
+ { "MSPM0C1104SDDFR", 0x57b3, 0x77},
+ { "MSPM0C1104SDSGR", 0x57b3, 0x79},
+};
+
+/* https://www.ti.com/lit/gpn/MSPM0L2228 Table 8-16 and so on */
+static const struct mspm0_part_info mspm0lx22x_parts[] = {
+ { "MSPM0L1227SRGER", 0x7C32, 0xF1},
+ { "MSPM0L1227SPTR", 0x7C32, 0xC9},
+ { "MSPM0L1227SPMR", 0x7C32, 0x1C},
+ { "MSPM0L1227SPNAR", 0x7C32, 0x91},
+ { "MSPM0L1227SPNR", 0x7C32, 0x39},
+ { "MSPM0L1228SRGER", 0x33F7, 0x13},
+ { "MSPM0L1228SRHBR", 0x33F7, 0x3A},
+ { "MSPM0L1228SRGZR", 0x33F7, 0xBC},
+ { "MSPM0L1228SPTR", 0x33F7, 0xF8},
+ { "MSPM0L1228SPMR", 0x33F7, 0xCE},
+ { "MSPM0L1228SPNAR", 0x33F7, 0x59},
+ { "MSPM0L1228SPNR", 0x33F7, 0x7},
+ { "MSPM0L2227SRGZR", 0x5E8F, 0x90},
+ { "MSPM0L2227SPTR", 0x5E8F, 0xA},
+ { "MSPM0L2227SPMR", 0x5E8F, 0x6D},
+ { "MSPM0L2227SPNAR", 0x5E8F, 0x24},
+ { "MSPM0L2227SPNR", 0x5E8F, 0x68},
+ { "MSPM0L2228SRGZR", 0x2C38, 0xB8},
+ { "MSPM0L2228SPTR", 0x2C38, 0x25},
+ { "MSPM0L2228SPMR", 0x2C38, 0x6E},
+ { "MSPM0L2228SPNAR", 0x2C38, 0x63},
+ { "MSPM0L2228SPNR", 0x2C38, 0x3C},
+};
+
+static const struct mspm0_family_info mspm0_finf[] = {
+ { "MSPM0L", 0xbb82, ARRAY_SIZE(mspm0l_parts), mspm0l_parts },
+ { "MSPM0Lx22x", 0xbb9f, ARRAY_SIZE(mspm0lx22x_parts), mspm0lx22x_parts },
+ { "MSPM0G", 0xbb88, ARRAY_SIZE(mspm0g_parts), mspm0g_parts },
+ { "MSPM0C", 0xbba1, ARRAY_SIZE(mspm0c_parts), mspm0c_parts },
+};
+
+/*
+ * OpenOCD command interface
+ */
+
+/*
+ * flash_bank mspm0 <base> <size> 0 0 <target#>
+ */
+FLASH_BANK_COMMAND_HANDLER(mspm0_flash_bank_command)
+{
+ struct mspm0_flash_bank *mspm0_info;
+
+ switch (bank->base) {
+ case MSPM0_FLASH_BASE_NONMAIN:
+ case MSPM0_FLASH_BASE_MAIN:
+ case MSPM0_FLASH_BASE_DATA:
+ break;
+ default:
+ LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT, bank->base);
+ return ERROR_FAIL;
+ }
+
+ mspm0_info = calloc(1, sizeof(struct mspm0_flash_bank));
+ if (!mspm0_info) {
+ LOG_ERROR("%s: Out of memory for mspm0_info!", __func__);
+ return ERROR_FAIL;
+ }
+
+ bank->driver_priv = mspm0_info;
+
+ mspm0_info->sector_size = 0x400;
+
+ return ERROR_OK;
+}
+
+/*
+ * Chip identification and status
+ */
+static int get_mspm0_info(struct flash_bank *bank, struct command_invocation *cmd)
+{
+ struct mspm0_flash_bank *mspm0_info = bank->driver_priv;
+
+ if (mspm0_info->did == 0)
+ return ERROR_FLASH_BANK_NOT_PROBED;
+
+ command_print_sameline(cmd,
+ "\nTI MSPM0 information: Chip is "
+ "%s rev %d Device Unique ID: 0x%" PRIu32 "\n",
+ mspm0_info->name, mspm0_info->version,
+ mspm0_info->traceid);
+ command_print_sameline(cmd,
+ "main flash: %uKiB in %u bank(s), sram: %uKiB, data flash: %uKiB",
+ mspm0_info->main_flash_size_kb,
+ mspm0_info->main_flash_num_banks, mspm0_info->sram_size_kb,
+ mspm0_info->data_flash_size_kb);
+
+ return ERROR_OK;
+}
+
+/* Extract a bitfield helper */
+static unsigned int mspm0_extract_val(unsigned int var, unsigned char hi, unsigned char lo)
+{
+ return (var & GENMASK(hi, lo)) >> lo;
+}
+
+static int mspm0_read_part_info(struct flash_bank *bank)
+{
+ struct mspm0_flash_bank *mspm0_info = bank->driver_priv;
+ struct target *target = bank->target;
+ const struct mspm0_family_info *minfo = NULL;
+
+ /* Read and parse chip identification and flash version register */
+ uint32_t did;
+ int retval = target_read_u32(target, MSPM0_DID, &did);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to read device ID");
+ return retval;
+ }
+ retval = target_read_u32(target, MSPM0_TRACEID, &mspm0_info->traceid);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to read trace ID");
+ return retval;
+ }
+ uint32_t userid;
+ retval = target_read_u32(target, MSPM0_USERID, &userid);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to read user ID");
+ return retval;
+ }
+ uint32_t flashram;
+ retval = target_read_u32(target, MSPM0_SRAMFLASH, &flashram);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to read sramflash register");
+ return retval;
+ }
+ uint32_t flashdesc;
+ retval = target_read_u32(target, FCTL_REG_DESC, &flashdesc);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to read flashctl description register");
+ return retval;
+ }
+
+ unsigned char version = mspm0_extract_val(did, 31, 28);
+ unsigned short pnum = mspm0_extract_val(did, 27, 12);
+ unsigned char variant = mspm0_extract_val(userid, 23, 16);
+ unsigned short part = mspm0_extract_val(userid, 15, 0);
+ unsigned short manufacturer = mspm0_extract_val(did, 11, 1);
+
+ /*
+ * Valid DIE and manufacturer ID?
+ * Check the ALWAYS_1 bit to be 1 and manufacturer to be 0x17. All MSPM0
+ * devices within the Device ID field of the factory constants will
+ * always read 0x17 as it is TI's JEDEC bank and company code. If 1
+ * and 0x17 is not read from their respective registers then it truly
+ * is not a MSPM0 device so we will return an error instead of
+ * going any further.
+ */
+ if (!(did & BIT(0)) || !(manufacturer & TI_MANUFACTURER_ID)) {
+ LOG_WARNING("Unknown Device ID[0x%" PRIx32 "], cannot identify target",
+ did);
+ LOG_DEBUG("did 0x%" PRIx32 ", traceid 0x%" PRIx32 ", userid 0x%" PRIx32
+ ", flashram 0x%" PRIx32 "", did, mspm0_info->traceid, userid,
+ flashram);
+ return ERROR_FLASH_OPERATION_FAILED;
+ }
+
+ /* Initialize master index selector and probe status*/
+ unsigned char minfo_idx = 0xff;
+ unsigned char probe_status = MSPM0_NO_ID_FOUND;
+
+ /* Check if we at least know the family of devices */
+ for (unsigned int i = 0; i < ARRAY_SIZE(mspm0_finf); i++) {
+ if (mspm0_finf[i].part_num == pnum) {
+ minfo_idx = i;
+ minfo = &mspm0_finf[i];
+ probe_status = MSPM0_DEV_ID_FOUND;
+ break;
+ }
+ }
+
+ /* Initialize part index selector*/
+ unsigned char pinfo_idx = 0xff;
+
+ /*
+ * If we can identify the part number then we will attempt to identify
+ * the specific chip. Otherwise, if we do not know the part number then
+ * it would be useless to identify the specific chip.
+ */
+ if (probe_status == MSPM0_DEV_ID_FOUND) {
+ /* Can we specifically identify the chip */
+ for (unsigned int i = 0; i < minfo->part_count; i++) {
+ if (minfo->part_info[i].part == part
+ && minfo->part_info[i].variant == variant) {
+ pinfo_idx = i;
+ probe_status = MSPM0_DEV_PART_ID_FOUND;
+ break;
+ }
+ }
+ }
+
+ /*
+ * We will check the status of our probe within this switch-case statement
+ * using these three scenarios.
+ *
+ * 1) Device, part, and variant ID is unknown.
+ * 2) Device ID is known but the part/variant ID is unknown.
+ * 3) Device ID and part/variant ID is known
+ *
+ * For scenario 1, we allow the user to continue because if the
+ * manufacturer matches TI's JEDEC value and ALWAYS_1 from the device ID
+ * field is correct then the assumption the user is using an MSPM0 device
+ * can be made.
+ */
+ switch (probe_status) {
+ case MSPM0_NO_ID_FOUND:
+ mspm0_info->name = "mspm0x";
+ LOG_INFO("Unidentified PART[0x%x]/variant[0x%x"
+ "], unknown DeviceID[0x%x"
+ "]. Attempting to proceed as %s.", part, variant, pnum,
+ mspm0_info->name);
+ break;
+ case MSPM0_DEV_ID_FOUND:
+ mspm0_info->name = mspm0_finf[minfo_idx].family_name;
+ LOG_INFO("Unidentified PART[0x%x]/variant[0x%x"
+ "], known DeviceID[0x%x"
+ "]. Attempting to proceed as %s.", part, variant, pnum,
+ mspm0_info->name);
+ break;
+ case MSPM0_DEV_PART_ID_FOUND:
+ default:
+ mspm0_info->name = mspm0_finf[minfo_idx].part_info[pinfo_idx].part_name;
+ LOG_DEBUG("Part: %s detected", mspm0_info->name);
+ break;
+ }
+
+ mspm0_info->did = did;
+ mspm0_info->version = version;
+ mspm0_info->data_flash_size_kb = mspm0_extract_val(flashram, 31, 26);
+ mspm0_info->main_flash_size_kb = mspm0_extract_val(flashram, 11, 0);
+ mspm0_info->main_flash_num_banks = mspm0_extract_val(flashram, 13, 12) + 1;
+ mspm0_info->sram_size_kb = mspm0_extract_val(flashram, 25, 16);
+ mspm0_info->flash_version = mspm0_extract_val(flashdesc, 15, 12);
+
+ /*
+ * Hardcode flash_word_size unless we find some other pattern
+ * See section 7.7 (Foot note mentions the flash word size).
+ * almost all values seem to be 8 bytes, but if there are variance,
+ * then we should update mspm0_part_info structure with this info.
+ */
+ mspm0_info->flash_word_size_bytes = 8;
+
+ LOG_DEBUG("Detected: main flash: %uKb in %u banks, sram: %uKb, data flash: %uKb",
+ mspm0_info->main_flash_size_kb, mspm0_info->main_flash_num_banks,
+ mspm0_info->sram_size_kb, mspm0_info->data_flash_size_kb);
+
+ return ERROR_OK;
+}
+
+/*
+ * Decode error values
+ */
+static const struct {
+ const unsigned char bit_offset;
+ const char *fail_string;
+} mspm0_fctl_fail_decode_strings[] = {
+ { 2, "CMDINPROGRESS" },
+ { 4, "FAILWEPROT" },
+ { 5, "FAILVERIFY" },
+ { 6, "FAILILLADDR" },
+ { 7, "FAILMODE" },
+ { 12, "FAILMISC" },
+};
+
+static const char *mspm0_fctl_translate_ret_err(unsigned int return_code)
+{
+ for (unsigned int i = 0; i < ARRAY_SIZE(mspm0_fctl_fail_decode_strings); i++) {
+ if (return_code & BIT(mspm0_fctl_fail_decode_strings[i].bit_offset))
+ return mspm0_fctl_fail_decode_strings[i].fail_string;
+ }
+
+ /* If unknown error notify the user*/
+ return "FAILUNKNOWN";
+}
+
+static int mspm0_fctl_get_sector_reg(struct flash_bank *bank, unsigned int addr,
+ unsigned int *reg, unsigned int *sector_mask)
+{
+ struct mspm0_flash_bank *mspm0_info = bank->driver_priv;
+ struct target *target = bank->target;
+ int ret = ERROR_OK;
+ unsigned int sector_num = (addr >> 10);
+ unsigned int sector_in_bank = sector_num;
+ unsigned int phys_sector_num = sector_num;
+ uint32_t sysctl_sec_status;
+ unsigned int exec_upper_bank;
+
+ /*
+ * If the device has dual banks we will need to check if it is configured
+ * to execute from the upper bank. In the scenario that we are executing
+ * from upper bank then we will need to protect it using CMDWEPROTA rather
+ * than CMDWEPROTB. We also need to take into account what sector
+ * we're using when going between banks.
+ */
+ if (mspm0_info->main_flash_num_banks > 1 &&
+ bank->base == MSPM0_FLASH_BASE_MAIN) {
+ ret = target_read_u32(target, SYSCTL_SECCFG_SECSTATUS, &sysctl_sec_status);
+ if (ret != ERROR_OK)
+ return ret;
+ exec_upper_bank = mspm0_extract_val(sysctl_sec_status, 12, 12);
+ if (exec_upper_bank) {
+ if (sector_num > (mspm0_info->main_flash_size_kb / 2)) {
+ phys_sector_num =
+ sector_num - (mspm0_info->main_flash_size_kb / 2);
+ } else {
+ phys_sector_num =
+ sector_num + (mspm0_info->main_flash_size_kb / 2);
+ }
+ }
+ sector_in_bank =
+ sector_num % (mspm0_info->main_flash_size_kb /
+ mspm0_info->main_flash_num_banks);
+ }
+
+ /*
+ * NOTE: MSPM0 devices of version A will use CMDWEPROTA and CMDWEPROTB
+ * for MAIN flash. CMDWEPROTC is included in the TRM/DATASHEET but for
+ * all practical purposes, it is considered reserved. If the flash
+ * version on the device is version B, then we will only use
+ * CMDWEPROTB for MAIN and DATA flash if the device has it.
+ */
+ switch (bank->base) {
+ case MSPM0_FLASH_BASE_MAIN:
+ case MSPM0_FLASH_BASE_DATA:
+ if (mspm0_info->flash_version < FCTL_FEATURE_VER_B) {
+ /* Use CMDWEPROTA */
+ if (phys_sector_num < 32) {
+ *sector_mask = BIT(phys_sector_num);
+ *reg = FCTL_REG_CMDWEPROTA;
+ }
+
+ /* Use CMDWEPROTB */
+ if (phys_sector_num >= 32 && sector_in_bank < 256) {
+ /* Dual bank system */
+ if (mspm0_info->main_flash_num_banks > 1)
+ *sector_mask = BIT(sector_in_bank / 8);
+ else /* Single bank system */
+ *sector_mask = BIT((sector_in_bank - 32) / 8);
+ *reg = FCTL_REG_CMDWEPROTB;
+ }
+ } else {
+ *sector_mask = BIT((sector_in_bank / 8) % 32);
+ *reg = FCTL_REG_CMDWEPROTB;
+ }
+ break;
+ case MSPM0_FLASH_BASE_NONMAIN:
+ *sector_mask = BIT(sector_num % 32);
+ *reg = FCTL_REG_CMDWEPROTNM;
+ break;
+ default:
+ /*
+ * Not expected to reach here due to check in mspm0_address_check()
+ * but adding it as another layer of safety.
+ */
+ ret = ERROR_FLASH_DST_OUT_OF_BANK;
+ break;
+ }
+
+ if (ret != ERROR_OK)
+ LOG_ERROR("Unable to map sector protect reg for address 0x%08x", addr);
+
+ return ret;
+}
+
+static int mspm0_address_check(struct flash_bank *bank, unsigned int addr)
+{
+ struct mspm0_flash_bank *mspm0_info = bank->driver_priv;
+ unsigned int flash_main_size = mspm0_info->main_flash_size_kb * 1024;
+ unsigned int flash_data_size = mspm0_info->data_flash_size_kb * 1024;
+ int ret = ERROR_FLASH_SECTOR_INVALID;
+
+ /*
+ * Before unprotecting any memory lets make sure that the address and
+ * bank given is a known bank and whether or not the address falls under
+ * the proper bank.
+ */
+ switch (bank->base) {
+ case MSPM0_FLASH_BASE_MAIN:
+ if (addr <= (MSPM0_FLASH_BASE_MAIN + flash_main_size))
+ ret = ERROR_OK;
+ break;
+ case MSPM0_FLASH_BASE_NONMAIN:
+ if (addr >= MSPM0_FLASH_BASE_NONMAIN && addr <= MSPM0_FLASH_END_NONMAIN)
+ ret = ERROR_OK;
+ break;
+ case MSPM0_FLASH_BASE_DATA:
+ if (addr >= MSPM0_FLASH_BASE_DATA &&
+ addr <= (MSPM0_FLASH_BASE_DATA + flash_data_size))
+ ret = ERROR_OK;
+ break;
+ default:
+ ret = ERROR_FLASH_DST_OUT_OF_BANK;
+ break;
+ }
+
+ return ret;
+}
+
+static int mspm0_fctl_unprotect_sector(struct flash_bank *bank, unsigned int addr)
+{
+ struct target *target = bank->target;
+ unsigned int reg = 0x0;
+ uint32_t sector_mask = 0x0;
+ int ret;
+
+ ret = mspm0_address_check(bank, addr);
+ switch (ret) {
+ case ERROR_FLASH_SECTOR_INVALID:
+ LOG_ERROR("Unable to map sector protect reg for address 0x%08x", addr);
+ break;
+ case ERROR_FLASH_DST_OUT_OF_BANK:
+ LOG_ERROR("Unable to determine which bank to use 0x%08x", addr);
+ break;
+ default:
+ mspm0_fctl_get_sector_reg(bank, addr, ®, §or_mask);
+ ret = target_write_u32(target, reg, ~sector_mask);
+ break;
+ }
+
+ return ret;
+}
+
+static int mspm0_fctl_cfg_command(struct flash_bank *bank,
+ uint32_t addr,
+ uint32_t cmd,
+ uint32_t byte_en)
+{
+ struct target *target = bank->target;
+
+ /*
+ * Configure the flash operation within the CMDTYPE register, byte_en
+ * bits if needed, and then set the address where the flash operation
+ * will execute.
+ */
+ int retval = target_write_u32(target, FCTL_REG_CMDTYPE, cmd);
+ if (retval != ERROR_OK)
+ return retval;
+ if (byte_en != 0) {
+ retval = target_write_u32(target, FCTL_REG_CMDBYTEN, byte_en);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ return target_write_u32(target, FCTL_REG_CMDADDR, addr);
+}
+
+static int mspm0_fctl_wait_cmd_ok(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ uint32_t return_code = 0;
+ int64_t start_ms;
+ int64_t elapsed_ms;
+
+ start_ms = timeval_ms();
+ while ((return_code & FCTL_STATCMD_CMDDONE_MASK) != FCTL_STATCMD_CMDDONE_STATDONE) {
+ int retval = target_read_u32(target, FCTL_REG_STATCMD, &return_code);
+ if (retval != ERROR_OK)
+ return retval;
+
+ elapsed_ms = timeval_ms() - start_ms;
+ if (elapsed_ms > 500)
+ keep_alive();
+ if (elapsed_ms > MSPM0_FLASH_TIMEOUT_MS)
+ break;
+ }
+
+ if ((return_code & FCTL_STATCMD_CMDPASS_MASK) != FCTL_STATCMD_CMDPASS_STATPASS) {
+ LOG_ERROR("Flash command failed: %s", mspm0_fctl_translate_ret_err(return_code));
+ return ERROR_FAIL;
+ }
+
+ return ERROR_OK;
+}
+
+static int mspm0_fctl_sector_erase(struct flash_bank *bank, uint32_t addr)
+{
+ struct target *target = bank->target;
+
+ /*
+ * TRM Says:
+ * Note that the CMDWEPROTx registers are reset to a protected state
+ * at the end of all program and erase operations. These registers
+ * must be re-configured by software before a new operation is
+ * initiated.
+ *
+ * This means that as we start erasing sector by sector, the protection
+ * registers are reset and need to be unprotected *again* for the next
+ * erase operation. Unfortunately, this means that we cannot do a unitary
+ * unprotect operation independent of flash erase operation
+ */
+ int retval = mspm0_fctl_unprotect_sector(bank, addr);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Unprotecting sector of memory at address 0x%08" PRIx32
+ " failed", addr);
+ return retval;
+ }
+
+ /* Actual erase operation */
+ retval = mspm0_fctl_cfg_command(bank, addr,
+ (FCTL_CMDTYPE_COMMAND_ERASE | FCTL_CMDTYPE_SIZE_SECTOR), 0);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = target_write_u32(target, FCTL_REG_CMDEXEC, FCTL_CMDEXEC_VAL_EXECUTE);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return mspm0_fctl_wait_cmd_ok(bank);
+}
+
+static int mspm0_protect_check(struct flash_bank *bank)
+{
+ struct mspm0_flash_bank *mspm0_info = bank->driver_priv;
+
+ if (mspm0_info->did == 0)
+ return ERROR_FLASH_BANK_NOT_PROBED;
+
+ /*
+ * TRM Says:
+ * Note that the CMDWEPROTx registers are reset to a protected state
+ * at the end of all program and erase operations. These registers
+ * must be re-configured by software before a new operation is
+ * initiated.
+ *
+ * This means that when any flash operation is performed at a block level,
+ * the block is locked back again. This prevents usage where we can set a
+ * protection level once at the flash level and then do erase / write
+ * operation without touching the protection register (since it is
+ * reset by hardware automatically). In effect, we cannot use the hardware
+ * defined protection scheme in openOCD.
+ *
+ * To deal with this protection scheme, the CMDWEPROTx register that
+ * correlates to the sector is modified at the time of operation and as far
+ * openOCD is concerned, the flash operates as completely un-protected
+ * flash.
+ */
+ for (unsigned int i = 0; i < bank->num_sectors; i++)
+ bank->sectors[i].is_protected = 0;
+
+ return ERROR_OK;
+}
+
+static int mspm0_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
+{
+ struct target *target = bank->target;
+ struct mspm0_flash_bank *mspm0_info = bank->driver_priv;
+ int retval = ERROR_OK;
+ uint32_t protect_reg_cache[MSPM0_MAX_PROTREGS];
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Please halt target for erasing flash");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (mspm0_info->did == 0)
+ return ERROR_FLASH_BANK_NOT_PROBED;
+
+ /* Pick a copy of the current protection config for later restoration */
+ for (unsigned int i = 0; i < mspm0_info->protect_reg_count; i++) {
+ retval = target_read_u32(target,
+ mspm0_info->protect_reg_base + (i * 4),
+ &protect_reg_cache[i]);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed saving flashctl protection status");
+ return retval;
+ }
+ }
+
+ switch (bank->base) {
+ case MSPM0_FLASH_BASE_MAIN:
+ for (unsigned int csa = first; csa <= last; csa++) {
+ unsigned int addr = csa * mspm0_info->sector_size;
+ retval = mspm0_fctl_sector_erase(bank, addr);
+ if (retval != ERROR_OK)
+ LOG_ERROR("Sector erase on MAIN failed at address 0x%08x "
+ "(sector: %u)", addr, csa);
+ }
+ break;
+ case MSPM0_FLASH_BASE_NONMAIN:
+ retval = mspm0_fctl_sector_erase(bank, MSPM0_FLASH_BASE_NONMAIN);
+ if (retval != ERROR_OK)
+ LOG_ERROR("Sector erase on NONMAIN failed");
+ break;
+ case MSPM0_FLASH_BASE_DATA:
+ for (unsigned int csa = first; csa <= last; csa++) {
+ unsigned int addr = (MSPM0_FLASH_BASE_DATA +
+ (csa * mspm0_info->sector_size));
+ retval = mspm0_fctl_sector_erase(bank, addr);
+ if (retval != ERROR_OK)
+ LOG_ERROR("Sector erase on DATA bank failed at address 0x%08x "
+ "(sector: %u)", addr, csa);
+ }
+ break;
+ default:
+ LOG_ERROR("Invalid memory region access");
+ retval = ERROR_FLASH_BANK_INVALID;
+ break;
+ }
+
+ /* If there were any issues in our checks, return the error */
+ if (retval != ERROR_OK)
+ return retval;
+
+ /*
+ * TRM Says:
+ * Note that the CMDWEPROTx registers are reset to a protected state
+ * at the end of all program and erase operations. These registers
+ * must be re-configured by software before a new operation is
+ * initiated
+ * Let us just Dump the protection registers back to the system.
+ * That way we retain the protection status as requested by the user
+ */
+ for (unsigned int i = 0; i < mspm0_info->protect_reg_count; i++) {
+ retval = target_write_u32(target, mspm0_info->protect_reg_base + (i * 4),
+ protect_reg_cache[i]);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed re-applying protection status of flashctl");
+ return retval;
+ }
+ }
+
+ return retval;
+}
+
+static int mspm0_write(struct flash_bank *bank, const unsigned char *buffer,
+ unsigned int offset, unsigned int count)
+{
+ struct target *target = bank->target;
+ struct mspm0_flash_bank *mspm0_info = bank->driver_priv;
+ uint32_t protect_reg_cache[MSPM0_MAX_PROTREGS];
+ int retval;
+
+ /*
+ * XXX: TRM Says:
+ * The number of program operations applied to a given word line must be
+ * monitored to ensure that the maximum word line program limit before
+ * erase is not violated.
+ *
+ * There is no reasonable way we can maintain that state in OpenOCD. So,
+ * Let the manufacturing path figure this out.
+ */
+
+ if (bank->target->state != TARGET_HALTED) {
+ LOG_ERROR("Please halt target for programming flash");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ if (mspm0_info->did == 0)
+ return ERROR_FLASH_BANK_NOT_PROBED;
+
+ /*
+ * Pick a copy of the current protection config for later restoration
+ * We need to restore these regs after every write, so instead of trying
+ * to figure things out on the fly, we just context save and restore
+ */
+ for (unsigned int i = 0; i < mspm0_info->protect_reg_count; i++) {
+ retval = target_read_u32(target,
+ mspm0_info->protect_reg_base + (i * 4),
+ &protect_reg_cache[i]);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed saving flashctl protection status");
+ return retval;
+ }
+ }
+
+ /* Add proper memory offset for bank being written to */
+ unsigned int addr = bank->base + offset;
+
+ while (count) {
+ unsigned int num_bytes_to_write;
+ uint32_t bytes_en;
+
+ /*
+ * If count is not 64 bit aligned, we will do byte wise op to keep things simple
+ * Usually this might mean we need to additional write ops towards
+ * trailing edge, but that is a tiny penalty for image downloads.
+ * NOTE: we are going to assume the device does not support multi-word
+ * programming - there does not seem to be discoverability!
+ */
+ if (count < mspm0_info->flash_word_size_bytes)
+ num_bytes_to_write = count;
+ else
+ num_bytes_to_write = mspm0_info->flash_word_size_bytes;
+
+ /* Data bytes to write */
+ bytes_en = (1 << num_bytes_to_write) - 1;
+ /* ECC chunks to write */
+ switch (mspm0_info->flash_word_size_bytes) {
+ case 8:
+ bytes_en |= BIT(8);
+ break;
+ case 16:
+ bytes_en |= BIT(16);
+ bytes_en |= (num_bytes_to_write > 8) ? BIT(17) : 0;
+ break;
+ default:
+ LOG_ERROR("Invalid flash_word_size_bytes %d",
+ mspm0_info->flash_word_size_bytes);
+ return ERROR_FAIL;
+ }
+
+ retval = mspm0_fctl_cfg_command(bank, addr,
+ (FCTL_CMDTYPE_COMMAND_PROGRAM | FCTL_CMDTYPE_SIZE_ONEWORD),
+ bytes_en);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mspm0_fctl_unprotect_sector(bank, addr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = target_write_buffer(target, FCTL_REG_CMDDATA0, num_bytes_to_write, buffer);
+ if (retval != ERROR_OK)
+ return retval;
+
+ addr += num_bytes_to_write;
+ buffer += num_bytes_to_write;
+ count -= num_bytes_to_write;
+
+ retval = target_write_u32(target, FCTL_REG_CMDEXEC, FCTL_CMDEXEC_VAL_EXECUTE);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mspm0_fctl_wait_cmd_ok(bank);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ /*
+ * TRM Says:
+ * Note that the CMDWEPROTx registers are reset to a protected state
+ * at the end of all program and erase operations. These registers
+ * must be re-configured by software before a new operation is
+ * initiated
+ * Let us just Dump the protection registers back to the system.
+ * That way we retain the protection status as requested by the user
+ */
+ for (unsigned int i = 0; i < mspm0_info->protect_reg_count; i++) {
+ retval = target_write_u32(target,
+ mspm0_info->protect_reg_base + (i * 4),
+ protect_reg_cache[i]);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed re-applying protection status of flashctl");
+ return retval;
+ }
+ }
+
+ return ERROR_OK;
+}
+
+static int mspm0_probe(struct flash_bank *bank)
+{
+ struct mspm0_flash_bank *mspm0_info = bank->driver_priv;
+
+ /*
+ * If this is a mspm0 chip, it has flash; probe() is just
+ * to figure out how much is present. Only do it once.
+ */
+ if (mspm0_info->did != 0)
+ return ERROR_OK;
+
+ /*
+ * mspm0_read_part_info() already handled error checking and
+ * reporting. Note that it doesn't write, so we don't care about
+ * whether the target is halted or not.
+ */
+ int retval = mspm0_read_part_info(bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (bank->sectors) {
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
+ bank->write_start_alignment = 4;
+ bank->write_end_alignment = 4;
+
+ switch (bank->base) {
+ case MSPM0_FLASH_BASE_NONMAIN:
+ bank->size = 1024;
+ bank->num_sectors = 0x1;
+ mspm0_info->protect_reg_base = FCTL_REG_CMDWEPROTNM;
+ mspm0_info->protect_reg_count = 1;
+ break;
+ case MSPM0_FLASH_BASE_MAIN:
+ bank->size = (mspm0_info->main_flash_size_kb * 1024);
+ bank->num_sectors = bank->size / mspm0_info->sector_size;
+ /*
+ * If the feature version bit read from the FCTL_REG_DESC is
+ * greater than or equal to 0xA then it means that the device
+ * will exclusively use CMDWEPROTB ONLY for MAIN memory protection
+ */
+ if (mspm0_info->flash_version >= FCTL_FEATURE_VER_B) {
+ mspm0_info->protect_reg_base = FCTL_REG_CMDWEPROTB;
+ mspm0_info->protect_reg_count = 1;
+ } else {
+ mspm0_info->protect_reg_base = FCTL_REG_CMDWEPROTA;
+ mspm0_info->protect_reg_count = 3;
+ }
+ break;
+ case MSPM0_FLASH_BASE_DATA:
+ if (!mspm0_info->data_flash_size_kb) {
+ LOG_INFO("Data region NOT available!");
+ bank->size = 0x0;
+ bank->num_sectors = 0x0;
+ return ERROR_OK;
+ }
+ /*
+ * Any MSPM0 device containing data bank will have a flashctl
+ * feature version of 0xA or higher. Since data bank is treated
+ * like MAIN memory, it will also exclusively use CMDWEPROTB for
+ * protection.
+ */
+ bank->size = (mspm0_info->data_flash_size_kb * 1024);
+ bank->num_sectors = bank->size / mspm0_info->sector_size;
+ mspm0_info->protect_reg_base = FCTL_REG_CMDWEPROTB;
+ mspm0_info->protect_reg_count = 1;
+ break;
+ default:
+ LOG_ERROR("Invalid bank address " TARGET_ADDR_FMT,
+ bank->base);
+ return ERROR_FAIL;
+ }
+
+ bank->sectors = calloc(bank->num_sectors, sizeof(struct flash_sector));
+ if (!bank->sectors) {
+ LOG_ERROR("Out of memory for sectors!");
+ return ERROR_FAIL;
+ }
+ for (unsigned int i = 0; i < bank->num_sectors; i++) {
+ bank->sectors[i].offset = i * mspm0_info->sector_size;
+ bank->sectors[i].size = mspm0_info->sector_size;
+ bank->sectors[i].is_erased = -1;
+ }
+
+ return ERROR_OK;
+}
+
+const struct flash_driver mspm0_flash = {
+ .name = "mspm0",
+ .flash_bank_command = mspm0_flash_bank_command,
+ .erase = mspm0_erase,
+ .protect = NULL,
+ .write = mspm0_write,
+ .read = default_flash_read,
+ .probe = mspm0_probe,
+ .auto_probe = mspm0_probe,
+ .erase_check = default_flash_blank_check,
+ .protect_check = mspm0_protect_check,
+ .info = get_mspm0_info,
+ .free_driver_priv = default_flash_free_driver_priv,
+};
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 50 ++
src/flash/nor/Makefile.am | 1 +
src/flash/nor/driver.h | 1 +
src/flash/nor/drivers.c | 1 +
src/flash/nor/mspm0.c | 1131 +++++++++++++++++++++++++++++++++++++++++++++
5 files changed, 1184 insertions(+)
create mode 100644 src/flash/nor/mspm0.c
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-03-09 03:19:06
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via b6b5edf13b5d3500c94a5afc7adda132768cd568 (commit)
from 7ec11e52387390ea1fab510f10fc6cd0ed200ef5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit b6b5edf13b5d3500c94a5afc7adda132768cd568
Author: Evgeniy Naydanov <evg...@sy...>
Date: Fri Feb 14 19:30:55 2025 +0300
rtos/linux: handle OOM in `linux_gdb_thread_packet()`
Return an error in case `calloc()` fails.
Change-Id: Id1b758a1edbae3d71d625d1992579b99720d77d6
Signed-off-by: Evgeniy Naydanov <evg...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8762
Tested-by: jenkins
Reviewed-by: zapb <de...@za...>
diff --git a/src/rtos/linux.c b/src/rtos/linux.c
index 5467988f3..91d9a39f2 100644
--- a/src/rtos/linux.c
+++ b/src/rtos/linux.c
@@ -1040,6 +1040,10 @@ static int linux_gdb_thread_packet(struct target *target,
return ERROR_TARGET_FAILURE;
char *out_str = calloc(MAX_THREADS * 17 + 10, 1);
+ if (!out_str) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
char *tmp_str = out_str;
tmp_str += sprintf(tmp_str, "m");
struct threads *temp = linux_os->thread_list;
-----------------------------------------------------------------------
Summary of changes:
src/rtos/linux.c | 4 ++++
1 file changed, 4 insertions(+)
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From: openocd-gerrit <ope...@us...> - 2025-03-09 03:13:50
|
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- Log -----------------------------------------------------------------
commit 7ec11e52387390ea1fab510f10fc6cd0ed200ef5
Author: Evgeniy Naydanov <evg...@sy...>
Date: Fri Feb 14 19:29:08 2025 +0300
rtos/rtos: handle OOM in `rtos_thread_packet()`
Return an error in case `calloc()` fails.
Change-Id: Ibb21a62991be83be8b219887953ccf27156f8af5
Signed-off-by: Evgeniy Naydanov <evg...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8763
Tested-by: jenkins
Reviewed-by: zapb <de...@za...>
diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index f218f6369..2c563d522 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -362,6 +362,10 @@ int rtos_thread_packet(struct connection *connection, char const *packet, int pa
str_size += strlen(detail->extra_info_str);
char *tmp_str = calloc(str_size + 9, sizeof(char));
+ if (!tmp_str) {
+ LOG_ERROR("Out of memory");
+ return ERROR_FAIL;
+ }
char *tmp_str_ptr = tmp_str;
if (detail->thread_name_str)
-----------------------------------------------------------------------
Summary of changes:
src/rtos/rtos.c | 4 ++++
1 file changed, 4 insertions(+)
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From: openocd-gerrit <ope...@us...> - 2025-03-08 17:52:00
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 953ad9e11658534ea4ca682c7f112db3059be1cc (commit)
from 7837f508a5cca2c82ec46f076d115853a4eaac38 (commit)
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commit 953ad9e11658534ea4ca682c7f112db3059be1cc
Author: Marc Schink <de...@za...>
Date: Thu Feb 13 22:37:40 2025 +0000
rtt: Raise error if control block was not found
Since RTT is not started if the control block was not found, an error
must be raised instead of just informing the user.
Change-Id: I2873e72f142ca572da97ee1fe91f6f1301307555
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8757
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/rtt/rtt.c b/src/rtt/rtt.c
index 42c3ee3ad..15b9a373a 100644
--- a/src/rtt/rtt.c
+++ b/src/rtt/rtt.c
@@ -140,8 +140,8 @@ int rtt_start(void)
addr);
rtt.ctrl.address = addr;
} else {
- LOG_INFO("rtt: No control block found");
- return ERROR_OK;
+ LOG_ERROR("rtt: No control block found");
+ return ERROR_FAIL;
}
}
-----------------------------------------------------------------------
Summary of changes:
src/rtt/rtt.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2025-03-08 17:51:17
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from a168c634126e9e6bb95c6e68b2db5afbb099abf7 (commit)
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commit 7837f508a5cca2c82ec46f076d115853a4eaac38
Author: Parshintsev Anatoly <ana...@sy...>
Date: Fri Nov 8 07:12:46 2024 +0300
target: fix wrap-around detection for read_memory/write_memory
while at it change the order of checks for requested region sizes to
get rid of potential overflow during multiplication.
Change-Id: I97dac68e7024591cfd7abb70c8c62dff791298fe
Signed-off-by: Parshintsev Anatoly <ana...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8572
Tested-by: jenkins
Reviewed-by: zapb <de...@za...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/target.c b/src/target/target.c
index 9c5a33d3d..0e41f0d10 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -4447,15 +4447,17 @@ COMMAND_HANDLER(handle_target_read_memory)
return ERROR_COMMAND_ARGUMENT_INVALID;
}
- const unsigned int width = width_bits / 8;
-
- if ((addr + (count * width)) < addr) {
- command_print(CMD, "read_memory: addr + count wraps to zero");
+ if (count > 65536) {
+ command_print(CMD, "read_memory: too large read request, exceeds 64K elements");
return ERROR_COMMAND_ARGUMENT_INVALID;
}
- if (count > 65536) {
- command_print(CMD, "read_memory: too large read request, exceeds 64K elements");
+ const unsigned int width = width_bits / 8;
+ /* -1 is needed to handle cases when (addr + count * width) results in zero
+ * due to overflow.
+ */
+ if ((addr + count * width - 1) < addr) {
+ command_print(CMD, "read_memory: memory region wraps over address zero");
return ERROR_COMMAND_ARGUMENT_INVALID;
}
@@ -4584,15 +4586,19 @@ static int target_jim_write_memory(Jim_Interp *interp, int argc,
return JIM_ERR;
}
- const unsigned int width = width_bits / 8;
-
- if ((addr + (count * width)) < addr) {
- Jim_SetResultString(interp, "write_memory: addr + len wraps to zero", -1);
+ if (count > 65536) {
+ Jim_SetResultString(interp,
+ "write_memory: too large memory write request, exceeds 64K elements", -1);
return JIM_ERR;
}
- if (count > 65536) {
- Jim_SetResultString(interp, "write_memory: too large memory write request, exceeds 64K elements", -1);
+ const unsigned int width = width_bits / 8;
+ /* -1 is needed to handle cases when (addr + count * width) results in zero
+ * due to overflow.
+ */
+ if ((addr + count * width - 1) < addr) {
+ Jim_SetResultFormatted(interp,
+ "write_memory: memory region wraps over address zero");
return JIM_ERR;
}
-----------------------------------------------------------------------
Summary of changes:
src/target/target.c | 30 ++++++++++++++++++------------
1 file changed, 18 insertions(+), 12 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2025-03-01 15:16:17
|
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generated because a ref change was pushed to the repository containing
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via d126cdb9239990dac88023d42fe5056401190e5e (commit)
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- Log -----------------------------------------------------------------
commit a168c634126e9e6bb95c6e68b2db5afbb099abf7
Author: Tomas Vanek <va...@fb...>
Date: Tue Feb 18 08:13:07 2025 +0100
configure: better differentiate CMSIS-DAP versions
and keep them together in the configuration summary.
Change-Id: I5937393590ac72f1d499457e67763686a79cadee
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8765
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/configure.ac b/configure.ac
index fda0b2a36..e31e056cc 100644
--- a/configure.ac
+++ b/configure.ac
@@ -136,16 +136,19 @@ m4_define([USB1_ADAPTERS],
[[ft232r], [Bitbang mode of FT232R based devices], [FT232R]],
[[vsllink], [Versaloon-Link JTAG Programmer], [VSLLINK]],
[[xds110], [TI XDS110 Debug Probe], [XDS110]],
- [[cmsis_dap_v2], [CMSIS-DAP v2 Compliant Debugger], [CMSIS_DAP_USB]],
[[osbdm], [OSBDM (JTAG only) Programmer], [OSBDM]],
[[opendous], [eStick/opendous JTAG Programmer], [OPENDOUS]],
[[armjtagew], [Olimex ARM-JTAG-EW Programmer], [ARMJTAGEW]],
[[rlink], [Raisonance RLink JTAG Programmer], [RLINK]],
[[usbprog], [USBProg JTAG Programmer], [USBPROG]],
- [[esp_usb_jtag], [Espressif JTAG Programmer], [ESP_USB_JTAG]]])
+ [[esp_usb_jtag], [Espressif JTAG Programmer], [ESP_USB_JTAG]],
+ [[cmsis_dap_v2], [CMSIS-DAP v2 compliant dongle (USB bulk)], [CMSIS_DAP_USB]]])
+
+# Please keep cmsis_dap_v2 the last in USB1_ADAPTERS
+# and cmsis_dap the first in HIDAPI_ADAPTERS
m4_define([HIDAPI_ADAPTERS],
- [[[cmsis_dap], [CMSIS-DAP Compliant Debugger], [CMSIS_DAP_HID]],
+ [[[cmsis_dap], [CMSIS-DAP v1 compliant dongle (HID)], [CMSIS_DAP_HID]],
[[nulink], [Nu-Link Programmer], [HLADAPTER_NULINK]]])
m4_define([HIDAPI_USB1_ADAPTERS],
@@ -878,7 +881,7 @@ AS_IF([test "x$use_internal_jimtcl" = "xyes"], [
echo
echo
echo OpenOCD configuration summary
-echo --------------------------------------------------
+echo ---------------------------------------------------
m4_foreach([adapter], [USB1_ADAPTERS,
HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS,
LIBFTDI_USB1_ADAPTERS,
@@ -889,7 +892,7 @@ m4_foreach([adapter], [USB1_ADAPTERS,
DUMMY_ADAPTER,
OPTIONAL_LIBRARIES,
COVERAGE],
- [s=m4_format(["%-40s"], ADAPTER_DESC([adapter]))
+ [s=m4_format(["%-41s"], ADAPTER_DESC([adapter]))
AS_CASE([$ADAPTER_VAR([adapter])],
[auto], [
echo "$s"yes '(auto)'
commit d126cdb9239990dac88023d42fe5056401190e5e
Author: Tomas Vanek <va...@fb...>
Date: Mon Feb 17 12:15:09 2025 +0100
drivers/cmsis_dap: fix misleading error selecting not compiled backend
If one of CMSIS-DAP backends was not compiled (due to
missing library or configure --disable-cmsis-dap) and
Tcl config explicitly selected it, a misleading message
"invalid backend argument to cmsis-dap backend <backend>"
was printed.
Create dummy backends in struct cmsis_dap_backend
to replace a not built backend.
Check for NULL open backend method to distinguish
the backend is dummy.
Rework 'cmsis-dap backend' command to honour dummy
backend. While on it print more helpful error messages.
Change-Id: I8f12aeaaecf19302032870bc232e5135c1d935e7
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8760
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c
index c8a7cf8fc..be9ebaed5 100644
--- a/src/jtag/drivers/cmsis_dap.c
+++ b/src/jtag/drivers/cmsis_dap.c
@@ -39,14 +39,22 @@
#include "cmsis_dap.h"
#include "libusb_helper.h"
-static const struct cmsis_dap_backend *const cmsis_dap_backends[] = {
-#if BUILD_CMSIS_DAP_USB == 1
- &cmsis_dap_usb_backend,
+/* Create a dummy backend for 'backend' command if real one does not build */
+#if BUILD_CMSIS_DAP_USB == 0
+const struct cmsis_dap_backend cmsis_dap_usb_backend = {
+ .name = "usb_bulk",
+};
#endif
-#if BUILD_CMSIS_DAP_HID == 1
- &cmsis_dap_hid_backend,
+#if BUILD_CMSIS_DAP_HID == 0
+const struct cmsis_dap_backend cmsis_dap_hid_backend = {
+ .name = "hid"
+};
#endif
+
+static const struct cmsis_dap_backend *const cmsis_dap_backends[] = {
+ &cmsis_dap_usb_backend,
+ &cmsis_dap_hid_backend,
};
/* USB Config */
@@ -261,26 +269,32 @@ static int cmsis_dap_open(void)
return ERROR_FAIL;
}
+ int retval = ERROR_FAIL;
if (cmsis_dap_backend >= 0) {
/* Use forced backend */
backend = cmsis_dap_backends[cmsis_dap_backend];
- if (backend->open(dap, cmsis_dap_vid, cmsis_dap_pid, adapter_get_required_serial()) != ERROR_OK)
- backend = NULL;
+ if (backend->open)
+ retval = backend->open(dap, cmsis_dap_vid, cmsis_dap_pid, adapter_get_required_serial());
+ else
+ LOG_ERROR("Requested CMSIS-DAP backend is disabled by configure");
+
} else {
/* Try all backends */
for (unsigned int i = 0; i < ARRAY_SIZE(cmsis_dap_backends); i++) {
backend = cmsis_dap_backends[i];
- if (backend->open(dap, cmsis_dap_vid, cmsis_dap_pid, adapter_get_required_serial()) == ERROR_OK)
+ if (!backend->open)
+ continue;
+
+ retval = backend->open(dap, cmsis_dap_vid, cmsis_dap_pid, adapter_get_required_serial());
+ if (retval == ERROR_OK)
break;
- else
- backend = NULL;
}
}
- if (!backend) {
+ if (retval != ERROR_OK) {
LOG_ERROR("unable to find a matching CMSIS-DAP device");
free(dap);
- return ERROR_FAIL;
+ return retval;
}
dap->backend = backend;
@@ -293,7 +307,8 @@ static int cmsis_dap_open(void)
static void cmsis_dap_close(struct cmsis_dap *dap)
{
if (dap->backend) {
- dap->backend->close(dap);
+ if (dap->backend->close)
+ dap->backend->close(dap);
dap->backend = NULL;
}
@@ -2192,22 +2207,27 @@ COMMAND_HANDLER(cmsis_dap_handle_vid_pid_command)
COMMAND_HANDLER(cmsis_dap_handle_backend_command)
{
- if (CMD_ARGC == 1) {
- if (strcmp(CMD_ARGV[0], "auto") == 0) {
- cmsis_dap_backend = -1; /* autoselect */
- } else {
- for (unsigned int i = 0; i < ARRAY_SIZE(cmsis_dap_backends); i++) {
- if (strcasecmp(cmsis_dap_backends[i]->name, CMD_ARGV[0]) == 0) {
+ if (CMD_ARGC != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ if (strcmp(CMD_ARGV[0], "auto") == 0) {
+ cmsis_dap_backend = -1; /* autoselect */
+ } else {
+ for (unsigned int i = 0; i < ARRAY_SIZE(cmsis_dap_backends); i++) {
+ if (strcasecmp(cmsis_dap_backends[i]->name, CMD_ARGV[0]) == 0) {
+ if (cmsis_dap_backends[i]->open) {
cmsis_dap_backend = i;
return ERROR_OK;
}
- }
- command_print(CMD, "invalid backend argument to cmsis-dap backend <backend>");
- return ERROR_COMMAND_ARGUMENT_INVALID;
+ command_print(CMD, "Requested cmsis-dap backend %s is disabled by configure",
+ cmsis_dap_backends[i]->name);
+ return ERROR_NOT_IMPLEMENTED;
+ }
}
- } else {
- return ERROR_COMMAND_SYNTAX_ERROR;
+
+ command_print(CMD, "invalid argument %s to cmsis-dap backend", CMD_ARGV[0]);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
}
return ERROR_OK;
-----------------------------------------------------------------------
Summary of changes:
configure.ac | 13 +++++----
src/jtag/drivers/cmsis_dap.c | 68 ++++++++++++++++++++++++++++----------------
2 files changed, 52 insertions(+), 29 deletions(-)
hooks/post-receive
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From: openocd-gerrit <ope...@us...> - 2025-03-01 15:13:07
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via accbeaed99bc6014d060259d6b0b0e080c0f44b4 (commit)
from c986b4dbf2ff81753adcd0235954cfd577831672 (commit)
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- Log -----------------------------------------------------------------
commit accbeaed99bc6014d060259d6b0b0e080c0f44b4
Author: Jim Paris <jim...@me...>
Date: Fri Feb 21 12:33:45 2025 -0500
gdb_server: fix invalid free
`gdb_service_free` calls `free(gdb_port_next)`, so this needs to be an
allocated string. Otherwise we trip up detectors like Android's tagged
pointers.
Change-Id: Ib08ea55a38af4e15c4fbae95f10db0e3684ae1af
Signed-off-by: Jim Paris <jim...@me...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8768
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 1866de0b5..71b7c7764 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -3898,7 +3898,8 @@ static int gdb_target_add_one(struct target *target)
}
}
} else if (strcmp(gdb_port_next, "pipe") == 0) {
- gdb_port_next = "disabled";
+ free(gdb_port_next);
+ gdb_port_next = strdup("disabled");
}
}
return retval;
-----------------------------------------------------------------------
Summary of changes:
src/server/gdb_server.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
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From: openocd-gerrit <ope...@us...> - 2025-03-01 15:12:31
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via c986b4dbf2ff81753adcd0235954cfd577831672 (commit)
from e1425845ea32713924cbfdfc9a328c6eb774f11f (commit)
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- Log -----------------------------------------------------------------
commit c986b4dbf2ff81753adcd0235954cfd577831672
Author: Marek Kraus <gam...@ou...>
Date: Sat Nov 23 15:54:26 2024 +0100
tcl/target: add Bouffalo Lab BL602 and BL702L chip series support
BL602, BL702 and BL702L series of chips are sharing same architecture,
so they all need same software reset mechanism as well.
Only difference (in terms of configuration needed for JTAG) are TAP ID,
workarea address and size. This is addressed by creating bl602_common.cfg
tcl file, which contains all those common stuff between the chips.
The script is prefixed by bl602, as this was
first *publicly* available chip from Bouffalo with this architecture.
This patch also improves reset mechanism. Previous reset mechanism did not
worked properly when slower JTAG adapter was used (it attached too late).
New reset mechanism uses various methods to keep CPU in BootROM, until
the JTAG adapter does not attach again after reset. Additionally,
we trigger SW Reset by directly using DMI commands to write to register
with system bus method, to avoid getting error about unsuccessful write.
The new method works on both FT232H (8MHz JTAG clock) and
unnamed CMSIS-DAP dongle (1.5MHz JTAG clock).
Change-Id: I5be3694927793fd3f64c9ed4ee6ded2db0d25cae
Signed-off-by: Marek Kraus <gam...@ou...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8593
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/target/bl602.cfg b/tcl/target/bl602.cfg
new file mode 100644
index 000000000..d110d3e3b
--- /dev/null
+++ b/tcl/target/bl602.cfg
@@ -0,0 +1,34 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Bouffalo Labs BL602 and BL604 target
+#
+# https://en.bouffalolab.com/product/?type=detail&id=1
+#
+# Default JTAG pins: (if not changed by eFuse configuration)
+# TDO - GPIO11
+# TMS - GPIO12
+# TCK - GPIO14
+# TDI - GPIO17
+#
+
+if { [info exists CHIPNAME] } {
+ set BL602_CHIPNAME $CHIPNAME
+} else {
+ set BL602_CHIPNAME bl602
+}
+
+set CPUTAPID 0x20000c05
+
+# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1 cache and XIP
+set WORKAREAADDR 0x42014000
+set WORKAREASIZE 0xC000
+
+source [find target/bl602_common.cfg]
+
+# JTAG reset is broken. Read comment of bl602_sw_reset_hbn_wait function for more information
+$_TARGETNAME configure -event reset-assert {
+ halt
+
+ bl602_sw_reset_hbn_wait
+}
diff --git a/tcl/target/bl602_common.cfg b/tcl/target/bl602_common.cfg
new file mode 100644
index 000000000..cf4bc3947
--- /dev/null
+++ b/tcl/target/bl602_common.cfg
@@ -0,0 +1,143 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Script for Bouffalo chips with similar architecture used in BL602
+# based on SiFive E21 core
+
+source [find mem_helper.tcl]
+
+transport select jtag
+
+if { [info exists CPUTAPID ] } {
+ set _CPUTAPID $CPUTAPID
+} else {
+ error "you must specify a tap id"
+}
+
+if { [info exists BL602_CHIPNAME] } {
+ set _CHIPNAME $BL602_CHIPNAME
+} else {
+ error "you must specify a chip name"
+}
+
+if { [info exists WORKAREAADDR] } {
+ set _WORKAREAADDR $WORKAREAADDR
+} else {
+ error "you must specify a work area address"
+}
+
+if { [info exists WORKAREASIZE] } {
+ set _WORKAREASIZE $WORKAREASIZE
+} else {
+ error "you must specify a work area size"
+}
+
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+
+riscv set_mem_access sysbus
+riscv set_enable_virt2phys off
+
+$_TARGETNAME configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1
+
+# Internal RC ticks on 32 MHz, so this speed should be safe to use.
+adapter speed 8000
+
+# Useful functions
+
+set dmcontrol 0x10
+set dmcontrol_dmactive [expr {1 << 0}]
+set dmcontrol_ndmreset [expr {1 << 1}]
+set dmcontrol_resumereq [expr {1 << 30}]
+set dmcontrol_haltreq [expr {1 << 31}]
+
+proc bl602_restore_clock_defaults { } {
+ # Switch clock to internal RC32M
+ # In HBN_GLB, set ROOT_CLK_SEL = 0
+ mmw 0x4000f030 0x0 0x00000003
+ # Wait for clock switch
+ sleep 10
+
+ # GLB_REG_BCLK_DIS_FALSE
+ mww 0x40000ffc 0x0
+
+ # HCLK is RC32M, so BCLK/HCLK doesn't need divider
+ # In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
+ mmw 0x40000000 0x0 0x00FFFF00
+ # Wait for clock to stabilize
+ sleep 10
+}
+
+# By spec, ndmreset should reset whole chip. This implementation resets only few parts of the chip.
+# CTRL_PWRON_RESET register in GLB core triggers full "power-on like" reset, so we use it instead
+# for full software reset.
+proc bl602_sw_reset { } {
+ # In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
+ mmw 0x40000018 0x0 0x00000007
+
+ # This Software reset method resets everything, so CPU as well.
+ # It does that in not much good way, resulting in Debug Module being reset as well.
+ # This also means, that right after CPU and Debug Module are turned on, we need to
+ # enable Debug Module and halt CPU if needed. Additionally, we trigger this SW reset
+ # through system bus access directly with DMI commands, to avoid errors printed by
+ # OpenOCD about unsuccessful register write.
+
+ # In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
+ riscv dmi_write 0x39 0x40000018
+ riscv dmi_write 0x3c 0x7
+
+ # We need to wait for chip to finish reset and execute BootROM
+ sleep 1
+
+ # JTAG Debug Transport Module is reset as well, so we need to get into RUN/IDLE state
+ runtest 10
+
+ # We need to enable Debug Module and halt the CPU, so we can reset Program Counter
+ # and to do additional clean-ups. If reset was called without halt, resume is handled
+ # by reset-deassert-post event handler.
+
+ # In Debug Module Control (dmcontrol), set dmactive to 1 and then haltreq to 1
+ riscv dmi_write $::dmcontrol $::dmcontrol_dmactive
+ riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_haltreq} ]
+
+ # Set Program Counter to start of BootROM
+ set_reg {pc 0x21000000}
+}
+
+# On BL602 and BL702, the only way to force chip stay in BootROM (until JTAG attaches)
+# is by putting infinity loop into HBN RAM (which is not reset by sw reset), and then
+# configure HBN registers, which will cause BootROM to jump into our code early in BootROM.
+proc bl602_sw_reset_hbn_wait {} {
+ # Restore clocks to defaults
+ bl602_restore_clock_defaults
+
+ # In HBN RAM, write infinity loop instruction
+ # beq zero, zero, 0
+ mww 0x40010000 0x00000063
+ # In HNB, set HBN_RSV0 (Status Flag) to "EHBN" (as uint32_t)
+ mww 0x4000f100 0x4e424845
+ # In HBN, set HBN_RSV1 (WakeUp Address) to HBN RAM address
+ mww 0x4000f104 0x40010000
+
+ # Perform software reset
+ bl602_sw_reset
+
+ # Clear HBN RAM, HBN_RSV0 and HBN_RSV1
+ mww 0x40010000 0x00000000
+ mww 0x4000f100 0x00000000
+ mww 0x4000f104 0x00000000
+
+ # This early jump method locks up BootROM through Trust Zone Controller.
+ # That means any read of BootROM returns 0xDEADBEEF.
+ # Only way to reset it, is through JTAG Reset, thus toggling ndmreset in dmcontrol.
+ riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_ndmreset} ]
+ riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive} ]
+}
+
+$_TARGETNAME configure -event reset-deassert-post {
+ # Resume the processor if reset was triggered without halt request
+ if {$halt == 0} {
+ riscv dmi_write $::dmcontrol [ expr {$::dmcontrol_dmactive | $::dmcontrol_resumereq} ]
+ }
+}
diff --git a/tcl/target/bl702.cfg b/tcl/target/bl702.cfg
index 5046cd189..8caf06ebe 100644
--- a/tcl/target/bl702.cfg
+++ b/tcl/target/bl702.cfg
@@ -12,62 +12,23 @@
# TDO - GPIO9
#
-source [find mem_helper.tcl]
-
-transport select jtag
-
if { [info exists CHIPNAME] } {
- set _CHIPNAME $CHIPNAME
+ set BL602_CHIPNAME $CHIPNAME
} else {
- set _CHIPNAME bl702
+ set BL602_CHIPNAME bl702
}
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000e05
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME riscv -chain-position $_TARGETNAME
-
-riscv set_mem_access sysbus
+set CPUTAPID 0x20000e05
-$_TARGETNAME configure -work-area-phys 0x22020000 -work-area-size 0x10000 -work-area-backup 1
+# For work-area we use DTCM instead of ITCM, due ITCM is used as buffer for L1 cache and XIP
+set WORKAREAADDR 0x22014000
+set WORKAREASIZE 0xC000
-# Internal RC ticks on 32 MHz, so this speed should be safe to use.
-adapter speed 4000
+source [find target/bl602_common.cfg]
-# Debug Module's ndmreset resets only Trust Zone Controller, so we need to do SW reset instead.
-# CTRL_PWRON_RESET triggers full "power-on like" reset.
-# This means that pinmux configuration to access JTAG is reset as well, and configured back early
-# in BootROM.
-$_TARGETNAME configure -event reset-assert-pre {
+# JTAG reset is broken. Read comment of bl602_sw_reset_hbn_wait function for more information
+$_TARGETNAME configure -event reset-assert {
halt
- # Switch clock to internal RC32M
- # In HBN_GLB, set ROOT_CLK_SEL = 0
- mmw 0x4000f030 0x0 0x00000003
- # Wait for clock switch
- sleep 10
-
- # GLB_REG_BCLK_DIS_FALSE
- mww 0x40000ffc 0x0
-
- # HCLK is RC32M, so BCLK/HCLK doesn't need divider
- # In GLB_CLK_CFG0, set BCLK_DIV = 0 and HCLK_DIV = 0
- mmw 0x40000000 0x0 0x00FFFF00
- # Wait for clock to stabilize
- sleep 10
-
- # Do reset
- # In GLB_SWRST_CFG2, clear CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET
- mmw 0x40000018 0x0 0x00000007
-
- # Since this full software reset resets GPIO pinmux as well, we will lose access
- # to JTAG right away after writing to register. This chip doesn't support abstract
- # memory access, so when this is done by progbuf or sysbus, OpenOCD will fail to read
- # if write was successful or not, and will print error about that. Since receiving of
- # this error is expected, we will turn off log printing for a moment,
- set lvl [lindex [debug_level] 1]
- debug_level -1
- # In GLB_SWRST_CFG2, set CTRL_SYS_RESET, CTRL_CPU_RESET and CTRL_PWRON_RESET to 1
- catch {mmw 0x40000018 0x7 0x0}
- debug_level $lvl
+ bl602_sw_reset_hbn_wait
}
diff --git a/tcl/target/bl702l.cfg b/tcl/target/bl702l.cfg
new file mode 100644
index 000000000..467dd8ce6
--- /dev/null
+++ b/tcl/target/bl702l.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Bouffalo Labs BL702L and BL704L target
+#
+# https://en.bouffalolab.com/product/?type=detail&id=26
+#
+# Default JTAG pins: (if not changed by eFuse configuration)
+# TMS - GPIO0
+# TDI - GPIO1
+# TCK - GPIO2
+# TDO - GPIO7
+#
+
+if { [info exists CHIPNAME] } {
+ set BL602_CHIPNAME $CHIPNAME
+} else {
+ set BL602_CHIPNAME bl702l
+}
+
+set CPUTAPID 0x20000e05
+
+# For work-area we use beginning of OCRAM, since BL702L have only ITCM, which can be taken
+# by L1 cache and XIP during runtime.
+set WORKAREAADDR 0x42020000
+set WORKAREASIZE 0x10000
+
+source [find target/bl602_common.cfg]
+
+# JTAG reset is broken. Read comment of bl602_sw_reset function for more information
+# On BL702L, we are forcing boot into ISP mode, so chip stays in BootROM until JTAG re-attach
+$_TARGETNAME configure -event reset-assert {
+ halt
+
+ # Restore clocks to defaults
+ bl602_restore_clock_defaults
+
+ # In HBN_RSV2, set HBN_RELEASE_CORE to HBN_RELEASE_CORE_FLAG (4)
+ # and HBN_USER_BOOT_SEL to 1 (ISP)
+ mww 0x4000f108 0x44000000
+
+ # Perform software reset
+ bl602_sw_reset
+
+ # Reset HBN_RSV2 so BootROM will not force ISP mode again
+ mww 0x4000f108 0x00000000
+}
-----------------------------------------------------------------------
Summary of changes:
tcl/target/bl602.cfg | 34 +++++++++++
tcl/target/bl602_common.cfg | 143 ++++++++++++++++++++++++++++++++++++++++++++
tcl/target/bl702.cfg | 59 ++++--------------
tcl/target/bl702l.cfg | 47 +++++++++++++++
4 files changed, 234 insertions(+), 49 deletions(-)
create mode 100644 tcl/target/bl602.cfg
create mode 100644 tcl/target/bl602_common.cfg
create mode 100644 tcl/target/bl702l.cfg
hooks/post-receive
--
Main OpenOCD repository
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|
From: openocd-gerrit <ope...@us...> - 2025-03-01 15:11:48
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e1425845ea32713924cbfdfc9a328c6eb774f11f (commit)
from 91c11ea469c7613d2b474149c48457dcc082ebed (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit e1425845ea32713924cbfdfc9a328c6eb774f11f
Author: Antonio Borneo <bor...@gm...>
Date: Wed Feb 26 23:25:03 2025 +0100
target: algorithm: change reg_name to const in init_reg_param()
The function init_reg_param() initializes a struct where the
pointer reg_name is assigned to a 'const char *'.
Change the prototype of init_reg_param() to make also the reg_name
parameter as 'const char *'.
Change-Id: Ib999eaa5786ad24aa2a361070162c6f362784758
Reported-by: Marek Kraus <gam...@ou...>
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8797
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Marek Kraus <gam...@ou...>
diff --git a/src/target/algorithm.c b/src/target/algorithm.c
index 64abffc7b..dee1f364b 100644
--- a/src/target/algorithm.c
+++ b/src/target/algorithm.c
@@ -26,7 +26,8 @@ void destroy_mem_param(struct mem_param *param)
param->value = NULL;
}
-void init_reg_param(struct reg_param *param, char *reg_name, uint32_t size, enum param_direction direction)
+void init_reg_param(struct reg_param *param, const char *reg_name,
+ uint32_t size, enum param_direction direction)
{
param->reg_name = reg_name;
param->size = size;
diff --git a/src/target/algorithm.h b/src/target/algorithm.h
index 25f1a66ab..45b3fd97a 100644
--- a/src/target/algorithm.h
+++ b/src/target/algorithm.h
@@ -35,8 +35,8 @@ void init_mem_param(struct mem_param *param,
uint32_t address, uint32_t size, enum param_direction dir);
void destroy_mem_param(struct mem_param *param);
-void init_reg_param(struct reg_param *param,
- char *reg_name, uint32_t size, enum param_direction dir);
+void init_reg_param(struct reg_param *param, const char *reg_name,
+ uint32_t size, enum param_direction dir);
void destroy_reg_param(struct reg_param *param);
#endif /* OPENOCD_TARGET_ALGORITHM_H */
-----------------------------------------------------------------------
Summary of changes:
src/target/algorithm.c | 3 ++-
src/target/algorithm.h | 4 ++--
2 files changed, 4 insertions(+), 3 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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From: openocd-gerrit <ope...@us...> - 2025-02-22 22:59:20
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 91c11ea469c7613d2b474149c48457dcc082ebed (commit)
from 9470853d476b431ead7218a3124717ffb4b10e50 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit 91c11ea469c7613d2b474149c48457dcc082ebed
Author: Marc Schink <de...@za...>
Date: Wed Jun 12 13:34:48 2024 +0200
rtos: Use lower case filenames
Change-Id: I309c7a649e33f516e28037fef2dc6e574d48c000
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8334
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/rtos/Makefile.am b/src/rtos/Makefile.am
index 0796910de..5267fea24 100644
--- a/src/rtos/Makefile.am
+++ b/src/rtos/Makefile.am
@@ -11,15 +11,15 @@ noinst_LTLIBRARIES += %D%/librtos.la
%D%/rtos_ucos_iii_stackings.c \
%D%/rtos_riot_stackings.c \
%D%/rtos_nuttx_stackings.c \
- %D%/FreeRTOS.c \
- %D%/ThreadX.c \
- %D%/eCos.c \
+ %D%/freertos.c \
+ %D%/threadx.c \
+ %D%/ecos.c \
%D%/linux.c \
%D%/chibios.c \
%D%/chromium-ec.c \
- %D%/embKernel.c \
+ %D%/embkernel.c \
%D%/mqx.c \
- %D%/uCOS-III.c \
+ %D%/ucos_iii.c \
%D%/nuttx.c \
%D%/rtkernel.c \
%D%/hwthread.c \
diff --git a/src/rtos/eCos.c b/src/rtos/ecos.c
similarity index 100%
rename from src/rtos/eCos.c
rename to src/rtos/ecos.c
diff --git a/src/rtos/embKernel.c b/src/rtos/embkernel.c
similarity index 100%
rename from src/rtos/embKernel.c
rename to src/rtos/embkernel.c
diff --git a/src/rtos/FreeRTOS.c b/src/rtos/freertos.c
similarity index 100%
rename from src/rtos/FreeRTOS.c
rename to src/rtos/freertos.c
diff --git a/src/rtos/ThreadX.c b/src/rtos/threadx.c
similarity index 100%
rename from src/rtos/ThreadX.c
rename to src/rtos/threadx.c
diff --git a/src/rtos/uCOS-III.c b/src/rtos/ucos_iii.c
similarity index 100%
rename from src/rtos/uCOS-III.c
rename to src/rtos/ucos_iii.c
-----------------------------------------------------------------------
Summary of changes:
src/rtos/Makefile.am | 10 +++++-----
src/rtos/{eCos.c => ecos.c} | 0
src/rtos/{embKernel.c => embkernel.c} | 0
src/rtos/{FreeRTOS.c => freertos.c} | 0
src/rtos/{ThreadX.c => threadx.c} | 0
src/rtos/{uCOS-III.c => ucos_iii.c} | 0
6 files changed, 5 insertions(+), 5 deletions(-)
rename src/rtos/{eCos.c => ecos.c} (100%)
rename src/rtos/{embKernel.c => embkernel.c} (100%)
rename src/rtos/{FreeRTOS.c => freertos.c} (100%)
rename src/rtos/{ThreadX.c => threadx.c} (100%)
rename src/rtos/{uCOS-III.c => ucos_iii.c} (100%)
hooks/post-receive
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Main OpenOCD repository
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From: openocd-gerrit <ope...@us...> - 2025-02-22 18:53:20
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 9470853d476b431ead7218a3124717ffb4b10e50 (commit)
from 297844cf46c7de5faa9de1c4a9f223b505dc3e9c (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 9470853d476b431ead7218a3124717ffb4b10e50
Author: Antonio Borneo <bor...@gm...>
Date: Wed Feb 19 22:30:45 2025 +0100
jep106: update to revision JEP106BL Feb 2025
Update to latest available document.
Change-Id: Ic7f31bf74c25aaebc5a2ecc7d5a0e516321bf862
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8766
Tested-by: jenkins
diff --git a/src/helper/jep106.inc b/src/helper/jep106.inc
index 53d0355c1..8bbaf4ca5 100644
--- a/src/helper/jep106.inc
+++ b/src/helper/jep106.inc
@@ -2,18 +2,18 @@
/*
* The manufacturer's standard identification code list appears in JEP106.
- * Copyright (c) 2024 JEDEC. All rights reserved.
+ * Copyright (c) 2025 JEDEC. All rights reserved.
*
* JEP106 is regularly updated. For the current manufacturer's standard
* identification code list, please visit the JEDEC website at www.jedec.org .
*/
-/* This file is aligned to revision JEP106BK September 2024. */
+/* This file is aligned to revision JEP106BL February 2025. */
[0][0x01 - 1] = "AMD",
[0][0x02 - 1] = "AMI",
[0][0x03 - 1] = "Fairchild",
-[0][0x04 - 1] = "Fujitsu",
+[0][0x04 - 1] = "RAMXEED Limited",
[0][0x05 - 1] = "GTE",
[0][0x06 - 1] = "Harris",
[0][0x07 - 1] = "Hitachi",
@@ -1373,7 +1373,7 @@
[10][0x65 - 1] = "Esperanto Technologies",
[10][0x66 - 1] = "JinSheng Electronic (Shenzhen) Co Ltd",
[10][0x67 - 1] = "Shenzhen Shi Bolunshuai Technology",
-[10][0x68 - 1] = "Shanghai Rui Xuan Information Tech",
+[10][0x68 - 1] = "Shanghai Ruixuan Information Tech",
[10][0x69 - 1] = "Fraunhofer IIS",
[10][0x6a - 1] = "Kandou Bus SA",
[10][0x6b - 1] = "Acer",
@@ -1745,7 +1745,7 @@
[13][0x5f - 1] = "Guangdong OPPO Mobile Telecommunication",
[13][0x60 - 1] = "Akeana",
[13][0x61 - 1] = "Lyczar",
-[13][0x62 - 1] = "Shenzhen Qiji Technology Co Ltd",
+[13][0x62 - 1] = "QJTEK",
[13][0x63 - 1] = "Shenzhen Shangzhaoyuan Technology",
[13][0x64 - 1] = "Han Stor",
[13][0x65 - 1] = "China Micro Semicon Co., Ltd.",
@@ -1893,7 +1893,7 @@
[14][0x75 - 1] = "HOGE Technology Co Ltd",
[14][0x76 - 1] = "United Micro Technology (Shenzhen) Co",
[14][0x77 - 1] = "Fabric of Truth Inc",
-[14][0x78 - 1] = "Epitech",
+[14][0x78 - 1] = "Elpitech",
[14][0x79 - 1] = "Elitestek",
[14][0x7a - 1] = "Cornelis Networks Inc",
[14][0x7b - 1] = "WingSemi Technologies Co Ltd",
@@ -1916,7 +1916,7 @@
[15][0x0e - 1] = "Shenzhen Ranshuo Technology Co Limited",
[15][0x0f - 1] = "ScaleFlux",
[15][0x10 - 1] = "XC Memory",
-[15][0x11 - 1] = "Guangzhou Beimu Technology Co., Ltd",
+[15][0x11 - 1] = "Guangzhou Beimu Technology Co Ltd",
[15][0x12 - 1] = "Rays Semiconductor Nanjing Co Ltd",
[15][0x13 - 1] = "Milli-Centi Intelligence Technology Jiangsu",
[15][0x14 - 1] = "Zilia Technologies",
@@ -1925,7 +1925,7 @@
[15][0x17 - 1] = "Nanjing Houmo Technology Co Ltd",
[15][0x18 - 1] = "Suzhou Yige Technology Co Ltd",
[15][0x19 - 1] = "Shenzhen Techwinsemi Technology Co Ltd",
-[15][0x1a - 1] = "Pure Array Technology (Shanghai) Co. Ltd",
+[15][0x1a - 1] = "Pure Array Technology (Shanghai) Co Ltd",
[15][0x1b - 1] = "Shenzhen Techwinsemi Technology Udstore",
[15][0x1c - 1] = "RISE MODE",
[15][0x1d - 1] = "NEWREESTAR",
@@ -2016,4 +2016,37 @@
[15][0x72 - 1] = "KEYSOM",
[15][0x73 - 1] = "Shenzhen YYF Info Tech Co Ltd",
[15][0x74 - 1] = "Sharetronics Data Technology Co Ltd",
+[15][0x75 - 1] = "AptCore Limited",
+[15][0x76 - 1] = "Uchampion Semiconductor Co Ltd",
+[15][0x77 - 1] = "YCT Semiconductor",
+[15][0x78 - 1] = "FADU Inc",
+[15][0x79 - 1] = "Hefei CLT Microelectronics Co LTD",
+[15][0x7a - 1] = "Smart Technologies (BD) Ltd",
+[15][0x7b - 1] = "Zhangdian District Qunyuan Computer Firm",
+[15][0x7c - 1] = "Silicon Xpandas Electronics Co Ltd",
+[15][0x7d - 1] = "PC Components Y Multimedia S",
+[15][0x7e - 1] = "Shenzhen Tanlr Technology Group Co Ltd",
+[16][0x01 - 1] = "Shenzhen JIEQING Technology Co Ltd",
+[16][0x02 - 1] = "Orionix",
+[16][0x03 - 1] = "JoulWatt Technology Co Ltd",
+[16][0x04 - 1] = "Tenstorrent",
+[16][0x05 - 1] = "Unis Flash Memory Technology (Chengdu)",
+[16][0x06 - 1] = "Huatu Stars",
+[16][0x07 - 1] = "Ardor Gaming",
+[16][0x08 - 1] = "QuanZhou KunFang Semiconductor Co Ltd",
+[16][0x09 - 1] = "EIAI PLANET",
+[16][0x0a - 1] = "Ningbo Lingkai Semiconductor Technology Inc",
+[16][0x0b - 1] = "Shenzhen Hancun Technology Co Ltd",
+[16][0x0c - 1] = "Hongkong Manyi Technology Co Limited",
+[16][0x0d - 1] = "Shenzhen Storgon Technology Co Ltd",
+[16][0x0e - 1] = "YUNTU Microelectronics",
+[16][0x0f - 1] = "Essencore",
+[16][0x10 - 1] = "Shenzhen Xingyun Lianchuang Computer Tech",
+[16][0x11 - 1] = "ShenZhen Aoscar Digital Tech Co Ltd",
+[16][0x12 - 1] = "XOC Technologies Inc",
+[16][0x13 - 1] = "BOS Semiconductors",
+[16][0x14 - 1] = "Eliyan Corp",
+[16][0x15 - 1] = "Hangzhou Lishu Technology Co Ltd",
+[16][0x16 - 1] = "Tier IV Inc",
+[16][0x17 - 1] = "Wuhan Xuanluzhe Network Technology Co",
/* EOF */
-----------------------------------------------------------------------
Summary of changes:
src/helper/jep106.inc | 49 +++++++++++++++++++++++++++++++++++++++++--------
1 file changed, 41 insertions(+), 8 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
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From: openocd-gerrit <ope...@us...> - 2025-02-22 18:38:03
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from f63b41bbe4ce33449ec18106620f57ba69ce7549 (commit)
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- Log -----------------------------------------------------------------
commit 297844cf46c7de5faa9de1c4a9f223b505dc3e9c
Author: Marc Schink <de...@za...>
Date: Thu Oct 10 17:07:20 2024 +0200
target: Use 'bool' data type in target_{step,resume}
While at it, adapt data types of related functions and fix some coding
style issues.
Change-Id: I74db9258fc17b1ee8aa446f35ae722ea7c2f67e6
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8524
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index c572f392a..1866de0b5 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -909,7 +909,7 @@ static void gdb_fileio_reply(struct target *target, struct connection *connectio
/* encounter unknown syscall, continue */
gdb_connection->frontend_state = TARGET_RUNNING;
- target_resume(target, 1, 0x0, 0, 0);
+ target_resume(target, true, 0x0, false, false);
return;
}
@@ -919,7 +919,7 @@ static void gdb_fileio_reply(struct target *target, struct connection *connectio
if (program_exited) {
/* Use target_resume() to let target run its own exit syscall handler. */
gdb_connection->frontend_state = TARGET_RUNNING;
- target_resume(target, 1, 0x0, 0, 0);
+ target_resume(target, true, 0x0, false, false);
} else {
gdb_connection->frontend_state = TARGET_HALTED;
rtos_update_threads(target);
@@ -1704,7 +1704,7 @@ static int gdb_step_continue_packet(struct connection *connection,
char const *packet, int packet_size)
{
struct target *target = get_target_from_connection(connection);
- int current = 0;
+ bool current = false;
uint64_t address = 0x0;
int retval = ERROR_OK;
@@ -1713,17 +1713,17 @@ static int gdb_step_continue_packet(struct connection *connection,
if (packet_size > 1)
address = strtoull(packet + 1, NULL, 16);
else
- current = 1;
+ current = true;
gdb_running_type = packet[0];
if (packet[0] == 'c') {
LOG_DEBUG("continue");
/* resume at current address, don't handle breakpoints, not debugging */
- retval = target_resume(target, current, address, 0, 0);
+ retval = target_resume(target, current, address, false, false);
} else if (packet[0] == 's') {
LOG_DEBUG("step");
/* step at current or address, don't handle breakpoints */
- retval = target_step(target, current, address, 0);
+ retval = target_step(target, current, address, false);
}
return retval;
}
@@ -3003,7 +3003,7 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
gdb_running_type = 'c';
LOG_TARGET_DEBUG(target, "target continue");
gdb_connection->output_flag = GDB_OUTPUT_ALL;
- retval = target_resume(target, 1, 0, 0, 0);
+ retval = target_resume(target, true, 0, false, false);
if (retval == ERROR_TARGET_NOT_HALTED)
LOG_TARGET_INFO(target, "target was not halted when resume was requested");
@@ -3031,7 +3031,7 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
bool fake_step = false;
struct target *ct = target;
- int current_pc = 1;
+ bool current_pc = true;
int64_t thread_id;
parse++;
if (parse[0] == ':') {
@@ -3129,7 +3129,7 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
return true;
}
- retval = target_step(ct, current_pc, 0, 0);
+ retval = target_step(ct, current_pc, 0, false);
if (retval == ERROR_TARGET_NOT_HALTED)
LOG_TARGET_INFO(ct, "target was not halted when step was requested");
@@ -3457,9 +3457,9 @@ static int gdb_fileio_response_packet(struct connection *connection,
/* After File-I/O ends, keep continue or step */
if (gdb_running_type == 'c')
- retval = target_resume(target, 1, 0x0, 0, 0);
+ retval = target_resume(target, true, 0x0, false, false);
else if (gdb_running_type == 's')
- retval = target_step(target, 1, 0x0, 0);
+ retval = target_step(target, true, 0x0, false);
else
retval = ERROR_FAIL;
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 3cc813005..609965ba5 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -589,8 +589,8 @@ static int aarch64_halt(struct target *target)
return aarch64_halt_one(target, HALT_SYNC);
}
-static int aarch64_restore_one(struct target *target, int current,
- uint64_t *address, int handle_breakpoints, int debug_execution)
+static int aarch64_restore_one(struct target *target, bool current,
+ uint64_t *address, bool handle_breakpoints, bool debug_execution)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct arm *arm = &armv8->arm;
@@ -602,7 +602,7 @@ static int aarch64_restore_one(struct target *target, int current,
if (!debug_execution)
target_free_all_working_areas(target);
- /* current = 1: continue on current pc, otherwise continue at <address> */
+ /* current = true: continue on current pc, otherwise continue at <address> */
resume_pc = buf_get_u64(arm->pc->value, 0, 64);
if (!current)
resume_pc = *address;
@@ -753,7 +753,8 @@ static int aarch64_restart_one(struct target *target, enum restart_mode mode)
/*
* prepare all but the current target for restart
*/
-static int aarch64_prep_restart_smp(struct target *target, int handle_breakpoints, struct target **p_first)
+static int aarch64_prep_restart_smp(struct target *target,
+ bool handle_breakpoints, struct target **p_first)
{
int retval = ERROR_OK;
struct target_list *head;
@@ -772,7 +773,8 @@ static int aarch64_prep_restart_smp(struct target *target, int handle_breakpoint
continue;
/* resume at current address, not in step mode */
- retval = aarch64_restore_one(curr, 1, &address, handle_breakpoints, 0);
+ retval = aarch64_restore_one(curr, true, &address, handle_breakpoints,
+ false);
if (retval == ERROR_OK)
retval = aarch64_prepare_restart_one(curr);
if (retval != ERROR_OK) {
@@ -799,7 +801,7 @@ static int aarch64_step_restart_smp(struct target *target)
LOG_DEBUG("%s", target_name(target));
- retval = aarch64_prep_restart_smp(target, 0, &first);
+ retval = aarch64_prep_restart_smp(target, false, &first);
if (retval != ERROR_OK)
return retval;
@@ -864,8 +866,8 @@ static int aarch64_step_restart_smp(struct target *target)
return retval;
}
-static int aarch64_resume(struct target *target, int current,
- target_addr_t address, int handle_breakpoints, int debug_execution)
+static int aarch64_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
int retval = 0;
uint64_t addr = address;
@@ -1113,8 +1115,8 @@ static int aarch64_post_debug_entry(struct target *target)
/*
* single-step a target
*/
-static int aarch64_step(struct target *target, int current, target_addr_t address,
- int handle_breakpoints)
+static int aarch64_step(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints)
{
struct armv8_common *armv8 = target_to_armv8(target);
struct aarch64_common *aarch64 = target_to_aarch64(target);
@@ -1147,7 +1149,7 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
if (retval != ERROR_OK)
return retval;
- if (target->smp && (current == 1)) {
+ if (target->smp && current) {
/*
* isolate current target so that it doesn't get resumed
* together with the others
@@ -1164,7 +1166,7 @@ static int aarch64_step(struct target *target, int current, target_addr_t addres
}
/* all other targets running, restore and restart the current target */
- retval = aarch64_restore_one(target, current, &address, 0, 0);
+ retval = aarch64_restore_one(target, current, &address, false, false);
if (retval == ERROR_OK)
retval = aarch64_restart_one(target, RESTART_LAZY);
diff --git a/src/target/arc.c b/src/target/arc.c
index 0c111d553..8757cafed 100644
--- a/src/target/arc.c
+++ b/src/target/arc.c
@@ -1100,7 +1100,7 @@ static int arc_assert_reset(struct target *target)
/* Resume the target and continue from the current
* PC register value. */
LOG_TARGET_DEBUG(target, "Starting CPU execution after reset");
- CHECK_RETVAL(target_resume(target, 1, 0, 0, 0));
+ CHECK_RETVAL(target_resume(target, true, 0, false, false));
}
target->state = TARGET_RESET;
@@ -1246,7 +1246,7 @@ exit:
return retval;
}
-static int arc_enable_interrupts(struct target *target, int enable)
+static int arc_enable_interrupts(struct target *target, bool enable)
{
uint32_t value;
@@ -1269,8 +1269,8 @@ static int arc_enable_interrupts(struct target *target, int enable)
return ERROR_OK;
}
-static int arc_resume(struct target *target, int current, target_addr_t address,
- int handle_breakpoints, int debug_execution)
+static int arc_resume(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints, bool debug_execution)
{
struct arc_common *arc = target_to_arc(target);
uint32_t resume_pc = 0;
@@ -1297,7 +1297,7 @@ static int arc_resume(struct target *target, int current, target_addr_t address,
CHECK_RETVAL(arc_enable_watchpoints(target));
}
- /* current = 1: continue on current PC, otherwise continue at <address> */
+ /* current = true: continue on current PC, otherwise continue at <address> */
if (!current) {
target_buffer_set_u32(target, pc->value, address);
pc->dirty = true;
@@ -2030,7 +2030,7 @@ static int arc_hit_watchpoint(struct target *target, struct watchpoint **hit_wat
/* Helper function which switches core to single_step mode by
* doing aux r/w operations. */
-static int arc_config_step(struct target *target, int enable_step)
+static int arc_config_step(struct target *target, bool enable_step)
{
uint32_t value;
@@ -2071,10 +2071,10 @@ static int arc_single_step_core(struct target *target)
CHECK_RETVAL(arc_debug_entry(target));
/* disable interrupts while stepping */
- CHECK_RETVAL(arc_enable_interrupts(target, 0));
+ CHECK_RETVAL(arc_enable_interrupts(target, false));
/* configure single step mode */
- CHECK_RETVAL(arc_config_step(target, 1));
+ CHECK_RETVAL(arc_config_step(target, true));
/* exit debug mode */
CHECK_RETVAL(arc_exit_debug(target));
@@ -2082,8 +2082,8 @@ static int arc_single_step_core(struct target *target)
return ERROR_OK;
}
-static int arc_step(struct target *target, int current, target_addr_t address,
- int handle_breakpoints)
+static int arc_step(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints)
{
/* get pointers to arch-specific information */
struct arc_common *arc = target_to_arc(target);
@@ -2095,7 +2095,7 @@ static int arc_step(struct target *target, int current, target_addr_t address,
return ERROR_TARGET_NOT_HALTED;
}
- /* current = 1: continue on current pc, otherwise continue at <address> */
+ /* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
buf_set_u32(pc->value, 0, 32, address);
pc->dirty = true;
@@ -2120,10 +2120,10 @@ static int arc_step(struct target *target, int current, target_addr_t address,
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
/* disable interrupts while stepping */
- CHECK_RETVAL(arc_enable_interrupts(target, 0));
+ CHECK_RETVAL(arc_enable_interrupts(target, false));
/* do a single step */
- CHECK_RETVAL(arc_config_step(target, 1));
+ CHECK_RETVAL(arc_config_step(target, true));
/* make sure we done our step */
alive_sleep(1);
diff --git a/src/target/arm11.c b/src/target/arm11.c
index c583a2ebd..756b36b95 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -30,8 +30,8 @@
#endif
-static int arm11_step(struct target *target, int current,
- target_addr_t address, int handle_breakpoints);
+static int arm11_step(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints);
/** Check and if necessary take control of the system
@@ -401,7 +401,8 @@ static int arm11_halt(struct target *target)
return ERROR_OK;
}
-static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t address)
+static uint32_t arm11_nextpc(struct arm11_common *arm11, bool current,
+ uint32_t address)
{
void *value = arm11->arm.pc->value;
@@ -435,8 +436,8 @@ static uint32_t arm11_nextpc(struct arm11_common *arm11, int current, uint32_t a
return address;
}
-static int arm11_resume(struct target *target, int current,
- target_addr_t address, int handle_breakpoints, int debug_execution)
+static int arm11_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
/* LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d", */
/* current, address, handle_breakpoints, debug_execution); */
@@ -469,7 +470,7 @@ static int arm11_resume(struct target *target, int current,
for (bp = target->breakpoints; bp; bp = bp->next) {
if (bp->address == address) {
LOG_DEBUG("must step over %08" TARGET_PRIxADDR "", bp->address);
- arm11_step(target, 1, 0, 0);
+ arm11_step(target, true, 0, false);
break;
}
}
@@ -543,8 +544,8 @@ static int arm11_resume(struct target *target, int current,
return ERROR_OK;
}
-static int arm11_step(struct target *target, int current,
- target_addr_t address, int handle_breakpoints)
+static int arm11_step(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints)
{
LOG_DEBUG("target->state: %s",
target_state_name(target));
@@ -569,13 +570,13 @@ static int arm11_step(struct target *target, int current,
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070) {
- address = arm11_nextpc(arm11, 0, address + 4);
+ address = arm11_nextpc(arm11, false, address + 4);
LOG_DEBUG("Skipping BKPT %08" TARGET_PRIxADDR, address);
}
/* skip over Wait for interrupt / Standby
* mcr 15, 0, r?, cr7, cr0, {4} */
else if ((next_instruction & 0xFFFF0FFF) == 0xee070f90) {
- address = arm11_nextpc(arm11, 0, address + 4);
+ address = arm11_nextpc(arm11, false, address + 4);
LOG_DEBUG("Skipping WFI %08" TARGET_PRIxADDR, address);
}
/* ignore B to self */
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index ad814e054..5550fb1e2 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -1697,10 +1697,10 @@ static void arm7_9_enable_breakpoints(struct target *target)
}
int arm7_9_resume(struct target *target,
- int current,
+ bool current,
target_addr_t address,
- int handle_breakpoints,
- int debug_execution)
+ bool handle_breakpoints,
+ bool debug_execution)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *arm = &arm7_9->arm;
@@ -1717,7 +1717,7 @@ int arm7_9_resume(struct target *target,
if (!debug_execution)
target_free_all_working_areas(target);
- /* current = 1: continue on current pc, otherwise continue at <address> */
+ /* current = true: continue on current pc, otherwise continue at <address> */
if (!current)
buf_set_u32(arm->pc->value, 0, 32, address);
@@ -1900,7 +1900,8 @@ void arm7_9_disable_eice_step(struct target *target)
embeddedice_store_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE]);
}
-int arm7_9_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
+int arm7_9_step(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints)
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
struct arm *arm = &arm7_9->arm;
@@ -1912,7 +1913,7 @@ int arm7_9_step(struct target *target, int current, target_addr_t address, int h
return ERROR_TARGET_NOT_HALTED;
}
- /* current = 1: continue on current pc, otherwise continue at <address> */
+ /* current = true: continue on current pc, otherwise continue at <address> */
if (!current)
buf_set_u32(arm->pc->value, 0, 32, address);
diff --git a/src/target/arm7_9_common.h b/src/target/arm7_9_common.h
index 92d0fd51a..c4a5b08d2 100644
--- a/src/target/arm7_9_common.h
+++ b/src/target/arm7_9_common.h
@@ -145,10 +145,10 @@ int arm7_9_early_halt(struct target *target);
int arm7_9_soft_reset_halt(struct target *target);
int arm7_9_halt(struct target *target);
-int arm7_9_resume(struct target *target, int current, target_addr_t address,
- int handle_breakpoints, int debug_execution);
-int arm7_9_step(struct target *target, int current, target_addr_t address,
- int handle_breakpoints);
+int arm7_9_resume(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints, bool debug_execution);
+int arm7_9_step(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints);
int arm7_9_read_memory(struct target *target, target_addr_t address,
uint32_t size, uint32_t count, uint8_t *buffer);
int arm7_9_write_memory(struct target *target, target_addr_t address,
diff --git a/src/target/arm_semihosting.c b/src/target/arm_semihosting.c
index b55758940..a7c47bf41 100644
--- a/src/target/arm_semihosting.c
+++ b/src/target/arm_semihosting.c
@@ -50,7 +50,7 @@ static int arm_semihosting_resume(struct target *target, int *retval)
if (is_armv8(target_to_armv8(target))) {
struct armv8_common *armv8 = target_to_armv8(target);
if (armv8->last_run_control_op == ARMV8_RUNCONTROL_RESUME) {
- *retval = target_resume(target, 1, 0, 0, 0);
+ *retval = target_resume(target, true, 0, false, false);
if (*retval != ERROR_OK) {
LOG_ERROR("Failed to resume target");
return 0;
@@ -58,7 +58,7 @@ static int arm_semihosting_resume(struct target *target, int *retval)
} else if (armv8->last_run_control_op == ARMV8_RUNCONTROL_STEP)
target->debug_reason = DBG_REASON_SINGLESTEP;
} else {
- *retval = target_resume(target, 1, 0, 0, 0);
+ *retval = target_resume(target, true, 0, false, false);
if (*retval != ERROR_OK) {
LOG_ERROR("Failed to resume target");
return 0;
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index a258c7fd4..597dc8990 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1514,7 +1514,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
}
}
- retval = target_resume(target, 0, entry_point, 1, 1);
+ retval = target_resume(target, false, entry_point, true, true);
if (retval != ERROR_OK)
return retval;
retval = run_it(target, exit_point, timeout_ms, arch_info);
diff --git a/src/target/armv7m.c b/src/target/armv7m.c
index 440ca49d1..dc2d84fe1 100644
--- a/src/target/armv7m.c
+++ b/src/target/armv7m.c
@@ -642,7 +642,7 @@ int armv7m_start_algorithm(struct target *target,
/* save previous core mode */
armv7m_algorithm_info->core_mode = core_mode;
- retval = target_resume(target, 0, entry_point, 1, 1);
+ retval = target_resume(target, false, entry_point, true, true);
return retval;
}
diff --git a/src/target/avr32_ap7k.c b/src/target/avr32_ap7k.c
index bbbf23659..1b051dc01 100644
--- a/src/target/avr32_ap7k.c
+++ b/src/target/avr32_ap7k.c
@@ -300,8 +300,8 @@ static int avr32_ap7k_deassert_reset(struct target *target)
return ERROR_OK;
}
-static int avr32_ap7k_resume(struct target *target, int current,
- target_addr_t address, int handle_breakpoints, int debug_execution)
+static int avr32_ap7k_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
struct breakpoint *breakpoint = NULL;
@@ -321,7 +321,7 @@ static int avr32_ap7k_resume(struct target *target, int current,
*/
}
- /* current = 1: continue on current pc, otherwise continue at <address> */
+ /* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
#if 0
if (retval != ERROR_OK)
@@ -382,8 +382,8 @@ static int avr32_ap7k_resume(struct target *target, int current,
return ERROR_OK;
}
-static int avr32_ap7k_step(struct target *target, int current,
- target_addr_t address, int handle_breakpoints)
+static int avr32_ap7k_step(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints)
{
LOG_ERROR("%s: implement me", __func__);
diff --git a/src/target/avrt.c b/src/target/avrt.c
index 8886a4677..3afe32015 100644
--- a/src/target/avrt.c
+++ b/src/target/avrt.c
@@ -22,10 +22,10 @@ static int avr_init_target(struct command_context *cmd_ctx, struct target *targe
static int avr_arch_state(struct target *target);
static int avr_poll(struct target *target);
static int avr_halt(struct target *target);
-static int avr_resume(struct target *target, int current, target_addr_t address,
- int handle_breakpoints, int debug_execution);
-static int avr_step(struct target *target, int current, target_addr_t address,
- int handle_breakpoints);
+static int avr_resume(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints, bool debug_execution);
+static int avr_step(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints);
static int avr_assert_reset(struct target *target);
static int avr_deassert_reset(struct target *target);
@@ -105,14 +105,15 @@ static int avr_halt(struct target *target)
return ERROR_OK;
}
-static int avr_resume(struct target *target, int current, target_addr_t address,
- int handle_breakpoints, int debug_execution)
+static int avr_resume(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints, bool debug_execution)
{
LOG_DEBUG("%s", __func__);
return ERROR_OK;
}
-static int avr_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
+static int avr_step(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints)
{
LOG_DEBUG("%s", __func__);
return ERROR_OK;
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index bfe698051..b32fec270 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -817,8 +817,8 @@ static int cortex_a_halt(struct target *target)
return ERROR_OK;
}
-static int cortex_a_internal_restore(struct target *target, int current,
- target_addr_t *address, int handle_breakpoints, int debug_execution)
+static int cortex_a_internal_restore(struct target *target, bool current,
+ target_addr_t *address, bool handle_breakpoints, bool debug_execution)
{
struct armv7a_common *armv7a = target_to_armv7a(target);
struct arm *arm = &armv7a->arm;
@@ -849,7 +849,7 @@ static int cortex_a_internal_restore(struct target *target, int current,
}
#endif
- /* current = 1: continue on current pc, otherwise continue at <address> */
+ /* current = true: continue on current pc, otherwise continue at <address> */
resume_pc = buf_get_u32(arm->pc->value, 0, 32);
if (!current)
resume_pc = *address;
@@ -965,7 +965,7 @@ static int cortex_a_internal_restart(struct target *target)
return ERROR_OK;
}
-static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
+static int cortex_a_restore_smp(struct target *target, bool handle_breakpoints)
{
int retval = 0;
struct target_list *head;
@@ -976,16 +976,16 @@ static int cortex_a_restore_smp(struct target *target, int handle_breakpoints)
if ((curr != target) && (curr->state != TARGET_RUNNING)
&& target_was_examined(curr)) {
/* resume current address , not in step mode */
- retval += cortex_a_internal_restore(curr, 1, &address,
- handle_breakpoints, 0);
+ retval += cortex_a_internal_restore(curr, true, &address,
+ handle_breakpoints, false);
retval += cortex_a_internal_restart(curr);
}
}
return retval;
}
-static int cortex_a_resume(struct target *target, int current,
- target_addr_t address, int handle_breakpoints, int debug_execution)
+static int cortex_a_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
int retval = 0;
/* dummy resume for smp toggle in order to reduce gdb impact */
@@ -997,7 +997,8 @@ static int cortex_a_resume(struct target *target, int current,
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
return 0;
}
- cortex_a_internal_restore(target, current, &address, handle_breakpoints, debug_execution);
+ cortex_a_internal_restore(target, current, &address, handle_breakpoints,
+ debug_execution);
if (target->smp) {
target->gdb_service->core[0] = -1;
retval = cortex_a_restore_smp(target, handle_breakpoints);
@@ -1168,8 +1169,8 @@ static int cortex_a_set_dscr_bits(struct target *target,
return retval;
}
-static int cortex_a_step(struct target *target, int current, target_addr_t address,
- int handle_breakpoints)
+static int cortex_a_step(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints)
{
struct cortex_a_common *cortex_a = target_to_cortex_a(target);
struct armv7a_common *armv7a = target_to_armv7a(target);
@@ -1184,7 +1185,7 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre
return ERROR_TARGET_NOT_HALTED;
}
- /* current = 1: continue on current pc, otherwise continue at <address> */
+ /* current = true: continue on current pc, otherwise continue at <address> */
r = arm->pc;
if (!current)
buf_set_u32(r->value, 0, 32, address);
@@ -1195,7 +1196,7 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre
* But since Cortex-A uses breakpoint for single step,
* we MUST handle breakpoints.
*/
- handle_breakpoints = 1;
+ handle_breakpoints = true;
if (handle_breakpoints) {
breakpoint = breakpoint_find(target, address);
if (breakpoint)
@@ -1222,7 +1223,7 @@ static int cortex_a_step(struct target *target, int current, target_addr_t addre
target->debug_reason = DBG_REASON_SINGLESTEP;
- retval = cortex_a_resume(target, 1, address, 0, 0);
+ retval = cortex_a_resume(target, true, address, false, false);
if (retval != ERROR_OK)
return retval;
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 9314d6675..e17f23c1d 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1359,7 +1359,7 @@ static int cortex_m_restore_one(struct target *target, bool current,
r->valid = true;
}
- /* current = 1: continue on current pc, otherwise continue at <address> */
+ /* current = true: continue on current pc, otherwise continue at <address> */
r = armv7m->arm.pc;
if (!current) {
buf_set_u32(r->value, 0, 32, *address);
@@ -1444,7 +1444,7 @@ static int cortex_m_restore_smp(struct target *target, bool handle_breakpoints)
continue;
int retval = cortex_m_restore_one(curr, true, &address,
- handle_breakpoints, false);
+ handle_breakpoints, false);
if (retval != ERROR_OK)
return retval;
@@ -1457,22 +1457,23 @@ static int cortex_m_restore_smp(struct target *target, bool handle_breakpoints)
return ERROR_OK;
}
-static int cortex_m_resume(struct target *target, int current,
- target_addr_t address, int handle_breakpoints, int debug_execution)
+static int cortex_m_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
- int retval = cortex_m_restore_one(target, !!current, &address, !!handle_breakpoints, !!debug_execution);
+ int retval = cortex_m_restore_one(target, current, &address,
+ handle_breakpoints, debug_execution);
if (retval != ERROR_OK) {
LOG_TARGET_ERROR(target, "context restore failed, aborting resume");
return retval;
}
if (target->smp && !debug_execution) {
- retval = cortex_m_restore_smp(target, !!handle_breakpoints);
+ retval = cortex_m_restore_smp(target, handle_breakpoints);
if (retval != ERROR_OK)
LOG_TARGET_WARNING(target, "resume of a SMP target failed, trying to resume current one");
}
- cortex_m_restart_one(target, !!debug_execution);
+ cortex_m_restart_one(target, debug_execution);
if (retval != ERROR_OK) {
LOG_TARGET_ERROR(target, "resume failed");
return retval;
@@ -1485,8 +1486,8 @@ static int cortex_m_resume(struct target *target, int current,
}
/* int irqstepcount = 0; */
-static int cortex_m_step(struct target *target, int current,
- target_addr_t address, int handle_breakpoints)
+static int cortex_m_step(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints)
{
struct cortex_m_common *cortex_m = target_to_cm(target);
struct armv7m_common *armv7m = &cortex_m->armv7m;
@@ -1506,7 +1507,7 @@ static int cortex_m_step(struct target *target, int current,
if (target->smp && target->gdb_service)
target->gdb_service->target = target;
- /* current = 1: continue on current pc, otherwise continue at <address> */
+ /* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
buf_set_u32(pc->value, 0, 32, address);
pc->dirty = true;
@@ -2316,7 +2317,7 @@ int cortex_m_profiling(struct target *target, uint32_t *samples,
/* Make sure the target is running */
target_poll(target);
if (target->state == TARGET_HALTED)
- retval = target_resume(target, 1, 0, 0, 0);
+ retval = target_resume(target, true, 0, false, false);
if (retval != ERROR_OK) {
LOG_TARGET_ERROR(target, "Error while resuming target");
diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index 953888de3..9b6f4756c 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -1115,10 +1115,10 @@ static int dsp563xx_halt(struct target *target)
}
static int dsp563xx_resume(struct target *target,
- int current,
+ bool current,
target_addr_t address,
- int handle_breakpoints,
- int debug_execution)
+ bool handle_breakpoints,
+ bool debug_execution)
{
int err;
struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
@@ -1132,7 +1132,7 @@ static int dsp563xx_resume(struct target *target,
if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) {
dsp563xx_write_core_reg(target, DSP563XX_REG_IDX_PC);
address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC];
- current = 0;
+ current = false;
}
LOG_DEBUG("%s %08X %08" TARGET_PRIXADDR, __func__, current, address);
@@ -1172,9 +1172,9 @@ static int dsp563xx_resume(struct target *target,
}
static int dsp563xx_step_ex(struct target *target,
- int current,
+ bool current,
uint32_t address,
- int handle_breakpoints,
+ bool handle_breakpoints,
int steps)
{
int err;
@@ -1196,7 +1196,7 @@ static int dsp563xx_step_ex(struct target *target,
if (current && dsp563xx->core_cache->reg_list[DSP563XX_REG_IDX_PC].dirty) {
dsp563xx_write_core_reg(target, DSP563XX_REG_IDX_PC);
address = dsp563xx->core_regs[DSP563XX_REG_IDX_PC];
- current = 0;
+ current = false;
}
LOG_DEBUG("%s %08X %08" PRIX32, __func__, current, address);
@@ -1288,9 +1288,9 @@ static int dsp563xx_step_ex(struct target *target,
}
static int dsp563xx_step(struct target *target,
- int current,
+ bool current,
target_addr_t address,
- int handle_breakpoints)
+ bool handle_breakpoints)
{
int err;
struct dsp563xx_common *dsp563xx = target_to_dsp563xx(target);
@@ -1359,7 +1359,7 @@ static int dsp563xx_deassert_reset(struct target *target)
* reset vector and need 2 cycles to fill
* the cache (fetch,decode,execute)
*/
- err = dsp563xx_step_ex(target, 1, 0, 1, 1);
+ err = dsp563xx_step_ex(target, true, 0, true, 1);
if (err != ERROR_OK)
return err;
}
@@ -1419,7 +1419,7 @@ static int dsp563xx_run_algorithm(struct target *target,
}
/* exec */
- retval = target_resume(target, 0, entry_point, 1, 1);
+ retval = target_resume(target, false, entry_point, true, true);
if (retval != ERROR_OK)
return retval;
@@ -1972,7 +1972,7 @@ static int dsp563xx_add_custom_watchpoint(struct target *target, uint32_t addres
if (err == ERROR_OK && was_running) {
/* Resume from current PC */
- err = dsp563xx_resume(target, 1, 0x0, 0, 0);
+ err = dsp563xx_resume(target, true, 0x0, false, false);
}
return err;
diff --git a/src/target/dsp5680xx.c b/src/target/dsp5680xx.c
index b370aafa4..3f9a6742c 100644
--- a/src/target/dsp5680xx.c
+++ b/src/target/dsp5680xx.c
@@ -993,8 +993,8 @@ static int dsp5680xx_poll(struct target *target)
return ERROR_OK;
}
-static int dsp5680xx_resume(struct target *target, int current,
- target_addr_t address, int hb, int d)
+static int dsp5680xx_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
if (target->state == TARGET_RUNNING) {
LOG_USER("Target already running.");
@@ -2048,7 +2048,7 @@ int dsp5680xx_f_wr(struct target *t, const uint8_t *b, uint32_t a, uint32_t coun
retval = core_tx_upper_data(target, tmp, &drscan_data);
err_check_propagate(retval);
- retval = dsp5680xx_resume(target, 0, ram_addr, 0, 0);
+ retval = dsp5680xx_resume(target, false, ram_addr, false, false);
err_check_propagate(retval);
int counter = FLUSH_COUNT_FLASH;
@@ -2234,8 +2234,8 @@ int dsp5680xx_f_lock(struct target *target)
return retval;
}
-static int dsp5680xx_step(struct target *target, int current, target_addr_t address,
- int handle_breakpoints)
+static int dsp5680xx_step(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints)
{
err_check(ERROR_FAIL, DSP5680XX_ERROR_NOT_IMPLEMENTED_STEP,
"Not implemented yet.");
diff --git a/src/target/esirisc.c b/src/target/esirisc.c
index fc2d20105..da40928da 100644
--- a/src/target/esirisc.c
+++ b/src/target/esirisc.c
@@ -846,8 +846,9 @@ static int esirisc_enable_step(struct target *target)
return ERROR_OK;
}
-static int esirisc_resume_or_step(struct target *target, int current, target_addr_t address,
- int handle_breakpoints, int debug_execution, bool step)
+static int esirisc_resume_or_step(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints, bool debug_execution,
+ bool step)
{
struct esirisc_common *esirisc = target_to_esirisc(target);
struct esirisc_jtag *jtag_info = &esirisc->jtag_info;
@@ -917,8 +918,8 @@ static int esirisc_resume_or_step(struct target *target, int current, target_add
return ERROR_OK;
}
-static int esirisc_resume(struct target *target, int current, target_addr_t address,
- int handle_breakpoints, int debug_execution)
+static int esirisc_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
LOG_TARGET_DEBUG(target, "-");
@@ -926,13 +927,13 @@ static int esirisc_resume(struct target *target, int current, target_addr_t addr
handle_breakpoints, debug_execution, false);
}
-static int esirisc_step(struct target *target, int current, target_addr_t address,
- int handle_breakpoints)
+static int esirisc_step(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints)
{
LOG_TARGET_DEBUG(target, "-");
return esirisc_resume_or_step(target, current, address,
- handle_breakpoints, 0, true);
+ handle_breakpoints, false, true);
}
static int esirisc_debug_step(struct target *target)
diff --git a/src/target/espressif/esp32.c b/src/target/espressif/esp32.c
index 324aa3993..4deb5e070 100644
--- a/src/target/espressif/esp32.c
+++ b/src/target/espressif/esp32.c
@@ -175,7 +175,8 @@ static int esp32_soc_reset(struct target *target)
LOG_DEBUG("Resuming the target");
xtensa = target_to_xtensa(target);
xtensa->suppress_dsr_errors = true;
- res = xtensa_resume(target, 0, ESP32_RTC_SLOW_MEM_BASE + 4, 0, 0);
+ res = xtensa_resume(target, false, ESP32_RTC_SLOW_MEM_BASE + 4, false,
+ false);
xtensa->suppress_dsr_errors = false;
if (res != ERROR_OK) {
LOG_ERROR("Failed to run stub (%d)!", res);
diff --git a/src/target/espressif/esp32_apptrace.c b/src/target/espressif/esp32_apptrace.c
index 125f36632..3202fd3d6 100644
--- a/src/target/espressif/esp32_apptrace.c
+++ b/src/target/espressif/esp32_apptrace.c
@@ -708,7 +708,7 @@ int esp32_apptrace_safe_halt_targets(struct esp32_apptrace_cmd_ctx *ctx,
}
while (stat) {
/* allow this CPU to leave ERI write critical section */
- res = target_resume(ctx->cpus[k], 1, 0, 1, 0);
+ res = target_resume(ctx->cpus[k], true, 0, true, false);
if (res != ERROR_OK) {
LOG_ERROR("Failed to resume target (%d)!", res);
breakpoint_remove(ctx->cpus[k], bp_addr);
@@ -796,7 +796,7 @@ static int esp32_apptrace_connect_targets(struct esp32_apptrace_cmd_ctx *ctx,
/* in SMP mode we need to call target_resume for one core only */
continue;
}
- res = target_resume(ctx->cpus[k], 1, 0, 1, 0);
+ res = target_resume(ctx->cpus[k], true, 0, true, false);
if (res != ERROR_OK) {
command_print(ctx->cmd, "Failed to resume target (%d)!", res);
return res;
@@ -1352,7 +1352,7 @@ static int esp32_sysview_stop(struct esp32_apptrace_cmd_ctx *ctx)
/* in SMP mode we need to call target_resume for one core only */
continue;
}
- res = target_resume(ctx->cpus[k], 1, 0, 1, 0);
+ res = target_resume(ctx->cpus[k], true, 0, true, false);
if (res != ERROR_OK) {
LOG_ERROR("sysview: Failed to resume target '%s' (%d)!", target_name(ctx->cpus[k]), res);
return res;
diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c
index 2abde479e..4f3914f66 100644
--- a/src/target/espressif/esp32s2.c
+++ b/src/target/espressif/esp32s2.c
@@ -370,7 +370,8 @@ static int esp32s2_on_halt(struct target *target)
return ret;
}
-static int esp32s2_step(struct target *target, int current, target_addr_t address, int handle_breakpoints)
+static int esp32s2_step(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints)
{
int ret = xtensa_step(target, current, address, handle_breakpoints);
if (ret == ERROR_OK) {
@@ -397,7 +398,7 @@ static int esp32s2_poll(struct target *target)
if (ret == ERROR_OK && esp_xtensa->semihost.need_resume) {
esp_xtensa->semihost.need_resume = false;
/* Resume xtensa_resume will handle BREAK instruction. */
- ret = target_resume(target, 1, 0, 1, 0);
+ ret = target_resume(target, true, 0, true, false);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to resume target");
return ret;
diff --git a/src/target/espressif/esp32s3.c b/src/target/espressif/esp32s3.c
index 2afb4b009..7507c11c2 100644
--- a/src/target/espressif/esp32s3.c
+++ b/src/target/espressif/esp32s3.c
@@ -175,7 +175,8 @@ static int esp32s3_soc_reset(struct target *target)
LOG_DEBUG("Resuming the target");
xtensa = target_to_xtensa(target);
xtensa->suppress_dsr_errors = true;
- res = xtensa_resume(target, 0, ESP32_S3_RTC_SLOW_MEM_BASE + 4, 0, 0);
+ res = xtensa_resume(target, false, ESP32_S3_RTC_SLOW_MEM_BASE + 4, false,
+ false);
xtensa->suppress_dsr_errors = false;
if (res != ERROR_OK) {
LOG_ERROR("Failed to run stub (%d)!", res);
diff --git a/src/target/espressif/esp_xtensa.c b/src/target/espressif/esp_xtensa.c
index 9b57f345e..4cadcb330 100644
--- a/src/target/espressif/esp_xtensa.c
+++ b/src/target/espressif/esp_xtensa.c
@@ -213,7 +213,7 @@ int esp_xtensa_profiling(struct target *target, uint32_t *samples,
/* Make sure the target is running */
target_poll(target);
if (target->state == TARGET_HALTED)
- retval = target_resume(target, 1, 0, 0, 0);
+ retval = target_resume(target, true, 0, false, false);
if (retval != ERROR_OK) {
LOG_TARGET_ERROR(target, "Error while resuming target");
diff --git a/src/target/espressif/esp_xtensa_smp.c b/src/target/espressif/esp_xtensa_smp.c
index c49146d78..b9e215644 100644
--- a/src/target/espressif/esp_xtensa_smp.c
+++ b/src/target/espressif/esp_xtensa_smp.c
@@ -218,7 +218,7 @@ int esp_xtensa_smp_poll(struct target *target)
!esp_xtensa_smp->other_core_does_resume) {
esp_xtensa->semihost.need_resume = false;
/* Resume xtensa_resume will handle BREAK instruction. */
- ret = target_resume(target, 1, 0, 1, 0);
+ ret = target_resume(target, true, 0, true, false);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to resume target");
return ret;
@@ -229,7 +229,7 @@ int esp_xtensa_smp_poll(struct target *target)
/* check whether any core polled by esp_xtensa_smp_update_halt_gdb() requested resume */
if (target->smp && other_core_resume_req) {
/* Resume xtensa_resume will handle BREAK instruction. */
- ret = target_resume(target, 1, 0, 1, 0);
+ ret = target_resume(target, true, 0, true, false);
if (ret != ERROR_OK) {
LOG_ERROR("Failed to resume target");
return ret;
@@ -334,8 +334,7 @@ static inline int esp_xtensa_smp_smpbreak_restore(struct target *target, uint32_
}
static int esp_xtensa_smp_resume_cores(struct target *target,
- int handle_breakpoints,
- int debug_execution)
+ bool handle_breakpoints, bool debug_execution)
{
struct target_list *head;
struct target *curr;
@@ -348,7 +347,7 @@ static int esp_xtensa_smp_resume_cores(struct target *target,
if ((curr != target) && (curr->state != TARGET_RUNNING) && target_was_examined(curr)) {
/* resume current address, not in SMP mode */
curr->smp = 0;
- int res = esp_xtensa_smp_resume(curr, 1, 0, handle_breakpoints, debug_execution);
+ int res = esp_xtensa_smp_resume(curr, true, 0, handle_breakpoints, debug_execution);
curr->smp = 1;
if (res != ERROR_OK)
return res;
@@ -358,10 +357,10 @@ static int esp_xtensa_smp_resume_cores(struct target *target,
}
int esp_xtensa_smp_resume(struct target *target,
- int current,
+ bool current,
target_addr_t address,
- int handle_breakpoints,
- int debug_execution)
+ bool handle_breakpoints,
+ bool debug_execution)
{
int res;
uint32_t smp_break;
@@ -420,9 +419,9 @@ int esp_xtensa_smp_resume(struct target *target,
}
int esp_xtensa_smp_step(struct target *target,
- int current,
+ bool current,
target_addr_t address,
- int handle_breakpoints)
+ bool handle_breakpoints)
{
int res;
uint32_t smp_break = 0;
diff --git a/src/target/espressif/esp_xtensa_smp.h b/src/target/espressif/esp_xtensa_smp.h
index 39afd8af1..ec074c11c 100644
--- a/src/target/espressif/esp_xtensa_smp.h
+++ b/src/target/espressif/esp_xtensa_smp.h
@@ -27,14 +27,14 @@ struct esp_xtensa_smp_common {
int esp_xtensa_smp_poll(struct target *target);
int esp_xtensa_smp_resume(struct target *target,
- int current,
+ bool current,
target_addr_t address,
- int handle_breakpoints,
- int debug_execution);
+ bool handle_breakpoints,
+ bool debug_execution);
int esp_xtensa_smp_step(struct target *target,
- int current,
+ bool current,
target_addr_t address,
- int handle_breakpoints);
+ bool handle_breakpoints);
int esp_xtensa_smp_assert_reset(struct target *target);
int esp_xtensa_smp_deassert_reset(struct target *target);
int esp_xtensa_smp_soft_reset_halt(struct target *target);
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index 1e7eb0961..840ca1b62 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -526,7 +526,7 @@ static int feroceon_bulk_write_memory(struct target *target,
arm->core_state = ARM_STATE_ARM;
embeddedice_write_reg(&arm7_9->eice_cache->reg_list[EICE_COMMS_DATA], 0);
- arm7_9_resume(target, 0, arm7_9->dcc_working_area->address, 1, 1);
+ arm7_9_resume(target, false, arm7_9->dcc_working_area->address, true, true);
/* send data over */
x = 0;
diff --git a/src/target/hla_target.c b/src/target/hla_target.c
index 6b0d2e95e..ef05df202 100644
--- a/src/target/hla_target.c
+++ b/src/target/hla_target.c
@@ -406,7 +406,8 @@ static int hl_deassert_reset(struct target *target)
target->SAVED_DCRDR = 0; /* clear both DCC busy bits on initial resume */
- return target->reset_halt ? ERROR_OK : target_resume(target, 1, 0, 0, 0);
+ return target->reset_halt ? ERROR_OK : target_resume(target, true, 0, false,
+ false);
}
static int adapter_halt(struct target *target)
@@ -434,9 +435,9 @@ static int adapter_halt(struct target *target)
return ERROR_OK;
}
-static int adapter_resume(struct target *target, int current,
- target_addr_t address, int handle_breakpoints,
- int debug_execution)
+static int adapter_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints,
+ bool debug_execution)
{
int res;
struct hl_interface *adapter = target_to_adapter(target);
@@ -525,8 +526,8 @@ static int adapter_resume(struct target *target, int current,
return ERROR_OK;
}
-static int adapter_step(struct target *target, int current,
- target_addr_t address, int handle_breakpoints)
+static int adapter_step(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints)
{
int res;
struct hl_interface *adapter = target_to_adapter(target);
diff --git a/src/target/lakemont.c b/src/target/lakemont.c
index 0340d0d0b..39a50c7a6 100644
--- a/src/target/lakemont.c
+++ b/src/target/lakemont.c
@@ -988,8 +988,8 @@ int lakemont_halt(struct target *t)
}
}
-int lakemont_resume(struct target *t, int current, target_addr_t address,
- int handle_breakpoints, int debug_execution)
+int lakemont_resume(struct target *t, bool current, target_addr_t address,
+ bool handle_breakpoints, bool debug_execution)
{
struct breakpoint *bp = NULL;
struct x86_32_common *x86_32 = target_to_x86_32(t);
@@ -1004,7 +1004,7 @@ int lakemont_resume(struct target *t, int current, target_addr_t address,
bp = breakpoint_find(t, eip);
if (bp /*&& bp->type == BKPT_SOFT*/) {
/* the step will step over the breakpoint */
- if (lakemont_step(t, 0, 0, 1) != ERROR_OK) {
+ if (lakemont_step(t, false, 0, true) != ERROR_OK) {
LOG_ERROR("%s stepping over a software breakpoint at 0x%08" PRIx32 " "
"failed to resume the target", __func__, eip);
return ERROR_FAIL;
@@ -1029,8 +1029,8 @@ int lakemont_resume(struct target *t, int current, target_addr_t address,
return ERROR_OK;
}
-int lakemont_step(struct target *t, int current,
- target_addr_t address, int handle_breakpoints)
+int lakemont_step(struct target *t, bool current, target_addr_t address,
+ bool handle_breakpoints)
{
struct x86_32_common *x86_32 = target_to_x86_32(t);
uint32_t eflags = buf_get_u32(x86_32->cache->reg_list[EFLAGS].value, 0, 32);
diff --git a/src/target/lakemont.h b/src/target/lakemont.h
index ca6557fcd..4c84f74ae 100644
--- a/src/target/lakemont.h
+++ b/src/target/lakemont.h
@@ -84,10 +84,10 @@ int lakemont_init_arch_info(struct target *t, struct x86_32_common *x86_32);
int lakemont_poll(struct target *t);
int lakemont_arch_state(struct target *t);
int lakemont_halt(struct target *t);
-int lakemont_resume(struct target *t, int current, target_addr_t address,
- int handle_breakpoints, int debug_execution);
-int lakemont_step(struct target *t, int current,
- target_addr_t address, int handle_breakpoints);
+int lakemont_resume(struct target *t, bool current, target_addr_t address,
+ bool handle_breakpoints, bool debug_execution);
+int lakemont_step(struct target *t, bool current,
+ target_addr_t address, bool handle_breakpoints);
int lakemont_reset_assert(struct target *t);
int lakemont_reset_deassert(struct target *t);
int lakemont_update_after_probemode_entry(struct target *t);
diff --git a/src/target/ls1_sap.c b/src/target/ls1_sap.c
index 9bd00c0e5..692f4cc9e 100644
--- a/src/target/ls1_sap.c
+++ b/src/target/ls1_sap.c
@@ -55,15 +55,15 @@ static int ls1_sap_halt(struct target *target)
return ERROR_OK;
}
-static int ls1_sap_resume(struct target *target, int current, target_addr_t address,
- int handle_breakpoints, int debug_execution)
+static int ls1_sap_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
LOG_DEBUG("%s", __func__);
return ERROR_OK;
}
-static int ls1_sap_step(struct target *target, int current, target_addr_t address,
- int handle_breakpoints)
+static int ls1_sap_step(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints)
{
LOG_DEBUG("%s", __func__);
return ERROR_OK;
diff --git a/src/target/mem_ap.c b/src/target/mem_ap.c
index 5b2bbb1ae..fdc52c307 100644
--- a/src/target/mem_ap.c
+++ b/src/target/mem_ap.c
@@ -102,8 +102,9 @@ static int mem_ap_halt(struct target *target)
return ERROR_OK;
}
-static int mem_ap_resume(struct target *target, int current, target_addr_t address,
- int handle_breakpoints, int debug_execution)
+static int mem_ap_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints,
+ bool debug_execution)
{
LOG_TARGET_DEBUG(target, "%s", __func__);
target->state = TARGET_RUNNING;
@@ -111,8 +112,8 @@ static int mem_ap_resume(struct target *target, int current, target_addr_t addre
return ERROR_OK;
}
-static int mem_ap_step(struct target *target, int current, target_addr_t address,
- int handle_breakpoints)
+static int mem_ap_step(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints)
{
LOG_TARGET_DEBUG(target, "%s", __func__);
target->state = TARGET_HALTED;
diff --git a/src/target/mips32.c b/src/target/mips32.c
index fcb7042cb..4527c5fa8 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -588,7 +588,7 @@ static int mips32_run_and_wait(struct target *target, target_addr_t entry_point,
int retval;
/* This code relies on the target specific resume() and poll()->debug_entry()
* sequence to write register values to the processor and the read them back */
- retval = target_resume(target, 0, entry_point, 0, 1);
+ retval = target_resume(target, false, entry_point, false, true);
if (retval != ERROR_OK)
return retval;
diff --git a/src/target/mips_m4k.c b/src/target/mips_m4k.c
index 1543de355..dc7450108 100644
--- a/src/target/mips_m4k.c
+++ b/src/target/mips_m4k.c
@@ -30,9 +30,9 @@ static int mips_m4k_set_breakpoint(struct target *target,
struct breakpoint *breakpoint);
static int mips_m4k_unset_breakpoint(struct target *target,
struct breakpoint *breakpoint);
-static int mips_m4k_internal_restore(struct target *target, int current,
- target_addr_t address, int handle_breakpoints,
- int debug_execution);
+static int mips_m4k_internal_restore(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints,
+ bool debug_execution);
static int mips_m4k_halt(struct target *target);
static int mips_m4k_bulk_write_memory(struct target *target, target_addr_t address,
uint32_t count, const uint8_t *buffer);
@@ -398,7 +398,8 @@ static int mips_m4k_single_step_core(struct target *target)
return ERROR_OK;
}
-static int mips_m4k_restore_smp(struct target *target, uint32_t address, int handle_breakpoints)
+static int mips_m4k_restore_smp(struct target *target, uint32_t address,
+ bool handle_breakpoints)
{
int retval = ERROR_OK;
struct target_list *head;
@@ -408,8 +409,8 @@ static int mips_m4k_restore_smp(struct target *target, uint32_t address, int han
struct target *curr = head->target;
if ((curr != target) && (curr->state != TARGET_RUNNING)) {
/* resume current address , not in step mode */
- ret = mips_m4k_internal_restore(curr, 1, address,
- handle_breakpoints, 0);
+ ret = mips_m4k_internal_restore(curr, true, address,
+ handle_breakpoints, false);
if (ret != ERROR_OK) {
LOG_TARGET_ERROR(curr, "failed to resume at address: 0x%" PRIx32,
@@ -421,8 +422,9 @@ static int mips_m4k_restore_smp(struct target *target, uint32_t address, int han
return retval;
}
-static int mips_m4k_internal_restore(struct target *target, int current,
- target_addr_t address, int handle_breakpoints, int debug_execution)
+static int mips_m4k_internal_restore(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints,
+ bool debug_execution)
{
struct mips32_common *mips32 = target_to_mips32(target);
struct mips_ejtag *ejtag_info = &mips32->ejtag_info;
@@ -440,7 +442,7 @@ static int mips_m4k_internal_restore(struct target *target, int current,
mips_m4k_enable_watchpoints(target);
}
- /* current = 1: continue on current pc, otherwise continue at <address> */
+ /* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
mips_m4k_isa_filter(mips32->isa_imp, &address);
buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32, address);
@@ -448,7 +450,7 @@ static int mips_m4k_internal_restore(struct target *target, int current,
mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].valid = true;
}
- if ((mips32->isa_imp > 1) && debug_execution) /* if more than one isa supported */
+ if (mips32->isa_imp > 1 && debug_execution) /* if more than one isa supported */
buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 1, mips32->isa_mode);
if (!current)
@@ -494,8 +496,8 @@ static int mips_m4k_internal_restore(struct target *target, int current,
return ERROR_OK;
}
-static int mips_m4k_resume(struct target *target, int current,
- target_addr_t address, int handle_breakpoints, int debug_execution)
+static int mips_m4k_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
int retval = ERROR_OK;
@@ -521,8 +523,8 @@ static int mips_m4k_resume(struct target *target, int current,
return retval;
}
-static int mips_m4k_step(struct target *target, int current,
- target_addr_t address, int handle_breakpoints)
+static int mips_m4k_step(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints)
{
/* get pointers to arch-specific information */
struct mips32_common *mips32 = target_to_mips32(target);
@@ -534,7 +536,7 @@ static int mips_m4k_step(struct target *target, int current,
return ERROR_TARGET_NOT_HALTED;
}
- /* current = 1: continue on current pc, otherwise continue at <address> */
+ /* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
mips_m4k_isa_filter(mips32->isa_imp, &address);
buf_set_u32(mips32->core_cache->reg_list[MIPS32_REGLIST_C0_PC_INDEX].value, 0, 32, address);
diff --git a/src/target/mips_mips64.c b/src/target/mips_mips64.c
index 9921e9380..85e377937 100644
--- a/src/target/mips_mips64.c
+++ b/src/target/mips_mips64.c
@@ -592,9 +592,9 @@ static int mips_mips64_unset_breakpoint(struct target *target,
return ERROR_OK;
}
-static int mips_mips64_resume(struct target *target, int current,
- uint64_t address, int handle_breakpoints,
- int debug_execution)
+static int mips_mips64_resume(struct target *target, bool current,
+ uint64_t address, bool handle_breakpoints,
+ bool debug_execution)
{
struct mips64_common *mips64 = target->arch_info;
struct mips_ejtag *ejtag_info = &mips64->ejtag_info;
@@ -622,7 +622,7 @@ static int mips_mips64_resume(struct target *target, int current,
}
pc = &mips64->core_cache->reg_list[MIPS64_PC];
- /* current = 1: continue on current pc, otherwise continue at <address> */
+ /* current = true: continue on current pc, otherwise continue at <address> */
if (!current) {
buf_set_u64(pc->value, 0, 64, address);
pc->dirty = true;
@@ -696,8 +696,8 @@ static int mips_mips64_resume(struct target *target, int current,
return ERROR_OK;
}
-static int mips_mips64_step(struct target *target, int current,
- uint64_t address, int handle_breakpoints)
+static int mips_mips64_step(struct target *target, bool current,
+ uint64_t address, bool handle_breakpoints)
{
struct mips64_common *mips64 = target->arch_info;
struct mips_ejtag *ejtag_info = &mips64->ejtag_info;
@@ -713,7 +713,7 @@ static int mips_mips64_step(struct target *target, int current,
if (mips64->mips64mode32)
address = mips64_extend_sign(address);
- /* current = 1: continue on current pc, otherwise continue at
+ /* current = true: continue on current pc, otherwise continue at
* <address> */
if (!current) {
buf_set_u64(pc->value, 0, 64, address);
diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c
index efc076c99..4b9d3bca6 100644
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@@ -775,9 +775,9 @@ static bool is_any_soft_breakpoint(struct target *target)
return false;
}
-static int or1k_resume_or_step(struct target *target, int current,
- uint32_t address, int handle_breakpoints,
- int debug_execution, int step)
+static int or1k_resume_or_step(struct target *target, bool current,
+ uint32_t address, bool handle_breakpoints, bool debug_execution,
+ int step)
{
struct or1k_common *or1k = target_to_or1k(target);
struct or1k_du *du_core = or1k_to_du(or1k);
@@ -885,9 +885,8 @@ static int or1k_resume_or_step(struct target *target, int current,
return ERROR_OK;
}
-static int or1k_resume(struct target *target, int current,
- target_addr_t address, int handle_breakpoints,
- int debug_execution)
+static int or1k_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints, bool debug_execution)
{
return or1k_resume_or_step(target, current, address,
handle_breakpoints,
@@ -895,12 +894,12 @@ static int or1k_resume(struct target *target, int current,
NO_SINGLE_STEP);
}
-static int or1k_step(struct target *target, int current,
- target_addr_t address, int handle_breakpoints)
+static int or1k_step(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints)
{
return or1k_resume_or_step(target, current, address,
handle_breakpoints,
- 0,
+ false,
SINGLE_STEP);
}
@@ -1216,7 +1215,7 @@ static int or1k_profiling(struct target *target, uint32_t *samples,
/* Make sure the target is running */
target_poll(target);
if (target->state == TARGET_HALTED)
- retval = target_resume(target, 1, 0, 0, 0);
+ retval = target_resume(target, true, 0, false, false);
if (retval != ERROR_OK) {
LOG_ERROR("Error while resuming target");
diff --git a/src/target/quark_d20xx.c b/src/target/quark_d20xx.c
index d63a42a6c..90cf6670e 100644
--- a/src/target/quark_d20xx.c
+++ b/src/target/quark_d20xx.c
@@ -65,7 +65,7 @@ static int quark_d20xx_reset_deassert(struct target *t)
}
/* resume target if reset mode is run */
if (!t->reset_halt) {
- retval = lakemont_resume(t, 1, 0, 0, 0);
+ retval = lakemont_resume(t, true, 0, false, false);
if (retval != ERROR_OK) {
LOG_ERROR("%s could not resume target", __func__);
return retval;
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c
index 302ace869..f4a7d0e5c 100644
--- a/src/target/riscv/riscv-011.c
+++ b/src/target/riscv/riscv-011.c
@@ -1192,7 +1192,7 @@ static int full_step(struct target *target, bool announce)
return ERROR_OK;
}
-static int resume(struct target *target, int debug_execution, bool step)
+static int resume(struct target *target, bool debug_execution, bool step)
{
if (debug_execution) {
LOG_ERROR("TODO: debug_execution is true");
@@ -1439,8 +1439,8 @@ static int strict_step(struct target *target, bool announce)
return ERROR_OK;
}
-static int step(struct target *target, int current, target_addr_t address,
- int handle_breakpoints)
+static int step(struct target *target, bool current, target_addr_t address,
+ bool handle_breakpoints)
{
jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
@@ -1929,8 +1929,9 @@ static int riscv011_poll(struct target *target)
return poll_target(target, true);
}
-static int riscv011_resume(struct target *target, int current,
- target_addr_t address, int handle_breakpoints, int debug_execution)
+static int riscv011_resume(struct target *target, bool current,
+ target_addr_t address, bool handle_breakpoints,
+ bool debug_execution)
{
RISCV_INFO(r);
jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 99f40a739..6a8577f5c 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -1096,16 +1096,15 @@ static int riscv_hit_watchpoint(struct target *target, struct watchpoint **hit_w
return ERROR_FAIL;
}
-
-static int oldriscv_step...
[truncated message content] |
|
From: openocd-gerrit <ope...@us...> - 2025-02-22 18:34:10
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f63b41bbe4ce33449ec18106620f57ba69ce7549 (commit)
from 0d7d178ed4fe2e99de804412fde9bb11c872f10a (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit f63b41bbe4ce33449ec18106620f57ba69ce7549
Author: Tomas Vanek <va...@fb...>
Date: Sat Feb 15 08:11:02 2025 +0100
drivers/linuxspidev: fix compilation on Linux older than 3.15
Although the commit [1] which introduced SPI_IOC_WR_MODE32 is 10 years
old, some hardware may enforce old Linux because the vendor
didn't bother with system updates.
Change-Id: I76d0b38c8646b1be329418860916b9f01b90990d
Link: [1] https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/include/uapi/linux/spi/spidev.h?h=linux-3.15.y&id=dc64d39b54c1e9db97a6fb1ca52598c981728157
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8759
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/linuxspidev.c b/src/jtag/drivers/linuxspidev.c
index 6a149a977..18abdc7db 100644
--- a/src/jtag/drivers/linuxspidev.c
+++ b/src/jtag/drivers/linuxspidev.c
@@ -302,8 +302,20 @@ static int spidev_init(void)
return ERROR_JTAG_INIT_FAILED;
}
+ int ret;
// Set SPI mode.
- int ret = ioctl(spi_fd, SPI_IOC_WR_MODE32, &spi_mode);
+#ifdef SPI_IOC_WR_MODE32
+ ret = ioctl(spi_fd, SPI_IOC_WR_MODE32, &spi_mode);
+#else
+ // Linux pre 3.15 does not support MODE32, use 8-bit ioctl
+ if (spi_mode & ~0xff) {
+ LOG_ERROR("SPI mode 0x%" PRIx32 ", system permits 8 bits only", spi_mode);
+ return ERROR_JTAG_INIT_FAILED;
+ }
+
+ uint8_t mode = (uint8_t)spi_mode;
+ ret = ioctl(spi_fd, SPI_IOC_WR_MODE, &mode);
+#endif
if (ret == -1) {
LOG_ERROR("Failed to set SPI mode 0x%" PRIx32, spi_mode);
return ERROR_JTAG_INIT_FAILED;
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/linuxspidev.c | 14 +++++++++++++-
1 file changed, 13 insertions(+), 1 deletion(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-02-21 21:22:09
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0d7d178ed4fe2e99de804412fde9bb11c872f10a (commit)
from 583506730d00cd88d2b8741993fa604c43a71658 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 0d7d178ed4fe2e99de804412fde9bb11c872f10a
Author: Evgeniy Naydanov <evg...@sy...>
Date: Wed Feb 12 21:12:30 2025 +0300
flash/nor/rsl10: drop unused `rsl10_info` in `rsl10_protect_check()`
`struct rsl10_info *chip` is only used in `rsl10_protect_check()` in an
assertion triggerring `-Wunused-variable` when compiled with `DNDEBUG`.
Drop it.
Change-Id: Ib302aea742131479f04f32e8fe8a88a3230ae203
Signed-off-by: Evgeniy Naydanov <evg...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8755
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/flash/nor/rsl10.c b/src/flash/nor/rsl10.c
index c286e9ac8..c33099787 100644
--- a/src/flash/nor/rsl10.c
+++ b/src/flash/nor/rsl10.c
@@ -155,11 +155,6 @@ static int rsl10_get_probed_chip_if_halted(struct flash_bank *bank, struct rsl10
static int rsl10_protect_check(struct flash_bank *bank)
{
- struct rsl10_bank *nbank = bank->driver_priv;
- struct rsl10_info *chip = nbank->chip;
-
- assert(chip);
-
uint32_t status;
int retval = target_read_u32(bank->target, RSL10_FLASH_REG_IF_STATUS, &status);
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/rsl10.c | 5 -----
1 file changed, 5 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-02-16 16:32:13
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 1f3f635693a1ddc85f362dc324cb49c3e7b75f27 (commit)
from ed4e58410446343a485625ee2722144cc23d55a6 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 1f3f635693a1ddc85f362dc324cb49c3e7b75f27
Author: Antonio Borneo <bor...@gm...>
Date: Thu Feb 6 11:48:30 2025 +0100
build: drop space after 'angie' folder name
The makefile consider the two white spaces between the end of the
folder name and the '#' character for the beginning of the comment
as part of the folder name.
This cause 'make install' to create a folder named 'angie ' that
is not welcome on all the OS.
Drop the comment and the space after the folder name.
Reported-by: Liviu Ionescu <il...@li...>
Change-Id: Iadd6803431edb83d0d84f4e4dc6d36b454f912ac
Signed-off-by: Antonio Borneo <bor...@gm...>
Fixes: 0ed03df6e95b ("amend angie build definitions to fix make dist")
Reviewed-on: https://review.openocd.org/c/openocd/+/8740
Reviewed-by: Liviu Ionescu
Tested-by: jenkins
Reviewed-by: Adrien Charruel <ach...@na...>
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index ec233b247..b0dd8e3ad 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -125,7 +125,7 @@ dist_ulink_DATA = $(ULINK_FIRMWARE)/ulink_firmware.hex
endif
if ANGIE
- angiedir = $(pkgdatadir)/angie # This is only for dist_angie_DATA.
+ angiedir = $(pkgdatadir)/angie
DRIVERFILES += %D%/angie.c
DRIVERFILES += %D%/angie/include/msgtypes.h
EXTRA_DIST += %D%/angie/README
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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From: openocd-gerrit <ope...@us...> - 2025-02-16 16:31:38
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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commit ed4e58410446343a485625ee2722144cc23d55a6
Author: Tomas Vanek <va...@fb...>
Date: Mon Feb 3 21:45:07 2025 +0100
jtag/core: fix segfault when adapter driver has no reset method
xlnx-pcie-xvc and linuxspidev adapter drivers does not implement
the reset method.
Although it is likely both adapters will implement the method in
the near future, avoid segfault and return an error instead.
Change-Id: If8ddf165dbc563cf6d64b2094968151075778ba7
Signed-off-by: Tomas Vanek <va...@fb...>
Fixes: commit 8850eb8f2c51 ("swd: get rid of jtag queue to assert/deassert srst")
Reviewed-on: https://review.openocd.org/c/openocd/+/8735
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/jtag/core.c b/src/jtag/core.c
index 89d53aecb..030c173be 100644
--- a/src/jtag/core.c
+++ b/src/jtag/core.c
@@ -631,6 +631,13 @@ static int adapter_system_reset(int req_srst)
/* Maybe change SRST signal state */
if (jtag_srst != req_srst) {
+ if (!adapter_driver->reset) {
+ if (req_srst)
+ LOG_ERROR("Adapter driver does not implement SRST handling");
+
+ return ERROR_NOT_IMPLEMENTED;
+ }
+
retval = adapter_driver->reset(0, req_srst);
if (retval != ERROR_OK) {
LOG_ERROR("SRST error");
-----------------------------------------------------------------------
Summary of changes:
src/jtag/core.c | 7 +++++++
1 file changed, 7 insertions(+)
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From: openocd-gerrit <ope...@us...> - 2025-02-16 16:31:01
|
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generated because a ref change was pushed to the repository containing
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- Log -----------------------------------------------------------------
commit 71f92c94468f370be80ce60dd76d5d924ddba69a
Author: Tomas Vanek <va...@fb...>
Date: Tue Jan 28 20:43:33 2025 +0100
target/cortex_m: call adapter_deassert_reset() only if srst is configured
Deasserting is useless if reset was not asserted except the very corner
case: changed reset_config during reset processing.
Change-Id: I1d1ea142980d67293daa348a2869b68ffd78d0eb
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8734
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 2cea203a2..9314d6675 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -1849,10 +1849,12 @@ static int cortex_m_deassert_reset(struct target *target)
target_state_name(target),
target_was_examined(target) ? "" : " not");
+ enum reset_types jtag_reset_config = jtag_get_reset_config();
+
/* deassert reset lines */
- adapter_deassert_reset();
+ if (jtag_reset_config & RESET_HAS_SRST)
+ adapter_deassert_reset();
- enum reset_types jtag_reset_config = jtag_get_reset_config();
if ((jtag_reset_config & RESET_HAS_SRST) &&
!(jtag_reset_config & RESET_SRST_NO_GATING) &&
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_m.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2025-02-16 16:29:35
|
This is an automated email from the git hooks/post-receive script. It was
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- Log -----------------------------------------------------------------
commit dcf02f46ff8355eb3f889aaa9d660f73dacede4f
Author: R. Diez <rdi...@ya...>
Date: Sat Jan 25 23:04:50 2025 +0100
Makefile.am: DISTCHECK_CONFIGURE_FLAGS -> AM_DISTCHECK_CONFIGURE_FLAGS
The Automake manual states: "The user can still extend or override
the flags provided there by defining the DISTCHECK_CONFIGURE_FLAGS
variable". Overriding variable DISTCHECK_CONFIGURE_FLAGS in Makefile.am
makes it impossible for the user to do that. I discovered this
when trying to pass --enable-internal-jimtcl to distcheck.
Change-Id: Ibe5b1f23ccf3fbaa21c48b574a1b3f3e9f6fb916
Signed-off-by: R. Diez <rdi...@ya...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8724
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/Makefile.am b/Makefile.am
index 155a2b3bb..271a2c165 100644
--- a/Makefile.am
+++ b/Makefile.am
@@ -7,7 +7,7 @@ AUTOMAKE_OPTIONS = gnu 1.6
.DELETE_ON_ERROR:
# make sure we pass the correct jimtcl flags to distcheck
-DISTCHECK_CONFIGURE_FLAGS = --disable-install-jim
+AM_DISTCHECK_CONFIGURE_FLAGS = --disable-install-jim
# do not run Jim Tcl tests (esp. during distcheck)
check-recursive: SUBDIRS :=
-----------------------------------------------------------------------
Summary of changes:
Makefile.am | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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From: openocd-gerrit <ope...@us...> - 2025-02-16 16:29:06
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 4deb76fc9d48aff71b1f2875eecc4b6964c0a0c7 (commit)
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- Log -----------------------------------------------------------------
commit 5e4ad24ba610e81ee6e9358154ef176e15c36fe7
Author: R. Diez <rdi...@ya...>
Date: Sat Jan 25 21:04:05 2025 +0100
configure.ac: show vdebug in the config summary
Also enable this adapter by default (auto).
Change-Id: Id011168b93c4cdc602ab78eabfb9a64ca8d8a7df
Signed-off-by: R. Diez <rdi...@ya...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8601
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/configure.ac b/configure.ac
index 4b10aabd5..fda0b2a36 100644
--- a/configure.ac
+++ b/configure.ac
@@ -172,6 +172,8 @@ m4_define([SERIAL_PORT_ADAPTERS],
m4_define([LINUXSPIDEV_ADAPTER],
[[[linuxspidev], [Linux spidev driver], [LINUXSPIDEV]]])
+m4_define([VDEBUG_ADAPTER],
+ [[[vdebug], [Cadence Virtual Debug Interface], [VDEBUG]]])
# The word 'Adapter' in "Dummy Adapter" below must begin with a capital letter
# because there is an M4 macro called 'adapter'.
@@ -302,6 +304,7 @@ AC_ARG_ADAPTERS([
LINUXSPIDEV_ADAPTER,
SERIAL_PORT_ADAPTERS,
DUMMY_ADAPTER,
+ VDEBUG_ADAPTER,
PCIE_ADAPTERS,
LIBJAYLINK_ADAPTERS
],[auto])
@@ -324,10 +327,6 @@ AC_ARG_ENABLE([jtag_vpi],
AS_HELP_STRING([--enable-jtag_vpi], [Enable building support for JTAG VPI]),
[build_jtag_vpi=$enableval], [build_jtag_vpi=no])
-AC_ARG_ENABLE([vdebug],
- AS_HELP_STRING([--enable-vdebug], [Enable building support for Cadence Virtual Debug Interface]),
- [build_vdebug=$enableval], [build_vdebug=no])
-
AC_ARG_ENABLE([jtag_dpi],
AS_HELP_STRING([--enable-jtag_dpi], [Enable building support for JTAG DPI]),
[build_jtag_dpi=$enableval], [build_jtag_dpi=no])
@@ -581,12 +580,6 @@ AS_IF([test "x$build_jtag_vpi" = "xyes"], [
AC_DEFINE([BUILD_JTAG_VPI], [0], [0 if you don't want JTAG VPI.])
])
-AS_IF([test "x$build_vdebug" = "xyes"], [
- AC_DEFINE([BUILD_VDEBUG], [1], [1 if you want Cadence vdebug interface.])
-], [
- AC_DEFINE([BUILD_VDEBUG], [0], [0 if you don't want Cadence vdebug interface.])
-])
-
AS_IF([test "x$build_jtag_dpi" = "xyes"], [
AC_DEFINE([BUILD_JTAG_DPI], [1], [1 if you want JTAG DPI.])
], [
@@ -738,6 +731,7 @@ PROCESS_ADAPTERS([PCIE_ADAPTERS], ["x$is_linux" = "xyes"], [Linux build])
PROCESS_ADAPTERS([SERIAL_PORT_ADAPTERS], ["x$can_build_buspirate" = "xyes"],
[internal error: validation should happen beforehand])
PROCESS_ADAPTERS([LINUXSPIDEV_ADAPTER], ["x$is_linux" = "xyes"], [Linux spidev])
+PROCESS_ADAPTERS([VDEBUG_ADAPTER], [true], [unused])
PROCESS_ADAPTERS([DUMMY_ADAPTER], [true], [unused])
AS_IF([test "x$enable_linuxgpiod" != "xno"], [
@@ -786,7 +780,6 @@ AM_CONDITIONAL([IMX_GPIO], [test "x$build_imx_gpio" = "xyes"])
AM_CONDITIONAL([AM335XGPIO], [test "x$build_am335xgpio" = "xyes"])
AM_CONDITIONAL([BITBANG], [test "x$build_bitbang" = "xyes"])
AM_CONDITIONAL([JTAG_VPI], [test "x$build_jtag_vpi" = "xyes"])
-AM_CONDITIONAL([VDEBUG], [test "x$build_vdebug" = "xyes"])
AM_CONDITIONAL([JTAG_DPI], [test "x$build_jtag_dpi" = "xyes"])
AM_CONDITIONAL([USB_BLASTER_DRIVER], [test "x$enable_usb_blaster" != "xno" -o "x$enable_usb_blaster_2" != "xno"])
AM_CONDITIONAL([AMTJTAGACCEL], [test "x$build_amtjtagaccel" = "xyes"])
@@ -892,6 +885,7 @@ m4_foreach([adapter], [USB1_ADAPTERS,
LIBGPIOD_ADAPTERS,
LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, SERIAL_PORT_ADAPTERS,
LINUXSPIDEV_ADAPTER,
+ VDEBUG_ADAPTER,
DUMMY_ADAPTER,
OPTIONAL_LIBRARIES,
COVERAGE],
-----------------------------------------------------------------------
Summary of changes:
configure.ac | 16 +++++-----------
1 file changed, 5 insertions(+), 11 deletions(-)
hooks/post-receive
--
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From: openocd-gerrit <ope...@us...> - 2025-02-16 16:28:37
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4deb76fc9d48aff71b1f2875eecc4b6964c0a0c7 (commit)
from a71f2b70894a8118730d912edf27fe488580bd4c (commit)
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- Log -----------------------------------------------------------------
commit 4deb76fc9d48aff71b1f2875eecc4b6964c0a0c7
Author: R. Diez <rdi...@ya...>
Date: Sat Jan 25 22:06:22 2025 +0100
options.c: option --help should yield exit code 0
--help is supported and there is no reason to signal failure
Change-Id: I59fda5336df47ec0b8172541a5fbfe60014bba7e
Signed-off-by: R. Diez <rdi...@ya...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8723
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/helper/options.c b/src/helper/options.c
index 50977a610..735b8af5f 100644
--- a/src/helper/options.c
+++ b/src/helper/options.c
@@ -334,7 +334,7 @@ int parse_cmdline_args(struct command_context *cmd_ctx, int argc, char *argv[])
LOG_OUTPUT(" | -d<n>\tset debug level to <level>\n");
LOG_OUTPUT("--log_output | -l\tredirect log output to file <name>\n");
LOG_OUTPUT("--command | -c\trun <command>\n");
- exit(-1);
+ exit(0);
}
if (version_flag) {
-----------------------------------------------------------------------
Summary of changes:
src/helper/options.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
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--
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From: openocd-gerrit <ope...@us...> - 2025-02-16 16:27:52
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a71f2b70894a8118730d912edf27fe488580bd4c (commit)
from 44e782d55bf1ce0d924c082281082496cdc2495e (commit)
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- Log -----------------------------------------------------------------
commit a71f2b70894a8118730d912edf27fe488580bd4c
Author: Antonio Borneo <bor...@gm...>
Date: Sat Jan 25 17:26:16 2025 +0100
README: report dependency from libjim
The support for jimtcl submodule is deprecated.
Report libjim as a dependency for building OpenOCD.
Change-Id: Iaaeb03dc810451c0d72add281016c81b8cbf7059
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8722
Reviewed-by: zapb <de...@za...>
Tested-by: jenkins
diff --git a/README b/README
index 950c71f70..fba758cfe 100644
--- a/README
+++ b/README
@@ -209,9 +209,7 @@ You'll also need:
- make
- libtool
- pkg-config >= 0.23 or pkgconf
-
-OpenOCD uses jimtcl library; build from git can retrieve jimtcl as git
-submodule.
+- libjim >= 0.79
Additionally, for building from git:
-----------------------------------------------------------------------
Summary of changes:
README | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2025-02-16 16:27:15
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 44e782d55bf1ce0d924c082281082496cdc2495e
Author: Daniel DeGrasse <dde...@te...>
Date: Thu Jan 16 22:33:48 2025 -0500
target/arc: allow reading memory while target runs
There is no reason that ARC can't support reading from memory over JTAG
while the target is executing, and this is in fact required for RTT
support. Remove this check from arc_mem_read and arc_mem_write
Change-Id: I2accfb4b99bf77c5473d133623e0eb0632cb45f6
Signed-off-by: Daniel DeGrasse <dde...@te...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8721
Tested-by: jenkins
Reviewed-by: Evgeniy Didin <di...@sy...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/arc_mem.c b/src/target/arc_mem.c
index 3daed1cbb..5132aca3d 100644
--- a/src/target/arc_mem.c
+++ b/src/target/arc_mem.c
@@ -161,11 +161,6 @@ int arc_mem_write(struct target *target, target_addr_t address, uint32_t size,
LOG_TARGET_DEBUG(target, "address: 0x%08" TARGET_PRIxADDR ", size: %" PRIu32 ", count: %" PRIu32,
address, size, count);
- if (target->state != TARGET_HALTED) {
- LOG_TARGET_ERROR(target, "not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
/* sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || !(count) || !(buffer))
return ERROR_COMMAND_SYNTAX_ERROR;
@@ -246,11 +241,6 @@ int arc_mem_read(struct target *target, target_addr_t address, uint32_t size,
LOG_TARGET_DEBUG(target, "Read memory: addr=0x%08" TARGET_PRIxADDR ", size=%" PRIu32
", count=%" PRIu32, address, size, count);
- if (target->state != TARGET_HALTED) {
- LOG_TARGET_WARNING(target, "target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
/* Sanitize arguments */
if (((size != 4) && (size != 2) && (size != 1)) || !(count) || !(buffer))
return ERROR_COMMAND_SYNTAX_ERROR;
-----------------------------------------------------------------------
Summary of changes:
src/target/arc_mem.c | 10 ----------
1 file changed, 10 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2025-02-16 16:25:12
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 9ccd6265dd56c75cc8d58359d33bf6d65a7524ab (commit)
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- Log -----------------------------------------------------------------
commit 9bb0a4558bc84b8be63aa937d4b7b9283614f132
Author: Chris Friedt <cf...@te...>
Date: Mon Dec 9 16:11:03 2024 -0500
target/arc: add RTT commands
Since RTT is architecture agnostic, add support for using it on
the ARC architecture as well.
Change-Id: Icd0dec105177a1a224bfb1a63f0be5f03561b166
Signed-off-by: Chris Friedt <cf...@te...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8720
Reviewed-by: zapb <de...@za...>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/arc.h b/src/target/arc.h
index a351802ac..4255840d1 100644
--- a/src/target/arc.h
+++ b/src/target/arc.h
@@ -22,6 +22,7 @@
#include "target_request.h"
#include "target_type.h"
#include "helper/bits.h"
+#include "rtt/rtt.h"
#include "arc_jtag.h"
#include "arc_cmd.h"
diff --git a/src/target/arc_cmd.c b/src/target/arc_cmd.c
index e7760b037..bf8a8aa28 100644
--- a/src/target/arc_cmd.c
+++ b/src/target/arc_cmd.c
@@ -906,5 +906,8 @@ const struct command_registration arc_monitor_command_handlers[] = {
.usage = "",
.chain = arc_core_command_handlers,
},
+ {
+ .chain = rtt_target_command_handlers,
+ },
COMMAND_REGISTRATION_DONE
};
-----------------------------------------------------------------------
Summary of changes:
src/target/arc.h | 1 +
src/target/arc_cmd.c | 3 +++
2 files changed, 4 insertions(+)
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From: openocd-gerrit <ope...@us...> - 2025-02-16 16:23:53
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from 4895a556fa6bafce14237b7e4c821d18fc55df02 (commit)
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- Log -----------------------------------------------------------------
commit 9ccd6265dd56c75cc8d58359d33bf6d65a7524ab
Author: Antonio Borneo <bor...@gm...>
Date: Fri Jan 10 17:11:24 2025 +0100
checkpatch: enable check for new typedefs
We should strictly check for every new typedef.
Let checkpatch detect them and let developer use
Checkpatch-ignore: NEW_TYPEDEFS
if it's really needed to add a new typedef.
With this change chackpatch will not complain for typedef on
function's type but only on enum, struct, variable's type.
Change-Id: I644a753e97de877d892af3a0219716f022fb1c59
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8710
Reviewed-by: zapb <de...@za...>
Tested-by: jenkins
diff --git a/.checkpatch.conf b/.checkpatch.conf
index 8cb9a3729..f432503e1 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -17,7 +17,6 @@
--ignore LINE_SPACING
--ignore LOGICAL_CONTINUATIONS
--ignore MACRO_WITH_FLOW_CONTROL
---ignore NEW_TYPEDEFS
--ignore PARENTHESIS_ALIGNMENT
--ignore PREFER_DEFINED_ATTRIBUTE_MACRO
--ignore PREFER_FALLTHROUGH
-----------------------------------------------------------------------
Summary of changes:
.checkpatch.conf | 1 -
1 file changed, 1 deletion(-)
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