openocd-commit — OpenOCD commit maling list - read only

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1283-g4e78563a0

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  4e78563a0083d32a7cbb3ebfa92f7b9142637bf3 (commit)
      from  d7fb95d8003b01c2d6aa3e53a2d3eafbddfcb5a1 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 4e78563a0083d32a7cbb3ebfa92f7b9142637bf3
Author: Evgeniy Naydanov <evg...@sy...>
Date:   Tue Oct 28 17:16:55 2025 +0300

    target/riscv: fix progbuf memory writes in case last write is busy
    
    Restarting the program buffer memory write pipeline when the write of
    the last element resulted in the busy response triggers an extra memory
    wrtite, that is cought by an assertion:
    ```
    src/target/riscv/riscv-013.c:5048: write_memory_progbuf_inner: Assertion
    `next_addr_on_target - args.address <= (target_addr_t)args.size *
    args.count' failed.
    ```
    
    Change-Id: I0f27145cad24686cf539aebfea7f6578b7cd78ab
    Signed-off-by: Evgeniy Naydanov <evg...@sy...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9233
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 370a15607..6fa5e025b 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -4875,7 +4875,8 @@ static int write_memory_progbuf_teardown(struct target *target)
  * failed write.
  */
 static int write_memory_progbuf_handle_busy(struct target *target,
-		target_addr_t *address_p, uint32_t size, const uint8_t *buffer)
+		target_addr_t *address_p, target_addr_t end_address, uint32_t size,
+		const uint8_t *buffer)
 {
 	int res = riscv013_clear_abstract_error(target);
 	if (res != ERROR_OK)
@@ -4891,8 +4892,12 @@ static int write_memory_progbuf_handle_busy(struct target *target,
 	if (register_read_direct(target, &address_on_target, GDB_REGNO_S0) != ERROR_OK)
 		return ERROR_FAIL;
 	const uint8_t * const curr_buff = buffer + (address_on_target - *address_p);
-	LOG_TARGET_DEBUG(target, "Restarting from 0x%" TARGET_PRIxADDR, *address_p);
 	*address_p = address_on_target;
+	if (*address_p == end_address) {
+		LOG_TARGET_DEBUG(target, "Got busy while reading after reading the last element");
+		return ERROR_OK;
+	}
+	LOG_TARGET_DEBUG(target, "Restarting from 0x%" TARGET_PRIxADDR, *address_p);
 	/* This restores the pipeline and ensures one item gets reliably written */
 	return write_memory_progbuf_startup(target, address_p, curr_buff, size);
 }
@@ -4970,7 +4975,8 @@ static int write_memory_progbuf_run_batch(struct target *target, struct riscv_ba
 		/* TODO: If dmi busy is encountered, the address of the last
 		 * successful write can be deduced by analysing the batch.
 		 */
-		return write_memory_progbuf_handle_busy(target, address_p, size, buffer);
+		return write_memory_progbuf_handle_busy(target, address_p, end_address,
+				size, buffer);
 	}
 	LOG_TARGET_ERROR(target, "Error when writing memory, abstractcs=0x%" PRIx32,
 			abstractcs);

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv-013.c | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1282-gd7fb95d80

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  d7fb95d8003b01c2d6aa3e53a2d3eafbddfcb5a1 (commit)
      from  12ab80ab45183ad0eafcf59c43eda229ec1c7b94 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit d7fb95d8003b01c2d6aa3e53a2d3eafbddfcb5a1
Author: Tomas Vanek <va...@fb...>
Date:   Sun Oct 26 10:25:05 2025 +0100

    tcl/target: update riscv commands in configs
    
    Adjust configs for the changed command riscv virt2phys_mode.
    
    Change-Id: Ib365bbb74b3b17e8f0b594e08ab73871f86cf89e
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9190
    Tested-by: jenkins

diff --git a/tcl/target/bl602_common.cfg b/tcl/target/bl602_common.cfg
index cf4bc3947..1fe5d9416 100644
--- a/tcl/target/bl602_common.cfg
+++ b/tcl/target/bl602_common.cfg
@@ -37,7 +37,7 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
 riscv set_mem_access sysbus
-riscv set_enable_virt2phys off
+riscv virt2phys_mode off
 
 $_TARGETNAME configure -work-area-phys $_WORKAREAADDR -work-area-size $_WORKAREASIZE -work-area-backup 1
 
diff --git a/tcl/target/bl616.cfg b/tcl/target/bl616.cfg
index ee59f1850..6f00c0546 100644
--- a/tcl/target/bl616.cfg
+++ b/tcl/target/bl616.cfg
@@ -27,7 +27,7 @@ set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
 riscv set_mem_access progbuf
-riscv set_enable_virt2phys off
+riscv virt2phys_mode off
 
 $_TARGETNAME configure -work-area-phys 0x40000000 -work-area-size 0x10000 -work-area-backup 1
 
diff --git a/tcl/target/rp2350.cfg b/tcl/target/rp2350.cfg
index 96bb9298f..be51931ec 100644
--- a/tcl/target/rp2350.cfg
+++ b/tcl/target/rp2350.cfg
@@ -100,7 +100,7 @@ if { [info exists _TARGETNAME_CM0] } {
 
 if { [info exists _TARGETNAME_RV0] } {
 	target create $_TARGETNAME_RV0 riscv -dap $_CHIPNAME.dap -ap-num 0xa000 -coreid 0
-	$_TARGETNAME_RV0 riscv set_enable_virt2phys off
+	$_TARGETNAME_RV0 riscv virt2phys_mode off
 
 	$_TARGETNAME_RV0 configure -event reset-init "_rv_reset_init"
 
@@ -117,7 +117,7 @@ if { [info exists _TARGETNAME_CM1] } {
 
 if { [info exists _TARGETNAME_RV1] } {
 	target create $_TARGETNAME_RV1 riscv -dap $_CHIPNAME.dap -ap-num 0xa000 -coreid 1
-	$_TARGETNAME_RV1 riscv set_enable_virt2phys off
+	$_TARGETNAME_RV1 riscv virt2phys_mode off
 }
 
 if { [info exists USE_SMP] } {

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/bl602_common.cfg | 2 +-
 tcl/target/bl616.cfg        | 2 +-
 tcl/target/rp2350.cfg       | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1281-g12ab80ab4

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  12ab80ab45183ad0eafcf59c43eda229ec1c7b94 (commit)
      from  68b0f7bdff8a20f3280b47e28b5215a5ae2522b6 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 12ab80ab45183ad0eafcf59c43eda229ec1c7b94
Author: Parshintsev Anatoly <ana...@sy...>
Date:   Fri Aug 15 22:46:56 2025 +0300

    target/riscv: fix SV57 translation for kernel address space
    
    Fixes address translation for SV57 addresses.
    
    See [1] for details.
    
    Link: https://github.com/riscv-collab/riscv-openocd/pull/1285 [1]
    Change-Id: I53f7062f16c0b9e8595f38c07810b2dbc300980b
    Signed-off-by: Parshintsev Anatoly <ana...@sy...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9187
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index d6b5804a6..8054a1c9b 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -274,7 +274,7 @@ static const virt2phys_info_t sv57 = {
 	.pte_ppn_shift = {10, 19, 28, 37, 46},
 	.pte_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ff, 0xff},
 	.pa_ppn_shift = {12, 21, 30, 39, 48},
-	.pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ff, 0xff},
+	.pa_ppn_mask = {0x1ff, 0x1ff, 0x1ff, 0x1ff, 0x1ff},
 };
 
 static const virt2phys_info_t sv57x4 = {

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1280-g68b0f7bdf

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  68b0f7bdff8a20f3280b47e28b5215a5ae2522b6 (commit)
      from  52ac91a73e19759a74bf4b834225fba7c6a95084 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 68b0f7bdff8a20f3280b47e28b5215a5ae2522b6
Author: Tim Newsome <ti...@si...>
Date:   Wed Aug 14 11:56:44 2019 -0700

    server: rtos: don't fake step for hwthread rtos.
    
    This is a cherry-pick of:
    Link: https://github.com/riscv-collab/riscv-openocd/commit/efce094b409179acbaa7726c112a10fcf8343503
    
    Fake step is a hack introduced to make things work with real RTOSs that
    have a concept of a current thread. The hwthread rtos always has access
    to all threads, so doesn't need it.
    
    This fixes a bug when running my MulticoreRegTest against HiFive
    Unleashed where OpenOCD would return the registers of the wrong thread
    after gdb stepped a hart.
    
    Change-Id: I64f538a133fb078c05a0c6b8121388b0b9d7f1b8
    Signed-off-by: Tim Newsome <ti...@si...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9177
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/src/rtos/hwthread.c b/src/rtos/hwthread.c
index 3f0041e0b..d4fc880f6 100644
--- a/src/rtos/hwthread.c
+++ b/src/rtos/hwthread.c
@@ -28,6 +28,7 @@ static int hwthread_read_buffer(struct rtos *rtos, target_addr_t address,
 		uint32_t size, uint8_t *buffer);
 static int hwthread_write_buffer(struct rtos *rtos, target_addr_t address,
 		uint32_t size, const uint8_t *buffer);
+static bool hwthread_needs_fake_step(struct target *target, int64_t thread_id);
 
 #define HW_THREAD_NAME_STR_SIZE (32)
 
@@ -59,6 +60,7 @@ const struct rtos_type hwthread_rtos = {
 	.set_reg = hwthread_set_reg,
 	.read_buffer = hwthread_read_buffer,
 	.write_buffer = hwthread_write_buffer,
+	.needs_fake_step = hwthread_needs_fake_step
 };
 
 struct hwthread_params {
@@ -449,3 +451,8 @@ static int hwthread_write_buffer(struct rtos *rtos, target_addr_t address,
 
 	return target_write_buffer(curr, address, size, buffer);
 }
+
+bool hwthread_needs_fake_step(struct target *target, int64_t thread_id)
+{
+	return false;
+}
diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 163d882a4..7957a5b6b 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -755,3 +755,10 @@ int rtos_write_buffer(struct target *target, target_addr_t address,
 		return target->rtos->type->write_buffer(target->rtos, address, size, buffer);
 	return ERROR_NOT_IMPLEMENTED;
 }
+
+bool rtos_needs_fake_step(struct target *target, int64_t thread_id)
+{
+	if (target->rtos->type->needs_fake_step)
+		return target->rtos->type->needs_fake_step(target, thread_id);
+	return target->rtos->current_thread != thread_id;
+}
diff --git a/src/rtos/rtos.h b/src/rtos/rtos.h
index ca6d7518d..bbd1d1a1d 100644
--- a/src/rtos/rtos.h
+++ b/src/rtos/rtos.h
@@ -79,6 +79,13 @@ struct rtos_type {
 			uint8_t *buffer);
 	int (*write_buffer)(struct rtos *rtos, target_addr_t address, uint32_t size,
 			const uint8_t *buffer);
+	/**
+	 * Possibly work around an annoying gdb behaviour: when the current thread
+	 * is changed in gdb, it assumes that the target can follow and also make
+	 * the thread current. This is an assumption that cannot hold for a real
+	 * target running a multi-threading OS. If an RTOS can do this, override
+	 * needs_fake_step(). */
+	bool (*needs_fake_step)(struct target *target, int64_t thread_id);
 };
 
 struct stack_register_offset {
@@ -137,6 +144,7 @@ int rtos_read_buffer(struct target *target, target_addr_t address,
 		uint32_t size, uint8_t *buffer);
 int rtos_write_buffer(struct target *target, target_addr_t address,
 		uint32_t size, const uint8_t *buffer);
+bool rtos_needs_fake_step(struct target *target, int64_t thread_id);
 
 // Keep in alphabetic order this list of rtos
 extern const struct rtos_type chibios_rtos;
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index d18d48a3a..486080bbd 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -3080,8 +3080,22 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
 		}
 
 		if (target->rtos) {
-			/* FIXME: why is this necessary? rtos state should be up-to-date here already! */
-			rtos_update_threads(target);
+			/* Sometimes this results in picking a different thread than
+			 * gdb just requested to step. Then we fake it, and now there's
+			 * a different thread selected than gdb expects, so register
+			 * accesses go to the wrong one!
+			 * E.g.:
+			 * Hg1$
+			 * P8=72101ce197869329$		# write r8 on thread 1
+			 * g$
+			 * vCont?$
+			 * vCont;s:1;c$				# rtos_update_threads changes to other thread
+			 * g$
+			 * qXfer:threads:read::0,fff$
+			 * P8=cc060607eb89ca7f$		# write r8 on other thread
+			 * g$
+			 */
+			 /* rtos_update_threads(target); */
 
 			target->rtos->gdb_target_for_threadid(connection, thread_id, &ct);
 
@@ -3089,8 +3103,7 @@ static bool gdb_handle_vcont_packet(struct connection *connection, const char *p
 			 * check if the thread to be stepped is the current rtos thread
 			 * if not, we must fake the step
 			 */
-			if (target->rtos->current_thread != thread_id)
-				fake_step = true;
+			fake_step = rtos_needs_fake_step(target, thread_id);
 		}
 
 		if (parse[0] == ';') {

-----------------------------------------------------------------------

Summary of changes:
 src/rtos/hwthread.c     |  7 +++++++
 src/rtos/rtos.c         |  7 +++++++
 src/rtos/rtos.h         |  8 ++++++++
 src/server/gdb_server.c | 21 +++++++++++++++++----
 4 files changed, 39 insertions(+), 4 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1279-g52ac91a73

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  52ac91a73e19759a74bf4b834225fba7c6a95084 (commit)
      from  8c410704154c28ca4354d85233ed76a29a031322 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 52ac91a73e19759a74bf4b834225fba7c6a95084
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Oct 7 14:03:15 2025 +0200

    target: riscv: move the SMP commands under riscv
    
    For all the targets that support SMP, the sub-commands 'smp' and
    'smp_gdb' are under the arch name:
    - aarch64 smp
    - cortex_a smp
    - cortex_m smp
    - esp32 smp
    - mips_m4k smp
    
    Keep consistency among OpenOCD commands, and move under the arch
    name 'riscv' the SMP subcommands.
    
    Change-Id: Iede7841c2df8161ff2c6fea3be561d1f26ad6cd0
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9165
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 54cf21a29..f2ffa3a75 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11800,16 +11800,16 @@ When utilizing version 0.11 of the RISC-V Debug Specification,
 and DBUS registers, respectively.
 @end deffn
 
-@deffn {Command} {smp} [on|off]
+@deffn {Command} {riscv smp} [on|off]
 Display, enable or disable SMP handling mode. This command is needed only if
 user wants to temporary @b{disable} SMP handling for an existing SMP group
 (see @code{aarch64 smp} for additional information). To define an SMP
 group the command @code{target smp} should be used.
 @end deffn
 
-@deffn {Command} {smp_gdb} [core_id]
+@deffn {Command} {riscv smp_gdb} [core_id]
 Display/set the current core displayed in GDB. This is needed only if
-@code{smp} was used.
+@code{riscv smp} was used.
 @end deffn
 
 @deffn {Config Command} {riscv use_bscan_tunnel} width [type]
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 07aa578a5..d6b5804a6 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -5838,6 +5838,9 @@ static const struct command_registration riscv_exec_command_handlers[] = {
 			"When off, users need to take care of memory coherency themselves, for example by using "
 			"`riscv exec_progbuf` to execute fence or CMO instructions."
 	},
+	{
+		.chain = smp_command_handlers
+	},
 	COMMAND_REGISTRATION_DONE
 };
 
@@ -5870,9 +5873,6 @@ static const struct command_registration riscv_command_handlers[] = {
 		.usage = "",
 		.chain = semihosting_common_handlers
 	},
-	{
-		.chain = smp_command_handlers
-	},
 	COMMAND_REGISTRATION_DONE
 };
 

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi         | 6 +++---
 src/target/riscv/riscv.c | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1278-g8c4107041

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  8c410704154c28ca4354d85233ed76a29a031322 (commit)
      from  be083909b709e05da7c2891bc0da59059e99f758 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 8c410704154c28ca4354d85233ed76a29a031322
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Oct 7 12:14:15 2025 +0200

    target: riscv: fix double free() in parse_reg_ranges()
    
    The buffer 'args' is allocated and freed in the caller function
    parse_reg_ranges().
    There is no reason to free it, only in some special case, in the
    called function parse_reg_ranges_impl().
    Scan build reports:
            src/target/riscv/riscv.c:4537:2: warning: Attempt to free
            released memory [unix.Malloc]
    
    Drop the free() in the called function.
    
    Change-Id: I2e308670c502f8e140603b4e5c16fc568088e1a8
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9164
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 9d858276b..07aa578a5 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -4473,7 +4473,6 @@ static int parse_reg_ranges_impl(struct list_head *ranges, char *args,
 			}
 		} else {
 			LOG_ERROR("Invalid argument '%s'.", arg);
-			free(args);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv.c | 1 -
 1 file changed, 1 deletion(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1277-gbe083909b

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  be083909b709e05da7c2891bc0da59059e99f758 (commit)
      from  ed9cf6d81d9ea9300625a9a69281a2a93e3012fc (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit be083909b709e05da7c2891bc0da59059e99f758
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Oct 7 12:06:54 2025 +0200

    target: riscv: fix memory leak in riscv_openocd_step_impl()
    
    The array 'wps_to_enable' is never freed.
    Scan build reports:
            src/target/riscv/riscv.c:4271:6: warning: Potential leak
            of memory pointed to by 'wps_to_enable' [unix.Malloc]
    
    Add the needed free().
    While there, check if the allocation is successful.
    
    Change-Id: I00e7ade37a43a97dcc245113ad93c48784fce609
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9163
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 7ad695c20..9d858276b 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -4210,9 +4210,15 @@ static int riscv_openocd_step_impl(struct target *target, bool current,
 
 	RISCV_INFO(r);
 	bool *wps_to_enable = calloc(r->trigger_count, sizeof(*wps_to_enable));
+	if (!wps_to_enable) {
+		LOG_ERROR("Out of memory");
+		return ERROR_FAIL;
+	}
+
 	if (disable_watchpoints(target, wps_to_enable) != ERROR_OK) {
 		LOG_TARGET_ERROR(target, "Failed to temporarily disable "
 				"watchpoints before single-step.");
+		free(wps_to_enable);
 		return ERROR_FAIL;
 	}
 
@@ -4257,6 +4263,8 @@ _exit:
 				"after single-step.");
 	}
 
+	free(wps_to_enable);
+
 	if (breakpoint && (riscv_add_breakpoint(target, breakpoint) != ERROR_OK)) {
 		success = false;
 		LOG_TARGET_ERROR(target, "Unable to restore the disabled breakpoint.");

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv.c | 8 ++++++++
 1 file changed, 8 insertions(+)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1276-ged9cf6d81

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  ed9cf6d81d9ea9300625a9a69281a2a93e3012fc (commit)
      from  18734bcf953324f9f40b518bc973634bfd9f41cd (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit ed9cf6d81d9ea9300625a9a69281a2a93e3012fc
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jul 26 19:32:43 2025 +0200

    checkpatch: enable check for switch/case alignment
    
    Now that the whole code is aligned with the coding style, enforce
    the check through checkpatch.
    
    Change-Id: Ie74ed98c5dfa61978d5551b60eb90acf746a3cc5
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9057
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/.checkpatch.conf b/.checkpatch.conf
index f432503e1..01be7a909 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -23,6 +23,5 @@
 --ignore PREFER_KERNEL_TYPES
 --ignore SPLIT_STRING
 --ignore SSCANF_TO_KSTRTO
---ignore SWITCH_CASE_INDENT_LEVEL
 --ignore TRACING_LOGGING
 --ignore VOLATILE

-----------------------------------------------------------------------

Summary of changes:
 .checkpatch.conf | 1 -
 1 file changed, 1 deletion(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1275-g18734bcf9

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  18734bcf953324f9f40b518bc973634bfd9f41cd (commit)
      from  ffdbdf6b03438a7c4474d98a60873a7b31e38880 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 18734bcf953324f9f40b518bc973634bfd9f41cd
Author: Tomas Vanek <va...@fb...>
Date:   Fri May 16 11:06:10 2025 +0800

    target/riscv: fix get mode filed for vsatp and hgatp
    
    Imported from
    https://github.com/riscv-collab/riscv-openocd/pull/1258
    developed by Mark Zhuang <mar...@sp...>
    
    Add the necessary get_filed and add a comment to indicate
    this section is for VU/VS mode
    
    Change-Id: I898bba6250258c5076a98eb95411fcabccc52b96
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9144
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Tested-by: jenkins

diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 3e587732e..7ad695c20 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -3034,6 +3034,8 @@ static int riscv_mmu(struct target *target, bool *enabled)
 	unsigned int xlen = riscv_xlen(target);
 
 	if (v_mode) {
+		/* In VU or VS mode, MMU is considered enabled when
+		 * either hgatp or vsatp mode is not OFF */
 		riscv_reg_t vsatp;
 		if (riscv_reg_get(target, &vsatp, GDB_REGNO_VSATP) != ERROR_OK) {
 			LOG_TARGET_ERROR(target, "Failed to read vsatp register; priv=0x%" PRIx64,
@@ -3041,7 +3043,7 @@ static int riscv_mmu(struct target *target, bool *enabled)
 			return ERROR_FAIL;
 		}
 		/* vsatp is identical to satp, so we can use the satp macros. */
-		if (RISCV_SATP_MODE(xlen) != SATP_MODE_OFF) {
+		if (get_field(vsatp, RISCV_SATP_MODE(xlen)) != SATP_MODE_OFF) {
 			LOG_TARGET_DEBUG(target, "VS-stage translation is enabled.");
 			*enabled = true;
 			return ERROR_OK;
@@ -3053,7 +3055,7 @@ static int riscv_mmu(struct target *target, bool *enabled)
 					priv);
 			return ERROR_FAIL;
 		}
-		if (RISCV_HGATP_MODE(xlen) != HGATP_MODE_OFF) {
+		if (get_field(hgatp, RISCV_HGATP_MODE(xlen)) != HGATP_MODE_OFF) {
 			LOG_TARGET_DEBUG(target, "G-stage address translation is enabled.");
 			*enabled = true;
 		} else {

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv.c | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1274-gffdbdf6b0

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  ffdbdf6b03438a7c4474d98a60873a7b31e38880 (commit)
      from  f5ce311103cac65a0d5000891d6ebebfe51e93ed (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit ffdbdf6b03438a7c4474d98a60873a7b31e38880
Author: Tomas Vanek <va...@fb...>
Date:   Thu May 15 16:32:19 2025 +0800

    target/riscv: fix address translation in hypervisor mode
    
    Imported from
    https://github.com/riscv-collab/riscv-openocd/pull/1258
    developed by zhefan.lv <zhe...@sp...>
    
    address translation don't need to care hstatus.HU
    
    Change-Id: I40a15ec17347dffaa6e663a637150dfb393471a0
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9143
    Tested-by: jenkins
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>

diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index ba5e5a791..3e587732e 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -3034,22 +3034,6 @@ static int riscv_mmu(struct target *target, bool *enabled)
 	unsigned int xlen = riscv_xlen(target);
 
 	if (v_mode) {
-		/* vsatp and hgatp registers are considered active for the
-		 * purposes of the address-translation algorithm unless the
-		 * effective privilege mode is U and hstatus.HU=0. */
-		if (effective_mode == PRV_U) {
-			riscv_reg_t hstatus;
-			if (riscv_reg_get(target, &hstatus, GDB_REGNO_HSTATUS) != ERROR_OK) {
-				LOG_TARGET_ERROR(target, "Failed to read hstatus register.");
-				return ERROR_FAIL;
-			}
-
-			if (get_field(hstatus, HSTATUS_HU) == 0)
-				/* In hypervisor mode regular satp translation
-				 * doesn't happen. */
-				return ERROR_OK;
-		}
-
 		riscv_reg_t vsatp;
 		if (riscv_reg_get(target, &vsatp, GDB_REGNO_VSATP) != ERROR_OK) {
 			LOG_TARGET_ERROR(target, "Failed to read vsatp register; priv=0x%" PRIx64,

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv.c | 16 ----------------
 1 file changed, 16 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1273-gf5ce31110

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  f5ce311103cac65a0d5000891d6ebebfe51e93ed (commit)
      from  3483756cba5038335654bee437b5f17b7e6b88fd (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit f5ce311103cac65a0d5000891d6ebebfe51e93ed
Author: Sriram Shanmuga <sri...@gm...>
Date:   Mon Jul 7 18:17:04 2025 +0300

    target/riscv: improve error messaging in case `sbasize` is zero
    
    Imported from
    https://github.com/riscv-collab/riscv-openocd/pull/1274
    
    From: Sriram Shanmuga <sri...@gm...>
    
    RISC-V Debug Specification v1.0 [3.14.22. System Bus Access Control and
    Status (`sbcs`, at 0x38)] states in `sbasize` field description:
    > Width of system bus addresses in bits. (0 indicates there is no bus
    access support.)
    
    Before the patch, the error message did not include the information
    about `sbcs.sbasize` being zero wich made it quite undescriptive:
    ```
    [riscv.cpu] Turning off memory sampling because it failed.
    
    ```
    
    Fixes #1270
    
    Change-Id: I5402dd57dc9a81f65ee4c67d24e11c366006427c
    Signed-off-by: Sriram Shanmuga <sri...@gm...>
    Signed-off-by: Evgeniy Naydanov <evg...@sy...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9142
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 3308f40b9..370a15607 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -2610,8 +2610,8 @@ static int sample_memory_bus_v1(struct target *target,
 {
 	RISCV013_INFO(info);
 	unsigned int sbasize = get_field(info->sbcs, DM_SBCS_SBASIZE);
-	if (sbasize > 64) {
-		LOG_TARGET_ERROR(target, "Memory sampling is only implemented for sbasize <= 64.");
+	if (sbasize == 0 || sbasize > 64) {
+		LOG_TARGET_ERROR(target, "Memory sampling is only implemented for non-zero sbasize <= 64.");
 		return ERROR_NOT_IMPLEMENTED;
 	}
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv-013.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1272-g3483756cb

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  3483756cba5038335654bee437b5f17b7e6b88fd (commit)
      from  4447fa4c987b03372320f13e576dfc2dcb4846ef (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 3483756cba5038335654bee437b5f17b7e6b88fd
Author: Tomas Vanek <va...@fb...>
Date:   Thu May 15 14:58:07 2025 +0800

    target/riscv: check nextdm address in abits range
    
    Imported from
    https://github.com/riscv-collab/riscv-openocd/pull/1257
    developed by Mark Zhuang <mar...@sp...>
    
    When abits not correctly configured, we hope to detect it
    as soon as possible.
    
    Change-Id: I0b7b170c39761fb531dda0747f88ace3f39ae03b
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9141
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Tested-by: jenkins

diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index d2afdba2d..3308f40b9 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -538,6 +538,7 @@ static bool check_dbgbase_exists(struct target *target)
 {
 	uint32_t next_dm = 0;
 	unsigned int count = 1;
+	riscv013_info_t *info = get_info(target);
 
 	LOG_TARGET_DEBUG(target, "Searching for DM with DMI base address (dbgbase) = 0x%x", target->dbgbase);
 	while (1) {
@@ -552,6 +553,12 @@ static bool check_dbgbase_exists(struct target *target)
 			LOG_TARGET_ERROR(target, "Reached the end of DM chain (detected %u DMs in total).", count);
 			break;
 		}
+		if (next_dm >> info->abits) {
+			LOG_TARGET_ERROR(target, "The address of the next Debug Module does not fit into %u bits, "
+					"which is the width of the DMI bus address. This is a HW bug",
+					info->abits);
+			break;
+		}
 		/* Safety: Avoid looping forever in case of buggy nextdm values in the hardware. */
 		if (count++ > RISCV_MAX_DMS) {
 			LOG_TARGET_ERROR(target, "Supporting no more than %d DMs on a DMI bus. Aborting", RISCV_MAX_DMS);

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv-013.c | 7 +++++++
 1 file changed, 7 insertions(+)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1271-g4447fa4c9

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  4447fa4c987b03372320f13e576dfc2dcb4846ef (commit)
      from  31b26601521e14bdf5e4997379a473d4f7611e02 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 4447fa4c987b03372320f13e576dfc2dcb4846ef
Author: Tim Newsome <ti...@si...>
Date:   Thu Sep 14 13:04:39 2023 -0700

    gdb_server,rtos: Differentiate rtos_get_gdb_reg failing and not implemented
    
    If it fails, then pass that failure on. If it's simply not implemented,
    then we can fall through and try target_get_gdb_reg_list_noread().
    
    This difference matters when the target representing the current
    hwthread is unavailable, but the target that is linked to the gdb
    connection is available. In that case we want the operation to return an
    error to gdb, instead of reading the register from the target that is
    available.
    
    Change-Id: I9c84ca556f818c5580e25ab349a34a226fcf0f43
    Signed-off-by: Tim Newsome <ti...@si...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9138
    Tested-by: jenkins
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 6a5d7b32c..163d882a4 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -600,7 +600,7 @@ int rtos_get_gdb_reg(struct connection *connection, int reg_num)
 
 		free(reg_list);
 	}
-	return ERROR_FAIL;
+	return ERROR_NOT_IMPLEMENTED;
 }
 
 /** Return a list of general registers. */
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 080e3360a..d18d48a3a 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1411,8 +1411,13 @@ static int gdb_get_register_packet(struct connection *connection,
 	LOG_DEBUG("-");
 #endif
 
-	if ((target->rtos) && (rtos_get_gdb_reg(connection, reg_num) == ERROR_OK))
-		return ERROR_OK;
+	if (target->rtos) {
+		retval = rtos_get_gdb_reg(connection, reg_num);
+		if (retval == ERROR_OK)
+			return ERROR_OK;
+		if (retval != ERROR_NOT_IMPLEMENTED)
+			return gdb_error(connection, retval);
+	}
 
 	retval = target_get_gdb_reg_list_noread(target, &reg_list, &reg_list_size,
 			REG_CLASS_ALL);

-----------------------------------------------------------------------

Summary of changes:
 src/rtos/rtos.c         | 2 +-
 src/server/gdb_server.c | 9 +++++++--
 2 files changed, 8 insertions(+), 3 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1270-g31b266015

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  31b26601521e14bdf5e4997379a473d4f7611e02 (commit)
      from  2913dff98ae81d50a1baa9af944080f02ad91708 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 31b26601521e14bdf5e4997379a473d4f7611e02
Author: Tomas Vanek <va...@fb...>
Date:   Thu Sep 18 08:04:44 2025 +0200

    rtos: introduce rtos_put_gdb_reg()
    
    and use it in rtos_get_gdb_reg() after get_thread_reg_value()
    to allow passing long register value without hackish use of
    struct rtos_reg.
    
    Fixes: 9123: rtos: Dynamically allocate memory for RTOS registers
    Link: https://review.openocd.org/c/openocd/+/9123
    Change-Id: I30a51dcca60d67a0f01aa957c9c6076f266b5758
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9135
    Tested-by: jenkins
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>

diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 45366268d..6a5d7b32c 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -503,6 +503,26 @@ int rtos_thread_packet(struct connection *connection, char const *packet, int pa
 	return GDB_THREAD_PACKET_NOT_CONSUMED;
 }
 
+static int rtos_put_gdb_reg(struct connection *connection,
+		uint8_t *reg_value, unsigned int reg_size)
+{
+	unsigned int reg_bytes = DIV_ROUND_UP(reg_size, 8);
+	unsigned int num_bytes = reg_bytes * 2 + 1; // for '\0'
+
+	char *hex = malloc(num_bytes);
+	if (!hex) {
+		LOG_ERROR("Out of memory");
+		return ERROR_FAIL;
+	}
+
+	size_t len = hexify(hex, reg_value, reg_bytes, num_bytes);
+
+	gdb_put_packet(connection, hex, len);
+	free(hex);
+
+	return ERROR_OK;
+}
+
 static int rtos_put_gdb_reg_list(struct connection *connection,
 		struct rtos_reg *reg_list, int num_regs)
 {
@@ -555,32 +575,19 @@ int rtos_get_gdb_reg(struct connection *connection, int reg_num)
 				return retval;
 			}
 
-			/* Create a reg_list with one register that can
-			 * accommodate the full size of the one we just got the
-			 * value for. To do that we allocate extra space off the
-			 * end of the struct, relying on the fact that
-			 * rtos_reg.value is the last element in the struct. */
-			reg_list = calloc(1, sizeof(*reg_list) + DIV_ROUND_UP(reg_size, 8));
-			if (!reg_list) {
-				free(reg_value);
-				LOG_ERROR("Failed to allocated reg_list for %d-byte register.",
-					  reg_size);
-				return ERROR_FAIL;
-			}
-			reg_list[0].number = reg_num;
-			reg_list[0].size = reg_size;
-			memcpy(&reg_list[0].value, reg_value, DIV_ROUND_UP(reg_size, 8));
+			retval = rtos_put_gdb_reg(connection, reg_value, reg_size);
+
 			free(reg_value);
-			num_regs = 1;
-		} else {
-			retval = target->rtos->type->get_thread_reg_list(target->rtos,
+			return retval;
+		}
+
+		retval = target->rtos->type->get_thread_reg_list(target->rtos,
 					current_threadid,
 					&reg_list,
 					&num_regs);
-			if (retval != ERROR_OK) {
-				LOG_ERROR("RTOS: failed to get register list");
-				return retval;
-			}
+		if (retval != ERROR_OK) {
+			LOG_ERROR("RTOS: failed to get register list");
+			return retval;
 		}
 
 		for (int i = 0; i < num_regs; ++i) {
diff --git a/src/rtos/rtos.h b/src/rtos/rtos.h
index 3077acc9d..ca6d7518d 100644
--- a/src/rtos/rtos.h
+++ b/src/rtos/rtos.h
@@ -53,8 +53,6 @@ struct rtos_reg {
 	uint32_t number;
 	uint32_t size;
 	uint8_t value[16];
-	/* WARNING: rtos_get_gdb_reg() relies on the fact that value is the last
-	 * element of this struct. Any new fields should be added *before* value. */
 };
 
 struct rtos_type {

-----------------------------------------------------------------------

Summary of changes:
 src/rtos/rtos.c | 51 +++++++++++++++++++++++++++++----------------------
 src/rtos/rtos.h |  2 --
 2 files changed, 29 insertions(+), 24 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1269-g2913dff98

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  2913dff98ae81d50a1baa9af944080f02ad91708 (commit)
      from  ab8fb1d9812767363643d98c8691d97cecf26fbc (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 2913dff98ae81d50a1baa9af944080f02ad91708
Author: Tomas Vanek <va...@fb...>
Date:   Wed Sep 17 15:50:32 2025 +0200

    doc: riscv: minor fixes in openocd.texi
    
    'smp' and 'smp_gdb' command do not have 'riscv' prefix.
    
    Document 'riscv use_bscan_tunnel' and 'riscv set_bscan_tunnel_ir'
    as {Config Command}
    
    Change-Id: I7b57613c9fedcccd6d6b1438d7fc2d28ea34ba65
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9133
    Tested-by: jenkins
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 5899ae936..54cf21a29 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11800,19 +11800,19 @@ When utilizing version 0.11 of the RISC-V Debug Specification,
 and DBUS registers, respectively.
 @end deffn
 
-@deffn {Command} {riscv smp} [on|off]
+@deffn {Command} {smp} [on|off]
 Display, enable or disable SMP handling mode. This command is needed only if
 user wants to temporary @b{disable} SMP handling for an existing SMP group
 (see @code{aarch64 smp} for additional information). To define an SMP
 group the command @code{target smp} should be used.
 @end deffn
 
-@deffn {Command} {riscv smp_gdb} [core_id]
+@deffn {Command} {smp_gdb} [core_id]
 Display/set the current core displayed in GDB. This is needed only if
-@code{riscv smp} was used.
+@code{smp} was used.
 @end deffn
 
-@deffn {Command} {riscv use_bscan_tunnel} width [type]
+@deffn {Config Command} {riscv use_bscan_tunnel} width [type]
 Enable or disable use of a BSCAN tunnel to reach the Debug Module. Supply the
 @var{width} of the DM transport TAP's instruction register to enable. The
 @var{width} should fit into 7 bits. Supply a value of 0 to disable.
@@ -11836,7 +11836,7 @@ tunneled DR scan consists of:
 @end enumerate
 @end deffn
 
-@deffn {Command} {riscv set_bscan_tunnel_ir} value
+@deffn {Config Command} {riscv set_bscan_tunnel_ir} value
 Allows the use_bscan_tunnel feature to target non Xilinx device by
 specifying the JTAG TAP IR used to access the bscan tunnel.
 @end deffn

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1268-gab8fb1d98

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  ab8fb1d9812767363643d98c8691d97cecf26fbc (commit)
      from  b4fb5a7baa78da869f68e5ad5aa885ae1f99daab (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit ab8fb1d9812767363643d98c8691d97cecf26fbc
Author: Tomas Vanek <va...@fb...>
Date:   Wed Sep 17 15:10:03 2025 +0200

    target/riscv: fix checking of number of parameters
    
    in command 'riscv resume_order' to prevent segfault
    on issuing the command without a parameter.
    
    Change-Id: I5d7f4f92c2fa8e9effaba2c000d111e491b7b64f
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9132
    Tested-by: jenkins

diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 31af2c33e..ba5e5a791 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -4825,7 +4825,7 @@ COMMAND_HANDLER(riscv_set_ir)
 
 COMMAND_HANDLER(riscv_resume_order)
 {
-	if (CMD_ARGC > 1)
+	if (CMD_ARGC != 1)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	if (!strcmp(CMD_ARGV[0], "normal")) {

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1267-gb4fb5a7ba

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  b4fb5a7baa78da869f68e5ad5aa885ae1f99daab (commit)
      from  a0eac82708eb6eddb0070aee6769975625c08dd9 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit b4fb5a7baa78da869f68e5ad5aa885ae1f99daab
Author: Tomas Vanek <va...@fb...>
Date:   Mon Sep 15 09:41:36 2025 +0200

    doc: import document changes relevant to riscv code update
    
    Checkpatch-ignore: UNKNOWN_COMMIT_ID, GIT_COMMIT_ID
    
    Based on riscv-collab OpenOCD fork commit 517c40ba8d2d ("Merge
    up to afbd01b0a46f3a81fe6076c002ad66973dcfb64c from upstream")
    
    See 8893: target: riscv: Sync with the RISC-V fork
    for list of original authors.
    
    Link: https://review.openocd.org/c/openocd/+/8893
    Change-Id: I43a71df0e6ac751fc87ba4671ebc892d397bcf3e
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9130
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index e69a8f6b0..5899ae936 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -11573,11 +11573,9 @@ an error if current CPU does not support DSP.
 @section RISC-V Architecture
 
 @uref{http://riscv.org/, RISC-V} is a free and open ISA. OpenOCD supports JTAG
-debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 32
-harts. (It's possible to increase this limit to 1024 by changing
-RISCV_MAX_HARTS in riscv.h.) OpenOCD primarily supports 0.13 of the RISC-V
-Debug Specification, but there is also support for legacy targets that
-implement version 0.11.
+debug of RV32 and RV64 cores in heterogeneous multicore systems of up to 2^20
+harts. OpenOCD primarily supports 0.13 of the RISC-V Debug Specification,
+but there is also support for legacy targets that implement version 0.11.
 
 @subsection RISC-V Terminology
 
@@ -11622,8 +11620,34 @@ follows:
 </feature>
 @end example
 
+@subsection RISC-V @code{$target_name configure} options
+@itemize
+@item @code{-ebreak} [@option{m}|@option{s}|@option{u}|@option{vs}|@option{vu}]
+@option{exception}|@option{halt} -- sets the desired behavior of @code{ebreak}
+instruction on the target. Defaults to @option{halt} in all execution modes.
+
+@itemize
+@item The last argument specifies which action should be taken when a hart
+executes a @code{ebreak}.
+
+@item The first argument specifies in which execution mode the @code{ebreak}
+behavior should change. If this option is omitted the configuration affects
+all execution modes.
+
+@item @code{cget} returns a TCL @code{dict} of execution mode - @code{ebreak}
+action pairs.
+@end itemize
+@end itemize
+
 @subsection RISC-V Debug Configuration Commands
 
+@deffn {Command} {riscv dump_sample_buf} [base64]
+Dump and clear the contents of the sample buffer. Which samples are collected
+is configured with @code{riscv memory_sample}. If the optional base64
+argument is passed, the raw buffer is dumped in base64 format, so that
+external tools can gather the data efficiently.
+@end deffn
+
 @deffn {Config Command} {riscv expose_csrs} n[-m|=name] [...]
 Configure which CSRs to expose in addition to the standard ones. The CSRs to expose
 can be specified as individual register numbers or register ranges (inclusive). For the
@@ -11638,13 +11662,13 @@ CSRs.
 
 @example
 # Expose a single RISC-V CSR number 128 under the name "csr128":
-$_TARGETNAME expose_csrs 128
+riscv expose_csrs 128
 
 # Expose multiple RISC-V CSRs 128..132 under names "csr128" through "csr132":
-$_TARGETNAME expose_csrs 128-132
+riscv expose_csrs 128-132
 
 # Expose a single RISC-V CSR number 1996 under custom name "csr_myregister":
-$_TARGETNAME expose_csrs 1996=myregister
+riscv expose_csrs 1996=myregister
 @end example
 @end deffn
 
@@ -11672,8 +11696,43 @@ $_TARGETNAME expose_custom 32=myregister
 @end example
 @end deffn
 
+@deffn {Config Command} {riscv hide_csrs} n[-m] [,n1[-m1]] [...]
+The RISC-V Specification defines many CSRs, and we may want to avoid showing
+each CSR to the user, as they may not be relevant to the task at hand. For
+example, we may choose not to show trigger or PMU registers for simple
+debugging scenarios. This command allows to mark individual registers or
+register ranges (inclusive) as "hidden". Such hidden registers won't be
+displayed in GDB or @code{reg} command output.
+
+@example
+
+# Hide range of RISC-V CSRs
+# CSR_TSELECT - 1952 and CSR_TDATA1 - 1953
+$_TARGETNAME riscv hide_csrs 1952-1953
+
+@end example
+@end deffn
+
+@deffn {Command} {riscv memory_sample} bucket address|clear [size=4]
+Configure OpenOCD to frequently read size bytes at the given addresses.
+Execute the command with no arguments to see the current configuration. Use
+clear to stop using a given bucket.
+
+OpenOCD will allocate a 1MB sample buffer, and when it fills up no more
+samples will be collected until it is emptied with @code{riscv
+dump_sample_buf}.
+@end deffn
+
+@deffn {Command} {riscv repeat_read} count address [size=4]
+Quickly read count words of the given size from address. This can be useful
+to read out a buffer that's memory-mapped to be accessed through a single
+address, or to sample a changing value in a memory-mapped device.
+@end deffn
+
 @deffn {Command} {riscv info}
-Displays some information OpenOCD detected about the target.
+Displays some information OpenOCD detected about the target. Output's format
+allows to use it directly with TCL's `array set` function. In case obtaining an
+info point failed, the corresponding value is displayed as "unavailable".
 @end deffn
 
 @deffn {Command} {riscv reset_delays} [wait]
@@ -11687,11 +11746,6 @@ Set the wall-clock timeout (in seconds) for individual commands. The default
 should work fine for all but the slowest targets (eg. simulators).
 @end deffn
 
-@deffn {Command} {riscv set_reset_timeout_sec} [seconds]
-Set the maximum time to wait for a hart to come out of reset after reset is
-deasserted.
-@end deffn
-
 @deffn {Command} {riscv set_mem_access} method1 [method2] [method3]
 Specify which RISC-V memory access method(s) shall be used, and in which order
 of priority. At least one method must be specified.
@@ -11710,16 +11764,18 @@ This command can be used to change the memory access methods if the default
 behavior is not suitable for a particular target.
 @end deffn
 
-@deffn {Command} {riscv set_enable_virtual} on|off
-When on, memory accesses are performed on physical or virtual memory depending
-on the current system configuration. When off (default), all memory accessses are performed
-on physical memory.
-@end deffn
-
-@deffn {Command} {riscv set_enable_virt2phys} on|off
-When on (default), memory accesses are performed on physical or virtual memory
-depending on the current satp configuration. When off, all memory accessses are
-performed on physical memory.
+@deffn {Command} {riscv virt2phys_mode} [@option{hw}|@option{sw}|@option{off}]
+Configure how OpenOCD translates virtual addresses to physical:
+@itemize @bullet
+@item @option{sw} - OpenOCD translates virtual addresses explicitly by
+traversing the page table entries (by performing physical memory accesses to
+read the respective entries). This is the default mode.
+@item @option{hw} - Virtual addresses are translated implicitly by hardware.
+(Virtual memory access will fail with an error if the hardware doesn't
+support the necessary functionality.)
+@item @option{off} - Virtual addresses are not translated (identity mapping is assumed).
+@end itemize
+Returns current translation mode if called without arguments.
 @end deffn
 
 @deffn {Command} {riscv resume_order} normal|reversed
@@ -11756,10 +11812,15 @@ Display/set the current core displayed in GDB. This is needed only if
 @code{riscv smp} was used.
 @end deffn
 
-@deffn {Command} {riscv use_bscan_tunnel} value
+@deffn {Command} {riscv use_bscan_tunnel} width [type]
 Enable or disable use of a BSCAN tunnel to reach the Debug Module. Supply the
-width of the DM transport TAP's instruction register to enable. Supply a
-value of 0 to disable.
+@var{width} of the DM transport TAP's instruction register to enable. The
+@var{width} should fit into 7 bits. Supply a value of 0 to disable.
+Pass a second argument (optional) to indicate Bscan Tunnel Type:
+@enumerate
+@item 0:(default) NESTED_TAP
+@item 1: DATA_REGISTER
+@end enumerate
 
 This BSCAN tunnel interface is specific to SiFive IP. Anybody may implement
 it, but currently there is no good documentation on it. In a nutshell, this
@@ -11775,19 +11836,43 @@ tunneled DR scan consists of:
 @end enumerate
 @end deffn
 
-@deffn {Command} {riscv set_ebreakm} on|off
-Control dcsr.ebreakm. When on (default), M-mode ebreak instructions trap to
-OpenOCD. When off, they generate a breakpoint exception handled internally.
+@deffn {Command} {riscv set_bscan_tunnel_ir} value
+Allows the use_bscan_tunnel feature to target non Xilinx device by
+specifying the JTAG TAP IR used to access the bscan tunnel.
 @end deffn
 
-@deffn {Command} {riscv set_ebreaks} on|off
-Control dcsr.ebreaks. When on (default), S-mode ebreak instructions trap to
-OpenOCD. When off, they generate a breakpoint exception handled internally.
+@deffn {Command} {riscv set_maskisr} [@option{off}|@option{steponly}]
+Selects whether interrupts will be disabled when single stepping. The default configuration is @option{off}.
+This feature is only useful on hardware that always steps into interrupts and doesn't support dcsr.stepie=0.
+Keep in mind, disabling the option does not guarantee that single stepping will go into interrupt handlers.
+To make that happen, dcsr.stepie would have to be written to 1 as well.
 @end deffn
 
-@deffn {Command} {riscv set_ebreaku} on|off
-Control dcsr.ebreaku. When on (default), U-mode ebreak instructions trap to
-OpenOCD. When off, they generate a breakpoint exception handled internally.
+The commands below can be used to prevent OpenOCD from using certain RISC-V trigger features.
+For example in cases when there are known issues in the target hardware.
+
+@deffn {Command} {riscv set_enable_trigger_feature} [(@option{eq}|@option{napot}|@option{ge_lt}|@option{all}) (@option{wp}|@option{none})]
+Control which RISC-V trigger features can be used by OpenOCD placing watchpoints.
+All trigger features are allowed by default. Only new watchpoints, inserted after this command,
+are affected (watchpoints that were already placed before are not changed).
+
+The first argument selects one of the configurable RISC-V trigger features:
+
+@itemize @minus
+@item @option{eq}: Equality match trigger
+@item @option{napot}: NAPOT trigger
+@item @option{ge_lt}: Chained pair of `greater-equal` and `less-than` triggers
+@item @option{all}: All trigger features which were described above
+@end itemize
+
+The second argument configures how OpenOCD should use the selected trigger feature:
+
+@itemize @minus
+@item @option{wp}: Enable this trigger feature for watchpoints - allow OpenOCD to use it. (Default.)
+@item @option{none}: Disable the use of this trigger feature. OpenOCD will not attempt to use it.
+@end itemize
+
+With no parameters, prints current trigger features configuration.
 @end deffn
 
 @subsection RISC-V Authentication Commands
@@ -11800,25 +11885,156 @@ set challenge [riscv authdata_read]
 riscv authdata_write [expr @{$challenge + 1@}]
 @end example
 
-@deffn {Command} {riscv authdata_read}
-Return the 32-bit value read from authdata.
+@deffn {Command} {riscv authdata_read} [index=0]
+Return the 32-bit value read from authdata or authdata0 (index=0), or
+authdata1 (index=1).
 @end deffn
 
-@deffn {Command} {riscv authdata_write} value
-Write the 32-bit value to authdata.
+@deffn {Command} {riscv authdata_write} [index=0] value
+Write the 32-bit value to authdata or authdata0 (index=0), or authdata1
+(index=1).
 @end deffn
 
 @subsection RISC-V DMI Commands
 
-The following commands allow direct access to the Debug Module Interface, which
-can be used to interact with custom debug features.
+The following commands allow for direct low-level access to the registers
+of the Debug Module (DM). They can be useful to access custom features in the DM.
+
+@deffn {Command} {riscv dm_read} reg_address
+Perform a 32-bit read from the register indicated by reg_address from the DM of the
+current target.
+@end deffn
+
+@deffn {Command} {riscv dm_write} reg_address value
+Write the 32-bit value to the register indicated by reg_address from the DM of the
+current target.
+@end deffn
+
+The following commands allow for direct low-level access to the Debug Module
+Interface (DMI). They can be useful to access any device that resides on the DMI.
 
 @deffn {Command} {riscv dmi_read} address
-Perform a 32-bit DMI read at address, returning the value.
+Perform a 32-bit read from the given DMI address, returning the value.
 @end deffn
 
 @deffn {Command} {riscv dmi_write} address value
-Perform a 32-bit DMI write of value at address.
+Perform a 32-bit write to the given DMI address.
+@end deffn
+
+@subsection RISC-V Trigger Commands
+
+The RISC-V Debug Specification defines several optional trigger types that don't
+map cleanly onto OpenOCD's notion of hardware breakpoints. For the types that
+the target supports, these commands let you
+set those triggers directly. (It's also possible to do so by writing the
+appropriate CSRs.)
+
+@deffn {Command} {riscv etrigger set} [@option{m}] [@option{s}] [@option{u}] [@option{vs}] [@option{vu}] exception_codes
+Set an exception trigger (type 5) on the current target, which halts the target when it
+fires.  @option{m}, @option{s}, @option{u}, @option{vs}, and @option{vu} control
+which execution modes the trigger fires in. @var{exception_codes} is a bit
+field, where each bit corresponds to an exception code in mcause (defined in the
+RISC-V Privileged Spec). The etrigger will fire on the exceptions whose bits are
+set in @var{exception_codes}.
+
+For details on this trigger type, see the RISC-V Debug Specification.
+@end deffn
+
+@deffn {Command} {riscv etrigger clear}
+Clear the type 5 trigger that was set using @command{riscv etrigger set}.
+@end deffn
+
+@deffn {Command} {riscv icount set} [@option{m}] [@option{s}] [@option{u}] [@option{vs}] [@option{vu}] [@option{pending}] count
+Set an instruction count
+trigger (type 3) on the current target, which halts the target when it fires.
+@option{m}, @option{s}, @option{u}, @option{vs}, and @option{vu} control which
+execution modes the trigger fires in. If [@option{pending}] is passed then the
+pending bit is set, which is unlikely to be useful unless you're debugging the
+hardware implementation of this trigger.
+@var{count} sets the number of instructions to execute before the trigger is
+taken.
+
+For details on this trigger type, see the RISC-V Debug Specification.
+@end deffn
+
+@deffn {Command} {riscv icount clear}
+Clear the type 3 trigger that was set using @command{riscv icount set}.
+@end deffn
+
+@deffn {Command} {riscv itrigger set} [@option{m}] [@option{s}] [@option{u}] [@option{vs}] [@option{vu}] [@option{nmi}] mie_bits
+Set an interrupt trigger (type 4) on the current target, which halts the target when it
+fires.  @option{m}, @option{s}, @option{u}, @option{vs}, and @option{vu} control
+which execution modes the trigger fires in.  If [@option{nmi}] is passed then
+the trigger will fire on non-maskable interrupts in those modes. @var{mie_bits}
+controls which interrupts the trigger fires on, using the same bit assignments
+as in the mie CSR (defined in the RISC-V Privileged Spec).
+
+For details on this trigger type, see the RISC-V Debug Specification.
+@end deffn
+
+@deffn {Command} {riscv reserve_trigger} [index @option{on|off}]
+Manages the set of reserved triggers. Reserving a trigger results in OpenOCD
+not using it internally (e.g. skipping it when setting a watchpoint or a
+hardware breakpoint), so that the user or the application has unfettered
+control over the trigger. By default there are no reserved triggers.
+
+@enumerate
+@item @var{index} specifies the index of a trigger to reserve or free up.
+@item The second argument specifies whether the trigger should be reserved
+(@var{on}) or a prior reservation cancelled (@var{off}).
+@item If called without parameters, returns indices of reserved triggers.
+@end enumerate
+
+@end deffn
+
+@deffn {Command} {riscv itrigger clear}
+Clear the type 4 trigger that was set using @command{riscv itrigger set}.
+@end deffn
+
+@subsection RISC-V Program Buffer Commands
+
+Program Buffer is an optional feature of RISC-V targets - it is a mechanism that debuggers
+can use to execute sequences of arbitrary instructions (small programs) on the target.
+For details on the Program Buffer, please refer to the RISC-V Debug Specification.
+
+@deffn {Command} {riscv exec_progbuf} inst1 [inst2 [... inst16]]
+Execute the given sequence of instructions on the target using the Program Buffer.
+The command can only be used on halted targets.
+
+The instructions @var{inst1} .. @var{inst16} shall be specified in their binary form
+(as 32-bit integers). In case a pair of compressed (16-bit) instructions is used,
+the first instruction should be placed to the lower 16-bits of the 32-bit value.
+The terminating @var{ebreak} instruction needs not be specified - it is added
+automatically if needed.
+@end deffn
+
+Examples:
+
+@example
+# Execute 32-bit instructions "fence rw,rw" (0x0330000f)
+# and "fence.i" (0x0000100f) using the Program Buffer,
+# in this order:
+
+riscv exec_progbuf 0x0330000f 0x0000100f
+
+# Execute 16-bit instructions "c.addi s0,s0,1" (0x0405)
+# and "c.add s1,s1,s0" (0x94a2) using the Program Buffer,
+# in this order:
+
+riscv exec_progbuf 0x94a20405
+@end example
+
+@deffn {Command} {riscv autofence} [on|off]
+When on (default), OpenOCD will automatically execute RISC-V fence instructions
+(@var{fence.i} and @var{fence rw, rw}) in these cases:
+@itemize @bullet
+@item before step or resume,
+@item before memory read via the Program Buffer,
+@item after memory write via the Program Buffer.
+@end itemize
+When off, users need to take care of memory coherency themselves, for example
+using the @var{riscv exec_progbuf} command to execute fences or CMO instructions
+(RISC-V Cache Management Operations).
 @end deffn
 
 @section ARC Architecture

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi | 304 +++++++++++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 260 insertions(+), 44 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1266-ga0eac8270

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  a0eac82708eb6eddb0070aee6769975625c08dd9 (commit)
      from  f354d259ffe613ed2e5c4369b8c25727baab32c5 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit a0eac82708eb6eddb0070aee6769975625c08dd9
Author: Tomas Vanek <va...@fb...>
Date:   Sat Sep 13 23:01:33 2025 +0200

    target, flash: utility for riscv repeat_read command
    
    Imported non-riscv part from
    https://github.com/riscv-collab/riscv-openocd/pull/510
    developed by Tim Newsome <ti...@si...>
    
    Introduce target_handle_md_output() parameter include_address.
    All callers set it true but riscv repeat_read command.
    
    Change-Id: I67b5aad15a33ad149d4047998b22407cb60098fd
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9127
    Tested-by: jenkins
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>

diff --git a/src/flash/nor/tcl.c b/src/flash/nor/tcl.c
index 6161f5d26..517d9aca1 100644
--- a/src/flash/nor/tcl.c
+++ b/src/flash/nor/tcl.c
@@ -720,7 +720,8 @@ COMMAND_HANDLER(handle_flash_md_command)
 
 	retval = flash_driver_read(bank, buffer, offset, sizebytes);
 	if (retval == ERROR_OK)
-		target_handle_md_output(CMD, target, address, wordsize, count, buffer);
+		target_handle_md_output(CMD, target, address, wordsize, count,
+				buffer, true);
 
 	free(buffer);
 
diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index d79d54282..a989c331b 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -2143,7 +2143,8 @@ COMMAND_HANDLER(dsp563xx_mem_command)
 		err = dsp563xx_read_memory(target, mem_type, address, sizeof(uint32_t),
 				count, buffer);
 		if (err == ERROR_OK)
-			target_handle_md_output(CMD, target, address, sizeof(uint32_t), count, buffer);
+			target_handle_md_output(CMD, target, address, sizeof(uint32_t),
+				count, buffer, true);
 
 	} else {
 		b = buffer;
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 92daffa49..31af2c33e 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -5231,7 +5231,7 @@ COMMAND_HANDLER(handle_repeat_read)
 	};
 	int result = r->access_memory(target, args);
 	if (result == ERROR_OK)
-		target_handle_md_output(cmd, target, address, size, count, buffer);
+		target_handle_md_output(cmd, target, address, size, count, buffer, false);
 	free(buffer);
 	return result;
 }
diff --git a/src/target/target.c b/src/target/target.c
index bdf0ff244..3d807ba35 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -3349,7 +3349,7 @@ COMMAND_HANDLER(handle_step_command)
 
 void target_handle_md_output(struct command_invocation *cmd,
 		struct target *target, target_addr_t address, unsigned int size,
-		unsigned int count, const uint8_t *buffer)
+		unsigned int count, const uint8_t *buffer, bool include_address)
 {
 	const unsigned int line_bytecnt = 32;
 	unsigned int line_modulo = line_bytecnt / size;
@@ -3378,7 +3378,7 @@ void target_handle_md_output(struct command_invocation *cmd,
 	}
 
 	for (unsigned int i = 0; i < count; i++) {
-		if (i % line_modulo == 0) {
+		if (include_address && i % line_modulo == 0) {
 			output_len += snprintf(output + output_len,
 					sizeof(output) - output_len,
 					TARGET_ADDR_FMT ": ",
@@ -3462,7 +3462,7 @@ COMMAND_HANDLER(handle_md_command)
 	struct target *target = get_current_target(CMD_CTX);
 	int retval = fn(target, address, size, count, buffer);
 	if (retval == ERROR_OK)
-		target_handle_md_output(CMD, target, address, size, count, buffer);
+		target_handle_md_output(CMD, target, address, size, count, buffer, true);
 
 	free(buffer);
 
diff --git a/src/target/target.h b/src/target/target.h
index b850b49cf..94e6aa335 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -775,7 +775,7 @@ void target_handle_event(struct target *t, enum target_event e);
 
 void target_handle_md_output(struct command_invocation *cmd,
 	struct target *target, target_addr_t address, unsigned int size,
-	unsigned int count, const uint8_t *buffer);
+	unsigned int count, const uint8_t *buffer, bool include_address);
 
 int target_profiling_default(struct target *target, uint32_t *samples, uint32_t
 		max_num_samples, uint32_t *num_samples, uint32_t seconds);

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/tcl.c      | 3 ++-
 src/target/dsp563xx.c    | 3 ++-
 src/target/riscv/riscv.c | 2 +-
 src/target/target.c      | 6 +++---
 src/target/target.h      | 2 +-
 5 files changed, 9 insertions(+), 7 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1265-gf354d259f

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  f354d259ffe613ed2e5c4369b8c25727baab32c5 (commit)
      from  6d764f5b099b40151de4f02e39231533cf14eae5 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit f354d259ffe613ed2e5c4369b8c25727baab32c5
Author: Tomas Vanek <va...@fb...>
Date:   Tue Oct 14 15:29:55 2025 +0200

    target/riscv: return ERROR_TARGET_NOT_HALTED
    
    instead of ERROR_FAIL where appropriate.
    
    Change-Id: I1881c0c6c437355007c3844556489162666023dc
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9171
    Tested-by: jenkins
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>

diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 9da9684e4..d2afdba2d 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -2323,7 +2323,7 @@ static int prep_for_vector_access(struct target *target,
 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target,
 				"Unable to access vector register: target not halted");
-		return ERROR_FAIL;
+		return ERROR_TARGET_NOT_HALTED;
 	}
 	if (prep_for_register_access(target, orig_mstatus, GDB_REGNO_VL) != ERROR_OK)
 		return ERROR_FAIL;
@@ -5476,7 +5476,7 @@ static int riscv013_step_or_resume_current_hart(struct target *target,
 {
 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target, "Hart is not halted!");
-		return ERROR_FAIL;
+		return ERROR_TARGET_NOT_HALTED;
 	}
 
 	LOG_TARGET_DEBUG(target, "resuming (operation=%s)",
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 7ef875f80..92daffa49 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -5425,7 +5425,7 @@ COMMAND_HANDLER(riscv_exec_progbuf)
 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target, "exec_progbuf: Can't execute "
 				"program buffer, target not halted.");
-		return ERROR_FAIL;
+		return ERROR_TARGET_NOT_HALTED;
 	}
 
 	if (riscv_progbuf_size(target) == 0) {
@@ -6039,7 +6039,7 @@ static int riscv_step_rtos_hart(struct target *target)
 
 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target, "Hart isn't halted before single step!");
-		return ERROR_FAIL;
+		return ERROR_TARGET_NOT_HALTED;
 	}
 	r->on_step(target);
 	if (r->step_current_hart(target) != ERROR_OK)
@@ -6229,7 +6229,7 @@ int riscv_enumerate_triggers(struct target *target)
 
 	if (target->state != TARGET_HALTED) {
 		LOG_TARGET_ERROR(target, "Unable to enumerate triggers: target not halted.");
-		return ERROR_FAIL;
+		return ERROR_TARGET_NOT_HALTED;
 	}
 
 	riscv_reg_t orig_tselect;

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv-013.c | 4 ++--
 src/target/riscv/riscv.c     | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1264-g6d764f5b0

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  6d764f5b099b40151de4f02e39231533cf14eae5 (commit)
      from  612707761357b5ab69f552a9120d9cf92340c6cd (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 6d764f5b099b40151de4f02e39231533cf14eae5
Author: Tim Newsome <ti...@si...>
Date:   Tue Oct 5 10:03:53 2021 -0700

    rtos: Dynamically allocate memory for RTOS registers
    
    Imported from
    https://github.com/riscv-collab/riscv-openocd/pull/647
    
    FreeRTOS part of patch dropped as it depends on other
    riscv-collab specific changes.
    
    This makes things work on RISC-V cores with large vector registers
    (which can be up to kilobytes in size).
    
    Change-Id: Ie53cb43a88e2a475f695cd5c1e28605569926817
    Signed-off-by: Tim Newsome <ti...@si...>
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9123
    Tested-by: jenkins
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>

diff --git a/src/rtos/hwthread.c b/src/rtos/hwthread.c
index b2a45ade9..3f0041e0b 100644
--- a/src/rtos/hwthread.c
+++ b/src/rtos/hwthread.c
@@ -17,8 +17,8 @@
 static bool hwthread_detect_rtos(struct target *target);
 static int hwthread_create(struct target *target);
 static int hwthread_update_threads(struct rtos *rtos);
-static int hwthread_get_thread_reg(struct rtos *rtos, int64_t thread_id,
-		uint32_t reg_num, struct rtos_reg *rtos_reg);
+static int hwthread_get_thread_reg_value(struct rtos *rtos, int64_t thread_id,
+		uint32_t reg_num, uint32_t *size, uint8_t **value);
 static int hwthread_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 		struct rtos_reg **reg_list, int *num_regs);
 static int hwthread_get_symbol_list_to_lookup(struct symbol_table_elem *symbol_list[]);
@@ -53,7 +53,7 @@ const struct rtos_type hwthread_rtos = {
 	.create = hwthread_create,
 	.update_threads = hwthread_update_threads,
 	.get_thread_reg_list = hwthread_get_thread_reg_list,
-	.get_thread_reg = hwthread_get_thread_reg,
+	.get_thread_reg_value = hwthread_get_thread_reg_value,
 	.get_symbol_list_to_lookup = hwthread_get_symbol_list_to_lookup,
 	.smp_init = hwthread_smp_init,
 	.set_reg = hwthread_set_reg,
@@ -291,8 +291,8 @@ static int hwthread_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 	return ERROR_OK;
 }
 
-static int hwthread_get_thread_reg(struct rtos *rtos, int64_t thread_id,
-		uint32_t reg_num, struct rtos_reg *rtos_reg)
+static int hwthread_get_thread_reg_value(struct rtos *rtos, int64_t thread_id,
+		uint32_t reg_num, uint32_t *size, uint8_t **value)
 {
 	if (!rtos)
 		return ERROR_FAIL;
@@ -321,11 +321,14 @@ static int hwthread_get_thread_reg(struct rtos *rtos, int64_t thread_id,
 	if (reg->type->get(reg) != ERROR_OK)
 		return ERROR_FAIL;
 
-	rtos_reg->number = reg->number;
-	rtos_reg->size = reg->size;
-	unsigned int bytes = (reg->size + 7) / 8;
-	assert(bytes <= sizeof(rtos_reg->value));
-	memcpy(rtos_reg->value, reg->value, bytes);
+	*size = reg->size;
+	unsigned int bytes = DIV_ROUND_UP(reg->size, 8);
+	*value = malloc(bytes);
+	if (!*value) {
+		LOG_ERROR("Failed to allocate memory for %d-bit register.", reg->size);
+		return ERROR_FAIL;
+	}
+	memcpy(*value, reg->value, bytes);
 
 	return ERROR_OK;
 }
diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 2ccccf1b0..45366268d 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -545,15 +545,33 @@ int rtos_get_gdb_reg(struct connection *connection, int reg_num)
 										target->rtos->current_thread);
 
 		int retval;
-		if (target->rtos->type->get_thread_reg) {
-			reg_list = calloc(1, sizeof(*reg_list));
-			num_regs = 1;
-			retval = target->rtos->type->get_thread_reg(target->rtos,
-					current_threadid, reg_num, &reg_list[0]);
+		if (target->rtos->type->get_thread_reg_value) {
+			uint32_t reg_size;
+			uint8_t *reg_value;
+			retval = target->rtos->type->get_thread_reg_value(target->rtos,
+					current_threadid, reg_num, &reg_size, &reg_value);
 			if (retval != ERROR_OK) {
 				LOG_ERROR("RTOS: failed to get register %d", reg_num);
 				return retval;
 			}
+
+			/* Create a reg_list with one register that can
+			 * accommodate the full size of the one we just got the
+			 * value for. To do that we allocate extra space off the
+			 * end of the struct, relying on the fact that
+			 * rtos_reg.value is the last element in the struct. */
+			reg_list = calloc(1, sizeof(*reg_list) + DIV_ROUND_UP(reg_size, 8));
+			if (!reg_list) {
+				free(reg_value);
+				LOG_ERROR("Failed to allocated reg_list for %d-byte register.",
+					  reg_size);
+				return ERROR_FAIL;
+			}
+			reg_list[0].number = reg_num;
+			reg_list[0].size = reg_size;
+			memcpy(&reg_list[0].value, reg_value, DIV_ROUND_UP(reg_size, 8));
+			free(reg_value);
+			num_regs = 1;
 		} else {
 			retval = target->rtos->type->get_thread_reg_list(target->rtos,
 					current_threadid,
diff --git a/src/rtos/rtos.h b/src/rtos/rtos.h
index dbaa7e8ce..3077acc9d 100644
--- a/src/rtos/rtos.h
+++ b/src/rtos/rtos.h
@@ -53,6 +53,8 @@ struct rtos_reg {
 	uint32_t number;
 	uint32_t size;
 	uint8_t value[16];
+	/* WARNING: rtos_get_gdb_reg() relies on the fact that value is the last
+	 * element of this struct. Any new fields should be added *before* value. */
 };
 
 struct rtos_type {
@@ -64,8 +66,10 @@ struct rtos_type {
 	/** Return a list of general registers, with their values filled out. */
 	int (*get_thread_reg_list)(struct rtos *rtos, int64_t thread_id,
 			struct rtos_reg **reg_list, int *num_regs);
-	int (*get_thread_reg)(struct rtos *rtos, int64_t thread_id,
-			uint32_t reg_num, struct rtos_reg *reg);
+	/** Return the size and value of the specified reg_num. The value is
+	 * allocated by the callee and freed by the caller. */
+	int (*get_thread_reg_value)(struct rtos *rtos, threadid_t thread_id,
+			uint32_t reg_num, uint32_t *size, uint8_t **value);
 	int (*get_symbol_list_to_lookup)(struct symbol_table_elem *symbol_list[]);
 	int (*clean)(struct target *target);
 	char * (*ps_command)(struct target *target);

-----------------------------------------------------------------------

Summary of changes:
 src/rtos/hwthread.c | 23 +++++++++++++----------
 src/rtos/rtos.c     | 28 +++++++++++++++++++++++-----
 src/rtos/rtos.h     |  8 ++++++--
 3 files changed, 42 insertions(+), 17 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1263-g612707761

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  612707761357b5ab69f552a9120d9cf92340c6cd (commit)
      from  da96d3d41b637796ce4eea4013c0c70af3490f23 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 612707761357b5ab69f552a9120d9cf92340c6cd
Author: Tim Newsome <ti...@si...>
Date:   Thu Oct 13 13:29:15 2022 -0700

    target/breakpoints: better wording for error reason
    
    Imported from
    https://github.com/riscv-collab/riscv-openocd/pull/767
    
    Extracted small part of
    target/riscv: Don't resume unavailable harts.
    
    Change-Id: Id6617230cfdadf93ba402e60fb704bdfe7af5c1e
    Signed-off-by: Tim Newsome <ti...@si...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8921
    Tested-by: jenkins
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index 7254eac7d..d65e5594f 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -78,7 +78,7 @@ static int breakpoint_add_internal(struct target *target,
 		reason = "resource not available";
 		goto fail;
 	case ERROR_TARGET_NOT_HALTED:
-		reason = "target running";
+		reason = "target not halted";
 		goto fail;
 	default:
 		reason = "unknown reason";
@@ -523,7 +523,7 @@ static int watchpoint_add_internal(struct target *target, target_addr_t address,
 		reason = "resource not available";
 		goto bye;
 	case ERROR_TARGET_NOT_HALTED:
-		reason = "target running";
+		reason = "target not halted";
 		goto bye;
 	default:
 		reason = "unrecognized error";

-----------------------------------------------------------------------

Summary of changes:
 src/target/breakpoints.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1262-gda96d3d41

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  da96d3d41b637796ce4eea4013c0c70af3490f23 (commit)
      from  768b4084ebee3f59976f2eb15dd07a93407bc5ca (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit da96d3d41b637796ce4eea4013c0c70af3490f23
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Aug 4 17:45:53 2025 +0200

    target: riscv-011: don't change 'debug_level' during target polling
    
    In the riscv fork, [1] has disable the debug log during target
    polling, with message:
            Improve low-level logging.
    
            Now logging is consistent and more readable.
            I did remove most logging during riscv_poll() since it clutters
            up the log/screen and is not generally helpful.
    
    This is questionable, because if the user enables the debug log,
    the messages should all be logged.
    
    Drop the code that overwrites the 'debug_level'.
    
    Link: https://github.com/riscv-collab/riscv-openocd/commit/54c65a9a4b71 [1]
    Change-Id: Ia86b998cf654760f36c2f217d44bcb9ffd9c3a94
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9072
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c
index 801bcba7d..2bef2228e 100644
--- a/src/target/riscv/riscv-011.c
+++ b/src/target/riscv/riscv-011.c
@@ -1931,11 +1931,6 @@ static int poll_target(struct target *target, bool announce)
 {
 	jtag_add_ir_scan(target->tap, &select_dbus, TAP_IDLE);
 
-	/* Inhibit debug logging during poll(), which isn't usually interesting and
-	 * just fills up the screen/logs with clutter. */
-	int old_debug_level = debug_level;
-	if (LOG_LEVEL_IS(LOG_LVL_DEBUG))
-		debug_level = LOG_LVL_INFO;
 	bits_t bits = {
 		.haltnot = 0,
 		.interrupt = 0
@@ -1943,8 +1938,6 @@ static int poll_target(struct target *target, bool announce)
 	if (read_bits(target, &bits) != ERROR_OK)
 		return ERROR_FAIL;
 
-	debug_level = old_debug_level;
-
 	if (bits.haltnot && bits.interrupt) {
 		target->state = TARGET_DEBUG_RUNNING;
 		LOG_DEBUG("debug running");

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv-011.c | 7 -------
 1 file changed, 7 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1261-g768b4084e

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  768b4084ebee3f59976f2eb15dd07a93407bc5ca (commit)
      from  bd303d6a3daa64a671eca6f951eaac88b86346de (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 768b4084ebee3f59976f2eb15dd07a93407bc5ca
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Aug 4 17:40:39 2025 +0200

    target: riscv: don't test 'debug_level' directly
    
    Use the macro 'LOG_LEVEL_IS()' to test 'debug_level'.
    
    Change-Id: Ic931fd2eff0fa97a7a315b4b276f85dfc5fc8d5f
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9071
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/src/target/riscv/batch.c b/src/target/riscv/batch.c
index 56143808f..5acbddaf3 100644
--- a/src/target/riscv/batch.c
+++ b/src/target/riscv/batch.c
@@ -204,7 +204,7 @@ static void log_batch(const struct riscv_batch *batch, size_t start_idx,
 		const struct riscv_scan_delays *delays, bool resets_delays,
 		size_t reset_delays_after)
 {
-	if (debug_level < LOG_LVL_DEBUG)
+	if (!LOG_LEVEL_IS(LOG_LVL_DEBUG))
 		return;
 
 	const unsigned int abits = riscv_get_dmi_address_bits(batch->target);
diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c
index 139d555f8..801bcba7d 100644
--- a/src/target/riscv/riscv-011.c
+++ b/src/target/riscv/riscv-011.c
@@ -391,7 +391,7 @@ static void dump_field(const struct scan_field *field)
 	static const char * const op_string[] = {"nop", "r", "w", "?"};
 	static const char * const status_string[] = {"+", "?", "F", "b"};
 
-	if (debug_level < LOG_LVL_DEBUG)
+	if (!LOG_LEVEL_IS(LOG_LVL_DEBUG))
 		return;
 
 	uint64_t out = buf_get_u64(field->out_value, 0, field->num_bits);
@@ -1934,7 +1934,7 @@ static int poll_target(struct target *target, bool announce)
 	/* Inhibit debug logging during poll(), which isn't usually interesting and
 	 * just fills up the screen/logs with clutter. */
 	int old_debug_level = debug_level;
-	if (debug_level >= LOG_LVL_DEBUG)
+	if (LOG_LEVEL_IS(LOG_LVL_DEBUG))
 		debug_level = LOG_LVL_INFO;
 	bits_t bits = {
 		.haltnot = 0,
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 2a947bd69..9da9684e4 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -368,7 +368,7 @@ static struct riscv_debug_reg_ctx get_riscv_debug_reg_ctx(const struct target *t
 static void log_debug_reg(struct target *target, enum riscv_debug_reg_ordinal reg,
 		riscv_reg_t value, const char *file, unsigned int line, const char *func)
 {
-	if (debug_level < LOG_LVL_DEBUG)
+	if (!LOG_LEVEL_IS(LOG_LVL_DEBUG))
 		return;
 	const struct riscv_debug_reg_ctx context = get_riscv_debug_reg_ctx(target);
 	char * const buf = malloc(riscv_debug_reg_to_s(NULL, reg, context, value, RISCV_DEBUG_REG_HIDE_UNNAMED_0) + 1);
@@ -735,7 +735,7 @@ int riscv013_execute_abstract_command(struct target *target, uint32_t command,
 {
 	assert(cmderr);
 	*cmderr = CMDERR_NONE;
-	if (debug_level >= LOG_LVL_DEBUG) {
+	if (LOG_LEVEL_IS(LOG_LVL_DEBUG)) {
 		switch (get_field(command, DM_COMMAND_CMDTYPE)) {
 		case 0:
 			LOG_DEBUG_REG(target, AC_ACCESS_REGISTER, command);
@@ -3094,7 +3094,7 @@ static int execute_autofence(struct target *target)
 static void log_memory_access128(target_addr_t address, uint64_t value_h,
 		uint64_t value_l, bool is_read)
 {
-	if (debug_level < LOG_LVL_DEBUG)
+	if (!LOG_LEVEL_IS(LOG_LVL_DEBUG))
 		return;
 
 	char fmt[80];
@@ -3106,7 +3106,7 @@ static void log_memory_access128(target_addr_t address, uint64_t value_h,
 static void log_memory_access64(target_addr_t address, uint64_t value,
 		unsigned int size_bytes, bool is_read)
 {
-	if (debug_level < LOG_LVL_DEBUG)
+	if (!LOG_LEVEL_IS(LOG_LVL_DEBUG))
 		return;
 
 	char fmt[80];

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/batch.c     | 2 +-
 src/target/riscv/riscv-011.c | 4 ++--
 src/target/riscv/riscv-013.c | 8 ++++----
 3 files changed, 7 insertions(+), 7 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1260-gbd303d6a3

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  bd303d6a3daa64a671eca6f951eaac88b86346de (commit)
      from  56141bb3490d8f39aad6c7a9be5a70f24d93a991 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit bd303d6a3daa64a671eca6f951eaac88b86346de
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Aug 2 19:33:37 2025 +0200

    target: riscv: align switch and case statements
    
    The coding style requires the 'case' to be at the same indentation
    level of its 'switch' statement.
    
    Align the code accordingly.
    
    While there, put at newline the command after the 'case'.
    
    No changes are reported by
            git log -p -w --ignore-blank-lines --patience
    apart from the newline after 'case'.
    
    Change-Id: Id856e24100de6fb0442afe8bc51545b0138ef02d
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9069
    Tested-by: jenkins
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/riscv/riscv-011.c b/src/target/riscv/riscv-011.c
index 69ad5fcbf..139d555f8 100644
--- a/src/target/riscv/riscv-011.c
+++ b/src/target/riscv/riscv-011.c
@@ -230,19 +230,25 @@ static unsigned int slot_offset(const struct target *target, slot_t slot)
 {
 	riscv011_info_t *info = get_info(target);
 	switch (riscv_xlen(target)) {
-		case 32:
-			switch (slot) {
-				case SLOT0: return 4;
-				case SLOT1: return 5;
-				case SLOT_LAST: return info->dramsize-1;
-			}
-			break;
-		case 64:
-			switch (slot) {
-				case SLOT0: return 4;
-				case SLOT1: return 6;
-				case SLOT_LAST: return info->dramsize-2;
-			}
+	case 32:
+		switch (slot) {
+		case SLOT0:
+			return 4;
+		case SLOT1:
+			return 5;
+		case SLOT_LAST:
+			return info->dramsize - 1;
+		}
+		break;
+	case 64:
+		switch (slot) {
+		case SLOT0:
+			return 4;
+		case SLOT1:
+			return 6;
+		case SLOT_LAST:
+			return info->dramsize - 2;
+		}
 	}
 	LOG_ERROR("slot_offset called with xlen=%d, slot=%d",
 			riscv_xlen(target), slot);
@@ -254,10 +260,10 @@ static uint32_t load(const struct target *target, unsigned int rd,
 		unsigned int base, int16_t offset)
 {
 	switch (riscv_xlen(target)) {
-		case 32:
-			return lw(rd, base, offset);
-		case 64:
-			return ld(rd, base, offset);
+	case 32:
+		return lw(rd, base, offset);
+	case 64:
+		return ld(rd, base, offset);
 	}
 	assert(0);
 	return 0; /* Silence -Werror=return-type */
@@ -267,10 +273,10 @@ static uint32_t store(const struct target *target, unsigned int src,
 		unsigned int base, int16_t offset)
 {
 	switch (riscv_xlen(target)) {
-		case 32:
-			return sw(src, base, offset);
-		case 64:
-			return sd(src, base, offset);
+	case 32:
+		return sw(src, base, offset);
+	case 64:
+		return sd(src, base, offset);
 	}
 	assert(0);
 	return 0; /* Silence -Werror=return-type */
@@ -641,13 +647,13 @@ static void scans_add_read(scans_t *scans, slot_t slot, bool set_interrupt)
 {
 	const struct target *target = scans->target;
 	switch (riscv_xlen(target)) {
-		case 32:
-			scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
-			break;
-		case 64:
-			scans_add_read32(scans, slot_offset(target, slot), false);
-			scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
-			break;
+	case 32:
+		scans_add_read32(scans, slot_offset(target, slot), set_interrupt);
+		break;
+	case 64:
+		scans_add_read32(scans, slot_offset(target, slot), false);
+		scans_add_read32(scans, slot_offset(target, slot) + 1, set_interrupt);
+		break;
 	}
 }
 
@@ -906,19 +912,19 @@ static int cache_write(struct target *target, unsigned int address, bool run)
 		dbus_status_t status = scans_get_u32(scans, i, DBUS_OP_START,
 				DBUS_OP_SIZE);
 		switch (status) {
-			case DBUS_STATUS_SUCCESS:
-				break;
-			case DBUS_STATUS_FAILED:
-				LOG_ERROR("Debug RAM write failed. Hardware error?");
-				scans_delete(scans);
-				return ERROR_FAIL;
-			case DBUS_STATUS_BUSY:
-				errors++;
-				break;
-			default:
-				LOG_ERROR("Got invalid bus access status: %d", status);
-				scans_delete(scans);
-				return ERROR_FAIL;
+		case DBUS_STATUS_SUCCESS:
+			break;
+		case DBUS_STATUS_FAILED:
+			LOG_ERROR("Debug RAM write failed. Hardware error?");
+			scans_delete(scans);
+			return ERROR_FAIL;
+		case DBUS_STATUS_BUSY:
+			errors++;
+			break;
+		default:
+			LOG_ERROR("Got invalid bus access status: %d", status);
+			scans_delete(scans);
+			return ERROR_FAIL;
 		}
 	}
 
@@ -1680,17 +1686,17 @@ static riscv_error_t handle_halt_routine(struct target *target)
 		uint32_t address = scans_get_u32(scans, i, DBUS_ADDRESS_START,
 				info->addrbits);
 		switch (status) {
-			case DBUS_STATUS_SUCCESS:
-				break;
-			case DBUS_STATUS_FAILED:
-				LOG_ERROR("Debug access failed. Hardware error?");
-				goto error;
-			case DBUS_STATUS_BUSY:
-				dbus_busy++;
-				break;
-			default:
-				LOG_ERROR("Got invalid bus access status: %d", status);
-				goto error;
+		case DBUS_STATUS_SUCCESS:
+			break;
+		case DBUS_STATUS_FAILED:
+			LOG_ERROR("Debug access failed. Hardware error?");
+			goto error;
+		case DBUS_STATUS_BUSY:
+			dbus_busy++;
+			break;
+		default:
+			LOG_ERROR("Got invalid bus access status: %d", status);
+			goto error;
 		}
 		if (data & DMCONTROL_INTERRUPT) {
 			interrupt_set++;
@@ -1699,111 +1705,111 @@ static riscv_error_t handle_halt_routine(struct target *target)
 		if (address == 4 || address == 5) {
 			unsigned int reg;
 			switch (result) {
-				case 0:
-					reg = 1;
-					break;
-				case 1:
-					reg = 2;
-					break;
-				case 2:
-					reg = 3;
-					break;
-				case 3:
-					reg = 4;
-					break;
-				case 4:
-					reg = 5;
-					break;
-				case 5:
-					reg = 6;
-					break;
-				case 6:
-					reg = 7;
-					break;
-					/* S0 */
-					/* S1 */
-				case 7:
-					reg = 10;
-					break;
-				case 8:
-					reg = 11;
-					break;
-				case 9:
-					reg = 12;
-					break;
-				case 10:
-					reg = 13;
-					break;
-				case 11:
-					reg = 14;
-					break;
-				case 12:
-					reg = 15;
-					break;
-				case 13:
-					reg = 16;
-					break;
-				case 14:
-					reg = 17;
-					break;
-				case 15:
-					reg = 18;
-					break;
-				case 16:
-					reg = 19;
-					break;
-				case 17:
-					reg = 20;
-					break;
-				case 18:
-					reg = 21;
-					break;
-				case 19:
-					reg = 22;
-					break;
-				case 20:
-					reg = 23;
-					break;
-				case 21:
-					reg = 24;
-					break;
-				case 22:
-					reg = 25;
-					break;
-				case 23:
-					reg = 26;
-					break;
-				case 24:
-					reg = 27;
-					break;
-				case 25:
-					reg = 28;
-					break;
-				case 26:
-					reg = 29;
-					break;
-				case 27:
-					reg = 30;
-					break;
-				case 28:
-					reg = 31;
-					break;
-				case 29:
-					reg = S1;
-					break;
-				case 30:
-					reg = S0;
-					break;
-				case 31:
-					reg = GDB_REGNO_DPC;
-					break;
-				case 32:
-					reg = GDB_REGNO_DCSR;
-					break;
-				default:
-					assert(0);
-					LOG_ERROR("Got invalid register result %d", result);
-					goto error;
+			case 0:
+				reg = 1;
+				break;
+			case 1:
+				reg = 2;
+				break;
+			case 2:
+				reg = 3;
+				break;
+			case 3:
+				reg = 4;
+				break;
+			case 4:
+				reg = 5;
+				break;
+			case 5:
+				reg = 6;
+				break;
+			case 6:
+				reg = 7;
+				break;
+				/* S0 */
+				/* S1 */
+			case 7:
+				reg = 10;
+				break;
+			case 8:
+				reg = 11;
+				break;
+			case 9:
+				reg = 12;
+				break;
+			case 10:
+				reg = 13;
+				break;
+			case 11:
+				reg = 14;
+				break;
+			case 12:
+				reg = 15;
+				break;
+			case 13:
+				reg = 16;
+				break;
+			case 14:
+				reg = 17;
+				break;
+			case 15:
+				reg = 18;
+				break;
+			case 16:
+				reg = 19;
+				break;
+			case 17:
+				reg = 20;
+				break;
+			case 18:
+				reg = 21;
+				break;
+			case 19:
+				reg = 22;
+				break;
+			case 20:
+				reg = 23;
+				break;
+			case 21:
+				reg = 24;
+				break;
+			case 22:
+				reg = 25;
+				break;
+			case 23:
+				reg = 26;
+				break;
+			case 24:
+				reg = 27;
+				break;
+			case 25:
+				reg = 28;
+				break;
+			case 26:
+				reg = 29;
+				break;
+			case 27:
+				reg = 30;
+				break;
+			case 28:
+				reg = 31;
+				break;
+			case 29:
+				reg = S1;
+				break;
+			case 30:
+				reg = S0;
+				break;
+			case 31:
+				reg = GDB_REGNO_DPC;
+				break;
+			case 32:
+				reg = GDB_REGNO_DCSR;
+				break;
+			default:
+				assert(0);
+				LOG_ERROR("Got invalid register result %d", result);
+				goto error;
 			}
 			if (riscv_xlen(target) == 32) {
 				reg_cache_set(target, reg, data & 0xffffffff);
@@ -1860,22 +1866,22 @@ static int handle_halt(struct target *target, bool announce)
 
 	int cause = get_field(info->dcsr, DCSR_CAUSE);
 	switch (cause) {
-		case DCSR_CAUSE_SWBP:
-			target->debug_reason = DBG_REASON_BREAKPOINT;
-			break;
-		case DCSR_CAUSE_HWBP:
-			target->debug_reason = DBG_REASON_WATCHPOINT;
-			break;
-		case DCSR_CAUSE_DEBUGINT:
-			target->debug_reason = DBG_REASON_DBGRQ;
-			break;
-		case DCSR_CAUSE_STEP:
-			target->debug_reason = DBG_REASON_SINGLESTEP;
-			break;
-		case DCSR_CAUSE_HALT:
-		default:
-			LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
-					cause, info->dcsr);
+	case DCSR_CAUSE_SWBP:
+		target->debug_reason = DBG_REASON_BREAKPOINT;
+		break;
+	case DCSR_CAUSE_HWBP:
+		target->debug_reason = DBG_REASON_WATCHPOINT;
+		break;
+	case DCSR_CAUSE_DEBUGINT:
+		target->debug_reason = DBG_REASON_DBGRQ;
+		break;
+	case DCSR_CAUSE_STEP:
+		target->debug_reason = DBG_REASON_SINGLESTEP;
+		break;
+	case DCSR_CAUSE_HALT:
+	default:
+		LOG_ERROR("Invalid halt cause %d in DCSR (0x%" PRIx64 ")",
+				cause, info->dcsr);
 	}
 
 	if (info->never_halted) {
@@ -2032,21 +2038,21 @@ static int read_memory(struct target *target, const struct riscv_mem_access_args
 
 	cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
 	switch (size) {
-		case 1:
-			cache_set32(target, 1, lb(S1, S0, 0));
-			cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
-			break;
-		case 2:
-			cache_set32(target, 1, lh(S1, S0, 0));
-			cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
-			break;
-		case 4:
-			cache_set32(target, 1, lw(S1, S0, 0));
-			cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
-			break;
-		default:
-			LOG_ERROR("Unsupported size: %d", size);
-			return ERROR_FAIL;
+	case 1:
+		cache_set32(target, 1, lb(S1, S0, 0));
+		cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
+		break;
+	case 2:
+		cache_set32(target, 1, lh(S1, S0, 0));
+		cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
+		break;
+	case 4:
+		cache_set32(target, 1, lw(S1, S0, 0));
+		cache_set32(target, 2, sw(S1, ZERO, DEBUG_RAM_START + 16));
+		break;
+	default:
+		LOG_ERROR("Unsupported size: %d", size);
+		return ERROR_FAIL;
 	}
 	cache_set_jump(target, 3);
 	cache_write(target, CACHE_NO_READ, false);
@@ -2089,17 +2095,17 @@ static int read_memory(struct target *target, const struct riscv_mem_access_args
 			dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
 					DBUS_OP_SIZE);
 			switch (status) {
-				case DBUS_STATUS_SUCCESS:
-					break;
-				case DBUS_STATUS_FAILED:
-					LOG_ERROR("Debug RAM write failed. Hardware error?");
-					goto error;
-				case DBUS_STATUS_BUSY:
-					dbus_busy++;
-					break;
-				default:
-					LOG_ERROR("Got invalid bus access status: %d", status);
-					return ERROR_FAIL;
+			case DBUS_STATUS_SUCCESS:
+				break;
+			case DBUS_STATUS_FAILED:
+				LOG_ERROR("Debug RAM write failed. Hardware error?");
+				goto error;
+			case DBUS_STATUS_BUSY:
+				dbus_busy++;
+				break;
+			default:
+				LOG_ERROR("Got invalid bus access status: %d", status);
+				return ERROR_FAIL;
 			}
 			uint64_t data = scans_get_u64(scans, j, DBUS_DATA_START,
 					DBUS_DATA_SIZE);
@@ -2110,19 +2116,19 @@ static int read_memory(struct target *target, const struct riscv_mem_access_args
 			} else if (i + j > 1) {
 				uint32_t offset = size * (i + j - 2);
 				switch (size) {
-					case 1:
-						buffer[offset] = data;
-						break;
-					case 2:
-						buffer[offset] = data;
-						buffer[offset+1] = data >> 8;
-						break;
-					case 4:
-						buffer[offset] = data;
-						buffer[offset+1] = data >> 8;
-						buffer[offset+2] = data >> 16;
-						buffer[offset+3] = data >> 24;
-						break;
+				case 1:
+					buffer[offset] = data;
+					break;
+				case 2:
+					buffer[offset] = data;
+					buffer[offset + 1] = data >> 8;
+					break;
+				case 4:
+					buffer[offset] = data;
+					buffer[offset + 1] = data >> 8;
+					buffer[offset + 2] = data >> 16;
+					buffer[offset + 3] = data >> 24;
+					break;
 				}
 			}
 			LOG_DEBUG("j=%d status=%d data=%09" PRIx64, j, status, data);
@@ -2167,21 +2173,21 @@ error:
 static int setup_write_memory(struct target *target, uint32_t size)
 {
 	switch (size) {
-		case 1:
-			cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
-			cache_set32(target, 1, sb(S0, T0, 0));
-			break;
-		case 2:
-			cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
-			cache_set32(target, 1, sh(S0, T0, 0));
-			break;
-		case 4:
-			cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
-			cache_set32(target, 1, sw(S0, T0, 0));
-			break;
-		default:
-			LOG_ERROR("Unsupported size: %d", size);
-			return ERROR_FAIL;
+	case 1:
+		cache_set32(target, 0, lb(S0, ZERO, DEBUG_RAM_START + 16));
+		cache_set32(target, 1, sb(S0, T0, 0));
+		break;
+	case 2:
+		cache_set32(target, 0, lh(S0, ZERO, DEBUG_RAM_START + 16));
+		cache_set32(target, 1, sh(S0, T0, 0));
+		break;
+	case 4:
+		cache_set32(target, 0, lw(S0, ZERO, DEBUG_RAM_START + 16));
+		cache_set32(target, 1, sw(S0, T0, 0));
+		break;
+	default:
+		LOG_ERROR("Unsupported size: %d", size);
+		return ERROR_FAIL;
 	}
 	cache_set32(target, 2, addi(T0, T0, size));
 	cache_set_jump(target, 3);
@@ -2241,21 +2247,21 @@ static int write_memory(struct target *target, const struct riscv_mem_access_arg
 				uint32_t value;
 				uint32_t offset = size * (i + j);
 				switch (size) {
-					case 1:
-						value = buffer[offset];
-						break;
-					case 2:
-						value = buffer[offset] |
-							(buffer[offset+1] << 8);
-						break;
-					case 4:
-						value = buffer[offset] |
-							((uint32_t) buffer[offset+1] << 8) |
-							((uint32_t) buffer[offset+2] << 16) |
-							((uint32_t) buffer[offset+3] << 24);
-						break;
-					default:
-						goto error;
+				case 1:
+					value = buffer[offset];
+					break;
+				case 2:
+					value = buffer[offset] |
+						(buffer[offset + 1] << 8);
+					break;
+				case 4:
+					value = buffer[offset] |
+						((uint32_t)buffer[offset + 1] << 8) |
+						((uint32_t)buffer[offset + 2] << 16) |
+						((uint32_t)buffer[offset + 3] << 24);
+					break;
+				default:
+					goto error;
 				}
 
 				scans_add_write32(scans, 4, value, true);
@@ -2274,17 +2280,17 @@ static int write_memory(struct target *target, const struct riscv_mem_access_arg
 			dbus_status_t status = scans_get_u32(scans, j, DBUS_OP_START,
 					DBUS_OP_SIZE);
 			switch (status) {
-				case DBUS_STATUS_SUCCESS:
-					break;
-				case DBUS_STATUS_FAILED:
-					LOG_ERROR("Debug RAM write failed. Hardware error?");
-					goto error;
-				case DBUS_STATUS_BUSY:
-					dbus_busy++;
-					break;
-				default:
-					LOG_ERROR("Got invalid bus access status: %d", status);
-					return ERROR_FAIL;
+			case DBUS_STATUS_SUCCESS:
+				break;
+			case DBUS_STATUS_FAILED:
+				LOG_ERROR("Debug RAM write failed. Hardware error?");
+				goto error;
+			case DBUS_STATUS_BUSY:
+				dbus_busy++;
+				break;
+			default:
+				LOG_ERROR("Got invalid bus access status: %d", status);
+				return ERROR_FAIL;
 			}
 			int interrupt = scans_get_u32(scans, j, DBUS_DATA_START + 33, 1);
 			if (interrupt)
diff --git a/src/target/riscv/riscv-013.c b/src/target/riscv/riscv-013.c
index 336a7514e..2a947bd69 100644
--- a/src/target/riscv/riscv-013.c
+++ b/src/target/riscv/riscv-013.c
@@ -592,15 +592,15 @@ static int increase_ac_busy_delay(struct target *target)
 static uint32_t __attribute__((unused)) abstract_register_size(unsigned int width)
 {
 	switch (width) {
-		case 32:
-			return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 2);
-		case 64:
-			return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 3);
-		case 128:
-			return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 4);
-		default:
-			LOG_ERROR("Unsupported register width: %d", width);
-			return 0;
+	case 32:
+		return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 2);
+	case 64:
+		return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 3);
+	case 128:
+		return set_field(0, AC_ACCESS_REGISTER_AARSIZE, 4);
+	default:
+		LOG_ERROR("Unsupported register width: %d", width);
+		return 0;
 	}
 }
 
@@ -737,12 +737,12 @@ int riscv013_execute_abstract_command(struct target *target, uint32_t command,
 	*cmderr = CMDERR_NONE;
 	if (debug_level >= LOG_LVL_DEBUG) {
 		switch (get_field(command, DM_COMMAND_CMDTYPE)) {
-			case 0:
-				LOG_DEBUG_REG(target, AC_ACCESS_REGISTER, command);
-				break;
-			default:
-				LOG_TARGET_DEBUG(target, "command=0x%x", command);
-				break;
+		case 0:
+			LOG_DEBUG_REG(target, AC_ACCESS_REGISTER, command);
+			break;
+		default:
+			LOG_TARGET_DEBUG(target, "command=0x%x", command);
+			break;
 		}
 	}
 
@@ -854,14 +854,14 @@ static int write_abstract_arg(struct target *target, unsigned int index,
 {
 	unsigned int offset = index * size_bits / 32;
 	switch (size_bits) {
-		default:
-			LOG_TARGET_ERROR(target, "Unsupported size: %d bits", size_bits);
-			return ERROR_FAIL;
-		case 64:
-			dm_write(target, DM_DATA0 + offset + 1, (uint32_t)(value >> 32));
-			/* falls through */
-		case 32:
-			dm_write(target, DM_DATA0 + offset, (uint32_t)value);
+	default:
+		LOG_TARGET_ERROR(target, "Unsupported size: %d bits", size_bits);
+		return ERROR_FAIL;
+	case 64:
+		dm_write(target, DM_DATA0 + offset + 1, (uint32_t)(value >> 32));
+		/* falls through */
+	case 32:
+		dm_write(target, DM_DATA0 + offset, (uint32_t)value);
 	}
 	return ERROR_OK;
 }
@@ -874,16 +874,16 @@ uint32_t riscv013_access_register_command(struct target *target, uint32_t number
 {
 	uint32_t command = set_field(0, DM_COMMAND_CMDTYPE, 0);
 	switch (size) {
-		case 32:
-			command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 2);
-			break;
-		case 64:
-			command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 3);
-			break;
-		default:
-			LOG_TARGET_ERROR(target, "%d-bit register %s not supported.",
-					size, riscv_reg_gdb_regno_name(target, number));
-			assert(0);
+	case 32:
+		command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 2);
+		break;
+	case 64:
+		command = set_field(command, AC_ACCESS_REGISTER_AARSIZE, 3);
+		break;
+	default:
+		LOG_TARGET_ERROR(target, "%d-bit register %s not supported.",
+				size, riscv_reg_gdb_regno_name(target, number));
+		assert(0);
 	}
 
 	if (number <= GDB_REGNO_XPR31) {
@@ -1003,19 +1003,19 @@ cleanup:
 static uint32_t abstract_memory_size(unsigned int width)
 {
 	switch (width) {
-		case 8:
-			return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 0);
-		case 16:
-			return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 1);
-		case 32:
-			return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 2);
-		case 64:
-			return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 3);
-		case 128:
-			return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 4);
-		default:
-			LOG_ERROR("Unsupported memory width: %d", width);
-			return 0;
+	case 8:
+		return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 0);
+	case 16:
+		return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 1);
+	case 32:
+		return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 2);
+	case 64:
+		return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 3);
+	case 128:
+		return set_field(0, AC_ACCESS_MEMORY_AAMSIZE, 4);
+	default:
+		LOG_ERROR("Unsupported memory width: %d", width);
+		return 0;
 	}
 }
 
@@ -1251,38 +1251,38 @@ static int scratch_read64(struct target *target, scratch_mem_t *scratch,
 {
 	uint32_t v;
 	switch (scratch->memory_space) {
-		case SPACE_DM_DATA:
-			if (dm_read(target, &v, DM_DATA0 + scratch->debug_address) != ERROR_OK)
-				return ERROR_FAIL;
-			*value = v;
-			if (dm_read(target, &v, DM_DATA1 + scratch->debug_address) != ERROR_OK)
-				return ERROR_FAIL;
-			*value |= ((uint64_t) v) << 32;
-			break;
-		case SPACE_DMI_PROGBUF:
-			if (dm_read(target, &v, DM_PROGBUF0 + scratch->debug_address) != ERROR_OK)
-				return ERROR_FAIL;
-			*value = v;
-			if (dm_read(target, &v, DM_PROGBUF1 + scratch->debug_address) != ERROR_OK)
+	case SPACE_DM_DATA:
+		if (dm_read(target, &v, DM_DATA0 + scratch->debug_address) != ERROR_OK)
+			return ERROR_FAIL;
+		*value = v;
+		if (dm_read(target, &v, DM_DATA1 + scratch->debug_address) != ERROR_OK)
+			return ERROR_FAIL;
+		*value |= ((uint64_t)v) << 32;
+		break;
+	case SPACE_DMI_PROGBUF:
+		if (dm_read(target, &v, DM_PROGBUF0 + scratch->debug_address) != ERROR_OK)
+			return ERROR_FAIL;
+		*value = v;
+		if (dm_read(target, &v, DM_PROGBUF1 + scratch->debug_address) != ERROR_OK)
+			return ERROR_FAIL;
+		*value |= ((uint64_t)v) << 32;
+		break;
+	case SPACE_DMI_RAM:
+		{
+			uint8_t buffer[8] = {0};
+			const struct riscv_mem_access_args args = {
+				.address = scratch->debug_address,
+				.read_buffer = buffer,
+				.size = 4,
+				.count = 2,
+				.increment = 4,
+			};
+			if (riscv013_access_memory(target, args) != ERROR_OK)
 				return ERROR_FAIL;
-			*value |= ((uint64_t) v) << 32;
-			break;
-		case SPACE_DMI_RAM:
-			{
-				uint8_t buffer[8] = {0};
-				const struct riscv_mem_access_args args = {
-					.address = scratch->debug_address,
-					.read_buffer = buffer,
-					.size = 4,
-					.count = 2,
-					.increment = 4,
-				};
-				if (riscv013_access_memory(target, args) != ERROR_OK)
-					return ERROR_FAIL;
-				*value = buf_get_u64(buffer,
-						/* first = */ 0, /* bit_num = */ 64);
-			}
-			break;
+			*value = buf_get_u64(buffer,
+					/* first = */ 0, /* bit_num = */ 64);
+		}
+		break;
 	}
 	return ERROR_OK;
 }
@@ -1291,38 +1291,38 @@ static int scratch_write64(struct target *target, scratch_mem_t *scratch,
 		uint64_t value)
 {
 	switch (scratch->memory_space) {
-		case SPACE_DM_DATA:
-			dm_write(target, DM_DATA0 + scratch->debug_address, (uint32_t)value);
-			dm_write(target, DM_DATA1 + scratch->debug_address, (uint32_t)(value >> 32));
-			break;
-		case SPACE_DMI_PROGBUF:
-			dm_write(target, DM_PROGBUF0 + scratch->debug_address, (uint32_t)value);
-			dm_write(target, DM_PROGBUF1 + scratch->debug_address, (uint32_t)(value >> 32));
-			riscv013_invalidate_cached_progbuf(target);
-			break;
-		case SPACE_DMI_RAM:
-			{
-				uint8_t buffer[8] = {
-					value,
-					value >> 8,
-					value >> 16,
-					value >> 24,
-					value >> 32,
-					value >> 40,
-					value >> 48,
-					value >> 56
-				};
-				const struct riscv_mem_access_args args = {
-					.address = scratch->debug_address,
-					.write_buffer = buffer,
-					.size = 4,
-					.count = 2,
-					.increment = 4,
-				};
-				if (riscv013_access_memory(target, args) != ERROR_OK)
-					return ERROR_FAIL;
-			}
-			break;
+	case SPACE_DM_DATA:
+		dm_write(target, DM_DATA0 + scratch->debug_address, (uint32_t)value);
+		dm_write(target, DM_DATA1 + scratch->debug_address, (uint32_t)(value >> 32));
+		break;
+	case SPACE_DMI_PROGBUF:
+		dm_write(target, DM_PROGBUF0 + scratch->debug_address, (uint32_t)value);
+		dm_write(target, DM_PROGBUF1 + scratch->debug_address, (uint32_t)(value >> 32));
+		riscv013_invalidate_cached_progbuf(target);
+		break;
+	case SPACE_DMI_RAM:
+		{
+			uint8_t buffer[8] = {
+				value,
+				value >> 8,
+				value >> 16,
+				value >> 24,
+				value >> 32,
+				value >> 40,
+				value >> 48,
+				value >> 56
+			};
+			const struct riscv_mem_access_args args = {
+				.address = scratch->debug_address,
+				.write_buffer = buffer,
+				.size = 4,
+				.count = 2,
+				.increment = 4,
+			};
+			if (riscv013_access_memory(target, args) != ERROR_OK)
+				return ERROR_FAIL;
+		}
+		break;
 	}
 	return ERROR_OK;
 }
@@ -2451,16 +2451,16 @@ int riscv013_set_register_buf(struct target *target, enum gdb_regno regno,
 static uint32_t sb_sbaccess(unsigned int size_bytes)
 {
 	switch (size_bytes) {
-		case 1:
-			return set_field(0, DM_SBCS_SBACCESS, 0);
-		case 2:
-			return set_field(0, DM_SBCS_SBACCESS, 1);
-		case 4:
-			return set_field(0, DM_SBCS_SBACCESS, 2);
-		case 8:
-			return set_field(0, DM_SBCS_SBACCESS, 3);
-		case 16:
-			return set_field(0, DM_SBCS_SBACCESS, 4);
+	case 1:
+		return set_field(0, DM_SBCS_SBACCESS, 0);
+	case 2:
+		return set_field(0, DM_SBCS_SBACCESS, 1);
+	case 4:
+		return set_field(0, DM_SBCS_SBACCESS, 2);
+	case 8:
+		return set_field(0, DM_SBCS_SBACCESS, 3);
+	case 16:
+		return set_field(0, DM_SBCS_SBACCESS, 4);
 	}
 	assert(0);
 	return 0;
@@ -2581,18 +2581,18 @@ static int sba_supports_access(struct target *target, unsigned int size_bytes)
 {
 	RISCV013_INFO(info);
 	switch (size_bytes) {
-		case 1:
-			return get_field(info->sbcs, DM_SBCS_SBACCESS8);
-		case 2:
-			return get_field(info->sbcs, DM_SBCS_SBACCESS16);
-		case 4:
-			return get_field(info->sbcs, DM_SBCS_SBACCESS32);
-		case 8:
-			return get_field(info->sbcs, DM_SBCS_SBACCESS64);
-		case 16:
-			return get_field(info->sbcs, DM_SBCS_SBACCESS128);
-		default:
-			return 0;
+	case 1:
+		return get_field(info->sbcs, DM_SBCS_SBACCESS8);
+	case 2:
+		return get_field(info->sbcs, DM_SBCS_SBACCESS16);
+	case 4:
+		return get_field(info->sbcs, DM_SBCS_SBACCESS32);
+	case 8:
+		return get_field(info->sbcs, DM_SBCS_SBACCESS64);
+	case 16:
+		return get_field(info->sbcs, DM_SBCS_SBACCESS128);
+	default:
+		return 0;
 	}
 }
 
@@ -3113,19 +3113,19 @@ static void log_memory_access64(target_addr_t address, uint64_t value,
 	sprintf(fmt, "M[0x%" TARGET_PRIxADDR "] %ss 0x%%0%d" PRIx64,
 			address, is_read ? "read" : "write", size_bytes * 2);
 	switch (size_bytes) {
-		case 1:
-			value &= 0xff;
-			break;
-		case 2:
-			value &= 0xffff;
-			break;
-		case 4:
-			value &= 0xffffffffUL;
-			break;
-		case 8:
-			break;
-		default:
-			assert(false);
+	case 1:
+		value &= 0xff;
+		break;
+	case 2:
+		value &= 0xffff;
+		break;
+	case 4:
+		value &= 0xffffffffUL;
+		break;
+	case 8:
+		break;
+	default:
+		assert(false);
 	}
 	LOG_DEBUG(fmt, value);
 }
@@ -4580,19 +4580,19 @@ riscv013_access_memory(struct target *target, const struct riscv_mem_access_args
 	for (unsigned int i = 0; i < r->num_enabled_mem_access_methods; ++i) {
 		enum riscv_mem_access_method method = r->mem_access_methods[i];
 		switch (method) {
-			case RISCV_MEM_ACCESS_PROGBUF:
-				skip_reason[method] = access_memory_progbuf(target, args);
-				break;
-			case RISCV_MEM_ACCESS_SYSBUS:
-				skip_reason[method] = access_memory_sysbus(target, args);
-				break;
-			case RISCV_MEM_ACCESS_ABSTRACT:
-				skip_reason[method] = access_memory_abstract(target, args);
-				break;
-			default:
-				LOG_TARGET_ERROR(target, "Unknown memory access method: %d", method);
-				assert(false && "Unknown memory access method");
-				goto failure;
+		case RISCV_MEM_ACCESS_PROGBUF:
+			skip_reason[method] = access_memory_progbuf(target, args);
+			break;
+		case RISCV_MEM_ACCESS_SYSBUS:
+			skip_reason[method] = access_memory_sysbus(target, args);
+			break;
+		case RISCV_MEM_ACCESS_ABSTRACT:
+			skip_reason[method] = access_memory_abstract(target, args);
+			break;
+		default:
+			LOG_TARGET_ERROR(target, "Unknown memory access method: %d", method);
+			assert(false && "Unknown memory access method");
+			goto failure;
 		}
 
 		if (is_mem_access_failed(skip_reason[method]))
diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 2b6d0c755..7ef875f80 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -462,16 +462,16 @@ static struct target_type *get_target_type(struct target *target)
 
 	RISCV_INFO(info);
 	switch (info->dtm_version) {
-		case DTM_DTMCS_VERSION_0_11:
-			return &riscv011_target;
-		case DTM_DTMCS_VERSION_1_0:
-			return &riscv013_target;
-		default:
-			/* TODO: once we have proper support for non-examined targets
-			 * we should have an assert here */
-			LOG_TARGET_ERROR(target, "Unsupported DTM version: %d",
-					info->dtm_version);
-			return NULL;
+	case DTM_DTMCS_VERSION_0_11:
+		return &riscv011_target;
+	case DTM_DTMCS_VERSION_1_0:
+		return &riscv013_target;
+	default:
+		/* TODO: once we have proper support for non-examined targets
+		 * we should have an assert here */
+		LOG_TARGET_ERROR(target, "Unsupported DTM version: %d",
+				info->dtm_version);
+		return NULL;
 	}
 }
 
@@ -1857,39 +1857,39 @@ static int riscv_trigger_detect_hit_bits(struct target *target, int64_t *unique_
 
 		uint64_t hit_mask = 0;
 		switch (type) {
-			case CSR_TDATA1_TYPE_LEGACY:
-				/* Doesn't support hit bit. */
-				break;
-			case CSR_TDATA1_TYPE_MCONTROL:
-				hit_mask = CSR_MCONTROL_HIT;
+		case CSR_TDATA1_TYPE_LEGACY:
+			/* Doesn't support hit bit. */
+			break;
+		case CSR_TDATA1_TYPE_MCONTROL:
+			hit_mask = CSR_MCONTROL_HIT;
+			*need_single_step = true;
+			break;
+		case CSR_TDATA1_TYPE_MCONTROL6:
+			hit_mask = CSR_MCONTROL6_HIT0 | CSR_MCONTROL6_HIT1;
+			if (r->tinfo_version == CSR_TINFO_VERSION_0) {
 				*need_single_step = true;
-				break;
-			case CSR_TDATA1_TYPE_MCONTROL6:
-				hit_mask = CSR_MCONTROL6_HIT0 | CSR_MCONTROL6_HIT1;
-				if (r->tinfo_version == CSR_TINFO_VERSION_0) {
+			} else if (r->tinfo_version == RISCV_TINFO_VERSION_UNKNOWN
+				|| r->tinfo_version == CSR_TINFO_VERSION_1) {
+				enum mctrl6hitstatus hits_status = check_mcontrol6_hit_status(target,
+							tdata1, hit_mask);
+				if (hits_status == M6_HIT_ERROR)
+					return ERROR_FAIL;
+				if (hits_status == M6_HIT_BEFORE || hits_status == M6_HIT_NOT_SUPPORTED)
 					*need_single_step = true;
-				} else if (r->tinfo_version == RISCV_TINFO_VERSION_UNKNOWN
-					|| r->tinfo_version == CSR_TINFO_VERSION_1) {
-					enum mctrl6hitstatus hits_status = check_mcontrol6_hit_status(target,
-								tdata1, hit_mask);
-					if (hits_status == M6_HIT_ERROR)
-						return ERROR_FAIL;
-					if (hits_status == M6_HIT_BEFORE || hits_status == M6_HIT_NOT_SUPPORTED)
-						*need_single_step = true;
-				}
-				break;
-			case CSR_TDATA1_TYPE_ICOUNT:
-				hit_mask = CSR_ICOUNT_HIT;
-				break;
-			case CSR_TDATA1_TYPE_ITRIGGER:
-				hit_mask = CSR_ITRIGGER_HIT(riscv_xlen(target));
-				break;
-			case CSR_TDATA1_TYPE_ETRIGGER:
-				hit_mask = CSR_ETRIGGER_HIT(riscv_xlen(target));
-				break;
-			default:
-				LOG_TARGET_DEBUG(target, "Trigger %u has unknown type %d", i, type);
-				continue;
+			}
+			break;
+		case CSR_TDATA1_TYPE_ICOUNT:
+			hit_mask = CSR_ICOUNT_HIT;
+			break;
+		case CSR_TDATA1_TYPE_ITRIGGER:
+			hit_mask = CSR_ITRIGGER_HIT(riscv_xlen(target));
+			break;
+		case CSR_TDATA1_TYPE_ETRIGGER:
+			hit_mask = CSR_ETRIGGER_HIT(riscv_xlen(target));
+			break;
+		default:
+			LOG_TARGET_DEBUG(target, "Trigger %u has unknown type %d", i, type);
+			continue;
 		}
 
 		/* FIXME: this logic needs to be changed to ignore triggers that are not
@@ -2562,71 +2562,71 @@ static int set_debug_reason(struct target *target, enum riscv_halt_reason halt_r
 	r->trigger_hit = -1;
 	r->need_single_step = false;
 	switch (halt_reason) {
-		case RISCV_HALT_EBREAK:
-			target->debug_reason = DBG_REASON_BREAKPOINT;
-			break;
-		case RISCV_HALT_TRIGGER:
-			target->debug_reason = DBG_REASON_UNDEFINED;
-			if (riscv_trigger_detect_hit_bits(target, &r->trigger_hit,
-					&r->need_single_step) != ERROR_OK)
-				return ERROR_FAIL;
-			// FIXME: handle multiple hit bits
-			if (r->trigger_hit != RISCV_TRIGGER_HIT_NOT_FOUND) {
-				/* We scan for breakpoints first. If no breakpoints are found we still
-				 * assume that debug reason is DBG_REASON_BREAKPOINT, unless
-				 * there is a watchpoint match - This is to take
-				 * ETrigger/ITrigger/ICount into account
-				 */
-				LOG_TARGET_DEBUG(target,
-					"Active hit bit is detected, trying to find trigger owner.");
-				for (struct breakpoint *bp = target->breakpoints; bp; bp = bp->next) {
-					if (bp->unique_id == r->trigger_hit) {
-						target->debug_reason = DBG_REASON_BREAKPOINT;
-						LOG_TARGET_DEBUG(target,
-							"Breakpoint with unique_id = %" PRIu32 " owns the trigger.",
-							bp->unique_id);
-					}
-				}
-				if (target->debug_reason == DBG_REASON_UNDEFINED) {
-					// by default we report all triggers as breakpoints
+	case RISCV_HALT_EBREAK:
+		target->debug_reason = DBG_REASON_BREAKPOINT;
+		break;
+	case RISCV_HALT_TRIGGER:
+		target->debug_reason = DBG_REASON_UNDEFINED;
+		if (riscv_trigger_detect_hit_bits(target, &r->trigger_hit,
+				&r->need_single_step) != ERROR_OK)
+			return ERROR_FAIL;
+		// FIXME: handle multiple hit bits
+		if (r->trigger_hit != RISCV_TRIGGER_HIT_NOT_FOUND) {
+			/* We scan for breakpoints first. If no breakpoints are found we still
+			 * assume that debug reason is DBG_REASON_BREAKPOINT, unless
+			 * there is a watchpoint match - This is to take
+			 * ETrigger/ITrigger/ICount into account
+			 */
+			LOG_TARGET_DEBUG(target,
+				"Active hit bit is detected, trying to find trigger owner.");
+			for (struct breakpoint *bp = target->breakpoints; bp; bp = bp->next) {
+				if (bp->unique_id == r->trigger_hit) {
 					target->debug_reason = DBG_REASON_BREAKPOINT;
-					for (struct watchpoint *wp = target->watchpoints; wp; wp = wp->next) {
-						if (wp->unique_id == r->trigger_hit) {
-							target->debug_reason = DBG_REASON_WATCHPOINT;
-							LOG_TARGET_DEBUG(target,
-								"Watchpoint with unique_id = %" PRIu32 " owns the trigger.",
-								wp->unique_id);
-						}
+					LOG_TARGET_DEBUG(target,
+						"Breakpoint with unique_id = %" PRIu32 " owns the trigger.",
+						bp->unique_id);
+				}
+			}
+			if (target->debug_reason == DBG_REASON_UNDEFINED) {
+				// by default we report all triggers as breakpoints
+				target->debug_reason = DBG_REASON_BREAKPOINT;
+				for (struct watchpoint *wp = target->watchpoints; wp; wp = wp->next) {
+					if (wp->unique_id == r->trigger_hit) {
+						target->debug_reason = DBG_REASON_WATCHPOINT;
+						LOG_TARGET_DEBUG(target,
+							"Watchpoint with unique_id = %" PRIu32 " owns the trigger.",
+							wp->unique_id);
 					}
 				}
-			} else {
-				LOG_TARGET_DEBUG(target,
-					"No trigger hit found, deriving debug reason without it.");
-				riscv_reg_t dpc;
-				if (riscv_reg_get(target, &dpc, GDB_REGNO_DPC) != ERROR_OK)
-					return ERROR_FAIL;
-				/* Here we don't have the hit bit set (likely, HW does not support it).
-				 * We are trying to guess the state. But here comes the problem:
-				 * if we have etrigger/itrigger/icount raised - we can't really
-				 * distinguish it from the breakpoint or watchpoint. There is not
-				 * much we can do here, except for checking current PC against pending
-				 * breakpoints and hope for the best)
-				 */
-				target->debug_reason = derive_debug_reason_without_hitbit(target, dpc);
 			}
-			break;
-		case RISCV_HALT_INTERRUPT:
-		case RISCV_HALT_GROUP:
-			target->debug_reason = DBG_REASON_DBGRQ;
-			break;
-		case RISCV_HALT_SINGLESTEP:
-			target->debug_reason = DBG_REASON_SINGLESTEP;
-			break;
-		case RISCV_HALT_UNKNOWN:
-			target->debug_reason = DBG_REASON_UNDEFINED;
-			break;
-		case RISCV_HALT_ERROR:
-			return ERROR_FAIL;
+		} else {
+			LOG_TARGET_DEBUG(target,
+				"No trigger hit found, deriving debug reason without it.");
+			riscv_reg_t dpc;
+			if (riscv_reg_get(target, &dpc, GDB_REGNO_DPC) != ERROR_OK)
+				return ERROR_FAIL;
+			/* Here we don't have the hit bit set (likely, HW does not support it).
+			 * We are trying to guess the state. But here comes the problem:
+			 * if we have etrigger/itrigger/icount raised - we can't really
+			 * distinguish it from the breakpoint or watchpoint. There is not
+			 * much we can do here, except for checking current PC against pending
+			 * breakpoints and hope for the best)
+			 */
+			target->debug_reason = derive_debug_reason_without_hitbit(target, dpc);
+		}
+		break;
+	case RISCV_HALT_INTERRUPT:
+	case RISCV_HALT_GROUP:
+		target->debug_reason = DBG_REASON_DBGRQ;
+		break;
+	case RISCV_HALT_SINGLESTEP:
+		target->debug_reason = DBG_REASON_SINGLESTEP;
+		break;
+	case RISCV_HALT_UNKNOWN:
+		target->debug_reason = DBG_REASON_UNDEFINED;
+		break;
+	case RISCV_HALT_ERROR:
+		return ERROR_FAIL;
 	}
 	LOG_TARGET_DEBUG(target, "debug_reason=%d", target->debug_reason);
 
@@ -3222,55 +3222,55 @@ static int riscv_virt2phys_v(struct target *target, target_addr_t virtual, targe
 	const virt2phys_info_t *vsatp_info;
 	/* VS-stage address translation. */
 	switch (vsatp_mode) {
-		case SATP_MODE_SV32:
-			vsatp_info = &sv32;
-			break;
-		case SATP_MODE_SV39:
-			vsatp_info = &sv39;
-			break;
-		case SATP_MODE_SV48:
-			vsatp_info = &sv48;
-			break;
-		case SATP_MODE_SV57:
-			vsatp_info = &sv57;
-			break;
-		case SATP_MODE_OFF:
-			vsatp_info = NULL;
-			LOG_TARGET_DEBUG(target, "vsatp mode is %d. No VS-stage translation. (vsatp: 0x%" PRIx64 ")",
-				vsatp_mode, vsatp);
-			break;
-		default:
-			LOG_TARGET_ERROR(target,
-				"vsatp mode %d is not supported. (vsatp: 0x%" PRIx64 ")",
-				vsatp_mode, vsatp);
-			return ERROR_FAIL;
+	case SATP_MODE_SV32:
+		vsatp_info = &sv32;
+		break;
+	case SATP_MODE_SV39:
+		vsatp_info = &sv39;
+		break;
+	case SATP_MODE_SV48:
+		vsatp_info = &sv48;
+		break;
+	case SATP_MODE_SV57:
+		vsatp_info = &sv57;
+		break;
+	case SATP_MODE_OFF:
+		vsatp_info = NULL;
+		LOG_TARGET_DEBUG(target, "vsatp mode is %d. No VS-stage translation. (vsatp: 0x%" PRIx64 ")",
+			vsatp_mode, vsatp);
+		break;
+	default:
+		LOG_TARGET_ERROR(target,
+			"vsatp mode %d is not supported. (vsatp: 0x%" PRIx64 ")",
+			vsatp_mode, vsatp);
+		return ERROR_FAIL;
 	}
 
 	const virt2phys_info_t *hgatp_info;
 	/* G-stage address translation. */
 	switch (hgatp_mode) {
-		case HGATP_MODE_SV32X4:
-			hgatp_info = &sv32x4;
-			break;
-		case HGATP_MODE_SV39X4:
-			hgatp_info = &sv39x4;
-			break;
-		case HGATP_MODE_SV48X4:
-			hgatp_info = &sv48x4;
-			break;
-		case HGATP_MODE_SV57X4:
-			hgatp_info = &sv57x4;
-			break;
-		case HGATP_MODE_OFF:
-			hgatp_info = NULL;
-			LOG_TARGET_DEBUG(target, "hgatp mode is %d. No G-stage translation. (hgatp: 0x%" PRIx64 ")",
-				hgatp_mode, hgatp);
-			break;
-		default:
-			LOG_TARGET_ERROR(target,
-				"hgatp mode %d is not supported. (hgatp: 0x%" PRIx64 ")",
-				hgatp_mode, hgatp);
-			return ERROR_FAIL;
+	case HGATP_MODE_SV32X4:
+		hgatp_info = &sv32x4;
+		break;
+	case HGATP_MODE_SV39X4:
+		hgatp_info = &sv39x4;
+		break;
+	case HGATP_MODE_SV48X4:
+		hgatp_info = &sv48x4;
+		break;
+	case HGATP_MODE_SV57X4:
+		hgatp_info = &sv57x4;
+		break;
+	case HGATP_MODE_OFF:
+		hgatp_info = NULL;
+		LOG_TARGET_DEBUG(target, "hgatp mode is %d. No G-stage translation. (hgatp: 0x%" PRIx64 ")",
+			hgatp_mode, hgatp);
+		break;
+	default:
+		LOG_TARGET_ERROR(target,
+			"hgatp mode %d is not supported. (hgatp: 0x%" PRIx64 ")",
+			hgatp_mode, hgatp);
+		return ERROR_FAIL;
 	}
 
 	/* For any virtual memory access, the original virtual address is
@@ -3340,26 +3340,26 @@ static int riscv_virt2phys(struct target *target, target_addr_t virtual, target_
 	int satp_mode = get_field(satp_value, RISCV_SATP_MODE(xlen));
 	const virt2phys_info_t *satp_info;
 	switch (satp_mode) {
-		case SATP_MODE_SV32:
-			satp_info = &sv32;
-			break;
-		case SATP_MODE_SV39:
-			satp_info = &sv39;
-			break;
-		case SATP_MODE_SV48:
-			satp_info = &sv48;
-			break;
-		case SATP_MODE_SV57:
-			satp_info = &sv57;
-			break;
-		case SATP_MODE_OFF:
-			LOG_TARGET_ERROR(target, "No translation or protection."
-				      " (satp: 0x%" PRIx64 ")", satp_value);
-			return ERROR_FAIL;
-		default:
-			LOG_TARGET_ERROR(target, "The translation mode is not supported."
-				      " (satp: 0x%" PRIx64 ")", satp_value);
-			return ERROR_FAIL;
+	case SATP_MODE_SV32:
+		satp_info = &sv32;
+		break;
+	case SATP_MODE_SV39:
+		satp_info = &sv39;
+		break;
+	case SATP_MODE_SV48:
+		satp_info = &sv48;
+		break;
+	case SATP_MODE_SV57:
+		satp_info = &sv57;
+		break;
+	case SATP_MODE_OFF:
+		LOG_TARGET_ERROR(target, "No translation or protection."
+			      " (satp: 0x%" PRIx64 ")", satp_value);
+		return ERROR_FAIL;
+	default:
+		LOG_TARGET_ERROR(target, "The translation mode is not supported."
+			      " (satp: 0x%" PRIx64 ")", satp_value);
+		return ERROR_FAIL;
 	}
 
 	return riscv_address_translate(target,
@@ -3503,10 +3503,10 @@ static int riscv_write_memory(struct target *target, target_addr_t address,
 static const char *riscv_get_gdb_arch(const struct target *target)
 {
 	switch (riscv_xlen(target)) {
-		case 32:
-			return "riscv:rv32";
-		case 64:
-			return "riscv:rv64";
+	case 32:
+		return "riscv:rv32";
+	case 64:
+		return "riscv:rv64";
 	}
 	LOG_TARGET_ERROR(target, "Unsupported xlen: %d", riscv_xlen(target));
 	return NULL;
@@ -3524,15 +3524,15 @@ static int riscv_get_gdb_reg_list_internal(struct target *target,
 	}
 
 	switch (reg_class) {
-		case REG_CLASS_GENERAL:
-			*reg_list_size = 33;
-			break;
-		case REG_CLASS_ALL:
-			*reg_list_size = target->reg_cache->num_regs;
-			break;
-		default:
-			LOG_TARGET_ERROR(target, "Unsupported reg_class: %d", reg_class);
-			return ERROR_FAIL;
+	case REG_CLASS_GENERAL:
+		*reg_list_size = 33;
+		break;
+	case REG_CLASS_ALL:
+		*reg_list_size = target->reg_cache->num_regs;
+		break;
+	default:
+		LOG_TARGET_ERROR(target, "Unsupported reg_class: %d", reg_class);
+		return ERROR_FAIL;
 	}
 
 	*reg_list = calloc(*reg_list_size, sizeof(struct reg *));
@@ -3859,25 +3859,25 @@ static int riscv_poll_hart(struct target *target, enum riscv_next_action *next_a
 	enum riscv_hart_state previous_riscv_state = 0;
 	enum target_state previous_target_state = target->state;
 	switch (target->state) {
-		case TARGET_UNKNOWN:
-			/* Special case, handled further down. */
-			previous_riscv_state = RISCV_STATE_UNAVAILABLE;	/* Need to assign something. */
-			break;
-		case TARGET_RUNNING:
-			previous_riscv_state = RISCV_STATE_RUNNING;
-			break;
-		case TARGET_HALTED:
-			previous_riscv_state = RISCV_STATE_HALTED;
-			break;
-		case TARGET_RESET:
-			previous_riscv_state = RISCV_STATE_HALTED;
-			break;
-		case TARGET_DEBUG_RUNNING:
-			previous_riscv_state = RISCV_STATE_RUNNING;
-			break;
-		case TARGET_UNAVAILABLE:
-			previous_riscv_state = RISCV_STATE_UNAVAILABLE;
-			break;
+	case TARGET_UNKNOWN:
+		/* Special case, handled further down. */
+		previous_riscv_state = RISCV_STATE_UNAVAILABLE;	/* Need to assign something. */
+		break;
+	case TARGET_RUNNING:
+		previous_riscv_state = RISCV_STATE_RUNNING;
+		break;
+	case TARGET_HALTED:
+		previous_riscv_state = RISCV_STATE_HALTED;
+		break;
+	case TARGET_RESET:
+		previous_riscv_state = RISCV_STATE_HALTED;
+		break;
+	case TARGET_DEBUG_RUNNING:
+		previous_riscv_state = RISCV_STATE_RUNNING;
+		break;
+	case TARGET_UNAVAILABLE:
+		previous_riscv_state = RISCV_STATE_UNAVAILABLE;
+		break;
 	}
 
 	/* If OpenOCD thinks we're running but this hart is halted then it's time
@@ -3900,79 +3900,79 @@ static int riscv_poll_hart(struct target *target, enum riscv_next_action *next_a
 
 	if (target->state == TARGET_UNKNOWN || state != previous_riscv_state) {
 		switch (state) {
-			case RISCV_STATE_HALTED:
-				if (previous_riscv_state == RISCV_STATE_UNAVAILABLE)
-					LOG_TARGET_INFO(target, "became available (halted)");
-
-				LOG_TARGET_DEBUG(target, "  triggered a halt; previous_target_state=%d",
-					previous_target_state);
-				target->state = TARGET_HALTED;
-				enum riscv_halt_reason halt_reason = riscv_halt_reason(target);
-				if (set_debug_reason(target, halt_reason) != ERROR_OK)
-					return ERROR_FAIL;
+		case RISCV_STATE_HALTED:
+			if (previous_riscv_state == RISCV_STATE_UNAVAILABLE)
+				LOG_TARGET_INFO(target, "became available (halted)");
 
-				if (halt_reason == RISCV_HALT_EBREAK) {
-					int retval;
-					/* Detect if this EBREAK is a semihosting request. If so, handle it. */
-					switch (riscv_semihosting(target, &retval)) {
-						case SEMIHOSTING_NONE:
-							break;
-						case SEMIHOSTING_WAITING:
-							/* This hart should remain halted. */
-							*next_action = RPH_REMAIN_HALTED;
-							break;
-						case SEMIHOSTING_HANDLED:
-							/* This hart should be resumed, along with any other
-							* harts that halted due to haltgroups. */
-							*next_action = RPH_RESUME;
-							return ERROR_OK;
-						case SEMIHOSTING_ERROR:
-							return retval;
-					}
+			LOG_TARGET_DEBUG(target, "  triggered a halt; previous_target_state=%d",
+				previous_target_state);
+			target->state = TARGET_HALTED;
+			enum riscv_halt_reason halt_reason = riscv_halt_reason(target);
+			if (set_debug_reason(target, halt_reason) != ERROR_OK)
+				return ERROR_FAIL;
+
+			if (halt_reason == RISCV_HALT_EBREAK) {
+				int retval;
+				/* Detect if this EBREAK is a semihosting request. If so, handle it. */
+				switch (riscv_semihosting(target, &retval)) {
+				case SEMIHOSTING_NONE:
+					break;
+				case SEMIHOSTING_WAITING:
+					/* This hart should remain halted. */
+					*next_action = RPH_REMAIN_HALTED;
+					break;
+				case SEMIHOSTING_HANDLED:
+					/* This hart should be resumed, along with any other
+					* harts that halted due to haltgroups. */
+					*next_action = RPH_RESUME;
+					return ERROR_OK;
+				case SEMIHOSTING_ERROR:
+					return retval;
 				}
+			}
 
-				if (r->handle_became_halted &&
-						r->handle_became_halted(target, previous_riscv_state) != ERROR_OK)
-					return ERROR_FAIL;
+			if (r->handle_became_halted &&
+					r->handle_became_halted(target, previous_riscv_state) != ERROR_OK)
+				return ERROR_FAIL;
 
-				/* We shouldn't do the callbacks yet. What if
-				 * there are multiple harts that halted at the
-				 * same time? We need to set debug reason on each
-				 * of them before calling a callback, which is
-				 * going to figure out the "current thread". */
+			/* We shouldn't do the callbacks yet. What if
+			 * there are multiple harts that halted at the
+			 * same time? We need to set debug reason on each
+			 * of them before calling a callback, which is
+			 * going to figure out the "current thread". */
 
-				r->halted_needs_event_callback = true;
-				if (previous_target_state == TARGET_DEBUG_RUNNING)
-					r->halted_callback_event = TARGET_EVENT_DEBUG_HALTED;
-				else
-					r->halted_callback_event = TARGET_EVENT_HALTED;
-				break;
-
-			case RISCV_STATE_RUNNING:
-				if (previous_riscv_state == RISCV_STATE_UNAVAILABLE)
-					LOG_TARGET_INFO(target, "became available (running)");
-
-				LOG_TARGET_DEBUG(target, "  triggered running");
-				target->state = TARGET_RUNNING;
-				target->debug_reason = DBG_REASON_NOTHALTED;
-				if (r->handle_became_running &&
-						r->handle_became_running(target, previous_riscv_state) != ERROR_OK)
-					return ERROR_FAIL;
-				break;
-
-			case RISCV_STATE_UNAVAILABLE:
-				LOG_TARGET_DEBUG(target, "  became unavailable");
-				LOG_TARGET_INFO(target, "became unavailable.");
-				target->state = TARGET_UNAVAILABLE;
-				if (r->handle_became_unavailable &&
-						r->handle_became_unavailable(target, previous_riscv_state) != ERROR_OK)
-					return ERROR_FAIL;
-				break;
+			r->halted_needs_event_callback = true;
+			if (previous_target_state == TARGET_DEBUG_RUNNING)
+				r->halted_callback_event = TARGET_EVENT_DEBUG_HALTED;
+			else
+				r->halted_callback_event = TARGET_EVENT_HALTED;
+			break;
+
+		case RISCV_STATE_RUNNING:
+			if (previous_riscv_state == RISCV_STATE_UNAVAILABLE)
+				LOG_TARGET_INFO(target, "became available (running)");
+
+			LOG_TARGET_DEBUG(target, "  triggered running");
+			target->state = TARGET_RUNNING;
+			target->debug_reason = DBG_REASON_NOTHALTED;
+			if (r->handle_became_running &&
+					r->handle_became_running(target, previous_riscv_state) != ERROR_OK)
+				return ERROR_FAIL;
+			break;
 
-			case RISCV_STATE_NON_EXISTENT:
-				LOG_TARGET_ERROR(target, "Hart is non-existent!");
-				target->state = TARGET_UNAVAILABLE;
-				break;
+		case RISCV_STATE_UNAVAILABLE:
+			LOG_TARGET_DEBUG(target, "  became unavailable");
+			LOG_TARGET_INFO(target, "became unavailable.");
+			target->state = TARGET_UNAVAILABLE;
+			if (r->handle_became_unavailable &&
+					r->handle_became_unavailable(target, previous_riscv_state) != ERROR_OK)
+				return ERROR_FAIL;
+			break;
+
+		case RISCV_STATE_NON_EXISTENT:
+			LOG_TARGET_ERROR(target, "Hart is non-existent!");
+			target->state = TARGET_UNAVAILABLE;
+			break;
 		}
 	}
 
@@ -4072,19 +4072,19 @@ int riscv_openocd_poll(struct target *target)
 			return ERROR_FAIL;
 
 		switch (next_action) {
-			case RPH_NONE:
-				if (t->state == TARGET_HALTED)
-					halted++;
-				if (t->state == TARGET_RUNNING ||
-					t->state == TARGET_DEBUG_RUNNING)
-					running++;
-				break;
-			case RPH_REMAIN_HALTED:
-				should_remain_halted++;
-				break;
-			case RPH_RESUME:
-				should_resume++;
-				break;
+		case RPH_NONE:
+			if (t->state == TARGET_HALTED)
+				halted++;
+			if (t->state == TARGET_RUNNING ||
+				t->state == TARGET_DEBUG_RUNNING)
+				running++;
+			break;
+		case RPH_REMAIN_HALTED:
+			should_remain_halted++;
+			break;
+		case RPH_RESUME:
+			should_resume++;
+			break;
 		}
 	}
 
@@ -6186,26 +6186,26 @@ static int disable_trigger_if_dmode(struct target *target, riscv_reg_t tdata1)
 {
 	bool dmode_is_set = false;
 	switch (get_field(tdata1, CSR_TDATA1_TYPE(riscv_xlen(target)))) {
-		case CSR_TDATA1_TYPE_LEGACY:
-			/* On these older cores we don't support software using
-			 * triggers. */
-			dmode_is_set = true;
-			break;
-		case CSR_TDATA1_TYPE_MCONTROL:
-			dmode_is_set = tdata1 & CSR_MCONTROL_DMODE(riscv_xlen(target));
-			break;
-		case CSR_TDATA1_TYPE_MCONTROL6:
-			dmode_is_set = tdata1 & CSR_MCONTROL6_DMODE(riscv_xlen(target));
-			break;
-		case CSR_TDATA1_TYPE_ICOUNT:
-			dmode_is_set = tdata1 & CSR_ICOUNT_DMODE(riscv_xlen(target));
-			break;
-		case CSR_TDATA1_TYPE_ITRIGGER:
-			dmode_is_set = tdata1 & CSR_ITRIGGER_DMODE(riscv_xlen(target));
-			break;
-		case CSR_TDATA1_TYPE_ETRIGGER:
-			dmode_is_set = tdata1 & CSR_ETRIGGER_DMODE(riscv_xlen(target));
-			break;
+	case CSR_TDATA1_TYPE_LEGACY:
+		/* On these older cores we don't support software using
+		 * triggers. */
+		dmode_is_set = true;
+		break;
+	case CSR_TDATA1_TYPE_MCONTROL:
+		dmode_is_set = tdata1 & CSR_MCONTROL_DMODE(riscv_xlen(target));
+		break;
+	case CSR_TDATA1_TYPE_MCONTROL6:
+		dmode_is_set = tdata1 & CSR_MCONTROL6_DMODE(riscv_xlen(target));
+		break;
+	case CSR_TDATA1_TYPE_ICOUNT:
+		dmode_is_set = tdata1 & CSR_ICOUNT_DMODE(riscv_xlen(target));
+		break;
+	case CSR_TDATA1_TYPE_ITRIGGER:
+		dmode_is_set = tdata1 & CSR_ITRIGGER_DMODE(riscv_xlen(target));
+		break;
+	case CSR_TDATA1_TYPE_ETRIGGER:
+		dmode_is_set = tdata1 & CSR_ETRIGGER_DMODE(riscv_xlen(target));
+		break;
 	}
 	if (!dmode_is_set)
 		/* Nothing to do */
diff --git a/src/target/riscv/riscv_reg.c b/src/target/riscv/riscv_reg.c
index e35cd7f4f..ba1bc2a85 100644
--- a/src/target/riscv/riscv_reg.c
+++ b/src/target/riscv/riscv_reg.c
@@ -325,17 +325,17 @@ uint32_t gdb_regno_size(const struct target *target, uint32_t regno)
 	if (regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095) {
 		const unsigned int csr_number = regno - GDB_REGNO_CSR0;
 		switch (csr_number) {
-			case CSR_DCSR:
-			case CSR_MVENDORID:
-			case CSR_MCOUNTINHIBIT:
+		case CSR_DCSR:
+		case CSR_MVENDORID:
+		case CSR_MCOUNTINHIBIT:
 
-			case CSR_FFLAGS:
-			case CSR_FRM:
-			case CSR_FCSR:
+		case CSR_FFLAGS:
+		case CSR_FRM:
+		case CSR_FCSR:
 
-			case CSR_SCOUNTEREN:
-			case CSR_MCOUNTEREN:
-				return 32;
+		case CSR_SCOUNTEREN:
+		case CSR_MCOUNTEREN:
+			return 32;
 		}
 	}
 	return riscv_xlen(target);
@@ -393,154 +393,154 @@ bool riscv_reg_impl_gdb_regno_exist(const struct target *target, uint32_t regno)
 	assert(regno >= GDB_REGNO_CSR0 && regno <= GDB_REGNO_CSR4095);
 	const unsigned int csr_number = regno - GDB_REGNO_CSR0;
 	switch (csr_number) {
-		case CSR_FFLAGS:
-		case CSR_FRM:
-		case CSR_FCSR:
-			return riscv_supports_extension(target, 'F');
-		case CSR_VSTART:
-		case CSR_VXSAT:
-		case CSR_VXRM:
-		case CSR_VL:
-		case CSR_VCSR:
-		case CSR_VTYPE:
-			return vlenb_exists(target);
-		case CSR_SCOUNTEREN:
-		case CSR_SSTATUS:
-		case CSR_STVEC:
-		case CSR_SIP:
-		case CSR_SIE:
-		case CSR_SSCRATCH:
-		case CSR_SEPC:
-		case CSR_SCAUSE:
-		case CSR_STVAL:
-		case CSR_SATP:
-			return riscv_supports_extension(target, 'S');
-		case CSR_MEDELEG:
-		case CSR_MIDELEG:
-			/* "In systems with only M-mode, or with both M-mode and
-			 * U-mode but without U-mode trap support, the medeleg and
-			 * mideleg registers should not exist." */
-			return riscv_supports_extension(target, 'S') ||
-				riscv_supports_extension(target, 'N');
-
-		case CSR_PMPCFG1:
-		case CSR_PMPCFG3:
-		case CSR_CYCLEH:
-		case CSR_TIMEH:
-		case CSR_INSTRETH:
-		case CSR_HPMCOUNTER3H:
-		case CSR_HPMCOUNTER4H:
-		case CSR_HPMCOUNTER5H:
-		case CSR_HPMCOUNTER6H:
-		case CSR_HPMCOUNTER7H:
-		case CSR_HPMCOUNTER8H:
-		case CSR_HPMCOUNTER9H:
-		case CSR_HPMCOUNTER10H:
-		case CSR_HPMCOUNTER11H:
-		case CSR_HPMCOUNTER12H:
-		case CSR_HPMCOUNTER13H:
-		case CSR_HPMCOUNTER14H:
-		case CSR_HPMCOUNTER15H:
-		case CSR_HPMCOUNTER16H:
-		case CSR_HPMCOUNTER17H:
-		case CSR_HPMCOUNTER18H:
-		case CSR_HPMCOUNTER19H:
-		case CSR_HPMCOUNTER20H:
-		case CSR_HPMCOUNTER21H:
-		case CSR_HPMCOUNTER22H:
-		case CSR_HPMCOUNTER23H:
-		case CSR_HPMCOUNTER24H:
-		case CSR_HPMCOUNTER25H:
-		case CSR_HPMCOUNTER26H:
-		case CSR_HPMCOUNTER27H:
-		case CSR_HPMCOUNTER28H:
-		case CSR_HPMCOUNTER29H:
-		case CSR_HPMCOUNTER30H:
-		case CSR_HPMCOUNTER31H:
-		case CSR_MCYCLEH:
-		case CSR_MINSTRETH:
-		case CSR_MHPMCOUNTER4H:
-		case CSR_MHPMCOUNTER5H:
-		case CSR_MHPMCOUNTER6H:
-		case CSR_MHPMCOUNTER7H:
-		case CSR_MHPMCOUNTER8H:
-		case CSR_MHPMCOUNTER9H:
-		case CSR_MHPMCOUNTER10H:
-		case CSR_MHPMCOUNTER11H:
-		case CSR_MHPMCOUNTER12H:
-		case CSR_MHPMCOUNTER13H:
-		case CSR_MHPMCOUNTER14H:
-		case CSR_MHPMCOUNTER15H:
-		case CSR_MHPMCOUNTER16H:
-		case CSR_MHPMCOUNTER17H:
-		case CSR_MHPMCOUNTER18H:
-		case CSR_MHPMCOUNTER19H:
-		case CSR_MHPMCOUNTER20H:
-		case CSR_MHPMCOUNTER21H:
-		case CSR_MHPMCOUNTER22H:
-		case CSR_MHPMCOUNTER23H:
-		case CSR_MHPMCOUNTER24H:
-		case CSR_MHPMCOUNTER25H:
-		case CSR_MHPMCOUNTER26H:
-		case CSR_MHPMCOUNTER27H:
-		case CSR_MHPMCOUNTER28H:
-		case CSR_MHPMCOUNTER29H:
-		case CSR_MHPMCOUNTER30H:
-		case CSR_MHPMCOUNTER31H:
-			return riscv_xlen(target) == 32;
-		case CSR_MCOUNTEREN:
-			return riscv_supports_extension(target, 'U');
-			/* Interrupts M-Mode CSRs. */
-		case CSR_MISELECT:
-		case CSR_MIREG:
-		case CSR_MVIEN:
-		case CSR_MVIP:
-		case CSR_MIEH:
-		case CSR_MIPH:
-			return reg_exists(target, GDB_REGNO_MTOPI);
-		case CSR_MIDELEGH:
-		case CSR_MVIENH:
-		case CSR_MVIPH:
-			return reg_exists(target, GDB_REGNO_MTOPI) &&
-				riscv_xlen(target) == 32 &&
-				riscv_supports_extension(target, 'S');
-			/* Interrupts S-Mode CSRs. */
-		case CSR_SISELECT:
-		case CSR_SIREG:
-		case CSR_STOPI:
-			return reg_exists(target, GDB_REGNO_MTOPI) &&
-				riscv_supports_extension(target, 'S');
-		case CSR_STOPEI:
-			return reg_exists(target, GDB_REGNO_MTOPEI) &&
-				riscv_supports_extension(target, 'S');
-		case CSR_SIEH:
-		case CSR_SIPH:
-			return reg_exists(target, GDB_REGNO_MTOPI) &&
-				riscv_xlen(target) == 32 &&
-				riscv_supports_extension(target, 'S');
-			/* Interrupts Hypervisor and VS CSRs. */
-		case CSR_HVIEN:
-		case CSR_HVICTL:
-		case CSR_HVIPRIO1:
-		case CSR_HVIPRIO2:
-		case CSR_VSISELECT:
-		case CSR_VSIREG:
-		case CSR_VSTOPI:
-			return reg_exists(target, GDB_REGNO_MTOPI) &&
-				riscv_supports_extension(target, 'H');
-		case CSR_VSTOPEI:
-			return reg_exists(target, GDB_REGNO_MTOPEI) &&
-				riscv_supports_extension(target, 'H');
-		case CSR_HIDELEGH:
-		case CSR_HVIENH:
-		case CSR_HVIPH:
-		case CSR_HVIPRIO1H:
-		case CSR_HVIPRIO2H:
-		case CSR_VSIEH:
-		case CSR_VSIPH:
-			return reg_exists(target, GDB_REGNO_MTOPI) &&
-				riscv_xlen(target) == 32 &&
-				riscv_supports_extension(target, 'H');
+	case CSR_FFLAGS:
+	case CSR_FRM:
+	case CSR_FCSR:
+		return riscv_supports_extension(target, 'F');
+	case CSR_VSTART:
+	case CSR_VXSAT:
+	case CSR_VXRM:
+	case CSR_VL:
+	case CSR_VCSR:
+	case CSR_VTYPE:
+		return vlenb_exists(target);
+	case CSR_SCOUNTEREN:
+	case CSR_SSTATUS:
+	case CSR_STVEC:
+	case CSR_SIP:
+	case CSR_SIE:
+	case CSR_SSCRATCH:
+	case CSR_SEPC:
+	case CSR_SCAUSE:
+	case CSR_STVAL:
+	case CSR_SATP:
+		return riscv_supports_extension(target, 'S');
+	case CSR_MEDELEG:
+	case CSR_MIDELEG:
+		/* "In systems with only M-mode, or with both M-mode and
+		 * U-mode but without U-mode trap support, the medeleg and
+		 * mideleg registers should not exist." */
+		return riscv_supports_extension(target, 'S') ||
+			riscv_supports_extension(target, 'N');
+
+	case CSR_PMPCFG1:
+	case CSR_PMPCFG3:
+	case CSR_CYCLEH:
+	case CSR_TIMEH:
+	case CSR_INSTRETH:
+	case CSR_HPMCOUNTER3H:
+	case CSR_HPMCOUNTER4H:
+	case CSR_HPMCOUNTER5H:
+	case CSR_HPMCOUNTER6H:
+	case CSR_HPMCOUNTER7H:
+	case CSR_HPMCOUNTER8H:
+	case CSR_HPMCOUNTER9H:
+	case CSR_HPMCOUNTER10H:
+	case CSR_HPMCOUNTER11H:
+	case CSR_HPMCOUNTER12H:
+	case CSR_HPMCOUNTER13H:
+	case CSR_HPMCOUNTER14H:
+	case CSR_HPMCOUNTER15H:
+	case CSR_HPMCOUNTER16H:
+	case CSR_HPMCOUNTER17H:
+	case CSR_HPMCOUNTER18H:
+	case CSR_HPMCOUNTER19H:
+	case CSR_HPMCOUNTER20H:
+	case CSR_HPMCOUNTER21H:
+	case CSR_HPMCOUNTER22H:
+	case CSR_HPMCOUNTER23H:
+	case CSR_HPMCOUNTER24H:
+	case CSR_HPMCOUNTER25H:
+	case CSR_HPMCOUNTER26H:
+	case CSR_HPMCOUNTER27H:
+	case CSR_HPMCOUNTER28H:
+	case CSR_HPMCOUNTER29H:
+	case CSR_HPMCOUNTER30H:
+	case CSR_HPMCOUNTER31H:
+	case CSR_MCYCLEH:
+	case CSR_MINSTRETH:
+	case CSR_MHPMCOUNTER4H:
+	case CSR_MHPMCOUNTER5H:
+	case CSR_MHPMCOUNTER6H:
+	case CSR_MHPMCOUNTER7H:
+	case CSR_MHPMCOUNTER8H:
+	case CSR_MHPMCOUNTER9H:
+	case CSR_MHPMCOUNTER10H:
+	case CSR_MHPMCOUNTER11H:
+	case CSR_MHPMCOUNTER12H:
+	case CSR_MHPMCOUNTER13H:
+	case CSR_MHPMCOUNTER14H:
+	case CSR_MHPMCOUNTER15H:
+	case CSR_MHPMCOUNTER16H:
+	case CSR_MHPMCOUNTER17H:
+	case CSR_MHPMCOUNTER18H:
+	case CSR_MHPMCOUNTER19H:
+	case CSR_MHPMCOUNTER20H:
+	case CSR_MHPMCOUNTER21H:
+	case CSR_MHPMCOUNTER22H:
+	case CSR_MHPMCOUNTER23H:
+	case CSR_MHPMCOUNTER24H:
+	case CSR_MHPMCOUNTER25H:
+	case CSR_MHPMCOUNTER26H:
+	case CSR_MHPMCOUNTER27H:
+	case CSR_MHPMCOUNTER28H:
+	case CSR_MHPMCOUNTER29H:
+	case CSR_MHPMCOUNTER30H:
+	case CSR_MHPMCOUNTER31H:
+		return riscv_xlen(target) == 32;
+	case CSR_MCOUNTEREN:
+		return riscv_supports_extension(target, 'U');
+		/* Interrupts M-Mode CSRs. */
+	case CSR_MISELECT:
+	case CSR_MIREG:
+	case CSR_MVIEN:
+	case CSR_MVIP:
+	case CSR_MIEH:
+	case CSR_MIPH:
+		return reg_exists(target, GDB_REGNO_MTOPI);
+	case CSR_MIDELEGH:
+	case CSR_MVIENH:
+	case CSR_MVIPH:
+		return reg_exists(target, GDB_REGNO_MTOPI) &&
+			riscv_xlen(target) == 32 &&
+			riscv_supports_extension(target, 'S');
+		/* Interrupts S-Mode CSRs. */
+	case CSR_SISELECT:
+	case CSR_SIREG:
+	case CSR_STOPI:
+		return reg_exists(target, GDB_REGNO_MTOPI) &&
+			riscv_supports_extension(target, 'S');
+	case CSR_STOPEI:
+		return reg_exists(target, GDB_REGNO_MTOPEI) &&
+			riscv_supports_extension(target, 'S');
+	case CSR_SIEH:
+	case CSR_SIPH:
+		return reg_exists(target, GDB_REGNO_MTOPI) &&
+			riscv_xlen(target) == 32 &&
+			riscv_supports_extension(target, 'S');
+		/* Interrupts Hypervisor and VS CSRs. */
+	case CSR_HVIEN:
+	case CSR_HVICTL:
+	case CSR_HVIPRIO1:
+	case CSR_HVIPRIO2:
+	case CSR_VSISELECT:
+	case CSR_VSIREG:
+	case CSR_VSTOPI:
+		return reg_exists(target, GDB_REGNO_MTOPI) &&
+			riscv_supports_extension(target, 'H');
+	case CSR_VSTOPEI:
+		return reg_exists(target, GDB_REGNO_MTOPEI) &&
+			riscv_supports_extension(target, 'H');
+	case CSR_HIDELEGH:
+	case CSR_HVIENH:
+	case CSR_HVIPH:
+	case CSR_HVIPRIO1H:
+	case CSR_HVIPRIO2H:
+	case CSR_VSIEH:
+	case CSR_VSIPH:
+		return reg_exists(target, GDB_REGNO_MTOPI) &&
+			riscv_xlen(target) == 32 &&
+			riscv_supports_extension(target, 'H');
 	}
 	return is_known_standard_csr(csr_number);
 }
diff --git a/src/target/riscv/riscv_reg_impl.h b/src/target/riscv/riscv_reg_impl.h
index a86020252..17e66935b 100644
--- a/src/target/riscv/riscv_reg_impl.h
+++ b/src/target/riscv/riscv_reg_impl.h
@@ -194,29 +194,29 @@ static inline bool riscv_reg_impl_gdb_regno_cacheable(enum gdb_regno regno,
 	/* Most CSRs won't ...
 
[truncated message content]

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1259-g56141bb34

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  56141bb3490d8f39aad6c7a9be5a70f24d93a991 (commit)
      from  5754aebc49450cc0da5c8a90ebd059160d21f256 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 56141bb3490d8f39aad6c7a9be5a70f24d93a991
Author: Bernhard Rosenkränzer <be...@ba...>
Date:   Tue May 6 01:34:18 2025 +0200

    target: riscv: Drop new typedefs added by the updated riscv-debug-spec files
    
    The advantage of this patch is that it brings the new code closer to
    OpenOCD coding style - the disadvantage is that it involves modifying
    autogenerated files, making it harder to drop in new versions when
    riscv-debug-spec changes.
    
    Change-Id: I4c317e11ab1652333b0bb44168f953ef452d3ef5
    Signed-off-by: Bernhard Rosenkränzer <be...@ba...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8896
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/src/target/riscv/batch.c b/src/target/riscv/batch.c
index ec68b3798..56143808f 100644
--- a/src/target/riscv/batch.c
+++ b/src/target/riscv/batch.c
@@ -172,7 +172,7 @@ static unsigned int decode_dmi(const struct riscv_batch *batch, char *text,
 	for (unsigned int i = 0; i < ARRAY_SIZE(description); i++) {
 		if (riscv_get_dmi_address(batch->target, description[i].address)
 				== address) {
-			const riscv_debug_reg_ctx_t context = {
+			const struct riscv_debug_reg_ctx context = {
 				.XLEN = { .value = 0, .is_set = false },
 				.DXLEN = { .value = 0, .is_set = false },
 				.abits = { .value = 0, .is_set = false },
diff --git a/src/target/riscv/debug_defines.c b/src/target/riscv/debug_defines.c
index 81644b2c2..0fe43a161 100644
--- a/src/target/riscv/debug_defines.c
+++ b/src/target/riscv/debug_defines.c
@@ -4,9 +4,9 @@
 #include "debug_defines.h"
 #include <stddef.h>
 #include <assert.h>
-static riscv_debug_reg_field_list_t dtm_idcode_get_version(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_idcode_get_version(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "Version",
 			.lsb = 0x1c,
@@ -18,9 +18,9 @@ static riscv_debug_reg_field_list_t dtm_idcode_get_version(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t dtm_idcode_get_partnumber(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_idcode_get_partnumber(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "PartNumber",
 			.lsb = 0xc,
@@ -32,9 +32,9 @@ static riscv_debug_reg_field_list_t dtm_idcode_get_partnumber(riscv_debug_reg_ct
 	return result;
 }
 
-static riscv_debug_reg_field_list_t dtm_idcode_get_manufid(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_idcode_get_manufid(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "ManufId",
 			.lsb = 1,
@@ -46,9 +46,9 @@ static riscv_debug_reg_field_list_t dtm_idcode_get_manufid(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t dtm_idcode_get_1(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_idcode_get_1(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "1",
 			.lsb = 0,
@@ -72,9 +72,9 @@ static const char *dtm_dtmcs_version_values[16] = {
 	[1] = "1_0",
 	[15] = "custom"
 };
-static riscv_debug_reg_field_list_t dtm_dtmcs_get_abits(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_dtmcs_get_abits(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "abits",
 			.lsb = 4,
@@ -86,9 +86,9 @@ static riscv_debug_reg_field_list_t dtm_dtmcs_get_abits(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t dtm_dtmcs_get_errinfo(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_dtmcs_get_errinfo(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "errinfo",
 			.lsb = 0x12,
@@ -100,9 +100,9 @@ static riscv_debug_reg_field_list_t dtm_dtmcs_get_errinfo(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t dtm_dtmcs_get_dtmhardreset(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_dtmcs_get_dtmhardreset(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dtmhardreset",
 			.lsb = 0x11,
@@ -114,9 +114,9 @@ static riscv_debug_reg_field_list_t dtm_dtmcs_get_dtmhardreset(riscv_debug_reg_c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t dtm_dtmcs_get_dmireset(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_dtmcs_get_dmireset(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dmireset",
 			.lsb = 0x10,
@@ -128,9 +128,9 @@ static riscv_debug_reg_field_list_t dtm_dtmcs_get_dmireset(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t dtm_dtmcs_get_idle(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_dtmcs_get_idle(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "idle",
 			.lsb = 0xc,
@@ -142,9 +142,9 @@ static riscv_debug_reg_field_list_t dtm_dtmcs_get_idle(riscv_debug_reg_ctx_t con
 	return result;
 }
 
-static riscv_debug_reg_field_list_t dtm_dtmcs_get_dmistat(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_dtmcs_get_dmistat(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dmistat",
 			.lsb = 0xa,
@@ -156,9 +156,9 @@ static riscv_debug_reg_field_list_t dtm_dtmcs_get_dmistat(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t dtm_dtmcs_get_version(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_dtmcs_get_version(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "version",
 			.lsb = 0,
@@ -171,10 +171,10 @@ static riscv_debug_reg_field_list_t dtm_dtmcs_get_version(riscv_debug_reg_ctx_t
 }
 
 static const char *dtm_dmi_op_values[4] = {};
-static riscv_debug_reg_field_list_t dtm_dmi_get_address(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_dmi_get_address(struct riscv_debug_reg_ctx context)
 {
 	assert(context.abits.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "address",
 			.lsb = 0x22,
@@ -186,9 +186,9 @@ static riscv_debug_reg_field_list_t dtm_dmi_get_address(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t dtm_dmi_get_data(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_dmi_get_data(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "data",
 			.lsb = 2,
@@ -200,9 +200,9 @@ static riscv_debug_reg_field_list_t dtm_dmi_get_data(riscv_debug_reg_ctx_t conte
 	return result;
 }
 
-static riscv_debug_reg_field_list_t dtm_dmi_get_op(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list dtm_dmi_get_op(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "op",
 			.lsb = 0,
@@ -276,9 +276,9 @@ static const char *csr_dcsr_mprven_values[2] = {
 	[0] = "disabled",
 	[1] = "enabled"
 };
-static riscv_debug_reg_field_list_t csr_dcsr_get_stoptime(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_stoptime(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "stoptime",
 			.lsb = 9,
@@ -290,9 +290,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_stoptime(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_cause(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_cause(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "cause",
 			.lsb = 6,
@@ -304,9 +304,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_cause(riscv_debug_reg_ctx_t con
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_v(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_v(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "v",
 			.lsb = 5,
@@ -318,9 +318,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_v(riscv_debug_reg_ctx_t context
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_mprven(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_mprven(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "mprven",
 			.lsb = 4,
@@ -332,9 +332,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_mprven(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_nmip(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_nmip(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "nmip",
 			.lsb = 3,
@@ -346,9 +346,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_nmip(riscv_debug_reg_ctx_t cont
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_debugver(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_debugver(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "debugver",
 			.lsb = 0x1c,
@@ -360,9 +360,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_debugver(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_extcause(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_extcause(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "extcause",
 			.lsb = 0x18,
@@ -374,9 +374,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_extcause(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_step(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_step(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "step",
 			.lsb = 2,
@@ -388,9 +388,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_step(riscv_debug_reg_ctx_t cont
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_cetrig(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_cetrig(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "cetrig",
 			.lsb = 0x13,
@@ -402,9 +402,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_cetrig(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_pelp(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_pelp(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "pelp",
 			.lsb = 0x12,
@@ -416,9 +416,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_pelp(riscv_debug_reg_ctx_t cont
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_ebreakvs(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_ebreakvs(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "ebreakvs",
 			.lsb = 0x11,
@@ -430,9 +430,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_ebreakvs(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_ebreakvu(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_ebreakvu(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "ebreakvu",
 			.lsb = 0x10,
@@ -444,9 +444,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_ebreakvu(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_ebreakm(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_ebreakm(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "ebreakm",
 			.lsb = 0xf,
@@ -458,9 +458,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_ebreakm(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_ebreaks(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_ebreaks(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "ebreaks",
 			.lsb = 0xd,
@@ -472,9 +472,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_ebreaks(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_ebreaku(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_ebreaku(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "ebreaku",
 			.lsb = 0xc,
@@ -486,9 +486,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_ebreaku(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_stepie(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_stepie(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "stepie",
 			.lsb = 0xb,
@@ -500,9 +500,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_stepie(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_stopcount(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_stopcount(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "stopcount",
 			.lsb = 0xa,
@@ -514,9 +514,9 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_stopcount(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dcsr_get_prv(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dcsr_get_prv(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "prv",
 			.lsb = 0,
@@ -528,10 +528,10 @@ static riscv_debug_reg_field_list_t csr_dcsr_get_prv(riscv_debug_reg_ctx_t conte
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dpc_get_dpc(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dpc_get_dpc(struct riscv_debug_reg_ctx context)
 {
 	assert(context.DXLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dpc",
 			.lsb = 0,
@@ -543,10 +543,10 @@ static riscv_debug_reg_field_list_t csr_dpc_get_dpc(riscv_debug_reg_ctx_t contex
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dscratch0_get_dscratch0(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dscratch0_get_dscratch0(struct riscv_debug_reg_ctx context)
 {
 	assert(context.DXLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dscratch0",
 			.lsb = 0,
@@ -558,10 +558,10 @@ static riscv_debug_reg_field_list_t csr_dscratch0_get_dscratch0(riscv_debug_reg_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_dscratch1_get_dscratch1(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_dscratch1_get_dscratch1(struct riscv_debug_reg_ctx context)
 {
 	assert(context.DXLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dscratch1",
 			.lsb = 0,
@@ -573,10 +573,10 @@ static riscv_debug_reg_field_list_t csr_dscratch1_get_dscratch1(riscv_debug_reg_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_tselect_get_index(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tselect_get_index(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "index",
 			.lsb = 0,
@@ -603,10 +603,10 @@ static const char *csr_tdata1_dmode_values[2] = {
 	[0] = "both",
 	[1] = "dmode"
 };
-static riscv_debug_reg_field_list_t csr_tdata1_get_dmode(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tdata1_get_dmode(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dmode",
 			.lsb = (context.XLEN.value + -5),
@@ -618,10 +618,10 @@ static riscv_debug_reg_field_list_t csr_tdata1_get_dmode(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_tdata1_get_type(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tdata1_get_type(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "type",
 			.lsb = (context.XLEN.value + -4),
@@ -633,10 +633,10 @@ static riscv_debug_reg_field_list_t csr_tdata1_get_type(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_tdata1_get_data(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tdata1_get_data(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "data",
 			.lsb = 0,
@@ -648,10 +648,10 @@ static riscv_debug_reg_field_list_t csr_tdata1_get_data(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_tdata2_get_data(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tdata2_get_data(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "data",
 			.lsb = 0,
@@ -663,10 +663,10 @@ static riscv_debug_reg_field_list_t csr_tdata2_get_data(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_tdata3_get_data(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tdata3_get_data(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "data",
 			.lsb = 0,
@@ -682,9 +682,9 @@ static const char *csr_tinfo_version_values[256] = {
 	[0] = "0",
 	[1] = "1"
 };
-static riscv_debug_reg_field_list_t csr_tinfo_get_version(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tinfo_get_version(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "version",
 			.lsb = 0x18,
@@ -696,9 +696,9 @@ static riscv_debug_reg_field_list_t csr_tinfo_get_version(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_tinfo_get_info(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tinfo_get_info(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "info",
 			.lsb = 0,
@@ -714,9 +714,9 @@ static const char *csr_tcontrol_mte_values[2] = {
 	[0] = "disabled",
 	[1] = "enabled"
 };
-static riscv_debug_reg_field_list_t csr_tcontrol_get_mpte(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tcontrol_get_mpte(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "mpte",
 			.lsb = 7,
@@ -728,9 +728,9 @@ static riscv_debug_reg_field_list_t csr_tcontrol_get_mpte(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_tcontrol_get_mte(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tcontrol_get_mte(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "mte",
 			.lsb = 3,
@@ -742,9 +742,9 @@ static riscv_debug_reg_field_list_t csr_tcontrol_get_mte(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_scontext_get_data(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_scontext_get_data(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "data",
 			.lsb = 0,
@@ -756,9 +756,9 @@ static riscv_debug_reg_field_list_t csr_scontext_get_data(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontext_get_hcontext(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontext_get_hcontext(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "hcontext",
 			.lsb = 0,
@@ -804,10 +804,10 @@ static const char *csr_mcontrol_match_values[16] = {
 	[12] = "not_mask_low",
 	[13] = "not_mask_high"
 };
-static riscv_debug_reg_field_list_t csr_mcontrol_get_dmode(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_dmode(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dmode",
 			.lsb = (context.XLEN.value + -5),
@@ -819,10 +819,10 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_dmode(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_type(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_type(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "type",
 			.lsb = (context.XLEN.value + -4),
@@ -834,10 +834,10 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_type(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_maskmax(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_maskmax(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "maskmax",
 			.lsb = (context.XLEN.value + -0xb),
@@ -849,9 +849,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_maskmax(riscv_debug_reg_ctx
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_match(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_match(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "match",
 			.lsb = 7,
@@ -863,9 +863,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_match(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_m(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_m(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "m",
 			.lsb = 6,
@@ -877,9 +877,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_m(riscv_debug_reg_ctx_t con
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_s(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_s(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "s",
 			.lsb = 4,
@@ -891,9 +891,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_s(riscv_debug_reg_ctx_t con
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_u(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_u(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "u",
 			.lsb = 3,
@@ -905,9 +905,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_u(riscv_debug_reg_ctx_t con
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_sizehi(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_sizehi(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "sizehi",
 			.lsb = 0x15,
@@ -919,9 +919,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_sizehi(riscv_debug_reg_ctx_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_hit(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_hit(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "hit",
 			.lsb = 0x14,
@@ -933,9 +933,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_hit(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_execute(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_execute(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "execute",
 			.lsb = 2,
@@ -947,9 +947,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_execute(riscv_debug_reg_ctx
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_select(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_select(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "select",
 			.lsb = 0x13,
@@ -961,9 +961,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_select(riscv_debug_reg_ctx_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_timing(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_timing(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "timing",
 			.lsb = 0x12,
@@ -975,9 +975,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_timing(riscv_debug_reg_ctx_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_sizelo(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_sizelo(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "sizelo",
 			.lsb = 0x10,
@@ -989,9 +989,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_sizelo(riscv_debug_reg_ctx_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_action(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_action(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "action",
 			.lsb = 0xc,
@@ -1003,9 +1003,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_action(riscv_debug_reg_ctx_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_chain(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_chain(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "chain",
 			.lsb = 0xb,
@@ -1017,9 +1017,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_chain(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_store(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_store(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "store",
 			.lsb = 1,
@@ -1031,9 +1031,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol_get_store(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol_get_load(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol_get_load(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "load",
 			.lsb = 0,
@@ -1092,10 +1092,10 @@ static const char *csr_mcontrol6_uncertainen_values[2] = {
 	[0] = "disabled",
 	[1] = "enabled"
 };
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_dmode(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_dmode(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dmode",
 			.lsb = (context.XLEN.value + -5),
@@ -1107,10 +1107,10 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_dmode(riscv_debug_reg_ctx_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_type(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_type(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "type",
 			.lsb = (context.XLEN.value + -4),
@@ -1122,9 +1122,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_type(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_match(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_match(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "match",
 			.lsb = 7,
@@ -1136,9 +1136,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_match(riscv_debug_reg_ctx_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_m(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_m(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "m",
 			.lsb = 6,
@@ -1150,9 +1150,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_m(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_uncertainen(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_uncertainen(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "uncertainen",
 			.lsb = 5,
@@ -1164,9 +1164,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_uncertainen(riscv_debug_re
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_s(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_s(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "s",
 			.lsb = 4,
@@ -1178,9 +1178,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_s(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_u(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_u(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "u",
 			.lsb = 3,
@@ -1192,9 +1192,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_u(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_uncertain(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_uncertain(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "uncertain",
 			.lsb = 0x1a,
@@ -1206,9 +1206,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_uncertain(riscv_debug_reg_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_hit1(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_hit1(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "hit1",
 			.lsb = 0x19,
@@ -1220,9 +1220,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_hit1(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_vs(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_vs(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "vs",
 			.lsb = 0x18,
@@ -1234,9 +1234,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_vs(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_vu(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_vu(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "vu",
 			.lsb = 0x17,
@@ -1248,9 +1248,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_vu(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_hit0(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_hit0(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "hit0",
 			.lsb = 0x16,
@@ -1262,9 +1262,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_hit0(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_select(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_select(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "select",
 			.lsb = 0x15,
@@ -1276,9 +1276,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_select(riscv_debug_reg_ctx
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_execute(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_execute(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "execute",
 			.lsb = 2,
@@ -1290,9 +1290,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_execute(riscv_debug_reg_ct
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_size(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_size(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "size",
 			.lsb = 0x10,
@@ -1304,9 +1304,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_size(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_action(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_action(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "action",
 			.lsb = 0xc,
@@ -1318,9 +1318,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_action(riscv_debug_reg_ctx
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_chain(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_chain(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "chain",
 			.lsb = 0xb,
@@ -1332,9 +1332,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_chain(riscv_debug_reg_ctx_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_store(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_store(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "store",
 			.lsb = 1,
@@ -1346,9 +1346,9 @@ static riscv_debug_reg_field_list_t csr_mcontrol6_get_store(riscv_debug_reg_ctx_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_mcontrol6_get_load(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_mcontrol6_get_load(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "load",
 			.lsb = 0,
@@ -1369,10 +1369,10 @@ static const char *csr_icount_action_values[64] = {
 	[8] = "external0",
 	[9] = "external1"
 };
-static riscv_debug_reg_field_list_t csr_icount_get_dmode(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_icount_get_dmode(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dmode",
 			.lsb = (context.XLEN.value + -5),
@@ -1384,10 +1384,10 @@ static riscv_debug_reg_field_list_t csr_icount_get_dmode(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_icount_get_type(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_icount_get_type(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "type",
 			.lsb = (context.XLEN.value + -4),
@@ -1399,9 +1399,9 @@ static riscv_debug_reg_field_list_t csr_icount_get_type(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_icount_get_m(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_icount_get_m(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "m",
 			.lsb = 9,
@@ -1413,9 +1413,9 @@ static riscv_debug_reg_field_list_t csr_icount_get_m(riscv_debug_reg_ctx_t conte
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_icount_get_pending(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_icount_get_pending(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "pending",
 			.lsb = 8,
@@ -1427,9 +1427,9 @@ static riscv_debug_reg_field_list_t csr_icount_get_pending(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_icount_get_s(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_icount_get_s(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "s",
 			.lsb = 7,
@@ -1441,9 +1441,9 @@ static riscv_debug_reg_field_list_t csr_icount_get_s(riscv_debug_reg_ctx_t conte
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_icount_get_u(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_icount_get_u(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "u",
 			.lsb = 6,
@@ -1455,9 +1455,9 @@ static riscv_debug_reg_field_list_t csr_icount_get_u(riscv_debug_reg_ctx_t conte
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_icount_get_vs(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_icount_get_vs(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "vs",
 			.lsb = 0x1a,
@@ -1469,9 +1469,9 @@ static riscv_debug_reg_field_list_t csr_icount_get_vs(riscv_debug_reg_ctx_t cont
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_icount_get_vu(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_icount_get_vu(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "vu",
 			.lsb = 0x19,
@@ -1483,9 +1483,9 @@ static riscv_debug_reg_field_list_t csr_icount_get_vu(riscv_debug_reg_ctx_t cont
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_icount_get_hit(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_icount_get_hit(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "hit",
 			.lsb = 0x18,
@@ -1497,9 +1497,9 @@ static riscv_debug_reg_field_list_t csr_icount_get_hit(riscv_debug_reg_ctx_t con
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_icount_get_count(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_icount_get_count(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "count",
 			.lsb = 0xa,
@@ -1511,9 +1511,9 @@ static riscv_debug_reg_field_list_t csr_icount_get_count(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_icount_get_action(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_icount_get_action(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "action",
 			.lsb = 0,
@@ -1534,10 +1534,10 @@ static const char *csr_itrigger_action_values[64] = {
 	[8] = "external0",
 	[9] = "external1"
 };
-static riscv_debug_reg_field_list_t csr_itrigger_get_hit(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_itrigger_get_hit(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "hit",
 			.lsb = (context.XLEN.value + -6),
@@ -1549,10 +1549,10 @@ static riscv_debug_reg_field_list_t csr_itrigger_get_hit(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_itrigger_get_dmode(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_itrigger_get_dmode(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dmode",
 			.lsb = (context.XLEN.value + -5),
@@ -1564,10 +1564,10 @@ static riscv_debug_reg_field_list_t csr_itrigger_get_dmode(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_itrigger_get_type(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_itrigger_get_type(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "type",
 			.lsb = (context.XLEN.value + -4),
@@ -1579,9 +1579,9 @@ static riscv_debug_reg_field_list_t csr_itrigger_get_type(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_itrigger_get_m(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_itrigger_get_m(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "m",
 			.lsb = 9,
@@ -1593,9 +1593,9 @@ static riscv_debug_reg_field_list_t csr_itrigger_get_m(riscv_debug_reg_ctx_t con
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_itrigger_get_s(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_itrigger_get_s(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "s",
 			.lsb = 7,
@@ -1607,9 +1607,9 @@ static riscv_debug_reg_field_list_t csr_itrigger_get_s(riscv_debug_reg_ctx_t con
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_itrigger_get_u(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_itrigger_get_u(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "u",
 			.lsb = 6,
@@ -1621,9 +1621,9 @@ static riscv_debug_reg_field_list_t csr_itrigger_get_u(riscv_debug_reg_ctx_t con
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_itrigger_get_vs(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_itrigger_get_vs(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "vs",
 			.lsb = 0xc,
@@ -1635,9 +1635,9 @@ static riscv_debug_reg_field_list_t csr_itrigger_get_vs(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_itrigger_get_vu(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_itrigger_get_vu(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "vu",
 			.lsb = 0xb,
@@ -1649,9 +1649,9 @@ static riscv_debug_reg_field_list_t csr_itrigger_get_vu(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_itrigger_get_nmi(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_itrigger_get_nmi(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "nmi",
 			.lsb = 0xa,
@@ -1663,9 +1663,9 @@ static riscv_debug_reg_field_list_t csr_itrigger_get_nmi(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_itrigger_get_action(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_itrigger_get_action(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "action",
 			.lsb = 0,
@@ -1686,10 +1686,10 @@ static const char *csr_etrigger_action_values[64] = {
 	[8] = "external0",
 	[9] = "external1"
 };
-static riscv_debug_reg_field_list_t csr_etrigger_get_hit(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_etrigger_get_hit(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "hit",
 			.lsb = (context.XLEN.value + -6),
@@ -1701,10 +1701,10 @@ static riscv_debug_reg_field_list_t csr_etrigger_get_hit(riscv_debug_reg_ctx_t c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_etrigger_get_dmode(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_etrigger_get_dmode(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dmode",
 			.lsb = (context.XLEN.value + -5),
@@ -1716,10 +1716,10 @@ static riscv_debug_reg_field_list_t csr_etrigger_get_dmode(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_etrigger_get_type(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_etrigger_get_type(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "type",
 			.lsb = (context.XLEN.value + -4),
@@ -1731,9 +1731,9 @@ static riscv_debug_reg_field_list_t csr_etrigger_get_type(riscv_debug_reg_ctx_t
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_etrigger_get_m(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_etrigger_get_m(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "m",
 			.lsb = 9,
@@ -1745,9 +1745,9 @@ static riscv_debug_reg_field_list_t csr_etrigger_get_m(riscv_debug_reg_ctx_t con
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_etrigger_get_s(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_etrigger_get_s(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "s",
 			.lsb = 7,
@@ -1759,9 +1759,9 @@ static riscv_debug_reg_field_list_t csr_etrigger_get_s(riscv_debug_reg_ctx_t con
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_etrigger_get_u(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_etrigger_get_u(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "u",
 			.lsb = 6,
@@ -1773,9 +1773,9 @@ static riscv_debug_reg_field_list_t csr_etrigger_get_u(riscv_debug_reg_ctx_t con
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_etrigger_get_vs(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_etrigger_get_vs(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "vs",
 			.lsb = 0xc,
@@ -1787,9 +1787,9 @@ static riscv_debug_reg_field_list_t csr_etrigger_get_vs(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_etrigger_get_vu(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_etrigger_get_vu(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "vu",
 			.lsb = 0xb,
@@ -1801,9 +1801,9 @@ static riscv_debug_reg_field_list_t csr_etrigger_get_vu(riscv_debug_reg_ctx_t co
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_etrigger_get_action(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_etrigger_get_action(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "action",
 			.lsb = 0,
@@ -1824,10 +1824,10 @@ static const char *csr_tmexttrigger_action_values[64] = {
 	[8] = "external0",
 	[9] = "external1"
 };
-static riscv_debug_reg_field_list_t csr_tmexttrigger_get_hit(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tmexttrigger_get_hit(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "hit",
 			.lsb = (context.XLEN.value + -6),
@@ -1839,10 +1839,10 @@ static riscv_debug_reg_field_list_t csr_tmexttrigger_get_hit(riscv_debug_reg_ctx
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_tmexttrigger_get_dmode(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tmexttrigger_get_dmode(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "dmode",
 			.lsb = (context.XLEN.value + -5),
@@ -1854,10 +1854,10 @@ static riscv_debug_reg_field_list_t csr_tmexttrigger_get_dmode(riscv_debug_reg_c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_tmexttrigger_get_type(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tmexttrigger_get_type(struct riscv_debug_reg_ctx context)
 {
 	assert(context.XLEN.is_set);
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "type",
 			.lsb = (context.XLEN.value + -4),
@@ -1869,9 +1869,9 @@ static riscv_debug_reg_field_list_t csr_tmexttrigger_get_type(riscv_debug_reg_ct
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_tmexttrigger_get_select(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tmexttrigger_get_select(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "select",
 			.lsb = 6,
@@ -1883,9 +1883,9 @@ static riscv_debug_reg_field_list_t csr_tmexttrigger_get_select(riscv_debug_reg_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_tmexttrigger_get_intctl(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tmexttrigger_get_intctl(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "intctl",
 			.lsb = 0x16,
@@ -1897,9 +1897,9 @@ static riscv_debug_reg_field_list_t csr_tmexttrigger_get_intctl(riscv_debug_reg_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_tmexttrigger_get_action(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_tmexttrigger_get_action(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "action",
 			.lsb = 0,
@@ -1920,9 +1920,9 @@ static const char *csr_textra32_sselect_values[4] = {
 	[1] = "scontext",
 	[2] = "asid"
 };
-static riscv_debug_reg_field_list_t csr_textra32_get_mhvalue(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_textra32_get_mhvalue(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "mhvalue",
 			.lsb = 0x1a,
@@ -1934,9 +1934,9 @@ static riscv_debug_reg_field_list_t csr_textra32_get_mhvalue(riscv_debug_reg_ctx
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_textra32_get_mhselect(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_textra32_get_mhselect(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "mhselect",
 			.lsb = 0x17,
@@ -1948,9 +1948,9 @@ static riscv_debug_reg_field_list_t csr_textra32_get_mhselect(riscv_debug_reg_ct
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_textra32_get_svalue(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_textra32_get_svalue(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "svalue",
 			.lsb = 2,
@@ -1962,9 +1962,9 @@ static riscv_debug_reg_field_list_t csr_textra32_get_svalue(riscv_debug_reg_ctx_
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_textra32_get_sbytemask(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_textra32_get_sbytemask(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "sbytemask",
 			.lsb = 0x12,
@@ -1976,9 +1976,9 @@ static riscv_debug_reg_field_list_t csr_textra32_get_sbytemask(riscv_debug_reg_c
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_textra32_get_sselect(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_textra32_get_sselect(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "sselect",
 			.lsb = 0,
@@ -1990,9 +1990,9 @@ static riscv_debug_reg_field_list_t csr_textra32_get_sselect(riscv_debug_reg_ctx
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_textra64_get_mhvalue(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_textra64_get_mhvalue(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_reg_field_list result = {
 		.field = {
 			.name = "mhvalue",
 			.lsb = 0x33,
@@ -2004,9 +2004,9 @@ static riscv_debug_reg_field_list_t csr_textra64_get_mhvalue(riscv_debug_reg_ctx
 	return result;
 }
 
-static riscv_debug_reg_field_list_t csr_textra64_get_mhselect(riscv_debug_reg_ctx_t context)
+static struct riscv_debug_reg_field_list csr_textra64_get_mhselect(struct riscv_debug_reg_ctx context)
 {
-	riscv_debug_reg_field_list_t result = {
+	struct riscv_debug_re...
 
[truncated message content]