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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1094-g6872f7e40

From: openocd-gerrit <ope...@us...> - 2025-07-25 16:53:40

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  6872f7e406ad74f366f55947d23becd5a5faca15 (commit)
      from  7e83049c93d8ec008b54e9dfe3774b9fc1c5ddcf (commit)

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- Log -----------------------------------------------------------------
commit 6872f7e406ad74f366f55947d23becd5a5faca15
Author: Marc Schink <de...@za...>
Date:   Tue Jul 8 07:57:27 2025 +0000

    adapter/xds110: Hide '(dis)connected' message
    
    Print a debug message rather than an info message because this
    information is not of importance for normal users.
    
    Change-Id: Ie91565df455ffc0bfe976d1782dd4318bfd2d30b
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8986
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/xds110.c b/src/jtag/drivers/xds110.c
index d1bb70590..6b3ca5cfb 100644
--- a/src/jtag/drivers/xds110.c
+++ b/src/jtag/drivers/xds110.c
@@ -428,7 +428,7 @@ static bool usb_connect(void)
 
 	/* Log the results */
 	if (result == 0)
-		LOG_INFO("XDS110: connected");
+		LOG_DEBUG("XDS110: connected");
 	else
 		LOG_ERROR("XDS110: failed to connect");
 
@@ -448,7 +448,7 @@ static void usb_disconnect(void)
 		xds110.ctx = NULL;
 	}
 
-	LOG_INFO("XDS110: disconnected");
+	LOG_DEBUG("XDS110: disconnected");
 }
 
 static bool usb_read(unsigned char *buffer, int size, int *bytes_read,

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/xds110.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1093-g7e83049c9

From: openocd-gerrit <ope...@us...> - 2025-07-25 16:52:46

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  7e83049c93d8ec008b54e9dfe3774b9fc1c5ddcf (commit)
       via  f11b677decdb78fa70c980640daef8757312c1e6 (commit)
      from  5d3f53363bc461fbc88f4e690c08f85057e17f5d (commit)

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- Log -----------------------------------------------------------------
commit 7e83049c93d8ec008b54e9dfe3774b9fc1c5ddcf
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jul 4 16:37:38 2025 +0200

    tcl: add support for stm32mp2xx targets and boards
    
    Add support for the targets stm32mp21x, stm32mp23x and stm32mp25x.
    Add support for the boards stm32mp235f-dk and stm32mp257f-dk.
    
    The board stm32mp215f-dk has no configuration file as it only
    provides a generic JTAG/SWD connector for the stm32mp21x SoC.
    
    Change-Id: I0256bebd8a5d5600066d8ae191d83344a35d3d37
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8985
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>

diff --git a/tcl/board/st/stm32mp235f-dk.cfg b/tcl/board/st/stm32mp235f-dk.cfg
new file mode 100644
index 000000000..1f660f19e
--- /dev/null
+++ b/tcl/board/st/stm32mp235f-dk.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MB1605 with stm32mp23x
+# https://www.st.com/en/evaluation-tools/stm32mp257f-dk.html
+
+source [find interface/stlink.cfg]
+
+transport select swd
+
+source [find target/st/stm32mp23x.cfg]
+
+reset_config srst_only
diff --git a/tcl/board/st/stm32mp257f-dk.cfg b/tcl/board/st/stm32mp257f-dk.cfg
new file mode 100644
index 000000000..182f1d00c
--- /dev/null
+++ b/tcl/board/st/stm32mp257f-dk.cfg
@@ -0,0 +1,12 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# MB1605
+# https://www.st.com/en/evaluation-tools/stm32mp257f-dk.html
+
+source [find interface/stlink.cfg]
+
+transport select swd
+
+source [find target/st/stm32mp25x.cfg]
+
+reset_config srst_only
diff --git a/tcl/target/st/stm32mp21x.cfg b/tcl/target/st/stm32mp21x.cfg
new file mode 100644
index 000000000..f4073a9f5
--- /dev/null
+++ b/tcl/target/st/stm32mp21x.cfg
@@ -0,0 +1,222 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP21x
+# STM32MP21x devices support both JTAG and SWD transports.
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp21x
+}
+
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA35] } {
+	set EN_CA35 1
+}
+if { ! [info exists EN_CM33] } {
+	set EN_CM33 1
+}
+
+set _ENDIAN little
+
+# jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x16503041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f
+if { [using_jtag] } {
+	swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+# define AXI & APB Memory Access Ports
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 2
+target create $_CHIPNAME.ap3 mem_ap -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
+
+# define the Cortex-A35
+cti create $_CHIPNAME.cti.a35 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80220000
+target create $_CHIPNAME.a35 aarch64 -dap $_CHIPNAME.dap -ap-num 1 -dbgbase 0x80210000 \
+	-cti $_CHIPNAME.cti.a35 -defer-examine
+
+# define the Cortex-M33
+target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 3 -defer-examine
+cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 3 -baseaddr 0xe0042000
+
+# define the system CTIs
+cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80080000
+cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80090000
+
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x800A0000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 1 -baseaddr 0x80040000
+
+targets $_CHIPNAME.a35
+
+reset_config srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# wait 1 seconds for bootrom
+adapter srst delay 1000
+
+# set CSW for AXI
+$_CHIPNAME.dap apsel 2
+$_CHIPNAME.dap apcsw 0x12800000
+
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP0 and AXI
+proc _enable_debug {} {
+	# Enable DBGMCU clock in RC
+	$::_CHIPNAME.axi mww 0x44200520 0x500
+
+	# set debug enable bits in DBGMCU_CR to get ap3/cm33 visible
+	$::_CHIPNAME.ap0 mww 0x80001004 0x7
+
+	# Freeze watchdogs on CPU halt
+	$::_CHIPNAME.axi mww 0x440a003c 0x00000026
+	$::_CHIPNAME.axi mww 0x440a0040 0x00000038
+}
+
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+# Uses AXI
+proc _rcc_enable_traceclk {} {
+	# set bit TRACEEN in RCC_DBGCFGR to clock TPIU
+	target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0
+}
+
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP0, AP1 and AP3
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80001004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return
+	}
+
+	if { $halt } {
+		if { $::EN_CA35 } {
+			$::_CHIPNAME.ap1 arp_examine
+			$::_CHIPNAME.ap1 arp_halt
+			$::_CHIPNAME.ap1 mww 0x80210300 0
+			target_mmw $::_CHIPNAME.ap1 0x80210088 0x00004000 0
+		}
+		if { $::EN_CM33 } {
+			$::_CHIPNAME.ap3 arp_examine
+			$::_CHIPNAME.ap3 arp_halt
+			$::_CHIPNAME.ap3 mww 0xe000edf0 0xa05f0001
+		}
+	}
+
+	# alert wrapper that debugger is ready
+	$::_CHIPNAME.ap0 mww 0x80001004 0x07
+}
+
+lappend _telnet_autocomplete_skip _enable_dbgmcu_on_devboot
+# In DEV BOOT the BootROM does not completes the sequence to enable the
+# visibility of DBGMCU on AP0.
+# Write a value in DBGMCU_DBG_AUTH_DEV from CID1.
+# Returns 1 if DEV BOOT is detected
+# Uses AP2 (AXI bus)
+proc _enable_dbgmcu_on_devboot {} {
+	$::_CHIPNAME.axi mww 0x44230004 0
+	set boot_pins [expr {[$::_CHIPNAME.axi read_memory 0x44230000 32 1] & 0xf}]
+	if {$boot_pins != 0x3 && $boot_pins != 0xc} {
+		return 0
+	}
+
+	set rifsc_rimc_cr [$::_CHIPNAME.axi read_memory 0x42080c00 32 1]
+	if {$rifsc_rimc_cr != 0x00008710} {
+		echo "RIFSC_RIMC_CR modified, skip activation of DBGMCU"
+		return 1
+	}
+
+	# Enable DBGMCU clock in RC
+	$::_CHIPNAME.axi mww 0x44200520 0x500
+
+	# Change DAP (AXI) CID, write in DBGMCU, set back DAP CID
+	$::_CHIPNAME.axi mww 0x42080c00 0x00008110
+	$::_CHIPNAME.axi mww 0x440A0104 1
+	$::_CHIPNAME.axi mww 0x42080c00 0x00008710
+	return 1
+}
+
+$_CHIPNAME.m33 configure -event reset-assert { }
+
+$_CHIPNAME.axi configure -event reset-assert-post {
+	adapter assert srst
+}
+
+$_CHIPNAME.axi configure -event reset-deassert-pre {
+	adapter deassert srst deassert trst
+	$::_CHIPNAME.axi arp_examine
+	set is_dev_boot [_enable_dbgmcu_on_devboot]
+	if { !$is_dev_boot } {
+		_handshake_with_wrapper $halt
+	}
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35 } {
+		$::_CHIPNAME.a35 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.a35 arp_halt
+		}
+	}
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap3 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.ap3 arp_halt
+			$::_CHIPNAME.m33 arp_halt
+		}
+	}
+}
+
+$_CHIPNAME.axi configure -event examine-end {
+	set is_dev_boot [_enable_dbgmcu_on_devboot]
+	if { $is_dev_boot } {
+		echo "Dev boot detected"
+	}
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35 } {
+		$::_CHIPNAME.a35 arp_examine
+	}
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap3 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+	}
+}
diff --git a/tcl/target/st/stm32mp23x.cfg b/tcl/target/st/stm32mp23x.cfg
new file mode 100644
index 000000000..015f816e4
--- /dev/null
+++ b/tcl/target/st/stm32mp23x.cfg
@@ -0,0 +1,215 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP23x
+# STM32MP23x devices support both JTAG and SWD transports.
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp23x
+}
+
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA35_0] } {
+	set EN_CA35_0 1
+}
+if { ! [info exists EN_CA35_1] } {
+	set EN_CA35_1 1
+}
+if { ! [info exists EN_CM33] } {
+	set EN_CM33   1
+}
+
+set _ENDIAN little
+
+# jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x16505041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f
+if { [using_jtag] } {
+	swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+# define AXI & APB Memory Access Ports
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 4
+target create $_CHIPNAME.ap8 mem_ap -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+
+# define the first Cortex-A35
+cti create $_CHIPNAME.cti.a35_0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80220000
+target create $_CHIPNAME.a35_0 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80210000 \
+	-cti $_CHIPNAME.cti.a35_0 -defer-examine
+
+# define the second Cortex-A35
+cti create $_CHIPNAME.cti.a35_1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80320000
+target create $_CHIPNAME.a35_1 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80310000 \
+	-cti $_CHIPNAME.cti.a35_1 -defer-examine
+
+# define the Cortex-M33
+target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr 0xe0042000
+
+# define the system CTIs
+cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80090000
+cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800a0000
+
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800b0000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80050000
+
+targets $_CHIPNAME.a35_0
+
+target smp $_CHIPNAME.a35_0 $_CHIPNAME.a35_1
+$_CHIPNAME.a35_0 configure -rtos hwthread
+$_CHIPNAME.a35_1 configure -rtos hwthread
+
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# wait 1 seconds for bootrom
+adapter srst delay 1000
+
+# set CSW for AXI
+$_CHIPNAME.dap apsel 4
+$_CHIPNAME.dap apcsw 0x12800000
+
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP0 and AXI
+proc _enable_debug {} {
+	# set debug enable bits in DBGMCU_CR to get ap8/cm33 visible
+	$::_CHIPNAME.ap0 mww 0x80010004 0x17
+
+	# Freeze watchdogs on CPU halt
+	$::_CHIPNAME.axi mww 0x4a010008 0x00000000
+	$::_CHIPNAME.axi mww 0x4a01003c 0x00000026
+	$::_CHIPNAME.axi mww 0x4a010040 0x00000038
+	$::_CHIPNAME.axi mww 0x4a010044 0x00000400
+	$::_CHIPNAME.axi mww 0x4a010048 0x00000400
+	$::_CHIPNAME.axi mww 0x4a01004c 0x00000600
+}
+
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+# Uses AXI
+proc _rcc_enable_traceclk {} {
+	# set bit TRACEEN in RCC_DBGCFGR to clock TPIU
+	target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0
+}
+
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP0
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80010004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return;
+	}
+
+	if { $halt } {
+		if { $::EN_CA35_0 || $::EN_CA35_1 } {
+			$::_CHIPNAME.ap0 arp_examine
+			$::_CHIPNAME.ap0 arp_halt
+		}
+		if { $::EN_CA35_0 } {
+			$::_CHIPNAME.ap0 mww 0x80210300 0
+			target_mmw $::_CHIPNAME.ap0 0x80210088 0x00004000 0
+		}
+		if { $::EN_CA35_1 } {
+			$::_CHIPNAME.ap0 mww 0x80310300 0
+			target_mmw $::_CHIPNAME.ap0 0x80310088 0x00004000 0
+		}
+		if { $::EN_CM33 } {
+			$::_CHIPNAME.ap8 arp_examine
+			$::_CHIPNAME.ap8 arp_halt
+			$::_CHIPNAME.ap8 mww 0xe000edf0 0xa05f0001
+		}
+	}
+
+	# alert wrapper that debugger is ready
+	$::_CHIPNAME.ap0 mww 0x80010004 0x17
+}
+
+$_CHIPNAME.m33 configure -event reset-assert { }
+
+$_CHIPNAME.axi configure -event reset-assert-post {
+	adapter assert srst
+}
+
+$_CHIPNAME.axi configure -event reset-deassert-pre {
+	adapter deassert srst deassert trst
+
+	$::_CHIPNAME.ap0 arp_examine
+	_handshake_with_wrapper $halt
+
+	$::_CHIPNAME.axi arp_examine
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35_0 } {
+		$::_CHIPNAME.a35_0 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.a35_0 arp_halt
+		}
+	}
+	if { $::EN_CA35_1 } {
+		$::_CHIPNAME.a35_1 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.a35_1 arp_halt
+		}
+	}
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap8 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.m33 arp_halt
+		}
+	}
+}
+
+$_CHIPNAME.axi configure -event examine-end {
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35_0 } {
+		$::_CHIPNAME.a35_0 arp_examine
+	}
+	if { $::EN_CA35_1 } {
+		$::_CHIPNAME.a35_1 arp_examine
+	}
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap8 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+	}
+}
diff --git a/tcl/target/st/stm32mp25x.cfg b/tcl/target/st/stm32mp25x.cfg
new file mode 100644
index 000000000..6807d64a1
--- /dev/null
+++ b/tcl/target/st/stm32mp25x.cfg
@@ -0,0 +1,247 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# STMicroelectronics STM32MP25x
+# STM32MP25x devices support both JTAG and SWD transports.
+
+# HLA does not support multi-cores nor custom CSW nor AP other than 0
+if { [using_hla] } {
+	echo "ERROR: HLA transport cannot work with this target."
+	shutdown
+}
+
+source [find target/swj-dp.tcl]
+source [find mem_helper.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME stm32mp25x
+}
+
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA35_0] } {
+	set EN_CA35_0 1
+}
+if { ! [info exists EN_CA35_1] } {
+	set EN_CA35_1 1
+}
+if { ! [info exists EN_CM33] } {
+	set EN_CM33   1
+}
+if { ! [info exists EN_CM0P] } {
+	set EN_CM0P   1
+}
+
+set _ENDIAN little
+
+# jtag scan chain
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Chip Level TAP Controller, only in jtag mode
+if { [info exists CLCTAPID] } {
+	set _CLCTAPID $CLCTAPID
+} else {
+	set _CLCTAPID 0x16505041
+}
+
+swj_newdap $_CHIPNAME tap -expected-id $_CPUTAPID -irlen 4 -ircapture 0x01 -irmask 0x0f
+if { [using_jtag] } {
+	swj_newdap $_CHIPNAME.clc tap -expected-id $_CLCTAPID -irlen 5
+}
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap
+
+# define AXI & APB Memory Access Ports
+# NOTE: do not change the order of target create
+target create $_CHIPNAME.ap0 mem_ap -dap $_CHIPNAME.dap -ap-num 0
+target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 4
+target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+target create $_CHIPNAME.ap8 mem_ap -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+
+# define the first Cortex-A35
+cti create $_CHIPNAME.cti.a35_0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80220000
+target create $_CHIPNAME.a35_0 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80210000 \
+	-cti $_CHIPNAME.cti.a35_0 -defer-examine
+
+# define the second Cortex-A35
+cti create $_CHIPNAME.cti.a35_1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80320000
+target create $_CHIPNAME.a35_1 aarch64 -dap $_CHIPNAME.dap -ap-num 0 -dbgbase 0x80310000 \
+	-cti $_CHIPNAME.cti.a35_1 -defer-examine
+
+# define the Cortex-M33
+target create $_CHIPNAME.m33 cortex_m -dap $_CHIPNAME.dap -ap-num 8 -defer-examine
+cti create $_CHIPNAME.cti.m33 -dap $_CHIPNAME.dap -ap-num 8 -baseaddr 0xe0042000
+
+# define the Cortex-M0+
+target create $_CHIPNAME.m0p cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
+cti create $_CHIPNAME.cti.m0p -dap $_CHIPNAME.dap -ap-num 2 -baseaddr 0xf0000000
+
+# define the system CTIs
+cti create $_CHIPNAME.cti.sys0 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80090000
+cti create $_CHIPNAME.cti.sys1 -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800a0000
+
+swo  create $_CHIPNAME.swo  -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x800b0000
+tpiu create $_CHIPNAME.tpiu -dap $_CHIPNAME.dap -ap-num 0 -baseaddr 0x80050000
+
+targets $_CHIPNAME.a35_0
+
+target smp $_CHIPNAME.a35_0 $_CHIPNAME.a35_1
+$_CHIPNAME.a35_0 configure -rtos hwthread
+$_CHIPNAME.a35_1 configure -rtos hwthread
+
+reset_config srst_gates_jtag srst_pulls_trst
+
+adapter speed 5000
+adapter srst pulse_width 200
+# wait 1 seconds for bootrom
+adapter srst delay 1000
+
+# set CSW for AXI
+$_CHIPNAME.dap apsel 4
+$_CHIPNAME.dap apcsw 0x12800000
+
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_ap2_cm0p
+proc _enable_ap2_cm0p {} {
+	# set bits C3LPEN and C3EN in RCC_C3CFGR to enable AP2 and CM0+ clock
+	target_mmw $::_CHIPNAME.axi 0x54200490 6 0
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP0 and AXI
+proc _enable_debug {} {
+	# set debug enable bits in DBGMCU_CR to get ap2/cm0+ and ap8/cm33 visible
+	# set DBG_SWD_SEL_N bit in DBGMCU_CR to get ap2/cm0+ on main debug interface
+	$::_CHIPNAME.ap0 mww 0x80010004 0x17
+
+	if { $::EN_CM0P } {
+		_enable_ap2_cm0p
+	}
+
+	# Freeze watchdogs on CPU halt
+	$::_CHIPNAME.axi mww 0x4a010008 0x00000000
+	$::_CHIPNAME.axi mww 0x4a01003c 0x00000026
+	$::_CHIPNAME.axi mww 0x4a010040 0x00000038
+	$::_CHIPNAME.axi mww 0x4a010044 0x00000400
+	$::_CHIPNAME.axi mww 0x4a010048 0x00000400
+	$::_CHIPNAME.axi mww 0x4a01004c 0x00000600
+}
+
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+# Uses AXI
+proc _rcc_enable_traceclk {} {
+	# set bit TRACEEN in RCC_DBGCFGR to clock TPIU
+	target_mmw $::_CHIPNAME.axi 0x44200520 0x200 0
+}
+
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP0
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap0 read_memory 0x80010004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return;
+	}
+
+	if { $halt } {
+		if { $::EN_CA35_0 || $::EN_CA35_1 } {
+			$::_CHIPNAME.ap0 arp_examine
+			$::_CHIPNAME.ap0 arp_halt
+		}
+		if { $::EN_CA35_0 } {
+			$::_CHIPNAME.ap0 mww 0x80210300 0
+			target_mmw $::_CHIPNAME.ap0 0x80210088 0x00004000 0
+		}
+		if { $::EN_CA35_1 } {
+			$::_CHIPNAME.ap0 mww 0x80310300 0
+			target_mmw $::_CHIPNAME.ap0 0x80310088 0x00004000 0
+		}
+		if { $::EN_CM33 } {
+			$::_CHIPNAME.ap8 arp_examine
+			$::_CHIPNAME.ap8 arp_halt
+			$::_CHIPNAME.ap8 mww 0xe000edf0 0xa05f0001
+		}
+	}
+
+	# alert wrapper that debugger is ready
+	$::_CHIPNAME.ap0 mww 0x80010004 0x17
+}
+
+$_CHIPNAME.m33 configure -event reset-assert { }
+$_CHIPNAME.m0p configure -event reset-assert { }
+
+$_CHIPNAME.axi configure -event reset-assert-post {
+	adapter assert srst
+}
+
+$_CHIPNAME.axi configure -event reset-deassert-pre {
+	adapter deassert srst deassert trst
+
+	$::_CHIPNAME.ap0 arp_examine
+	_handshake_with_wrapper $halt
+
+	$::_CHIPNAME.axi arp_examine
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35_0 } {
+		$::_CHIPNAME.a35_0 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.a35_0 arp_halt
+		}
+	}
+	if { $::EN_CA35_1 } {
+		$::_CHIPNAME.a35_1 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.a35_1 arp_halt
+		}
+	}
+	if { $::EN_CM0P } {
+		$::_CHIPNAME.ap2 arp_examine
+		$::_CHIPNAME.m0p arp_examine
+	}
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap8 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.m33 arp_halt
+		}
+	}
+}
+
+$_CHIPNAME.m0p configure -event examine-start {
+	_enable_ap2_cm0p
+}
+
+$_CHIPNAME.axi configure -event examine-end {
+	_enable_debug
+	_rcc_enable_traceclk
+	if { $::EN_CA35_0 } {
+		$::_CHIPNAME.a35_0 arp_examine
+	}
+	if { $::EN_CA35_1 } {
+		$::_CHIPNAME.a35_1 arp_examine
+	}
+	if { $::EN_CM33 } {
+		$::_CHIPNAME.ap8 arp_examine
+		$::_CHIPNAME.m33 arp_examine
+	}
+	if { $::EN_CM0P } {
+		$::_CHIPNAME.ap2 arp_examine
+		$::_CHIPNAME.m0p arp_examine
+	}
+}

commit f11b677decdb78fa70c980640daef8757312c1e6
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jul 4 16:34:29 2025 +0200

    tcl: stm32mp15x: modify handshake to open debug port, add hwthread
    
    Align the target script to the handshake implemented in the latest
    version of stm32wrapper4dbg to get access to the debug port.
    
    Use hwthread with the SMP node.
    
    Allow ignoring/masking some CPU from the configuration with the
    variables EN_<cpu>.
    
    Change-Id: I7117dd7df20b4f6b6e28f911e3e91ee763bdd200
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8984
    Tested-by: jenkins

diff --git a/tcl/target/st/stm32mp15x.cfg b/tcl/target/st/stm32mp15x.cfg
index bcdda73e9..979a5a491 100644
--- a/tcl/target/st/stm32mp15x.cfg
+++ b/tcl/target/st/stm32mp15x.cfg
@@ -18,6 +18,17 @@ if { [info exists CHIPNAME] } {
 	set _CHIPNAME stm32mp15x
 }
 
+# Set to 0 to prevent CPU examine. Default examine them
+if { ! [info exists EN_CA7_0] } {
+	set EN_CA7_0 1
+}
+if { ! [info exists EN_CA7_1] } {
+	set EN_CA7_1 1
+}
+if { ! [info exists EN_CM4] } {
+	set EN_CM4   1
+}
+
 if { [info exists CPUTAPID] } {
 	set _CPUTAPID $CPUTAPID
 } else {
@@ -42,20 +53,21 @@ if { [using_jtag] } {
 
 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
 
-# FIXME: Cortex-M code requires target accessible during reset, but this is not possible in STM32MP1
-# so defer-examine it until the reset framework get merged
 # NOTE: keep ap-num and dbgbase to speed-up examine after reset
 # NOTE: do not change the order of target create
 target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
 target create $_CHIPNAME.ap2 mem_ap -dap $_CHIPNAME.dap -ap-num 2
 target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
-target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
-target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000
+target create $_CHIPNAME.cpu0 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000 -defer-examine
+target create $_CHIPNAME.cpu1 cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 1 -dbgbase 0xE00D2000 -defer-examine
 target create $_CHIPNAME.cm4 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -defer-examine
 
 targets $_CHIPNAME.cpu0
 
 target smp $_CHIPNAME.cpu0 $_CHIPNAME.cpu1
+$_CHIPNAME.cpu0 configure -rtos hwthread
+$_CHIPNAME.cpu1 configure -rtos hwthread
+
 $_CHIPNAME.cpu0 cortex_a maskisr on
 $_CHIPNAME.cpu1 cortex_a maskisr on
 $_CHIPNAME.cpu0 cortex_a dacrfixup on
@@ -96,7 +108,16 @@ proc axi_nsecure {} {
 
 axi_secure
 
-proc dbgmcu_enable_debug {} {
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP1
+proc _enable_debug {} {
 	# set debug enable bits in DBGMCU_CR to get ap2 and cm4 visible
 	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000007}
 	# freeze watchdog 1 and 2 on cores halted
@@ -104,30 +125,97 @@ proc dbgmcu_enable_debug {} {
 	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
 }
 
-proc toggle_cpu0_dbg_claim0 {} {
-	# toggle CPU0 DBG_CLAIM[0]
-	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
-	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP1
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap1 read_memory 0xe0081004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return
+	}
+
+	if { $halt }  {
+		$::_CHIPNAME.ap1 arp_halt
+		if { $::EN_CA7_0 } {
+			$::_CHIPNAME.ap1 arp_halt
+			$::_CHIPNAME.ap1 mww 0xe00d0300 0
+			target_mmw $::_CHIPNAME.ap1 0xe00d0088 0x00004000 0
+		}
+	}
+
+	$::_CHIPNAME.ap1 mww 0xe0081004 0x7
 }
 
-proc detect_cpu1 {} {
+lappend _telnet_autocomplete_skip _detect_cpu1
+# Uses AP1
+proc _detect_cpu1 {} {
+	if { !$::EN_CA7_1 } {
+		return
+	}
+
 	set cpu1_prsr [$::_CHIPNAME.ap1 read_memory 0xE00D2314 32 1]
 	set dual_core [expr {$cpu1_prsr & 1}]
-	if {! $dual_core} {$::_CHIPNAME.cpu1 configure -defer-examine}
+	if { !$dual_core } {
+		set ::EN_CA7_1 0
+	}
 }
 
-proc rcc_enable_traceclk {} {
+lappend _telnet_autocomplete_skip _rcc_enable_traceclk
+proc _rcc_enable_traceclk {} {
 	$::_CHIPNAME.ap2 mww 0x5000080c 0x301
 }
 
 # FIXME: most of handler below will be removed once reset framework get merged
-$_CHIPNAME.ap1  configure -event reset-deassert-pre  {adapter deassert srst deassert trst;catch {dap init};catch {$::_CHIPNAME.dap apid 1}}
-$_CHIPNAME.ap2  configure -event reset-deassert-pre  {dbgmcu_enable_debug;rcc_enable_traceclk}
-$_CHIPNAME.cpu0 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu0 arp_examine}
-$_CHIPNAME.cpu1 configure -event reset-deassert-pre  {$::_CHIPNAME.cpu1 arp_examine allow-defer}
-$_CHIPNAME.cpu0 configure -event reset-deassert-post {toggle_cpu0_dbg_claim0}
-$_CHIPNAME.cm4  configure -event reset-deassert-post {$::_CHIPNAME.cm4 arp_examine;if {[$::_CHIPNAME.ap2 curstate] == "halted"} {$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_poll;$::_CHIPNAME.cm4 arp_halt}}
-$_CHIPNAME.ap1  configure -event examine-start       {dap init}
-$_CHIPNAME.ap2  configure -event examine-start       {dbgmcu_enable_debug}
-$_CHIPNAME.cpu0 configure -event examine-end         {detect_cpu1}
-$_CHIPNAME.ap2  configure -event examine-end         {rcc_enable_traceclk;$::_CHIPNAME.cm4 arp_examine}
+$_CHIPNAME.cm4  configure -event reset-assert { }
+
+$_CHIPNAME.ap1  configure -event reset-assert-post {
+	adapter assert srst
+}
+
+$_CHIPNAME.ap1  configure -event reset-deassert-pre {
+	adapter deassert srst deassert trst
+	$::_CHIPNAME.ap1 arp_examine
+	_handshake_with_wrapper $halt
+	if { $::EN_CA7_0 } {
+		$::_CHIPNAME.cpu0 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.cpu0 arp_halt
+		}
+	}
+	if { $::EN_CA7_1 } {
+		$::_CHIPNAME.cpu1 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.cpu1 arp_halt
+		}
+	}
+	_enable_debug
+}
+
+$_CHIPNAME.ap2  configure -event reset-deassert-pre {
+	_rcc_enable_traceclk
+	if { $::EN_CM4 } {
+		$::_CHIPNAME.cm4 arp_examine
+		if { $halt } {
+			$::_CHIPNAME.cm4 arp_halt
+		}
+	}
+}
+
+$_CHIPNAME.ap1 configure -event examine-end {
+	_enable_debug
+	_detect_cpu1
+	if { $::EN_CA7_0 } {
+		$::_CHIPNAME.cpu0 arp_examine
+	}
+	if { $::EN_CA7_1 } {
+		$::_CHIPNAME.cpu1 arp_examine
+	}
+}
+
+$_CHIPNAME.ap2  configure -event examine-end {
+	_rcc_enable_traceclk
+	if { $::EN_CM4 } {
+		$::_CHIPNAME.cm4 arp_examine
+	}
+}

-----------------------------------------------------------------------

Summary of changes:
 .../st/{nucleo-u083rc.cfg => stm32mp235f-dk.cfg}   |   6 +-
 .../{st_nucleo_wb55.cfg => st/stm32mp257f-dk.cfg}  |   7 +-
 tcl/target/st/stm32mp15x.cfg                       | 132 +++++++++--
 tcl/target/st/stm32mp21x.cfg                       | 222 ++++++++++++++++++
 tcl/target/st/stm32mp23x.cfg                       | 215 ++++++++++++++++++
 tcl/target/st/stm32mp25x.cfg                       | 247 +++++++++++++++++++++
 6 files changed, 800 insertions(+), 29 deletions(-)
 copy tcl/board/st/{nucleo-u083rc.cfg => stm32mp235f-dk.cfg} (50%)
 copy tcl/board/{st_nucleo_wb55.cfg => st/stm32mp257f-dk.cfg} (54%)
 create mode 100644 tcl/target/st/stm32mp21x.cfg
 create mode 100644 tcl/target/st/stm32mp23x.cfg
 create mode 100644 tcl/target/st/stm32mp25x.cfg


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Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1091-g5d3f53363

From: openocd-gerrit <ope...@us...> - 2025-07-25 16:52:13

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 5d3f53363bc461fbc88f4e690c08f85057e17f5d
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jul 4 16:29:47 2025 +0200

    tcl: stm32mp13x: modify handshake to open debug port
    
    Align the target script to the handshake implemented in the latest
    version of stm32wrapper4dbg to get access to the debug port.
    
    Change-Id: Ia1c7773330fda776abb4385331fddbf431d11c39
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8983
    Tested-by: jenkins

diff --git a/tcl/target/st/stm32mp13x.cfg b/tcl/target/st/stm32mp13x.cfg
index bcf25c904..164e0ff1f 100644
--- a/tcl/target/st/stm32mp13x.cfg
+++ b/tcl/target/st/stm32mp13x.cfg
@@ -46,7 +46,7 @@ dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.tap -ignore-syspwrupack
 # NOTE: do not change the order of target create
 target create $_CHIPNAME.ap1 mem_ap -dap $_CHIPNAME.dap -ap-num 1
 target create $_CHIPNAME.axi mem_ap -dap $_CHIPNAME.dap -ap-num 0
-target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000
+target create $_CHIPNAME.cpu cortex_a -dap $_CHIPNAME.dap -ap-num 1 -coreid 0 -dbgbase 0xE00D0000 -defer-examine
 
 $_CHIPNAME.cpu cortex_a maskisr on
 $_CHIPNAME.cpu cortex_a dacrfixup on
@@ -76,27 +76,59 @@ proc axi_nsecure {} {
 
 axi_secure
 
-proc dbgmcu_enable_debug {} {
+# mmw with target selection
+proc target_mmw {target reg setbits clearbits} {
+	set val [eval $target read_memory $reg 32 1]
+	set val [expr {($val & ~$clearbits) | $setbits}]
+	eval $target mww $reg $val
+}
+
+lappend _telnet_autocomplete_skip _enable_debug
+# Uses AP1
+proc _enable_debug {} {
 	# keep clock enabled in low-power
-	## catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
+	catch {$::_CHIPNAME.ap1 mww 0xe0081004 0x00000004}
 	# freeze watchdog 1 and 2 on core halted
 	catch {$::_CHIPNAME.ap1 mww 0xe008102c 0x00000004}
 	catch {$::_CHIPNAME.ap1 mww 0xe008104c 0x00000008}
 }
 
-proc toggle_cpu_dbg_claim0 {} {
-	# toggle CPU0 DBG_CLAIM[0]
-	$::_CHIPNAME.ap1 mww 0xe00d0fa0 1
-	$::_CHIPNAME.ap1 mww 0xe00d0fa4 1
+lappend _telnet_autocomplete_skip _handshake_with_wrapper
+# Uses AP1
+proc _handshake_with_wrapper { halt } {
+	set dbgmcu_cr 0
+	catch {set dbgmcu_cr [eval $::_CHIPNAME.ap1 read_memory 0xe0081004 32 1]}
+	if {[expr {($dbgmcu_cr & 0x07) == 0x00}]} {
+		echo "\nWARNING: FSBL wrapper not detected. Board in dev boot mode?\n"
+		return
+	}
+
+	if { $halt } {
+		$::_CHIPNAME.ap1 arp_halt
+		$::_CHIPNAME.ap1 mww 0xe00d0300 0
+		target_mmw $::_CHIPNAME.ap1 0xe00d0088 0x00004000 0
+	}
+
+	$::_CHIPNAME.ap1 mww 0xe0081004 0x7
 }
 
 # FIXME: most of handlers below will be removed once reset framework get merged
+$_CHIPNAME.ap1 configure -event reset-assert-post {
+	adapter assert srst
+}
+
 $_CHIPNAME.ap1 configure -event reset-deassert-pre {
 	adapter deassert srst deassert trst
-	catch {dap init}
-	catch {$::_CHIPNAME.dap apid 1}
+	$::_CHIPNAME.ap1 arp_examine
+	_handshake_with_wrapper $halt
+	_enable_debug
+	$::_CHIPNAME.cpu arp_examine
+	if { $halt } {
+		$::_CHIPNAME.cpu arp_halt
+	}
+}
+
+$_CHIPNAME.ap1 configure -event examine-end {
+	_enable_debug
+	$::_CHIPNAME.cpu arp_examine
 }
-$_CHIPNAME.cpu configure -event reset-deassert-pre  {$::_CHIPNAME.cpu arp_examine}
-$_CHIPNAME.cpu configure -event reset-deassert-post {toggle_cpu_dbg_claim0; dbgmcu_enable_debug}
-$_CHIPNAME.ap1 configure -event examine-start       {dap init}
-$_CHIPNAME.ap1 configure -event examine-end         {dbgmcu_enable_debug}

commit 9bb6fa67ca6de6f725df78ac8a415b5b47fb9420
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Jul 4 16:50:46 2025 +0200

    tcl: move STM32 MPU files in vendor folder
    
    Move the existing files for STM32MP13x and STM32MP15x in the
    folder "st".
    Rename the board files using the correct names.
    While there, add the missing URL to one of the boards.
    
    Change-Id: If8b92f55e3390ebc75df6a2ea09fcf798ea0b8cf
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8982
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>

diff --git a/tcl/board/stm32mp13x_dk.cfg b/tcl/board/st/stm32mp135f-dk.cfg
similarity index 83%
rename from tcl/board/stm32mp13x_dk.cfg
rename to tcl/board/st/stm32mp135f-dk.cfg
index 8ece24844..2259e0425 100644
--- a/tcl/board/stm32mp13x_dk.cfg
+++ b/tcl/board/st/stm32mp135f-dk.cfg
@@ -7,6 +7,6 @@ source [find interface/stlink.cfg]
 
 transport select swd
 
-source [find target/stm32mp13x.cfg]
+source [find target/st/stm32mp13x.cfg]
 
 reset_config srst_only
diff --git a/tcl/board/stm32mp15x_dk2.cfg b/tcl/board/st/stm32mp157f-dk2.cfg
similarity index 72%
rename from tcl/board/stm32mp15x_dk2.cfg
rename to tcl/board/st/stm32mp157f-dk2.cfg
index ba1c7f78a..b193ae3a0 100644
--- a/tcl/board/stm32mp15x_dk2.cfg
+++ b/tcl/board/st/stm32mp157f-dk2.cfg
@@ -3,11 +3,12 @@
 # board MB1272B
 # http://www.st.com/en/evaluation-tools/stm32mp157a-dk1.html
 # http://www.st.com/en/evaluation-tools/stm32mp157c-dk2.html
+# http://www.st.com/en/evaluation-tools/stm32mp157f-dk2.html
 
 source [find interface/stlink.cfg]
 
 transport select swd
 
-source [find target/stm32mp15x.cfg]
+source [find target/st/stm32mp15x.cfg]
 
 reset_config srst_only
diff --git a/tcl/file_renaming.cfg b/tcl/file_renaming.cfg
index 0a3c7ba65..20679b6ab 100644
--- a/tcl/file_renaming.cfg
+++ b/tcl/file_renaming.cfg
@@ -17,6 +17,8 @@ set _file_renaming {
 	board/nordic_nrf51822_mkit.cfg	board/nordic/nrf51822-mkit.cfg
 	board/nordic_nrf51_dk.cfg		board/nordic/nrf51-dk.cfg
 	board/nordic_nrf52_dk.cfg		board/nordic/nrf52-dk.cfg
+	board/stm32mp13x_dk.cfg			board/st/stm32mp135f-dk.cfg
+	board/stm32mp15x_dk2.cfg		board/st/stm32mp157f-dk2.cfg
 	target/nrf51.cfg	target/nordic/nrf51.cfg
 	target/nrf52.cfg	target/nordic/nrf52.cfg
 	target/nrf53.cfg	target/nordic/nrf53.cfg
diff --git a/tcl/target/stm32mp13x.cfg b/tcl/target/st/stm32mp13x.cfg
similarity index 100%
rename from tcl/target/stm32mp13x.cfg
rename to tcl/target/st/stm32mp13x.cfg
diff --git a/tcl/target/stm32mp15x.cfg b/tcl/target/st/stm32mp15x.cfg
similarity index 100%
rename from tcl/target/stm32mp15x.cfg
rename to tcl/target/st/stm32mp15x.cfg

-----------------------------------------------------------------------

Summary of changes:
 .../{stm32mp13x_dk.cfg => st/stm32mp135f-dk.cfg}   |  2 +-
 .../{stm32mp15x_dk2.cfg => st/stm32mp157f-dk2.cfg} |  3 +-
 tcl/file_renaming.cfg                              |  2 +
 tcl/target/{ => st}/stm32mp13x.cfg                 | 58 +++++++++++++++++-----
 tcl/target/{ => st}/stm32mp15x.cfg                 |  0
 5 files changed, 50 insertions(+), 15 deletions(-)
 rename tcl/board/{stm32mp13x_dk.cfg => st/stm32mp135f-dk.cfg} (83%)
 rename tcl/board/{stm32mp15x_dk2.cfg => st/stm32mp157f-dk2.cfg} (72%)
 rename tcl/target/{ => st}/stm32mp13x.cfg (67%)
 rename tcl/target/{ => st}/stm32mp15x.cfg (100%)


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- Log -----------------------------------------------------------------
commit 1f56ea647d63b7495d513227622413f1826d75f9
Author: Liam Fletcher <lia...@mi...>
Date:   Mon May 26 10:42:56 2025 +0100

    tcl: add microchip's pic64gx curiosity config
    
    Microchip's PIC64GX Curiosity Board has a RISC-V core complex with 4
    application processors and one monitor processor. The Curiosity kit also
    has an on-board debug interface based around an FTDI 4232H device.
    
    This patch adds basic target, interface and board support for PIC64GX
    Curiosity Kit.
    
    Change-Id: I2234d8725744fbae00b3909773b370e5c18debd8
    Signed-off-by: Liam Fletcher <lia...@mi...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8878
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/board/microchip/pic64gx-curiosity-kit.cfg b/tcl/board/microchip/pic64gx-curiosity-kit.cfg
new file mode 100644
index 000000000..e7e67ea4b
--- /dev/null
+++ b/tcl/board/microchip/pic64gx-curiosity-kit.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Microchip RISC-V board
+#
+# https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx
+#
+adapter speed 6000
+
+source [find interface/microchip/embedded_flashpro5.cfg]
+source [find target/microchip/pic64gx.cfg]
diff --git a/tcl/target/microchip/pic64gx.cfg b/tcl/target/microchip/pic64gx.cfg
new file mode 100644
index 000000000..25cef6b23
--- /dev/null
+++ b/tcl/target/microchip/pic64gx.cfg
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: Pic64gx processor by Microchip Technologies
+#
+# https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64gx
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME pic64gx
+}
+
+# Process COREID variable
+if {![exists COREID]} {
+	set COREID -1
+}
+
+transport select jtag
+
+# PIC64GX hart id to name lookup table
+array set hart_names {
+	0	e51
+	1	u54_1
+	2	u54_2
+	3	u54_3
+	4	u54_4
+}
+
+# PIC64GX table
+set pic64gx_tap_info {
+	PIC64GX1000 0x0f8531cf
+}
+
+proc expected_ids {tap_list} {
+	set str ""
+	dict for {key value} $tap_list {
+		append str "-expected-id" " " $value " "
+	}
+
+	return $str
+}
+
+set irlen 8
+set expected_ids [expected_ids $pic64gx_tap_info]
+eval jtag newtap $_CHIPNAME cpu -irlen $irlen $expected_ids -ignore-version
+
+if {$COREID == -1} {
+	# Single debug connection to all harts
+	set _TARGETNAME_0 $_CHIPNAME.$hart_names(0)
+	set _TARGETNAME_1 $_CHIPNAME.$hart_names(1)
+	set _TARGETNAME_2 $_CHIPNAME.$hart_names(2)
+	set _TARGETNAME_3 $_CHIPNAME.$hart_names(3)
+	set _TARGETNAME_4 $_CHIPNAME.$hart_names(4)
+
+	target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -rtos hwthread
+	target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 -rtos hwthread
+	target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 2 -rtos hwthread
+	target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 3 -rtos hwthread
+	target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu -coreid 4 -rtos hwthread
+	target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4
+} else {
+	# Debug connection to a specific hart
+	set _TARGETNAME_0 $_CHIPNAME.$hart_names($COREID)
+	target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid $COREID
+}
+
+# Only TRSTn supported
+reset_config trst_only

commit 6e87864dfc35a1513ffa02972812954e97efdf86
Author: Liam Fletcher <lia...@mi...>
Date:   Mon May 26 10:54:40 2025 +0100

    tcl: add embedded flashpro5 config
    
    To support Microchips Embedded Flashpro5
    
    Change-Id: I7861e0772fd4cbf0539725d238c59ae15bbcca41
    Signed-off-by: Liam Fletcher <lia...@mi...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8879
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/contrib/60-openocd.rules b/contrib/60-openocd.rules
index 29f8d7a6d..6632841a4 100644
--- a/contrib/60-openocd.rules
+++ b/contrib/60-openocd.rules
@@ -190,6 +190,10 @@ ATTRS{idVendor}=="138e", ATTRS{idProduct}=="9000", MODE="660", GROUP="plugdev",
 # Debug Board for Neo1973
 ATTRS{idVendor}=="1457", ATTRS{idProduct}=="5118", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
+# Microchip RISC-V Debug
+ATTRS{idVendor}=="1514", ATTRS{idProduct}=="2008", MODE="660", GROUP="plugdev", TAG+="uaccess"
+ATTRS{idVendor}=="1514", ATTRS{idProduct}=="200a", MODE="660", GROUP="plugdev", TAG+="uaccess"
+
 # OSBDM
 ATTRS{idVendor}=="15a2", ATTRS{idProduct}=="0042", MODE="660", GROUP="plugdev", TAG+="uaccess"
 ATTRS{idVendor}=="15a2", ATTRS{idProduct}=="0058", MODE="660", GROUP="plugdev", TAG+="uaccess"
diff --git a/tcl/interface/microchip/embedded_flashpro5.cfg b/tcl/interface/microchip/embedded_flashpro5.cfg
new file mode 100644
index 000000000..117a54458
--- /dev/null
+++ b/tcl/interface/microchip/embedded_flashpro5.cfg
@@ -0,0 +1,40 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Embedded FlashPro5
+#
+# https://www.microchip.com/en-us/development-tool/flashpro5
+#
+
+adapter driver ftdi
+
+# vidpid 1514:2008 = embedded flashpro5
+# vidpid 1514:200a = pic64gx
+ftdi vid_pid 0x1514 0x2008 0x1514 0x200a
+
+# That FTDI has 4 channels (channel 0 and 1 are MPSSE-capable, 2 and 3 are bitbang
+ftdi channel 0
+
+# Initial Layout - data[0..15] direction[0..15]
+ftdi layout_init 0x0018 0xfdfb
+#     Signal        Data    Direction       Notes
+# AD0 TCK           0       1 (out)         Port A TCK
+# AD1 TDI           0       1 (out)         Port A TDI
+# AD2 TDO           0       0 (in)          PORT A TDO
+# AD3 TMS           1       1 (out)         Port A TMS
+# AD4 GPIOL0        1       1 (out)         Port A TRST
+# AD5 GPIOL1        0       1 (out)         (unused)
+# AD6 GPIOL2        0       1 (out)         (unused)
+# AD7 GPIOL3        0       1 (out)         (unused)
+
+# BD0 TCK           0       1 (out)         FTDI_UART_B_TXD
+# BD1 TDI           0       0 (in)          FTDI_UART_B_RXD
+# BD2 TDO           0       1 (out)         (unused)
+# BD3 TMS           0       1 (out)         (unused)
+# BD4 GPIOL0        0       1 (out)         (unused)
+# BD5 GPIOL1        0       1 (out)         (unused)
+# BD6 GPIOL2        0       1 (out)         (unused)
+# BD7 GPIOL2        0       1 (out)         (unused)
+
+# Signals definition
+ftdi layout_signal nTRST -data 0x0010 -oe 0x0010

-----------------------------------------------------------------------

Summary of changes:
 contrib/60-openocd.rules                       |  4 +++
 tcl/board/microchip/pic64gx-curiosity-kit.cfg  | 10 +++++++
 tcl/interface/microchip/embedded_flashpro5.cfg | 40 ++++++++++++++++++++++++++
 tcl/target/microchip/{mpfs.cfg => pic64gx.cfg} | 26 +++++++----------
 4 files changed, 64 insertions(+), 16 deletions(-)
 create mode 100644 tcl/board/microchip/pic64gx-curiosity-kit.cfg
 create mode 100644 tcl/interface/microchip/embedded_flashpro5.cfg
 copy tcl/target/microchip/{mpfs.cfg => pic64gx.cfg} (73%)


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commit d06ecba2e62f3e1de914dd9ef019b85ea422d483
Author: Liam Fletcher <lia...@mi...>
Date:   Mon May 26 10:30:07 2025 +0100

    target: add microchip polarfire soc config
    
    Microchip's PolarFire SoC has a RISC-V core complex with four
    application processors and one monitor processor. This basic
    configuration can be used to attach to all proccessor's or a single
    processor, specified by the run-time argument $COREID
    
    It can be used with most FTDI based debug interfaces and has been tested
    with interface/ftdi/olimex-arm-usb-tiny-h.cfg.
    
    Change-Id: I75dd965f1ce550807706d00fe17de887d36f0b02
    Signed-off-by: Liam Fletcher <lia...@mi...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8877
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/microchip/mpfs.cfg b/tcl/target/microchip/mpfs.cfg
new file mode 100644
index 000000000..3a63e3d3b
--- /dev/null
+++ b/tcl/target/microchip/mpfs.cfg
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+#
+# Target: MPFS PolarFire SoC-series processors by Microchip Technologies
+#
+# https://www.microchip.com/en-us/products/fpgas-and-plds/system-on-chip-fpgas/polarfire-soc-fpgas
+#
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME mpfs
+}
+
+# Process COREID variable
+if { ![exists COREID] } {
+	set COREID -1
+}
+
+transport select jtag
+
+# PolarFire SoC (MPFS) hart id to name lookup table
+array set hart_names {
+	0	e51
+	1	u54_1
+	2	u54_2
+	3	u54_3
+	4	u54_4
+}
+
+# MPFS devices table
+set mpfs_cpu_tap_info {
+	MPFS025  0x0f8531cf
+	MPFS095  0x0f8181cf
+	MPFS160  0x0f8191cf
+	MPFS250  0x0f81a1cf
+	MPFS460  0x0f81b1cf
+	RTPFS160 0x0f8991cf
+	RTPFS460 0x0f89b1cf
+}
+
+proc expected_ids {tap_list} {
+	set str ""
+	dict for {key value} $tap_list {
+		append str "-expected-id" " " $value " "
+	}
+
+	return $str
+}
+
+set irlen 8
+set expected_ids [expected_ids $mpfs_cpu_tap_info]
+eval jtag newtap $_CHIPNAME cpu -irlen $irlen $expected_ids -ignore-version
+
+if {$COREID == -1} {
+	# Single debug connection to all HART's
+	set _TARGETNAME_0 $_CHIPNAME.$hart_names(0)
+	set _TARGETNAME_1 $_CHIPNAME.$hart_names(1)
+	set _TARGETNAME_2 $_CHIPNAME.$hart_names(2)
+	set _TARGETNAME_3 $_CHIPNAME.$hart_names(3)
+	set _TARGETNAME_4 $_CHIPNAME.$hart_names(4)
+
+	target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid 0 -rtos hwthread
+	target create $_TARGETNAME_1 riscv -chain-position $_CHIPNAME.cpu -coreid 1 -rtos hwthread
+	target create $_TARGETNAME_2 riscv -chain-position $_CHIPNAME.cpu -coreid 2 -rtos hwthread
+	target create $_TARGETNAME_3 riscv -chain-position $_CHIPNAME.cpu -coreid 3 -rtos hwthread
+	target create $_TARGETNAME_4 riscv -chain-position $_CHIPNAME.cpu -coreid 4 -rtos hwthread
+	target smp $_TARGETNAME_0 $_TARGETNAME_1 $_TARGETNAME_2 $_TARGETNAME_3 $_TARGETNAME_4
+} else {
+	# Debug connection to a specific hart
+	set _TARGETNAME_0 $_CHIPNAME.$hart_names($COREID)
+	target create $_TARGETNAME_0 riscv -chain-position $_CHIPNAME.cpu -coreid $COREID
+}
+
+# Only TRSTn supported
+reset_config trst_only

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/microchip/mpfs.cfg | 75 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 75 insertions(+)
 create mode 100644 tcl/target/microchip/mpfs.cfg


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1086-ga19294909

From: openocd-gerrit <ope...@us...> - 2025-07-25 16:39:12

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- Log -----------------------------------------------------------------
commit a192949095b3fc10a3916ee1d52d92d3b019fbea
Author: Nicolas Derumigny <nic...@in...>
Date:   Tue Nov 5 15:49:04 2024 +0000

    jtag: drivers: xlnx-axi-xvc: Add support for Xilinx XVC over direct bus interface (AXI)
    
    This change allow to use direct mapping of the JTAG interface using
    Xilinx Virtual Cable (XVC) over AXI. This merges the existing XVC PCIe
    code and the patch proposed by Jeremy Garff
    (https://review.openocd.org/c/openocd/+/6594).
    
    This is useful when using on a Zynq/ZynqMP/uBlaze host with direct
    access to the debug bridge over AXI.  You can then use the debug bridge
    Xilinx IP (AXIXVC) to debug a remote device.
    
    Signed-off-by: Nicolas Derumigny <nic...@in...>
    Change-Id: I934591b489e30b400b87772b1437e6030440904c
    Reviewed-on: https://review.openocd.org/c/openocd/+/8595
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index 9bbb2c36a..df94e20b8 100644
--- a/configure.ac
+++ b/configure.ac
@@ -177,8 +177,8 @@ m4_define([REMOTE_BITBANG_ADAPTER],
 m4_define([LIBJAYLINK_ADAPTERS],
 	[[[jlink], [SEGGER J-Link Programmer], [JLINK]]])
 
-m4_define([PCIE_ADAPTERS],
-	[[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_XVC]]])
+m4_define([XVC_ADAPTERS],
+	[[[xlnx_xvc], [Xilinx XVC PCIe and AXI drives], [XLNX_XVC]]])
 
 m4_define([SERIAL_PORT_ADAPTERS],
 	[[[buspirate], [Bus Pirate], [BUS_PIRATE]]])
@@ -335,7 +335,7 @@ AC_ARG_ADAPTERS([
   JTAG_DPI_ADAPTER,
   JTAG_VPI_ADAPTER,
   RSHIM_ADAPTER,
-  PCIE_ADAPTERS,
+  XVC_ADAPTERS,
   LIBJAYLINK_ADAPTERS
   ],[auto])
 
@@ -644,7 +644,7 @@ PROCESS_ADAPTERS([DMEM_ADAPTER], ["x$is_linux" = "xyes"], [Linux /dev/mem])
 PROCESS_ADAPTERS([SYSFSGPIO_ADAPTER], ["x$is_linux" = "xyes"], [Linux sysfs])
 PROCESS_ADAPTERS([REMOTE_BITBANG_ADAPTER], [true], [unused])
 PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o "x$use_libjaylink" = "xyes"], [libjaylink-0.2])
-PROCESS_ADAPTERS([PCIE_ADAPTERS], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_pci_h" = "xyes"], [Linux build])
+PROCESS_ADAPTERS([XVC_ADAPTERS], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_pci_h" = "xyes"], [Linux build])
 PROCESS_ADAPTERS([SERIAL_PORT_ADAPTERS], ["x$can_build_buspirate" = "xyes"],
                                          [internal error: validation should happen beforehand])
 PROCESS_ADAPTERS([LINUXSPIDEV_ADAPTER], ["x$is_linux" = "xyes" -a "x$ac_cv_header_linux_spi_spidev_h" = "xyes"],
@@ -840,7 +840,8 @@ m4_foreach([adapterTuple], [USB1_ADAPTERS,
 	DMEM_ADAPTER,
 	SYSFSGPIO_ADAPTER,
 	REMOTE_BITBANG_ADAPTER,
-	LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, SERIAL_PORT_ADAPTERS,
+	LIBJAYLINK_ADAPTERS, XVC_ADAPTERS,
+	SERIAL_PORT_ADAPTERS,
 	LINUXSPIDEV_ADAPTER,
 	VDEBUG_ADAPTER,
 	JTAG_DPI_ADAPTER,
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 6d607d697..90ed9d3b6 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -613,6 +613,12 @@ emulation model of target hardware.
 
 @item @b{xlnx_pcie_xvc}
 @* A JTAG driver exposing Xilinx Virtual Cable over PCI Express to OpenOCD as JTAG/SWD interface.
+@* Link: @url{https://www.xilinx.com/products/intellectual-property/debug-bridge.html}
+
+@item @b{xlnx_axi_xvc}
+@* A JTAG driver exposing JTAG to OpenOCD over AXI-mapped registers.
+@* Link: @url{https://docs.amd.com/r/en-US/pg437-axi-jtag/Introduction}
+@* Link: @url{https://china.xilinx.com/support/documentation/application_notes/xapp1251-xvc-zynq-petalinux.pdf}
 
 @item @b{linuxspidev}
 @* A SPI based SWD driver using Linux SPI devices.
@@ -3352,6 +3358,21 @@ The string will be of the format "DDDD:BB:SS.F" such as "0000:65:00.1".
 @end deffn
 @end deffn
 
+@deffn {Interface Driver} {xlnx_axi_xvc}
+This driver supports the Xilinx JTAG mapping over AXI using the AXI to JTAG
+Converter or the AXI-to-JTAG mode of the debug bridge.
+It is commonly found in Xilinx MPSoC based designs. It allows debugging
+fabric based JTAG/SWD devices such as Cortex-M1/M3 or RISC-V softcores. Access to this
+is exposed via extended capability registers in the AXI-mapped configuration space.
+
+@deffn {Config Command} {xlnx_axi_xvc dev_addr} addr
+Specifies the address of the AXI-mapped registers via parameter @var{addr}.
+
+The correct value for @var{addr} is specified in the "Address Editor" tab
+in Vivado.
+@end deffn
+@end deffn
+
 @deffn {Interface Driver} {bcm2835gpio}
 This GPIO interface is present in Raspberry Pi 0-4 which is a cheap
 single-board computer exposing some GPIOs on its expansion header.
diff --git a/src/jtag/drivers/xlnx-xvc.c b/src/jtag/drivers/xlnx-xvc.c
index 5208e2b87..6b3359538 100644
--- a/src/jtag/drivers/xlnx-xvc.c
+++ b/src/jtag/drivers/xlnx-xvc.c
@@ -1,8 +1,14 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
 /*
- * Copyright (c) 2019 Google, LLC.
- * Author: Moritz Fischer <mo...@go...>
+ *	 Copyright (C) 2019 Google, LLC.
+ *	 Moritz Fischer <mo...@go...>
+ *
+ *	 Copyright (C) 2021 Western Digital Corporation or its affiliates
+ *	 Jeremy Garff <jer...@wd...>
+ *
+ *	 Copyright (C) 2024 Inria
+ *	 Nicolas Derumigny <nic...@in...>
  */
 
 #ifdef HAVE_CONFIG_H
@@ -11,13 +17,14 @@
 
 #include <stdint.h>
 #include <stdlib.h>
-#include <math.h>
 #include <unistd.h>
 #include <linux/pci.h>
+#include <sys/mman.h>
 
 #include <jtag/interface.h>
-#include <jtag/swd.h>
 #include <jtag/commands.h>
+#include <jtag/interface.h>
+#include <jtag/swd.h>
 #include <helper/replacements.h>
 #include <helper/bits.h>
 
@@ -28,14 +35,24 @@
 
 #define PCIE_EXT_CAP_LST	0x100
 
-#define XLNX_XVC_EXT_CAP	0x00
-#define XLNX_XVC_VSEC_HDR	0x04
-#define XLNX_XVC_LEN_REG	0x0C
-#define XLNX_XVC_TMS_REG	0x10
-#define XLNX_XVC_TDX_REG	0x14
+#define XLNX_PCIE_XVC_EXT_CAP	0x00
+#define XLNX_PCIE_XVC_VSEC_HDR	0x04
+#define XLNX_PCIE_XVC_LEN_REG	0x0C
+#define XLNX_PCIE_XVC_TMS_REG	0x10
+#define XLNX_PCIE_XVC_TDX_REG	0x14
+
+#define XLNX_PCIE_XVC_CAP_SIZE	0x20
+#define XLNX_PCIE_XVC_VSEC_ID	0x8
+
+#define XLNX_AXI_XVC_LEN_REG	0x00
+#define XLNX_AXI_XVC_TMS_REG	0x04
+#define XLNX_AXI_XVC_TDI_REG	0x08
+#define XLNX_AXI_XVC_TDO_REG	0x0c
+#define XLNX_AXI_XVC_CTRL_REG	0x10
+#define XLNX_AXI_XVC_MAX_REG	0x18
+
+#define XLNX_AXI_XVC_CTRL_REG_ENABLE_MASK	0x01
 
-#define XLNX_XVC_CAP_SIZE	0x20
-#define XLNX_XVC_VSEC_ID	0x8
 #define XLNX_XVC_MAX_BITS	0x20
 
 #define MASK_ACK(x) (((x) >> 9) & 0x7)
@@ -47,8 +64,23 @@ struct xlnx_pcie_xvc {
 	char *device;
 };
 
+struct xlnx_axi_xvc {
+	int fd;
+	uint32_t *base;
+	char *device_addr;
+	// Defaults to `/dev/mem` if NULL
+	char *device_file;
+};
+
+enum xlnx_xvc_type_t {
+	PCIE,
+	AXI
+};
+
 static struct xlnx_pcie_xvc xlnx_pcie_xvc_state;
 static struct xlnx_pcie_xvc *xlnx_pcie_xvc = &xlnx_pcie_xvc_state;
+static struct xlnx_axi_xvc xlnx_axi_xvc_state;
+static struct xlnx_axi_xvc *xlnx_axi_xvc = &xlnx_axi_xvc_state;
 
 static int xlnx_pcie_xvc_read_reg(const int offset, uint32_t *val)
 {
@@ -60,9 +92,9 @@ static int xlnx_pcie_xvc_read_reg(const int offset, uint32_t *val)
 	 * space accessor functions
 	 */
 	err = pread(xlnx_pcie_xvc->fd, &res, sizeof(res),
-		    xlnx_pcie_xvc->offset + offset);
+			xlnx_pcie_xvc->offset + offset);
 	if (err != sizeof(res)) {
-		LOG_ERROR("Failed to read offset %x", offset);
+		LOG_ERROR("Failed to read offset 0x%x", offset);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
 
@@ -72,6 +104,19 @@ static int xlnx_pcie_xvc_read_reg(const int offset, uint32_t *val)
 	return ERROR_OK;
 }
 
+static int xlnx_axi_xvc_read_reg(const int offset, uint32_t *val)
+{
+	uintptr_t b = ((uintptr_t)xlnx_axi_xvc->base) + offset;
+	volatile uint32_t *w = (uint32_t *)b;
+
+	if (val) {
+		__atomic_thread_fence(__ATOMIC_SEQ_CST);
+		*val = *w;
+	}
+
+	return ERROR_OK;
+}
+
 static int xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)
 {
 	int err;
@@ -81,9 +126,9 @@ static int xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)
 	 * space accessor functions
 	 */
 	err = pwrite(xlnx_pcie_xvc->fd, &val, sizeof(val),
-		     xlnx_pcie_xvc->offset + offset);
+			 xlnx_pcie_xvc->offset + offset);
 	if (err != sizeof(val)) {
-		LOG_ERROR("Failed to write offset: %x with value: %" PRIx32,
+		LOG_ERROR("Failed to write offset: 0x%x with value: %" PRIx32,
 			  offset, val);
 		return ERROR_JTAG_DEVICE_ERROR;
 	}
@@ -91,37 +136,117 @@ static int xlnx_pcie_xvc_write_reg(const int offset, const uint32_t val)
 	return ERROR_OK;
 }
 
+static int xlnx_axi_xvc_write_reg(const int offset, const uint32_t val)
+{
+	uintptr_t b = ((uintptr_t)xlnx_axi_xvc->base) + offset;
+	volatile uint32_t *w = (uint32_t *)b;
+
+	*w = val;
+	__atomic_thread_fence(__ATOMIC_SEQ_CST);
+
+	return ERROR_OK;
+}
+
 static int xlnx_pcie_xvc_transact(size_t num_bits, uint32_t tms, uint32_t tdi,
 				  uint32_t *tdo)
 {
 	int err;
 
-	err = xlnx_pcie_xvc_write_reg(XLNX_XVC_LEN_REG, num_bits);
+	err = xlnx_pcie_xvc_write_reg(XLNX_PCIE_XVC_LEN_REG, num_bits);
 	if (err != ERROR_OK)
 		return err;
 
-	err = xlnx_pcie_xvc_write_reg(XLNX_XVC_TMS_REG, tms);
+	err = xlnx_pcie_xvc_write_reg(XLNX_PCIE_XVC_TMS_REG, tms);
 	if (err != ERROR_OK)
 		return err;
 
-	err = xlnx_pcie_xvc_write_reg(XLNX_XVC_TDX_REG, tdi);
+	err = xlnx_pcie_xvc_write_reg(XLNX_PCIE_XVC_TDX_REG, tdi);
 	if (err != ERROR_OK)
 		return err;
 
-	err = xlnx_pcie_xvc_read_reg(XLNX_XVC_TDX_REG, tdo);
+	err = xlnx_pcie_xvc_read_reg(XLNX_PCIE_XVC_TDX_REG, tdo);
 	if (err != ERROR_OK)
 		return err;
 
 	if (tdo)
 		LOG_DEBUG_IO("Transact num_bits: %zu, tms: %" PRIx32 ", tdi: %" PRIx32 ", tdo: %" PRIx32,
-			     num_bits, tms, tdi, *tdo);
+				 num_bits, tms, tdi, *tdo);
 	else
 		LOG_DEBUG_IO("Transact num_bits: %zu, tms: %" PRIx32 ", tdi: %" PRIx32 ", tdo: <null>",
-			     num_bits, tms, tdi);
+				 num_bits, tms, tdi);
+	return ERROR_OK;
+}
+
+static int xlnx_axi_xvc_transact(size_t num_bits, uint32_t tms, uint32_t tdi,
+				  uint32_t *tdo)
+{
+	uint32_t ctrl;
+	int done = 0;
+	int err;
+
+	err = xlnx_axi_xvc_write_reg(XLNX_AXI_XVC_LEN_REG, num_bits);
+	if (err != ERROR_OK)
+		return err;
+
+	err = xlnx_axi_xvc_write_reg(XLNX_AXI_XVC_TMS_REG, tms);
+	if (err != ERROR_OK)
+		return err;
+
+	err = xlnx_axi_xvc_write_reg(XLNX_AXI_XVC_TDI_REG, tdi);
+	if (err != ERROR_OK)
+		return err;
+
+	err = xlnx_axi_xvc_write_reg(XLNX_AXI_XVC_CTRL_REG, XLNX_AXI_XVC_CTRL_REG_ENABLE_MASK);
+	if (err != ERROR_OK)
+		return err;
+
+	while (!done) {
+		err = xlnx_axi_xvc_read_reg(XLNX_AXI_XVC_CTRL_REG, &ctrl);
+		if (err != ERROR_OK)
+			return err;
+
+		if (!(ctrl & XLNX_AXI_XVC_CTRL_REG_ENABLE_MASK))
+			done = 1;
+
+		/*
+		 There is no delay here intentionally.	The usleep()
+		 function doesn't block and burns CPU cycles anyway.
+		 The turnaround time is fast enough at high JTAG rates
+		 that adding the call can slow down the overall
+		 throughput.	So we'll just sacrifice the CPU to get
+		 best performance.
+
+		 Additionally there is no timeout.	The underlying
+		 hardware is guaranteed to unset the enable bit within
+		 32 JTAG clock cycles.	There is no hardware condition
+		 that will keep it set forever.  Essentially, the hardware
+		 is also our timeout mechanism.
+		*/
+	}
+
+	err = xlnx_axi_xvc_read_reg(XLNX_AXI_XVC_TDO_REG, tdo);
+	if (err != ERROR_OK)
+		return err;
+
+	if (tdo)
+		LOG_DEBUG_IO("Transact num_bits: %zu, tms: 0x%x, tdi: 0x%x, tdo: 0x%x",
+				 num_bits, tms, tdi, *tdo);
+	else
+		LOG_DEBUG_IO("Transact num_bits: %zu, tms: 0x%x, tdi: 0x%x, tdo: <null>",
+				 num_bits, tms, tdi);
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_execute_stableclocks(struct jtag_command *cmd)
+static int xlnx_xvc_transact(size_t num_bits, uint32_t tms, uint32_t tdi,
+		uint32_t *tdo, enum xlnx_xvc_type_t xvc_type)
+{
+	if (xvc_type == PCIE)
+		return xlnx_pcie_xvc_transact(num_bits, tms, tdi, tdo);
+	assert(xvc_type == AXI);
+	return xlnx_axi_xvc_transact(num_bits, tms, tdi, tdo);
+}
+
+static int xlnx_xvc_execute_stableclocks(struct jtag_command *cmd, enum xlnx_xvc_type_t xvc_type)
 {
 	int tms = tap_get_state() == TAP_RESET ? 1 : 0;
 	size_t left = cmd->cmd.stableclocks->num_cycles;
@@ -132,7 +257,7 @@ static int xlnx_pcie_xvc_execute_stableclocks(struct jtag_command *cmd)
 
 	while (left) {
 		write = MIN(XLNX_XVC_MAX_BITS, left);
-		err = xlnx_pcie_xvc_transact(write, tms, 0, NULL);
+		err = xlnx_xvc_transact(write, tms, 0, NULL, xvc_type);
 		if (err != ERROR_OK)
 			return err;
 		left -= write;
@@ -141,12 +266,12 @@ static int xlnx_pcie_xvc_execute_stableclocks(struct jtag_command *cmd)
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_execute_statemove(size_t skip)
+static int xlnx_xvc_execute_statemove(size_t skip, enum xlnx_xvc_type_t xvc_type)
 {
 	uint8_t tms_scan = tap_get_tms_path(tap_get_state(),
-					    tap_get_end_state());
+						tap_get_end_state());
 	int tms_count = tap_get_tms_path_len(tap_get_state(),
-					     tap_get_end_state());
+						 tap_get_end_state());
 	int err;
 
 	LOG_DEBUG("statemove starting at (skip: %zu) %s end in %s", skip,
@@ -154,7 +279,7 @@ static int xlnx_pcie_xvc_execute_statemove(size_t skip)
 		  tap_state_name(tap_get_end_state()));
 
 
-	err = xlnx_pcie_xvc_transact(tms_count - skip, tms_scan >> skip, 0, NULL);
+	err = xlnx_xvc_transact(tms_count - skip, tms_scan >> skip, 0, NULL, xvc_type);
 	if (err != ERROR_OK)
 		return err;
 
@@ -163,7 +288,8 @@ static int xlnx_pcie_xvc_execute_statemove(size_t skip)
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
+static int xlnx_xvc_execute_runtest(struct jtag_command *cmd,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	int err = ERROR_OK;
 
@@ -175,7 +301,7 @@ static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
 
 	if (tap_get_state() != TAP_IDLE) {
 		tap_set_end_state(TAP_IDLE);
-		err = xlnx_pcie_xvc_execute_statemove(0);
+		err = xlnx_xvc_execute_statemove(0, xvc_type);
 		if (err != ERROR_OK)
 			return err;
 	};
@@ -185,7 +311,7 @@ static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
 
 	while (left) {
 		write = MIN(XLNX_XVC_MAX_BITS, left);
-		err = xlnx_pcie_xvc_transact(write, 0, 0, NULL);
+		err = xlnx_xvc_transact(write, 0, 0, NULL, xvc_type);
 		if (err != ERROR_OK)
 			return err;
 		left -= write;
@@ -193,12 +319,13 @@ static int xlnx_pcie_xvc_execute_runtest(struct jtag_command *cmd)
 
 	tap_set_end_state(tmp_state);
 	if (tap_get_state() != tap_get_end_state())
-		err = xlnx_pcie_xvc_execute_statemove(0);
+		err = xlnx_xvc_execute_statemove(0, xvc_type);
 
 	return err;
 }
 
-static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd)
+static int xlnx_xvc_execute_pathmove(struct jtag_command *cmd,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	unsigned int num_states = cmd->cmd.pathmove->num_states;
 	enum tap_state *path = cmd->cmd.pathmove->path;
@@ -210,9 +337,9 @@ static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd)
 
 	for (unsigned int i = 0; i < num_states; i++) {
 		if (path[i] == tap_state_transition(tap_get_state(), false)) {
-			err = xlnx_pcie_xvc_transact(1, 0, 0, NULL);
+			err = xlnx_xvc_transact(1, 0, 0, NULL, xvc_type);
 		} else if (path[i] == tap_state_transition(tap_get_state(), true)) {
-			err = xlnx_pcie_xvc_transact(1, 1, 0, NULL);
+			err = xlnx_xvc_transact(1, 1, 0, NULL, xvc_type);
 		} else {
 			LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition.",
 				  tap_state_name(tap_get_state()),
@@ -229,7 +356,8 @@ static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd)
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
+static int xlnx_xvc_execute_scan(struct jtag_command *cmd,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	enum scan_type type = jtag_scan_type(cmd->cmd.scan);
 	enum tap_state saved_end_state = cmd->cmd.scan->end_state;
@@ -253,13 +381,13 @@ static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
 	 */
 	if (ir_scan && tap_get_state() != TAP_IRSHIFT) {
 		tap_set_end_state(TAP_IRSHIFT);
-		err = xlnx_pcie_xvc_execute_statemove(0);
+		err = xlnx_xvc_execute_statemove(0, xvc_type);
 		if (err != ERROR_OK)
 			goto out_err;
 		tap_set_end_state(saved_end_state);
 	} else if (!ir_scan && (tap_get_state() != TAP_DRSHIFT)) {
 		tap_set_end_state(TAP_DRSHIFT);
-		err = xlnx_pcie_xvc_execute_statemove(0);
+		err = xlnx_xvc_execute_statemove(0, xvc_type);
 		if (err != ERROR_OK)
 			goto out_err;
 		tap_set_end_state(saved_end_state);
@@ -271,8 +399,8 @@ static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
 		/* the last TMS should be a 1, to leave the state */
 		tms = left <= XLNX_XVC_MAX_BITS ? BIT(write - 1) : 0;
 		tdi = (type != SCAN_IN) ? buf_get_u32(rd_ptr, 0, write) : 0;
-		err = xlnx_pcie_xvc_transact(write, tms, tdi, type != SCAN_OUT ?
-					     &tdo : NULL);
+		err = xlnx_xvc_transact(write, tms, tdi, type != SCAN_OUT ?
+						 &tdo : NULL, xvc_type);
 		if (err != ERROR_OK)
 			goto out_err;
 		left -= write;
@@ -285,7 +413,7 @@ static int xlnx_pcie_xvc_execute_scan(struct jtag_command *cmd)
 	free(buf);
 
 	if (tap_get_state() != tap_get_end_state())
-		err = xlnx_pcie_xvc_execute_statemove(1);
+		err = xlnx_xvc_execute_statemove(1, xvc_type);
 
 	return err;
 
@@ -294,19 +422,14 @@ out_err:
 	return err;
 }
 
-static void xlnx_pcie_xvc_execute_reset(struct jtag_command *cmd)
-{
-	LOG_DEBUG("reset trst: %i srst: %i", cmd->cmd.reset->trst,
-		  cmd->cmd.reset->srst);
-}
-
-static void xlnx_pcie_xvc_execute_sleep(struct jtag_command *cmd)
+static void xlnx_xvc_execute_sleep(struct jtag_command *cmd)
 {
 	LOG_DEBUG("sleep %" PRIu32 "", cmd->cmd.sleep->us);
 	usleep(cmd->cmd.sleep->us);
 }
 
-static int xlnx_pcie_xvc_execute_tms(struct jtag_command *cmd)
+static int xlnx_xvc_execute_tms(struct jtag_command *cmd,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	const size_t num_bits = cmd->cmd.tms->num_bits;
 	const uint8_t *bits = cmd->cmd.tms->bits;
@@ -320,7 +443,7 @@ static int xlnx_pcie_xvc_execute_tms(struct jtag_command *cmd)
 	while (left) {
 		write = MIN(XLNX_XVC_MAX_BITS, left);
 		tms = buf_get_u32(bits, 0, write);
-		err = xlnx_pcie_xvc_transact(write, tms, 0, NULL);
+		err = xlnx_xvc_transact(write, tms, 0, NULL, xvc_type);
 		if (err != ERROR_OK)
 			return err;
 		left -= write;
@@ -330,29 +453,30 @@ static int xlnx_pcie_xvc_execute_tms(struct jtag_command *cmd)
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_execute_command(struct jtag_command *cmd)
+static int xlnx_xvc_execute_command(struct jtag_command *cmd,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	LOG_DEBUG("%s: cmd->type: %u", __func__, cmd->type);
 	switch (cmd->type) {
 	case JTAG_STABLECLOCKS:
-		return xlnx_pcie_xvc_execute_stableclocks(cmd);
+		return xlnx_xvc_execute_stableclocks(cmd, xvc_type);
 	case JTAG_RUNTEST:
-		return xlnx_pcie_xvc_execute_runtest(cmd);
+		return xlnx_xvc_execute_runtest(cmd, xvc_type);
 	case JTAG_TLR_RESET:
 		tap_set_end_state(cmd->cmd.statemove->end_state);
-		return xlnx_pcie_xvc_execute_statemove(0);
+		return xlnx_xvc_execute_statemove(0, xvc_type);
 	case JTAG_PATHMOVE:
-		return xlnx_pcie_xvc_execute_pathmove(cmd);
+		return xlnx_xvc_execute_pathmove(cmd, xvc_type);
 	case JTAG_SCAN:
-		return xlnx_pcie_xvc_execute_scan(cmd);
+		return xlnx_xvc_execute_scan(cmd, xvc_type);
 	case JTAG_RESET:
-		xlnx_pcie_xvc_execute_reset(cmd);
+		LOG_INFO("WARN: XVC driver has no reset.");
 		break;
 	case JTAG_SLEEP:
-		xlnx_pcie_xvc_execute_sleep(cmd);
+		xlnx_xvc_execute_sleep(cmd);
 		break;
 	case JTAG_TMS:
-		return xlnx_pcie_xvc_execute_tms(cmd);
+		return xlnx_xvc_execute_tms(cmd, xvc_type);
 	default:
 		LOG_ERROR("BUG: Unknown JTAG command type encountered.");
 		return ERROR_JTAG_QUEUE_FAILED;
@@ -361,13 +485,14 @@ static int xlnx_pcie_xvc_execute_command(struct jtag_command *cmd)
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_execute_queue(struct jtag_command *cmd_queue)
+static int xlnx_xvc_execute_queue(struct jtag_command *cmd_queue,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	struct jtag_command *cmd = cmd_queue;
 	int ret;
 
 	while (cmd) {
-		ret = xlnx_pcie_xvc_execute_command(cmd);
+		ret = xlnx_xvc_execute_command(cmd, xvc_type);
 
 		if (ret != ERROR_OK)
 			return ret;
@@ -378,6 +503,15 @@ static int xlnx_pcie_xvc_execute_queue(struct jtag_command *cmd_queue)
 	return ERROR_OK;
 }
 
+static int xlnx_pcie_xvc_execute_queue(struct jtag_command *cmd_queue)
+{
+	return xlnx_xvc_execute_queue(cmd_queue, PCIE);
+}
+
+static int xlnx_axi_xvc_execute_queue(struct jtag_command *cmd_queue)
+{
+	return xlnx_xvc_execute_queue(cmd_queue, AXI);
+}
 
 static int xlnx_pcie_xvc_init(void)
 {
@@ -399,8 +533,8 @@ static int xlnx_pcie_xvc_init(void)
 	 * vendor specific header */
 	xlnx_pcie_xvc->offset = PCIE_EXT_CAP_LST;
 	while (xlnx_pcie_xvc->offset <= PCI_CFG_SPACE_EXP_SIZE - sizeof(cap) &&
-	       xlnx_pcie_xvc->offset >= PCIE_EXT_CAP_LST) {
-		err = xlnx_pcie_xvc_read_reg(XLNX_XVC_EXT_CAP, &cap);
+		   xlnx_pcie_xvc->offset >= PCIE_EXT_CAP_LST) {
+		err = xlnx_pcie_xvc_read_reg(XLNX_PCIE_XVC_EXT_CAP, &cap);
 		if (err != ERROR_OK)
 			return err;
 		LOG_DEBUG("Checking capability at 0x%x; id=0x%04" PRIx32 " version=0x%" PRIx32 " next=0x%" PRIx32,
@@ -409,7 +543,7 @@ static int xlnx_pcie_xvc_init(void)
 			 PCI_EXT_CAP_VER(cap),
 			 PCI_EXT_CAP_NEXT(cap));
 		if (PCI_EXT_CAP_ID(cap) == PCI_EXT_CAP_ID_VNDR) {
-			err = xlnx_pcie_xvc_read_reg(XLNX_XVC_VSEC_HDR, &vh);
+			err = xlnx_pcie_xvc_read_reg(XLNX_PCIE_XVC_VSEC_HDR, &vh);
 			if (err != ERROR_OK)
 				return err;
 			LOG_DEBUG("Checking possible match at 0x%x; id: 0x%" PRIx32 "; rev: 0x%" PRIx32 "; length: 0x%" PRIx32,
@@ -417,14 +551,14 @@ static int xlnx_pcie_xvc_init(void)
 				 PCI_VNDR_HEADER_ID(vh),
 				 PCI_VNDR_HEADER_REV(vh),
 				 PCI_VNDR_HEADER_LEN(vh));
-			if ((PCI_VNDR_HEADER_ID(vh) == XLNX_XVC_VSEC_ID) &&
-			    (PCI_VNDR_HEADER_LEN(vh) == XLNX_XVC_CAP_SIZE))
+			if ((PCI_VNDR_HEADER_ID(vh) == XLNX_PCIE_XVC_VSEC_ID) &&
+				(PCI_VNDR_HEADER_LEN(vh) == XLNX_PCIE_XVC_CAP_SIZE))
 				break;
 		}
 		xlnx_pcie_xvc->offset = PCI_EXT_CAP_NEXT(cap);
 	}
-	if ((xlnx_pcie_xvc->offset > PCI_CFG_SPACE_EXP_SIZE - XLNX_XVC_CAP_SIZE) ||
-	     xlnx_pcie_xvc->offset < PCIE_EXT_CAP_LST) {
+	if ((xlnx_pcie_xvc->offset > PCI_CFG_SPACE_EXP_SIZE - XLNX_PCIE_XVC_CAP_SIZE) ||
+		 xlnx_pcie_xvc->offset < PCIE_EXT_CAP_LST) {
 		close(xlnx_pcie_xvc->fd);
 		return ERROR_JTAG_INIT_FAILED;
 	}
@@ -434,6 +568,44 @@ static int xlnx_pcie_xvc_init(void)
 	return ERROR_OK;
 }
 
+static int xlnx_axi_xvc_init(void)
+{
+	uint64_t baseaddr;
+
+	if (xlnx_axi_xvc->device_addr) {
+		baseaddr = strtoul(xlnx_axi_xvc->device_addr, NULL, 0);
+	} else {
+		LOG_ERROR("Please set device addr.");
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
+	if (xlnx_axi_xvc->device_file) {
+		LOG_INFO("Opening %s for AXI communication", xlnx_axi_xvc->device_file);
+		xlnx_axi_xvc->fd = open(xlnx_axi_xvc->device_file, O_RDWR | O_SYNC);
+	} else {
+		LOG_INFO("Opening /dev/mem for AXI communication");
+		xlnx_axi_xvc->fd = open("/dev/mem", O_RDWR | O_SYNC);
+	}
+
+	if (xlnx_axi_xvc->fd < 0) {
+		LOG_ERROR("Failed to open device file, check permissions.");
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
+	xlnx_axi_xvc->base = mmap(0, XLNX_AXI_XVC_MAX_REG, PROT_READ | PROT_WRITE,
+								  MAP_SHARED, xlnx_axi_xvc->fd, baseaddr);
+	if (xlnx_axi_xvc->base == MAP_FAILED) {
+		LOG_ERROR("mmap() failed, check permissions.");
+		close(xlnx_axi_xvc->fd);
+		return ERROR_JTAG_INIT_FAILED;
+	}
+
+	LOG_INFO("Mapped Xilinx XVC/AXI vaddr %p paddr 0x%" PRIx64,
+			 xlnx_axi_xvc->base, baseaddr);
+
+	return ERROR_OK;
+}
+
 static int xlnx_pcie_xvc_quit(void)
 {
 	int err;
@@ -445,21 +617,55 @@ static int xlnx_pcie_xvc_quit(void)
 	return ERROR_OK;
 }
 
+static int xlnx_axi_xvc_quit(void)
+{
+	int err;
+
+	munmap(xlnx_axi_xvc->base, XLNX_AXI_XVC_MAX_REG);
+	free(xlnx_pcie_xvc->device);
+	free(xlnx_axi_xvc->device_file);
+	free(xlnx_axi_xvc->device_addr);
+
+	err = close(xlnx_axi_xvc->fd);
+	if (err)
+		return err;
+
+	return ERROR_OK;
+}
+
 COMMAND_HANDLER(xlnx_pcie_xvc_handle_config_command)
 {
-	if (CMD_ARGC < 1)
+	if (CMD_ARGC != 1)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	/* we can't really free this in a safe manner, so at least
-	 * limit the memory we're leaking by freeing the old one first
-	 * before allocating a new one ...
-	 */
 	free(xlnx_pcie_xvc->device);
 
 	xlnx_pcie_xvc->device = strdup(CMD_ARGV[0]);
 	return ERROR_OK;
 }
 
+COMMAND_HANDLER(xlnx_axi_xvc_handle_dev_addr_command)
+{
+	if (CMD_ARGC != 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	free(xlnx_axi_xvc->device_addr);
+
+	xlnx_axi_xvc->device_addr = strdup(CMD_ARGV[0]);
+	return ERROR_OK;
+}
+
+COMMAND_HANDLER(xlnx_axi_xvc_handle_dev_file_command)
+{
+	if (CMD_ARGC != 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	free(xlnx_axi_xvc->device_file);
+
+	xlnx_axi_xvc->device_file = strdup(CMD_ARGV[0]);
+	return ERROR_OK;
+}
+
 static const struct command_registration xlnx_pcie_xvc_subcommand_handlers[] = {
 	{
 		.name = "config",
@@ -482,11 +688,45 @@ static const struct command_registration xlnx_pcie_xvc_command_handlers[] = {
 	COMMAND_REGISTRATION_DONE
 };
 
+static const struct command_registration xlnx_axi_xvc_subcommand_handlers[] = {
+	{
+		.name = "dev_addr",
+		.handler = xlnx_axi_xvc_handle_dev_addr_command,
+		.mode = COMMAND_CONFIG,
+		.help = "Configure XVC/AXI JTAG device memory address",
+		.usage = "addr",
+	},
+	{
+		.name = "dev_file",
+		.handler = xlnx_axi_xvc_handle_dev_file_command,
+		.mode = COMMAND_CONFIG,
+		.help = "Configure XVC/AXI JTAG device file location",
+		.usage = "addr",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
+static const struct command_registration xlnx_axi_xvc_command_handlers[] = {
+	{
+		.name = "xlnx_axi_xvc",
+		.mode = COMMAND_ANY,
+		.help = "perform xlnx_axi_xvc management",
+		.chain = xlnx_axi_xvc_subcommand_handlers,
+		.usage = "",
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
 static struct jtag_interface xlnx_pcie_xvc_jtag_ops = {
 	.execute_queue = &xlnx_pcie_xvc_execute_queue,
 };
 
-static int xlnx_pcie_xvc_swd_sequence(const uint8_t *seq, size_t length)
+static struct jtag_interface xlnx_axi_xvc_jtag_ops = {
+	.execute_queue = &xlnx_axi_xvc_execute_queue,
+};
+
+static int xlnx_xvc_swd_sequence(const uint8_t *seq, size_t length,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	size_t left, write;
 	uint32_t send;
@@ -496,7 +736,7 @@ static int xlnx_pcie_xvc_swd_sequence(const uint8_t *seq, size_t length)
 	while (left) {
 		write = MIN(XLNX_XVC_MAX_BITS, left);
 		send = buf_get_u32(seq, 0, write);
-		err = xlnx_pcie_xvc_transact(write, send, 0, NULL);
+		err = xlnx_xvc_transact(write, send, 0, NULL, xvc_type);
 		if (err != ERROR_OK)
 			return err;
 		left -= write;
@@ -506,21 +746,22 @@ static int xlnx_pcie_xvc_swd_sequence(const uint8_t *seq, size_t length)
 	return ERROR_OK;
 }
 
-static int xlnx_pcie_xvc_swd_switch_seq(enum swd_special_seq seq)
+static int xlnx_xvc_swd_switch_seq(enum swd_special_seq seq,
+		enum xlnx_xvc_type_t xvc_type)
 {
 	switch (seq) {
 	case LINE_RESET:
 		LOG_DEBUG("SWD line reset");
-		return xlnx_pcie_xvc_swd_sequence(swd_seq_line_reset,
-						  swd_seq_line_reset_len);
+		return xlnx_xvc_swd_sequence(swd_seq_line_reset,
+						  swd_seq_line_reset_len, xvc_type);
 	case JTAG_TO_SWD:
 		LOG_DEBUG("JTAG-to-SWD");
-		return xlnx_pcie_xvc_swd_sequence(swd_seq_jtag_to_swd,
-						  swd_seq_jtag_to_swd_len);
+		return xlnx_xvc_swd_sequence(swd_seq_jtag_to_swd,
+						  swd_seq_jtag_to_swd_len, xvc_type);
 	case SWD_TO_JTAG:
 		LOG_DEBUG("SWD-to-JTAG");
-		return xlnx_pcie_xvc_swd_sequence(swd_seq_swd_to_jtag,
-						  swd_seq_swd_to_jtag_len);
+		return xlnx_xvc_swd_sequence(swd_seq_swd_to_jtag,
+						  swd_seq_swd_to_jtag_len, xvc_type);
 	default:
 		LOG_ERROR("Sequence %d not supported", seq);
 		return ERROR_FAIL;
@@ -529,19 +770,31 @@ static int xlnx_pcie_xvc_swd_switch_seq(enum swd_special_seq seq)
 	return ERROR_OK;
 }
 
+static int xlnx_pcie_xvc_swd_switch_seq(enum swd_special_seq seq)
+{
+	return xlnx_xvc_swd_switch_seq(seq, PCIE);
+}
+
+static int xlnx_axi_xvc_swd_switch_seq(enum swd_special_seq seq)
+{
+	return xlnx_xvc_swd_switch_seq(seq, AXI);
+}
+
 static int queued_retval;
 
-static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
-					uint32_t ap_delay_clk);
+static void xlnx_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+					uint32_t ap_delay_clk,
+					enum xlnx_xvc_type_t xvc_type);
 
-static void swd_clear_sticky_errors(void)
+static void swd_clear_sticky_errors(enum xlnx_xvc_type_t xvc_type)
 {
-	xlnx_pcie_xvc_swd_write_reg(swd_cmd(false,  false, DP_ABORT),
-		STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0);
+	xlnx_xvc_swd_write_reg(swd_cmd(false,  false, DP_ABORT),
+		STKCMPCLR | STKERRCLR | WDERRCLR | ORUNERRCLR, 0, xvc_type);
 }
 
-static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
-				       uint32_t ap_delay_clk)
+static void xlnx_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
+					uint32_t ap_delay_clk,
+					enum xlnx_xvc_type_t xvc_type)
 {
 	uint32_t res, ack, rpar;
 	int err;
@@ -550,23 +803,23 @@ static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
 
 	cmd |= SWD_CMD_START | SWD_CMD_PARK;
 	/* cmd + ack */
-	err = xlnx_pcie_xvc_transact(12, cmd, 0, &res);
+	err = xlnx_xvc_transact(12, cmd, 0, &res, xvc_type);
 	if (err != ERROR_OK)
 		goto err_out;
 
 	ack = MASK_ACK(res);
 
 	/* read data */
-	err = xlnx_pcie_xvc_transact(32, 0, 0, &res);
+	err = xlnx_xvc_transact(32, 0, 0, &res, xvc_type);
 	if (err != ERROR_OK)
 		goto err_out;
 
 	/* parity + trn */
-	err = xlnx_pcie_xvc_transact(2, 0, 0, &rpar);
+	err = xlnx_xvc_transact(2, 0, 0, &rpar, xvc_type);
 	if (err != ERROR_OK)
 		goto err_out;
 
-	LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
+	LOG_DEBUG("%s %s %s reg %X = %08" PRIx32,
 		  ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
 		  "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
 		  cmd & SWD_CMD_APNDP ? "AP" : "DP",
@@ -583,19 +836,19 @@ static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
 		if (value)
 			*value = res;
 		if (cmd & SWD_CMD_APNDP)
-			err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
+			err = xlnx_xvc_transact(ap_delay_clk, 0, 0, NULL, xvc_type);
 		queued_retval = err;
 		return;
 	case SWD_ACK_WAIT:
 		LOG_DEBUG_IO("SWD_ACK_WAIT");
-		swd_clear_sticky_errors();
+		swd_clear_sticky_errors(xvc_type);
 		return;
 	case SWD_ACK_FAULT:
 		LOG_DEBUG_IO("SWD_ACK_FAULT");
 		queued_retval = ack;
 		return;
 	default:
-		LOG_DEBUG_IO("No valid acknowledge: ack=%02"PRIx32, ack);
+		LOG_DEBUG_IO("No valid acknowledge: ack=%02" PRIx32, ack);
 		queued_retval = ack;
 		return;
 	}
@@ -603,8 +856,21 @@ err_out:
 	queued_retval = err;
 }
 
-static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+static void xlnx_pcie_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
 					uint32_t ap_delay_clk)
+{
+	xlnx_xvc_swd_read_reg(cmd, value, ap_delay_clk, PCIE);
+}
+
+static void xlnx_axi_xvc_swd_read_reg(uint8_t cmd, uint32_t *value,
+					uint32_t ap_delay_clk)
+{
+	xlnx_xvc_swd_read_reg(cmd, value, ap_delay_clk, AXI);
+}
+
+static void xlnx_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+					uint32_t ap_delay_clk,
+					enum xlnx_xvc_type_t xvc_type)
 {
 	uint32_t res, ack;
 	int err;
@@ -613,23 +879,23 @@ static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
 
 	cmd |= SWD_CMD_START | SWD_CMD_PARK;
 	/* cmd + trn + ack */
-	err = xlnx_pcie_xvc_transact(13, cmd, 0, &res);
+	err = xlnx_xvc_transact(13, cmd, 0, &res, xvc_type);
 	if (err != ERROR_OK)
 		goto err_out;
 
 	ack = MASK_ACK(res);
 
 	/* write data */
-	err = xlnx_pcie_xvc_transact(32, value, 0, NULL);
+	err = xlnx_xvc_transact(32, value, 0, NULL, xvc_type);
 	if (err != ERROR_OK)
 		goto err_out;
 
 	/* parity + trn */
-	err = xlnx_pcie_xvc_transact(2, parity_u32(value), 0, NULL);
+	err = xlnx_xvc_transact(2, parity_u32(value), 0, NULL, xvc_type);
 	if (err != ERROR_OK)
 		goto err_out;
 
-	LOG_DEBUG("%s %s %s reg %X = %08"PRIx32,
+	LOG_DEBUG("%s %s %s reg %X = %08" PRIx32,
 		  ack == SWD_ACK_OK ? "OK" : ack == SWD_ACK_WAIT ?
 		  "WAIT" : ack == SWD_ACK_FAULT ? "FAULT" : "JUNK",
 		  cmd & SWD_CMD_APNDP ? "AP" : "DP",
@@ -640,19 +906,19 @@ static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
 	switch (ack) {
 	case SWD_ACK_OK:
 		if (cmd & SWD_CMD_APNDP)
-			err = xlnx_pcie_xvc_transact(ap_delay_clk, 0, 0, NULL);
+			err = xlnx_xvc_transact(ap_delay_clk, 0, 0, NULL, xvc_type);
 		queued_retval = err;
 		return;
 	case SWD_ACK_WAIT:
 		LOG_DEBUG_IO("SWD_ACK_WAIT");
-		swd_clear_sticky_errors();
+		swd_clear_sticky_errors(xvc_type);
 		return;
 	case SWD_ACK_FAULT:
 		LOG_DEBUG_IO("SWD_ACK_FAULT");
 		queued_retval = ack;
 		return;
 	default:
-		LOG_DEBUG_IO("No valid acknowledge: ack=%02"PRIx32, ack);
+		LOG_DEBUG_IO("No valid acknowledge: ack=%02" PRIx32, ack);
 		queued_retval = ack;
 		return;
 	}
@@ -661,12 +927,24 @@ err_out:
 	queued_retval = err;
 }
 
-static int xlnx_pcie_xvc_swd_run_queue(void)
+static void xlnx_pcie_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+					uint32_t ap_delay_clk)
+{
+	xlnx_xvc_swd_write_reg(cmd, value, ap_delay_clk, PCIE);
+}
+
+static void xlnx_axi_xvc_swd_write_reg(uint8_t cmd, uint32_t value,
+					uint32_t ap_delay_clk)
+{
+	xlnx_xvc_swd_write_reg(cmd, value, ap_delay_clk, AXI);
+}
+
+static int xlnx_xvc_swd_run_queue(enum xlnx_xvc_type_t xvc_type)
 {
 	int err;
 
 	/* we want at least 8 idle cycles between each transaction */
-	err = xlnx_pcie_xvc_transact(8, 0, 0, NULL);
+	err = xlnx_xvc_transact(8, 0, 0, NULL, xvc_type);
 	if (err != ERROR_OK)
 		return err;
 
@@ -677,19 +955,37 @@ static int xlnx_pcie_xvc_swd_run_queue(void)
 	return err;
 }
 
-static int xlnx_pcie_xvc_swd_init(void)
+static int xlnx_pcie_xvc_swd_run_queue(void)
+{
+	return xlnx_xvc_swd_run_queue(PCIE);
+}
+
+static int xlnx_axi_xvc_swd_run_queue(void)
+{
+	return xlnx_xvc_swd_run_queue(AXI);
+}
+
+static int xlnx_xvc_swd_init(void)
 {
 	return ERROR_OK;
 }
 
 static const struct swd_driver xlnx_pcie_xvc_swd_ops = {
-	.init = xlnx_pcie_xvc_swd_init,
+	.init = xlnx_xvc_swd_init,
 	.switch_seq = xlnx_pcie_xvc_swd_switch_seq,
 	.read_reg = xlnx_pcie_xvc_swd_read_reg,
 	.write_reg = xlnx_pcie_xvc_swd_write_reg,
 	.run = xlnx_pcie_xvc_swd_run_queue,
 };
 
+static const struct swd_driver xlnx_axi_xvc_swd_ops = {
+	.init = xlnx_xvc_swd_init,
+	.switch_seq = xlnx_axi_xvc_swd_switch_seq,
+	.read_reg = xlnx_axi_xvc_swd_read_reg,
+	.write_reg = xlnx_axi_xvc_swd_write_reg,
+	.run = xlnx_axi_xvc_swd_run_queue,
+};
+
 struct adapter_driver xlnx_pcie_xvc_adapter_driver = {
 	.name = "xlnx_pcie_xvc",
 	.transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD,
@@ -702,3 +998,16 @@ struct adapter_driver xlnx_pcie_xvc_adapter_driver = {
 	.jtag_ops = &xlnx_pcie_xvc_jtag_ops,
 	.swd_ops  = &xlnx_pcie_xvc_swd_ops,
 };
+
+struct adapter_driver xlnx_axi_xvc_adapter_driver = {
+	.name = "xlnx_axi_xvc",
+	.transport_ids = TRANSPORT_JTAG | TRANSPORT_SWD,
+	.transport_preferred_id = TRANSPORT_JTAG,
+	.commands = xlnx_axi_xvc_command_handlers,
+
+	.init = &xlnx_axi_xvc_init,
+	.quit = &xlnx_axi_xvc_quit,
+
+	.jtag_ops = &xlnx_axi_xvc_jtag_ops,
+	.swd_ops  = &xlnx_axi_xvc_swd_ops,
+};
diff --git a/src/jtag/interface.h b/src/jtag/interface.h
index 834997361..fb26c94ad 100644
--- a/src/jtag/interface.h
+++ b/src/jtag/interface.h
@@ -411,6 +411,7 @@ extern struct adapter_driver usbprog_adapter_driver;
 extern struct adapter_driver vdebug_adapter_driver;
 extern struct adapter_driver vsllink_adapter_driver;
 extern struct adapter_driver xds110_adapter_driver;
+extern struct adapter_driver xlnx_axi_xvc_adapter_driver;
 extern struct adapter_driver xlnx_pcie_xvc_adapter_driver;
 
 #endif /* OPENOCD_JTAG_INTERFACE_H */
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index 4bb2822d1..099b84425 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -156,7 +156,8 @@ struct adapter_driver *adapter_drivers[] = {
 		&xds110_adapter_driver,
 #endif
 #if BUILD_XLNX_XVC == 1
-		&xlnx_pcie_xvc_adapter_driver,
+	&xlnx_pcie_xvc_adapter_driver,
+	&xlnx_axi_xvc_adapter_driver,
 #endif
 
 		NULL,
diff --git a/src/jtag/startup.tcl b/src/jtag/startup.tcl
index 2d8ebf041..88d802fcb 100644
--- a/src/jtag/startup.tcl
+++ b/src/jtag/startup.tcl
@@ -413,6 +413,12 @@ proc xlnx_pcie_xvc_config args {
 	eval xlnx_pcie_xvc config $args
 }
 
+lappend _telnet_autocomplete_skip xlnx_axi_xvc_config
+proc xlnx_axi_xvc_config args {
+	echo "DEPRECATED! use 'xlnx_axi_xvc config' not 'xlnx_axi_xvc_config'"
+	eval xlnx_axi_xvc config $args
+}
+
 lappend _telnet_autocomplete_skip ulink_download_firmware
 proc ulink_download_firmware args {
 	echo "DEPRECATED! use 'ulink download_firmware' not 'ulink_download_firmware'"

commit 8cdf8cb99567654ff2b33feb781680159c9fbd63
Author: Nicolas Derumigny <nic...@in...>
Date:   Mon Jun 30 11:21:18 2025 +0200

    driver: jtag: rename xlnx-pcie-xvc to xlnx-xvc
    
    Rename xlnx-pcie-xvc.c to xlnx-xvc.c in provision for AXI support
    
    Signed-off-by: Nicolas Derumigny <nic...@in...>
    Change-Id: I287fdcb8edf97f48c6f8614ac4c456f8ba197011
    Reviewed-on: https://review.openocd.org/c/openocd/+/8980
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/configure.ac b/configure.ac
index 453cbcfb5..9bbb2c36a 100644
--- a/configure.ac
+++ b/configure.ac
@@ -178,7 +178,7 @@ m4_define([LIBJAYLINK_ADAPTERS],
 	[[[jlink], [SEGGER J-Link Programmer], [JLINK]]])
 
 m4_define([PCIE_ADAPTERS],
-	[[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_PCIE_XVC]]])
+	[[[xlnx_pcie_xvc], [Xilinx XVC/PCIe], [XLNX_XVC]]])
 
 m4_define([SERIAL_PORT_ADAPTERS],
 	[[[buspirate], [Bus Pirate], [BUS_PIRATE]]])
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index b0dd8e3ad..e55e0478c 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -179,8 +179,8 @@ endif
 if LINUXSPIDEV
 DRIVERFILES += %D%/linuxspidev.c
 endif
-if XLNX_PCIE_XVC
-DRIVERFILES += %D%/xlnx-pcie-xvc.c
+if XLNX_XVC
+DRIVERFILES += %D%/xlnx-xvc.c
 endif
 if BCM2835GPIO
 DRIVERFILES += %D%/bcm2835gpio.c
diff --git a/src/jtag/drivers/xlnx-pcie-xvc.c b/src/jtag/drivers/xlnx-xvc.c
similarity index 100%
rename from src/jtag/drivers/xlnx-pcie-xvc.c
rename to src/jtag/drivers/xlnx-xvc.c
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index 834247245..4bb2822d1 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -155,7 +155,7 @@ struct adapter_driver *adapter_drivers[] = {
 #if BUILD_XDS110 == 1
 		&xds110_adapter_driver,
 #endif
-#if BUILD_XLNX_PCIE_XVC == 1
+#if BUILD_XLNX_XVC == 1
 		&xlnx_pcie_xvc_adapter_driver,
 #endif
 

-----------------------------------------------------------------------

Summary of changes:
 configure.ac                                     |  11 +-
 doc/openocd.texi                                 |  21 +
 src/jtag/drivers/Makefile.am                     |   4 +-
 src/jtag/drivers/{xlnx-pcie-xvc.c => xlnx-xvc.c} | 523 ++++++++++++++++++-----
 src/jtag/interface.h                             |   1 +
 src/jtag/interfaces.c                            |   5 +-
 src/jtag/startup.tcl                             |   6 +
 7 files changed, 455 insertions(+), 116 deletions(-)
 rename src/jtag/drivers/{xlnx-pcie-xvc.c => xlnx-xvc.c} (50%)


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- Log -----------------------------------------------------------------
commit cbc32c3831e39fd07f5fe0dc1cfb9a7be77ffa86
Author: Tomas Vanek <va...@fb...>
Date:   Thu Jul 3 06:52:29 2025 +0200

    flash/nor/stm32l4x: fix permanent write protection on STM32U5
    
    Unlike other devices supported by this driver STM32U5 devices
    have a new UNLOCK bit in FLASH_WRP1AR, WRP1BR, WRP2AR, WRP2BR
    registers. Writing zero to this bit makes the write protection
    block permanent with no way to unprotect.
    
    Commit 6554d176e926 ("flash/stm32l4x: support STM32U59/U5Ax devices")
    and later commits with additional U5 devices lack support for
    the UNLOCK bit and therefore makes write protection permanent
    without warning.
    
    Introduce the new bit flag F_WRP_HAS_LOCK and mark U5 devices by it.
    Set UNLOCK bit in stm32l4_write_one_wrpxy() if F_WRP_HAS_LOCK is set.
    
    Change-Id: I26b97d855e094a21540e3377f367520683af2eac
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8981
    Tested-by: jenkins

diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index f16333201..8001aaf00 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -152,6 +152,9 @@
 /* this flag indicates that programming should be done in quad-word
  * the default programming word size is double-word */
 #define F_QUAD_WORD_PROG    BIT(4)
+/* the registers WRPxyR have UNLOCK bit - writing zero locks the write
+ * protection region permanently! */
+#define F_WRP_HAS_LOCK		BIT(5)
 /* end of STM32L4 flags ******************************************************/
 
 
@@ -500,7 +503,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .num_revs              = ARRAY_SIZE(stm32u53_u54xx_revs),
 	  .device_str            = "STM32U535/U545",
 	  .max_flash_size_kb     = 512,
-	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
+								| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0BFA07A0,
 	  .otp_base              = 0x0BFA0000,
@@ -692,7 +696,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .num_revs              = ARRAY_SIZE(stm32u59_u5axx_revs),
 	  .device_str            = "STM32U59/U5Axx",
 	  .max_flash_size_kb     = 4096,
-	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
+								| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0BFA07A0,
 	  .otp_base              = 0x0BFA0000,
@@ -704,7 +709,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .num_revs              = ARRAY_SIZE(stm32u57_u58xx_revs),
 	  .device_str            = "STM32U57/U58xx",
 	  .max_flash_size_kb     = 2048,
-	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
+								| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0BFA07A0,
 	  .otp_base              = 0x0BFA0000,
@@ -716,7 +722,8 @@ static const struct stm32l4_part_info stm32l4_parts[] = {
 	  .num_revs              = ARRAY_SIZE(stm32u5f_u5gxx_revs),
 	  .device_str            = "STM32U5F/U5Gxx",
 	  .max_flash_size_kb     = 4096,
-	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ | F_HAS_L5_FLASH_REGS,
+	  .flags                 = F_HAS_DUAL_BANK | F_QUAD_WORD_PROG | F_HAS_TZ
+								| F_HAS_L5_FLASH_REGS | F_WRP_HAS_LOCK,
 	  .flash_regs_base       = 0x40022000,
 	  .fsize_addr            = 0x0BFA07A0,
 	  .otp_base              = 0x0BFA0000,
@@ -1287,6 +1294,8 @@ static int stm32l4_write_one_wrpxy(struct flash_bank *bank, struct stm32l4_wrp *
 	int wrp_end = wrpxy->last - wrpxy->offset;
 
 	uint32_t wrp_value = (wrp_start & stm32l4_info->wrpxxr_mask) | ((wrp_end & stm32l4_info->wrpxxr_mask) << 16);
+	if (stm32l4_info->part_info->flags & F_WRP_HAS_LOCK)
+		wrp_value |= FLASH_WRPXYR_UNLOCK;
 
 	return stm32l4_write_option(bank, stm32l4_info->flash_regs[wrpxy->reg_idx], wrp_value, 0xffffffff);
 }
diff --git a/src/flash/nor/stm32l4x.h b/src/flash/nor/stm32l4x.h
index 07b3615a2..1f4f2344f 100644
--- a/src/flash/nor/stm32l4x.h
+++ b/src/flash/nor/stm32l4x.h
@@ -69,6 +69,9 @@
 #define FLASH_U5_DUALBANK		BIT(21)
 #define FLASH_TZEN				BIT(31)
 
+/* FLASH_WRPxyR register bits */
+#define FLASH_WRPXYR_UNLOCK		BIT(31)
+
 /* FLASH secure block based bank 1/2 register offsets */
 #define FLASH_SECBB1(X) (0x80 + 4 * (X - 1))
 #define FLASH_SECBB2(X) (0xA0 + 4 * (X - 1))

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/stm32l4x.c | 17 +++++++++++++----
 src/flash/nor/stm32l4x.h |  3 +++
 2 files changed, 16 insertions(+), 4 deletions(-)


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- Log -----------------------------------------------------------------
commit 09a54c3a89af563329adf757990e0c6dd83a1095
Author: Tomas Vanek <va...@fb...>
Date:   Fri Jan 3 18:23:07 2025 +0100

    target/arm_adi: add URLs of latest ARM ADI spec
    
    While on it warn about screwed SWD diagrams in ADI spec
    and add reference to a SWD timing diagram.
    
    Change-Id: I628d707ebf8ce7c22ba19bdcfd06028d4eaa60f8
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8690
    Tested-by: jenkins

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index df897b80e..67a3fcc57 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -50,8 +50,16 @@
 /*
  * Relevant specifications from ARM include:
  *
- * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031F
+ * ARM(tm) Debug Interface v5 Architecture Specification    ARM IHI 0031G
+ * https://developer.arm.com/documentation/ihi0031/latest/
+ *
  * ARM(tm) Debug Interface v6 Architecture Specification    ARM IHI 0074C
+ * https://developer.arm.com/documentation/ihi0074/latest/
+ *
+ * Note that diagrams B4-1 to B4-7 in both ADI specifications show
+ * SWCLK signal mostly in wrong polarity. See detailed SWD timing
+ * https://developer.arm.com/documentation/dui0499/b/arm-dstream-target-interface-connections/swd-timing-requirements
+ *
  * CoreSight(tm) v1.0 Architecture Specification            ARM IHI 0029B
  *
  * CoreSight(tm) DAP-Lite TRM, ARM DDI 0316D

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_adi_v5.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)


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commit f71b0bbd7b31627dfdfb87741cf207d83335357c
Author: Tomas Vanek <va...@fb...>
Date:   Fri Jan 3 15:04:43 2025 +0100

    jtag/swd: extend ap_delay_hint parameter comments
    
    Assure that zero is passed in ap_delay_hint in case of DP r/w.
    
    Change-Id: I5cd53b99950a7f1398b88f7394b3e66530803479
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8689
    Tested-by: jenkins

diff --git a/src/jtag/swd.h b/src/jtag/swd.h
index 3fe1365b5..c4b6215ab 100644
--- a/src/jtag/swd.h
+++ b/src/jtag/swd.h
@@ -270,6 +270,7 @@ struct swd_driver {
 	 * @param Where to store value to read from register
 	 * @param ap_delay_hint Number of idle cycles that may be
 	 * needed after an AP access to avoid WAITs
+	 * or zero in case of DP read.
 	 */
 	void (*read_reg)(uint8_t cmd, uint32_t *value, uint32_t ap_delay_hint);
 
@@ -280,6 +281,7 @@ struct swd_driver {
 	 * @param Value to be written to the register
 	 * @param ap_delay_hint Number of idle cycles that may be
 	 * needed after an AP access to avoid WAITs
+	 * or zero in case of DP write.
 	 */
 	void (*write_reg)(uint8_t cmd, uint32_t value, uint32_t ap_delay_hint);
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/swd.h | 2 ++
 1 file changed, 2 insertions(+)


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- Log -----------------------------------------------------------------
commit 537d907555ddd5137a6fecfc6d0d74b404b3445a
Author: Nishanth Menon <nm...@ti...>
Date:   Mon Jun 23 12:41:04 2025 -0500

    tcl/board/ti_*_swd_native.cfg: Add explicit transport info
    
    We use swd emulation in direct memory operations. Instead of relying
    on deprecated autoselect of transport, explicitly state swd as
    transport scheme.
    
    Change-Id: Iec7e2ad18edd365992cd7ba88558494bccf49fd2
    Signed-off-by: Nishanth Menon <nm...@ti...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8975
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/board/ti_am625_swd_native.cfg b/tcl/board/ti_am625_swd_native.cfg
index dc4b20579..65314fe5d 100644
--- a/tcl/board/ti_am625_swd_native.cfg
+++ b/tcl/board/ti_am625_swd_native.cfg
@@ -14,6 +14,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
 	set SOC am625
diff --git a/tcl/board/ti_am62a7_swd_native.cfg b/tcl/board/ti_am62a7_swd_native.cfg
index 99fc0b0b3..3d5e89228 100644
--- a/tcl/board/ti_am62a7_swd_native.cfg
+++ b/tcl/board/ti_am62a7_swd_native.cfg
@@ -14,6 +14,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
 	set SOC am62a7
diff --git a/tcl/board/ti_am62p_swd_native.cfg b/tcl/board/ti_am62p_swd_native.cfg
index fa549f358..a8c6bd120 100644
--- a/tcl/board/ti_am62p_swd_native.cfg
+++ b/tcl/board/ti_am62p_swd_native.cfg
@@ -14,6 +14,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
 	set SOC am62p
diff --git a/tcl/board/ti_j721e_swd_native.cfg b/tcl/board/ti_j721e_swd_native.cfg
index 3041c3c34..38316387a 100644
--- a/tcl/board/ti_j721e_swd_native.cfg
+++ b/tcl/board/ti_j721e_swd_native.cfg
@@ -14,6 +14,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
         set SOC j721e
diff --git a/tcl/board/ti_j722s_swd_native.cfg b/tcl/board/ti_j722s_swd_native.cfg
index bbe0d508c..a171ec358 100644
--- a/tcl/board/ti_j722s_swd_native.cfg
+++ b/tcl/board/ti_j722s_swd_native.cfg
@@ -15,6 +15,7 @@
 
 # We are using dmem, which uses dapdirect_swd transport
 adapter driver dmem
+transport select swd
 
 if { ![info exists SOC] } {
 	set SOC j722s

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/ti_am625_swd_native.cfg  | 1 +
 tcl/board/ti_am62a7_swd_native.cfg | 1 +
 tcl/board/ti_am62p_swd_native.cfg  | 1 +
 tcl/board/ti_j721e_swd_native.cfg  | 1 +
 tcl/board/ti_j722s_swd_native.cfg  | 1 +
 5 files changed, 5 insertions(+)


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From: openocd-gerrit <ope...@us...> - 2025-06-29 07:43:39

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- Log -----------------------------------------------------------------
commit 04d51723d042f87057a012086003c19144732f3d
Author: R. Diez <rdi...@rd...>
Date:   Sat Jun 21 21:41:38 2025 +0200

    configure.ac: show the dmem adapter in the config summary
    
    Also enable this adapter by default (auto).
    
    Change-Id: I61597c8572115f838ab0c92021163436eb7b0d59
    Signed-off-by: R. Diez <rdi...@rd...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8971
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/configure.ac b/configure.ac
index 5a05f3171..453cbcfb5 100644
--- a/configure.ac
+++ b/configure.ac
@@ -165,6 +165,9 @@ m4_define([LIBFTDI_USB1_ADAPTERS],
 m4_define([LIBGPIOD_ADAPTERS],
 	[[[linuxgpiod], [Linux GPIO bitbang through libgpiod], [LINUXGPIOD]]])
 
+m4_define([DMEM_ADAPTER],
+	[[[dmem], [CoreSight Direct Memory], [DMEM]]])
+
 m4_define([SYSFSGPIO_ADAPTER],
 	[[[sysfsgpio], [Linux GPIO bitbang through sysfs], [SYSFSGPIO]]])
 
@@ -302,10 +305,6 @@ AS_IF([test "x$debug_malloc" = "xyes" -a "x$have_glibc" = "xyes"], [
   AC_DEFINE([_DEBUG_FREE_SPACE_],[1], [Include malloc free space in logging])
 ])
 
-AC_ARG_ENABLE([dmem],
-  AS_HELP_STRING([--enable-dmem], [Enable building the dmem driver]),
-  [build_dmem=$enableval], [build_dmem=no])
-
 m4_define([AC_ARG_ADAPTERS], [
   m4_foreach([adapterTuple], [$1],
 	[AC_ARG_ENABLE(ADAPTER_OPT([adapterTuple]),
@@ -326,6 +325,7 @@ AC_ARG_ADAPTERS([
   LIBFTDI_ADAPTERS,
   LIBFTDI_USB1_ADAPTERS,
   LIBGPIOD_ADAPTERS,
+  DMEM_ADAPTER,
   SYSFSGPIO_ADAPTER,
   REMOTE_BITBANG_ADAPTER,
   LINUXSPIDEV_ADAPTER,
@@ -503,12 +503,6 @@ AS_IF([test "x$build_parport" = "xyes"], [
   AC_DEFINE([BUILD_PARPORT], [0], [0 if you don't want parport.])
 ])
 
-AS_IF([test "x$build_dmem" = "xyes"], [
-  AC_DEFINE([BUILD_DMEM], [1], [1 if you want to debug via Direct Mem.])
-], [
-  AC_DEFINE([BUILD_DMEM], [0], [0 if you don't want to debug via Direct Mem.])
-])
-
 AS_IF([test "x$ADAPTER_VAR([dummy])" != "xno"], [
   build_bitbang=yes
 ])
@@ -646,6 +640,7 @@ PROCESS_ADAPTERS([HIDAPI_USB1_ADAPTERS], ["x$use_hidapi" = "xyes" -a "x$use_libu
 PROCESS_ADAPTERS([LIBFTDI_ADAPTERS], ["x$use_libftdi" = "xyes"], [libftdi])
 PROCESS_ADAPTERS([LIBFTDI_USB1_ADAPTERS], ["x$use_libftdi" = "xyes" -a "x$use_libusb1" = "xyes"], [libftdi and libusb-1.x])
 PROCESS_ADAPTERS([LIBGPIOD_ADAPTERS], ["x$use_libgpiod" = "xyes"], [Linux libgpiod])
+PROCESS_ADAPTERS([DMEM_ADAPTER], ["x$is_linux" = "xyes"], [Linux /dev/mem])
 PROCESS_ADAPTERS([SYSFSGPIO_ADAPTER], ["x$is_linux" = "xyes"], [Linux sysfs])
 PROCESS_ADAPTERS([REMOTE_BITBANG_ADAPTER], [true], [unused])
 PROCESS_ADAPTERS([LIBJAYLINK_ADAPTERS], ["x$use_internal_libjaylink" = "xyes" -o "x$use_libjaylink" = "xyes"], [libjaylink-0.2])
@@ -744,7 +739,6 @@ AM_CONDITIONAL([USE_LIBFTDI], [test "x$use_libftdi" = "xyes"])
 AM_CONDITIONAL([USE_LIBGPIOD], [test "x$use_libgpiod" = "xyes"])
 AM_CONDITIONAL([USE_HIDAPI], [test "x$use_hidapi" = "xyes"])
 AM_CONDITIONAL([USE_LIBJAYLINK], [test "x$use_libjaylink" = "xyes"])
-AM_CONDITIONAL([DMEM], [test "x$build_dmem" = "xyes"])
 AM_CONDITIONAL([HAVE_CAPSTONE], [test "x$enable_capstone" != "xno"])
 
 AM_CONDITIONAL([INTERNAL_JIMTCL], [test "x$use_internal_jimtcl" = "xyes"])
@@ -843,6 +837,7 @@ m4_foreach([adapterTuple], [USB1_ADAPTERS,
 	HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS,
 	LIBFTDI_USB1_ADAPTERS,
 	LIBGPIOD_ADAPTERS,
+	DMEM_ADAPTER,
 	SYSFSGPIO_ADAPTER,
 	REMOTE_BITBANG_ADAPTER,
 	LIBJAYLINK_ADAPTERS, PCIE_ADAPTERS, SERIAL_PORT_ADAPTERS,

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 17 ++++++-----------
 1 file changed, 6 insertions(+), 11 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1079-g7f1f18399

From: openocd-gerrit <ope...@us...> - 2025-06-29 07:43:23

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The branch, master has been updated
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       via  ff274122dc2fbf509b24480e97a98291db53a338 (commit)
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- Log -----------------------------------------------------------------
commit 7f1f18399ce626e30d5176fb9740ed5fcd312c43
Author: Antonio Borneo <bor...@gm...>
Date:   Sun Jun 22 11:03:41 2025 +0200

    jtag/drivers: dmem: fix build on Linux 32 bits
    
    On 32 bits machine both 'uintptr_t' and pointers are 32 bit.
    The cast
    (volatile uint32_t *)((uintptr_t)dmem_emu_virt_base_addr + addr)
    fails with error
            error: cast to pointer from integer of different size
            [-Werror=int-to-pointer-cast]
    in lines 100 and 109 because:
    - 'addr' is a 'uint64_t';
    - adding 'uintptr_t' and 'uint64_t' returns a 64 bit value;
    - cast the 64 bit to 'uint32_t *' is an error.
    
    In the code the value passed to 'addr' is always 32 bit wide, so
    there is no need to pass it as 'uint64_t'.
    
    Change the type of 'addr' to 'uint32_t'.
    Fix also some format string to fit both 32 and 64 bits machines.
    
    Change-Id: I90ff7cd3731cb24a0fc91fe7b69c532b5c698ba0
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8974
    Reviewed-by: Nishanth Menon <nm...@ti...>
    Tested-by: jenkins
    Reviewed-by: R. Diez <rdi...@rd...>

diff --git a/src/jtag/drivers/dmem.c b/src/jtag/drivers/dmem.c
index e50e84aee..c1eb5b80d 100644
--- a/src/jtag/drivers/dmem.c
+++ b/src/jtag/drivers/dmem.c
@@ -93,14 +93,14 @@ static bool dmem_is_emulated_ap(struct adiv5_ap *ap, unsigned int *idx)
 	return false;
 }
 
-static void dmem_emu_set_ap_reg(uint64_t addr, uint32_t val)
+static void dmem_emu_set_ap_reg(uint32_t addr, uint32_t val)
 {
 	addr &= ~ARM_APB_PADDR31;
 
 	*(volatile uint32_t *)((uintptr_t)dmem_emu_virt_base_addr + addr) = val;
 }
 
-static uint32_t dmem_emu_get_ap_reg(uint64_t addr)
+static uint32_t dmem_emu_get_ap_reg(uint32_t addr)
 {
 	uint32_t val;
 
@@ -113,7 +113,7 @@ static uint32_t dmem_emu_get_ap_reg(uint64_t addr)
 
 static int dmem_emu_ap_q_read(unsigned int ap_idx, unsigned int reg, uint32_t *data)
 {
-	uint64_t addr;
+	uint32_t addr;
 	int ret = ERROR_OK;
 	struct dmem_emu_ap_info *ap_info = &dmem_emu_ap_list[ap_idx];
 
@@ -164,7 +164,7 @@ static int dmem_emu_ap_q_read(unsigned int ap_idx, unsigned int reg, uint32_t *d
 
 static int dmem_emu_ap_q_write(unsigned int ap_idx, unsigned int reg, uint32_t data)
 {
-	uint64_t addr;
+	uint32_t addr;
 	int ret = ERROR_OK;
 	struct dmem_emu_ap_info *ap_info = &dmem_emu_ap_list[ap_idx];
 
@@ -519,7 +519,7 @@ static int dmem_dap_init(void)
 						 MAP_SHARED, dmem_fd,
 						 dmem_mapped_start);
 	if (dmem_map_base == MAP_FAILED) {
-		LOG_ERROR("Mapping address 0x%lx for 0x%lx bytes failed!",
+		LOG_ERROR("Mapping address 0x%zx for 0x%zx bytes failed!",
 			dmem_mapped_start, dmem_mapped_size);
 		goto error_fail;
 	}
@@ -543,7 +543,7 @@ static int dmem_dap_init(void)
 									   MAP_SHARED, dmem_fd,
 									   dmem_mapped_start);
 		if (dmem_emu_map_base == MAP_FAILED) {
-			LOG_ERROR("Mapping EMU address 0x%lx for 0x%lx bytes failed!",
+			LOG_ERROR("Mapping EMU address 0x%" PRIx64 " for 0x%" PRIx64 " bytes failed!",
 					  dmem_emu_base_address, dmem_emu_size);
 			goto error_fail;
 		}

commit ff274122dc2fbf509b24480e97a98291db53a338
Author: Tim Newsome <ti...@si...>
Date:   Thu Nov 10 10:32:23 2022 -0800

    gdb_server: Improve info message.
    
    Add target name and state to "Not running when halt was requested"
    message.
    
    Imported from
    https://github.com/riscv-collab/riscv-openocd/pull/763
    
    Change-Id: Ic84e9a884b57caa270cfee0ca6fa6a0dd8e5d2bd
    Signed-off-by: Tim Newsome <ti...@si...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8916
    Tested-by: jenkins
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index b5007d927..3eba15070 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -3761,7 +3761,8 @@ static int gdb_input_inner(struct connection *connection)
 					target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT);
 				gdb_con->ctrl_c = false;
 			} else {
-				LOG_INFO("The target is not running when halt was requested, stopping GDB.");
+				LOG_TARGET_INFO(target, "Not running when halt was requested, stopping GDB. (state=%d)",
+						target->state);
 				target_call_event_callbacks(target, TARGET_EVENT_GDB_HALT);
 			}
 		}

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/dmem.c | 12 ++++++------
 src/server/gdb_server.c |  3 ++-
 2 files changed, 8 insertions(+), 7 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1077-ge8dca1124

From: openocd-gerrit <ope...@us...> - 2025-06-29 07:43:11

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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit e8dca112453ae01bdfa04e1a1da8d20d5eb08d8f
Author: Tomas Vanek <va...@fb...>
Date:   Mon May 26 07:54:05 2025 +0200

    doc: fix bp usage
    
    Commit c8926d14579528bfcead1e179baf7cb846513db4
    ("cortex_a hybrid & context breakpoints") missed doc update.
    
    Add info about settig hybrid & context breakpoints to chapter
    15.5 Breakpoint and Watchpoint commands
    
    Change-Id: I4a6fdc83a4c30ad8437c49796de8e6d8c6375c0c
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8934
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 494042530..6d607d697 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -9731,12 +9731,14 @@ hardware support for a handful of code breakpoints and data
 watchpoints.
 In addition, CPUs almost always support software breakpoints.
 
-@deffn {Command} {bp} [address len [@option{hw}]]
+@deffn {Command} {bp} [address [asid] len [@option{hw} | @option{hw_ctx}]]
 With no parameters, lists all active breakpoints.
 Else sets a breakpoint on code execution starting
 at @var{address} for @var{length} bytes.
-This is a software breakpoint, unless @option{hw} is specified
-in which case it will be a hardware breakpoint.
+This is a software breakpoint, unless @option{hw} or @option{hw_ctx}
+is specified in which case it will be a hardware, context or hybrid breakpoint.
+The context and hybrid breakpoints require an additional parameter @var{asid}:
+address space identifier.
 
 (@xref{arm9vectorcatch,,arm9 vector_catch}, or @pxref{xscalevectorcatch,,xscale vector_catch},
 for similar mechanisms that do not consume hardware breakpoints.)

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)


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From: openocd-gerrit <ope...@us...> - 2025-06-29 07:41:55

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commit f9077f302658eaf5d114d3f84f838a45481af0ac
Author: Tomas Vanek <va...@fb...>
Date:   Wed Jun 18 12:01:08 2025 +0200

    flash/nor/rp2xxx: save ACCESSCTRL over ROM API calls
    
    Especially after the flash probe (used in gdb-attach event)
    we need to completely restore the original security state to allow
    'resume' or gdb 'continue' without injecting strange errors
    to application code.
    
    Save all ACCESSCTRL registers potentially changed by triggering CFGRESET.
    Restore them at cleanup.
    
    Fixes: commit ea775d49fc71 ("flash/nor/rp2040: add RP2350 support")
    Change-Id: I964886d5b1d0269497c343811ee4dcd5c31953db
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8961
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nor/rp2xxx.c b/src/flash/nor/rp2xxx.c
index fa13ec527..30c6e9914 100644
--- a/src/flash/nor/rp2xxx.c
+++ b/src/flash/nor/rp2xxx.c
@@ -41,10 +41,18 @@
 #define BOOTROM_STATE_RESET_OTHER_CORE   0x02
 #define BOOTROM_STATE_RESET_GLOBAL_STATE 0x04
 
-#define ACCESSCTRL_LOCK_OFFSET     0x40060000u
-#define ACCESSCTRL_LOCK_DEBUG_BITS 0x00000008u
-#define ACCESSCTRL_CFGRESET_OFFSET 0x40060008u
-#define ACCESSCTRL_WRITE_PASSWORD  0xacce0000u
+#define ACCESSCTRL_LOCK_OFFSET			0x40060000u
+#define ACCESSCTRL_CFGRESET_OFFSET		0x40060008u
+#define ACCESSCTRL_GPIO_NSMASK0_OFFSET	0x4006000cu
+#define ACCESSCTRL_GPIO_ROM_OFFSET		0x40060014u
+#define ACCESSCTRL_GPIO_XIP_AUX_OFFSET	0x400600e8u
+
+#define ACCESSCTRL_SAVE_BASE			ACCESSCTRL_GPIO_NSMASK0_OFFSET
+#define ACCESSCTRL_SAVE_SIZE \
+			(ACCESSCTRL_GPIO_XIP_AUX_OFFSET + 4 - ACCESSCTRL_SAVE_BASE)
+
+#define ACCESSCTRL_LOCK_DEBUG_BITS		0x00000008u
+#define ACCESSCTRL_WRITE_PASSWORD		0xacce0000u
 
 #define RP2040_SSI_DR0			0x18000060
 #define RP2040_QSPI_CTRL		0x4001800c
@@ -211,6 +219,8 @@ struct rp2xxx_flash_bank {
 	unsigned int sfdp_dummy, sfdp_dummy_detect;
 
 	struct cortex_m_saved_security saved_security;
+	bool accessctrl_dirty;
+	uint8_t saved_accessctrl[ACCESSCTRL_SAVE_SIZE]; /* in target byte order */
 };
 
 #ifndef LOG_ROM_SYMBOL_DEBUG
@@ -601,8 +611,28 @@ static int rp2xxx_call_rom_func(struct target *target, struct rp2xxx_flash_bank
 	return rp2xxx_call_rom_func_batch(target, priv, &call, 1);
 }
 
-static int rp2350_init_accessctrl(struct target *target)
+static int rp2350_save_accessctrl(struct target *target, struct rp2xxx_flash_bank *priv)
 {
+	return target_read_memory(target, ACCESSCTRL_SAVE_BASE, 4, ACCESSCTRL_SAVE_SIZE / 4,
+							  priv->saved_accessctrl);
+}
+
+static int rp2350_restore_accessctrl(struct target *target, struct rp2xxx_flash_bank *priv)
+{
+	// Add write passwords to all ACCESSCTRL regs from ACCESSCTRL_GPIO_ROM to the end
+	// (exclude not keyed ACCESSCTRL_GPIO_NSMASK0 and ACCESSCTRL_GPIO_NSMASK1
+	for (unsigned int i = ACCESSCTRL_GPIO_ROM_OFFSET - ACCESSCTRL_SAVE_BASE;
+			 i < ACCESSCTRL_SAVE_SIZE; i += 4)
+		target_buffer_set_u32(target, priv->saved_accessctrl + i,
+			target_buffer_get_u32(target, priv->saved_accessctrl + i) | ACCESSCTRL_WRITE_PASSWORD);
+
+	return target_write_memory(target, ACCESSCTRL_SAVE_BASE, 4, ACCESSCTRL_SAVE_SIZE / 4,
+							   priv->saved_accessctrl);
+}
+
+static int rp2350_init_accessctrl(struct target *target, struct rp2xxx_flash_bank *priv)
+{
+	priv->accessctrl_dirty = false;
 	// Attempt to reset ACCESSCTRL, in case Secure access to SRAM has been
 	// blocked, which will stop us from loading/running algorithms such as RCP
 	// init. (Also ROM, QMI regs are needed later)
@@ -620,6 +650,13 @@ static int rp2350_init_accessctrl(struct target *target)
 	if (accessctrl_lock_reg & ACCESSCTRL_LOCK_DEBUG_BITS) {
 		LOG_ERROR("ACCESSCTRL is locked, so can't reset permissions. Following steps might fail");
 	} else {
+		int retval = rp2350_save_accessctrl(target, priv);
+		if (retval == ERROR_OK)
+			priv->accessctrl_dirty = true;
+		// If the ACCESSCTRL backup copy is valid, mark it dirty
+		// as we immediately proceed to ACCESSCTRL config reset.
+		// Don't fail on save ACCESSCTRL error, not vital for ROM API call
+
 		LOG_DEBUG("Reset ACCESSCTRL permissions via CFGRESET");
 		return target_write_u32(target, ACCESSCTRL_CFGRESET_OFFSET, ACCESSCTRL_WRITE_PASSWORD | 1u);
 	}
@@ -704,7 +741,7 @@ static int setup_for_raw_flash_cmd(struct target *target, struct rp2xxx_flash_ba
 	}
 
 	if (IS_RP2350(priv->id)) {
-		err = rp2350_init_accessctrl(target);
+		err = rp2350_init_accessctrl(target, priv);
 		if (err != ERROR_OK) {
 			LOG_ERROR("Failed to init ACCESSCTRL before ROM call");
 			return err;
@@ -833,12 +870,19 @@ static void cleanup_after_raw_flash_cmd(struct target *target, struct rp2xxx_fla
 	LOG_DEBUG("Cleaning up after flash operations");
 
 	if (IS_RP2350(priv->id)) {
-		/* TODO: restore ACCESSCTRL */
-		if (is_arm(target_to_arm(target))) {
-			int retval = cortex_m_security_restore(target, &priv->saved_security);
-			if (retval != ERROR_OK)
-				LOG_WARNING("RP2xxx: security state was not restored properly. Debug 'resume' will probably fail, use 'reset' instead");
+		int retval1 = ERROR_OK;
+		if (priv->accessctrl_dirty) {
+			retval1 = rp2350_restore_accessctrl(target, priv);
+			priv->accessctrl_dirty = false;
 		}
+
+		int retval2 = ERROR_OK;
+		if (is_arm(target_to_arm(target)))
+			retval2 = cortex_m_security_restore(target, &priv->saved_security);
+
+		if (retval1 != ERROR_OK || retval2 != ERROR_OK)
+			LOG_WARNING("RP2xxx: security state was not restored properly. Debug 'resume' will probably fail, use 'reset' instead");
+		/* Don't fail on security restore error, not vital for flash operation */
 	}
 	if (priv->stack) {
 		target_free_working_area(target, priv->stack);

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/rp2xxx.c | 66 +++++++++++++++++++++++++++++++++++++++++---------
 1 file changed, 55 insertions(+), 11 deletions(-)


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- Log -----------------------------------------------------------------
commit c4fb64e76c526799fc43f72fe2cdd4606c8b9b52
Author: Tomas Vanek <va...@fb...>
Date:   Wed Jun 18 09:44:03 2025 +0200

    flash/nor/rp2xxx: save security state over target algo
    
    RP2040 and RP2350 flash driver runs a ROM API target algorithm
    in probe to setup QSPI command interface. The Cortex-M33 core
    of RP2350 has to be in secure mode with SAU and MPU switched off
    to ensure ROM API call working properly.
    
    Especially after the flash probe (used in gdb-attach event)
    we need to completely restore the original security state to allow
    'resume' or gdb 'continue' without injecting strange errors
    to application code.
    
    Use cortex_m support to set secure mode and to restore it back.
    
    Fixes: commit ea775d49fc71 ("flash/nor/rp2040: add RP2350 support")
    Change-Id: I72096bfecbb45a8aa4d3a7a37ad140532b3b00b2
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8960
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/flash/nor/rp2xxx.c b/src/flash/nor/rp2xxx.c
index 85c591104..fa13ec527 100644
--- a/src/flash/nor/rp2xxx.c
+++ b/src/flash/nor/rp2xxx.c
@@ -209,6 +209,8 @@ struct rp2xxx_flash_bank {
 	bool size_override;
 	struct flash_device spi_dev;		/* detected model of SPI flash */
 	unsigned int sfdp_dummy, sfdp_dummy_detect;
+
+	struct cortex_m_saved_security saved_security;
 };
 
 #ifndef LOG_ROM_SYMBOL_DEBUG
@@ -630,23 +632,12 @@ static int rp2350_init_arm_core0(struct target *target, struct rp2xxx_flash_bank
 	// run in the Secure state, so flip the state now before attempting to
 	// execute any code on the core.
 	int retval;
-	uint32_t dscsr;
-	retval = target_read_u32(target, DCB_DSCSR, &dscsr);
+	retval = cortex_m_set_secure(target, &priv->saved_security);
 	if (retval != ERROR_OK) {
-		LOG_ERROR("RP2350 init ARM core: DSCSR read failed");
+		LOG_ERROR("RP2350 init ARM core: set secure mode failed");
 		return retval;
 	}
 
-	LOG_DEBUG("DSCSR: 0x%08" PRIx32, dscsr);
-	if (!(dscsr & DSCSR_CDS)) {
-		LOG_DEBUG("Setting Current Domain Secure in DSCSR");
-		retval = target_write_u32(target, DCB_DSCSR, (dscsr & ~DSCSR_CDSKEY) | DSCSR_CDS);
-		if (retval != ERROR_OK) {
-			LOG_ERROR("RP2350 init ARM core: DSCSR read failed");
-			return retval;
-		}
-	}
-
 	if (!priv->stack) {
 		LOG_ERROR("No stack for flash programming code");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
@@ -840,6 +831,15 @@ static void cleanup_after_raw_flash_cmd(struct target *target, struct rp2xxx_fla
 	   driver state. Best to clean up our allocations manually after
 	   completing each flash call, so we know to make fresh ones next time. */
 	LOG_DEBUG("Cleaning up after flash operations");
+
+	if (IS_RP2350(priv->id)) {
+		/* TODO: restore ACCESSCTRL */
+		if (is_arm(target_to_arm(target))) {
+			int retval = cortex_m_security_restore(target, &priv->saved_security);
+			if (retval != ERROR_OK)
+				LOG_WARNING("RP2xxx: security state was not restored properly. Debug 'resume' will probably fail, use 'reset' instead");
+		}
+	}
 	if (priv->stack) {
 		target_free_working_area(target, priv->stack);
 		priv->stack = 0;

commit f547e55076e847889387904c6a0803e742aeb36d
Author: Tomas Vanek <va...@fb...>
Date:   Tue Jun 17 16:23:12 2025 +0200

    target/cortex_m: introduce security manipulation routines
    
    Running target algorithms on ARMv8M may require core in secure
    mode with SAU and MPU off (as set after reset).
    
    cortex_m_set_secure() forces this mode with optional save of
    the previous state.
    
    cortex_m_security_restore() restores previously saved state.
    
    Change-Id: Ia71826db47ee7b0557eaffd55244ce13eacbcb4b
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8959
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 8eaf70f60..0501a5b2f 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -2563,6 +2563,112 @@ static bool cortex_m_has_tz(struct target *target)
 	return (dauthstatus & DAUTHSTATUS_SID_MASK) != 0;
 }
 
+int cortex_m_set_secure(struct target *target, struct cortex_m_saved_security *ssec)
+{
+	if (ssec) {
+		ssec->dscsr_dirty = false;
+		ssec->sau_ctrl_dirty = false;
+		ssec->mpu_ctrl_dirty = false;
+	}
+
+	if (!cortex_m_has_tz(target))
+		return ERROR_OK;
+
+	uint32_t dscsr;
+	int retval = target_read_u32(target, DCB_DSCSR, &dscsr);
+	if (retval != ERROR_OK) {
+		LOG_TARGET_ERROR(target, "ARMv8M set secure: DSCSR read failed");
+		return retval;
+	}
+	if (!(dscsr & DSCSR_CDS)) {
+		if (ssec) {
+			ssec->dscsr_dirty = true;
+			ssec->dscsr = dscsr;
+		}
+		LOG_TARGET_DEBUG(target, "Setting Current Domain Secure in DSCSR");
+		retval = target_write_u32(target, DCB_DSCSR, DSCSR_CDS);
+		if (retval != ERROR_OK) {
+			LOG_TARGET_ERROR(target, "ARMv8M set secure: DSCSR write failed");
+			return retval;
+		}
+	}
+
+	uint32_t sau_ctrl;
+	retval = target_read_u32(target, SAU_CTRL, &sau_ctrl);
+	if (retval != ERROR_OK) {
+		LOG_TARGET_ERROR(target, "ARMv8M set secure: SAU_CTRL read failed");
+		return retval;
+	}
+	if (sau_ctrl & SAU_CTRL_ENABLE) {
+		if (ssec) {
+			ssec->sau_ctrl_dirty = true;
+			ssec->sau_ctrl = sau_ctrl;
+		}
+		retval = target_write_u32(target, SAU_CTRL, sau_ctrl & ~SAU_CTRL_ENABLE);
+		if (retval != ERROR_OK) {
+			LOG_TARGET_ERROR(target, "ARMv8M set secure: SAU_CTRL write failed");
+			return retval;
+		}
+	}
+
+	uint32_t mpu_ctrl;
+	retval = target_read_u32(target, MPU_CTRL, &mpu_ctrl);
+	if (retval != ERROR_OK) {
+		LOG_TARGET_ERROR(target, "ARMv8M set secure: MPU_CTRL read failed");
+		return retval;
+	}
+	if (mpu_ctrl & MPU_CTRL_ENABLE) {
+		if (ssec) {
+			ssec->mpu_ctrl_dirty = true;
+			ssec->mpu_ctrl = mpu_ctrl;
+		}
+		retval = target_write_u32(target, MPU_CTRL, mpu_ctrl & ~MPU_CTRL_ENABLE);
+		if (retval != ERROR_OK) {
+			LOG_TARGET_ERROR(target, "ARMv8M set secure: MPU_CTRL write failed");
+			return retval;
+		}
+	}
+	return ERROR_OK;
+}
+
+int cortex_m_security_restore(struct target *target, struct cortex_m_saved_security *ssec)
+{
+	int retval;
+	if (!cortex_m_has_tz(target))
+		return ERROR_OK;
+
+	if (!ssec)
+		return ERROR_OK;
+
+	if (ssec->mpu_ctrl_dirty) {
+		retval = target_write_u32(target, MPU_CTRL, ssec->mpu_ctrl);
+		if (retval != ERROR_OK) {
+			LOG_TARGET_ERROR(target, "ARMv8M security restore: MPU_CTRL write failed");
+			return retval;
+		}
+		ssec->mpu_ctrl_dirty = false;
+	}
+
+	if (ssec->sau_ctrl_dirty) {
+		retval = target_write_u32(target, SAU_CTRL, ssec->sau_ctrl);
+		if (retval != ERROR_OK) {
+			LOG_TARGET_ERROR(target, "ARMv8M security restore: SAU_CTRL write failed");
+			return retval;
+		}
+		ssec->sau_ctrl_dirty = false;
+	}
+
+	if (ssec->dscsr_dirty) {
+		LOG_TARGET_DEBUG(target, "Restoring Current Domain Security in DSCSR");
+		retval = target_write_u32(target, DCB_DSCSR, ssec->dscsr & ~DSCSR_CDSKEY);
+		if (retval != ERROR_OK) {
+			LOG_TARGET_ERROR(target, "ARMv8M set secure: DSCSR write failed");
+			return retval;
+		}
+		ssec->dscsr_dirty = false;
+	}
+	return ERROR_OK;
+}
 
 #define MVFR0          0xE000EF40
 #define MVFR0_SP_MASK  0x000000F0
diff --git a/src/target/cortex_m.h b/src/target/cortex_m.h
index 144f24560..82b2c1ecd 100644
--- a/src/target/cortex_m.h
+++ b/src/target/cortex_m.h
@@ -167,6 +167,8 @@ struct cortex_m_part_info {
 #define NVIC_DFSR		0xE000ED30
 #define NVIC_MMFAR		0xE000ED34
 #define NVIC_BFAR		0xE000ED38
+#define MPU_CTRL		0xE000ED94
+#define SAU_CTRL		0xE000EDD0
 #define NVIC_SFSR		0xE000EDE4
 #define NVIC_SFAR		0xE000EDE8
 
@@ -184,6 +186,9 @@ struct cortex_m_part_info {
 #define DFSR_VCATCH			8
 #define DFSR_EXTERNAL		16
 
+#define MPU_CTRL_ENABLE		BIT(0)
+#define SAU_CTRL_ENABLE		BIT(0)
+
 #define FPCR_CODE 0
 #define FPCR_LITERAL 1
 #define FPCR_REPLACE_REMAP  (0ul << 30)
@@ -264,6 +269,15 @@ struct cortex_m_common {
 	bool incorrect_halt_erratum;
 };
 
+struct cortex_m_saved_security {
+	bool dscsr_dirty;
+	uint32_t dscsr;
+	bool sau_ctrl_dirty;
+	uint32_t sau_ctrl;
+	bool mpu_ctrl_dirty;
+	uint32_t mpu_ctrl;
+};
+
 static inline bool is_cortex_m_or_hla(const struct cortex_m_common *cortex_m)
 {
 	return cortex_m->common_magic == CORTEX_M_COMMON_MAGIC;
@@ -341,4 +355,17 @@ void cortex_m_deinit_target(struct target *target);
 int cortex_m_profiling(struct target *target, uint32_t *samples,
 	uint32_t max_num_samples, uint32_t *num_samples, uint32_t seconds);
 
+/**
+ * Forces Cortex-M core to the basic secure context with SAU and MPU off
+ * @param ssec pointer to save previous security state or NULL
+ * @returns error code or ERROR_OK if secure mode was set or is not applicable
+ * (not ARMv8M with security extension)
+ */
+int cortex_m_set_secure(struct target *target, struct cortex_m_saved_security *ssec);
+
+/**
+ * Restores saved security context to MPU_CTRL, SAU_CTRL and DSCSR
+ */
+int cortex_m_security_restore(struct target *target, struct cortex_m_saved_security *ssec);
+
 #endif /* OPENOCD_TARGET_CORTEX_M_H */

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/rp2xxx.c |  26 ++++++------
 src/target/cortex_m.c  | 106 +++++++++++++++++++++++++++++++++++++++++++++++++
 src/target/cortex_m.h  |  27 +++++++++++++
 3 files changed, 146 insertions(+), 13 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1073-gce3bf664c

From: openocd-gerrit <ope...@us...> - 2025-06-29 07:39:54

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- Log -----------------------------------------------------------------
commit ce3bf664c81569b2eb457f676814eade9d464141
Author: R. Diez <rdi...@rd...>
Date:   Sat Jun 21 22:05:17 2025 +0200

    configure.ac: rename M4 macro 'adapter' to prevent accidental conflicts
    
    Also remove a comment about such a conflict which had been already noticed.
    
    Change-Id: I6f301ccbd1261ea1c15c44a02d3f34f0cf5cb9f4
    Signed-off-by: R. Diez <rdi...@rd...>
    
    Reviewed-on: https://review.openocd.org/c/openocd/+/8972
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/configure.ac b/configure.ac
index 4b9471629..5a05f3171 100644
--- a/configure.ac
+++ b/configure.ac
@@ -206,8 +206,6 @@ m4_define([HOST_ARM_OR_AARCH64_BITBANG_ADAPTERS],
 	[[imx_gpio], [Bitbanging on NXP IMX processors], [IMX_GPIO]],
 	[[am335xgpio], [Bitbanging on AM335x (as found in Beaglebones)], [AM335XGPIO]]])
 
-# The word 'Adapter' in "Dummy Adapter" below must begin with a capital letter
-# because there is an M4 macro called 'adapter'.
 m4_define([DUMMY_ADAPTER],
 	[[[dummy], [Dummy Adapter], [DUMMY]]])
 
@@ -309,15 +307,15 @@ AC_ARG_ENABLE([dmem],
   [build_dmem=$enableval], [build_dmem=no])
 
 m4_define([AC_ARG_ADAPTERS], [
-  m4_foreach([adapter], [$1],
-	[AC_ARG_ENABLE(ADAPTER_OPT([adapter]),
-		AS_HELP_STRING([--enable-ADAPTER_OPT([adapter])[[[=yes/no/auto]]]],
-			[Enable building support for the ]ADAPTER_DESC([adapter])[ (default is $2)]),
+  m4_foreach([adapterTuple], [$1],
+	[AC_ARG_ENABLE(ADAPTER_OPT([adapterTuple]),
+		AS_HELP_STRING([--enable-ADAPTER_OPT([adapterTuple])[[[=yes/no/auto]]]],
+			[Enable building support for the ]ADAPTER_DESC([adapterTuple])[ (default is $2)]),
 		[case "${enableval}" in
 			yes|no|auto) ;;
-			*) AC_MSG_ERROR([Option --enable-ADAPTER_OPT([adapter]) has invalid value "${enableval}".]) ;;
+			*) AC_MSG_ERROR([Option --enable-ADAPTER_OPT([adapterTuple]) has invalid value "${enableval}".]) ;;
 			esac],
-		[ADAPTER_VAR([adapter])=$2])
+		[ADAPTER_VAR([adapterTuple])=$2])
   ])
 ])
 
@@ -622,21 +620,23 @@ PKG_CHECK_MODULES([LIBJAYLINK], [libjaylink >= 0.2],
 # Arg $3: What prerequisites are missing, to be shown in an error message
 #         if an adapter was requested but cannot be enabled.
 m4_define([PROCESS_ADAPTERS], [
-  m4_foreach([adapter], [$1], [
+  m4_foreach([adapterTuple], [$1], [
 	AS_IF([test $2], [
-		AS_IF([test "x$ADAPTER_VAR([adapter])" != "xno"], [
-			AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [1], [1 if you want the ]ADAPTER_DESC([adapter]).)
+		AS_IF([test "x$ADAPTER_VAR([adapterTuple])" != "xno"], [
+			AC_DEFINE([BUILD_]ADAPTER_SYM([adapterTuple]), [1],
+			          [1 if you want the ]ADAPTER_DESC([adapterTuple]).)
 		], [
-			AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [0], [0 if you do not want the ]ADAPTER_DESC([adapter]).)
+			AC_DEFINE([BUILD_]ADAPTER_SYM([adapterTuple]), [0],
+			          [0 if you do not want the ]ADAPTER_DESC([adapterTuple]).)
 		])
 	], [
-		AS_IF([test "x$ADAPTER_VAR([adapter])" = "xyes"], [
-			AC_MSG_ERROR([$3 is required for [adapter] "ADAPTER_DESC([adapter])".])
+		AS_IF([test "x$ADAPTER_VAR([adapterTuple])" = "xyes"], [
+			AC_MSG_ERROR([$3 is required for [adapterTuple] "ADAPTER_DESC([adapterTuple])".])
 		])
-		ADAPTER_VAR([adapter])=no
-		AC_DEFINE([BUILD_]ADAPTER_SYM([adapter]), [0], [0 if you do not want the ]ADAPTER_DESC([adapter]).)
+		ADAPTER_VAR([adapterTuple])=no
+		AC_DEFINE([BUILD_]ADAPTER_SYM([adapterTuple]), [0], [0 if you do not want the ]ADAPTER_DESC([adapterTuple]).)
 	])
-	AM_CONDITIONAL(ADAPTER_SYM([adapter]), [test "x$ADAPTER_VAR([adapter])" != "xno"])
+	AM_CONDITIONAL(ADAPTER_SYM([adapterTuple]), [test "x$ADAPTER_VAR([adapterTuple])" != "xno"])
   ])
 ])
 
@@ -839,7 +839,7 @@ echo
 echo
 echo OpenOCD configuration summary
 echo ---------------------------------------------------
-m4_foreach([adapter], [USB1_ADAPTERS,
+m4_foreach([adapterTuple], [USB1_ADAPTERS,
 	HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS,
 	LIBFTDI_USB1_ADAPTERS,
 	LIBGPIOD_ADAPTERS,
@@ -857,8 +857,8 @@ m4_foreach([adapter], [USB1_ADAPTERS,
 	DUMMY_ADAPTER,
 	OPTIONAL_LIBRARIES,
 	COVERAGE],
-	[s=m4_format(["%-49s"], ADAPTER_DESC([adapter]))
-	AS_CASE([$ADAPTER_VAR([adapter])],
+	[s=m4_format(["%-49s"], ADAPTER_DESC([adapterTuple]))
+	AS_CASE([$ADAPTER_VAR([adapterTuple])],
 		[auto], [
 			echo "$s"yes '(auto)'
 		],
@@ -870,8 +870,8 @@ m4_foreach([adapter], [USB1_ADAPTERS,
 		],
 		[
 			AC_MSG_ERROR(m4_normalize([
-				Error in [adapter] "ADAPTER_ARG([adapter])": Variable "ADAPTER_VAR([adapter])"
-				has invalid value "$ADAPTER_VAR([adapter])".]))
+				Error in [adapterTuple] "ADAPTER_ARG([adapterTuple])": Variable "ADAPTER_VAR([adapterTuple])"
+				has invalid value "$ADAPTER_VAR([adapterTuple])".]))
 	])
 ])
 echo

commit 13b74c3fc7718d3ac639d6c382b2a4e3ec70a6d1
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 21 12:11:24 2025 +0200

    helper: types: fix proper return type in example of ARRAY_SIZE()
    
    The example in the comment above the declaration of the macro
    ARRAY_SIZE() assigns the value to a variable of type 'unsigned'
    that is not allowed by the coding style (should be 'unsigned int')
    and is not correct since the macro uses 'sizeof()' and the type
    returned is 'size_t'.
    
    Fix the comment.
    
    Change-Id: I18c32b5328a229ab74b56dafab46a064ce5d23c5
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8970
    Reviewed-by: zapb <de...@za...>
    Tested-by: jenkins

diff --git a/src/helper/types.h b/src/helper/types.h
index 53249e5b7..b3edd2118 100644
--- a/src/helper/types.h
+++ b/src/helper/types.h
@@ -51,7 +51,7 @@
  * Compute the number of elements of a variable length array.
  * <code>
  * const char *strs[] = { "a", "b", "c" };
- * unsigned num_strs = ARRAY_SIZE(strs);
+ * size_t num_strs = ARRAY_SIZE(strs);
  * </code>
  */
 #define ARRAY_SIZE(x) (sizeof(x) / sizeof(*(x)))

-----------------------------------------------------------------------

Summary of changes:
 configure.ac       | 44 ++++++++++++++++++++++----------------------
 src/helper/types.h |  2 +-
 2 files changed, 23 insertions(+), 23 deletions(-)


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From: openocd-gerrit <ope...@us...> - 2025-06-29 07:39:43

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- Log -----------------------------------------------------------------
commit 6631419beba62893075eae5e1e13ddba9062d4f5
Author: Henrik Brix Andersen <he...@ve...>
Date:   Wed Dec 11 09:34:57 2024 +0100

    jtag: drivers: xlnx-pcie-xvc: use correct TMS polarity during pathmove
    
    The xlnx_pcie_xvc_execute_pathmove() function checks whether TMS
    should be high or low for transitioning from the current state to the
    next state, but then calls xlnx_pcie_xvc_transact() with the opposite
    level, leading to invalid state transitions.
    
    Fix the polarity of TMS in the calls to xlnx_pcie_xvc_transact() to
    match the required TMS level.
    
    Change-Id: I2383e41fb70063e26aa69fabcf728df597607934
    Signed-off-by: Henrik Brix Andersen <he...@ve...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8613
    Reviewed-by: Moritz Fischer <mo...@go...>
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Nicolas Derumigny <nic...@in...>

diff --git a/src/jtag/drivers/xlnx-pcie-xvc.c b/src/jtag/drivers/xlnx-pcie-xvc.c
index 3baa183d9..5208e2b87 100644
--- a/src/jtag/drivers/xlnx-pcie-xvc.c
+++ b/src/jtag/drivers/xlnx-pcie-xvc.c
@@ -210,9 +210,9 @@ static int xlnx_pcie_xvc_execute_pathmove(struct jtag_command *cmd)
 
 	for (unsigned int i = 0; i < num_states; i++) {
 		if (path[i] == tap_state_transition(tap_get_state(), false)) {
-			err = xlnx_pcie_xvc_transact(1, 1, 0, NULL);
-		} else if (path[i] == tap_state_transition(tap_get_state(), true)) {
 			err = xlnx_pcie_xvc_transact(1, 0, 0, NULL);
+		} else if (path[i] == tap_state_transition(tap_get_state(), true)) {
+			err = xlnx_pcie_xvc_transact(1, 1, 0, NULL);
 		} else {
 			LOG_ERROR("BUG: %s -> %s isn't a valid TAP transition.",
 				  tap_state_name(tap_get_state()),

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/xlnx-pcie-xvc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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- Log -----------------------------------------------------------------
commit 8194fc48bd3f06071a9068e385a122499447340a
Author: Marc Schink <de...@za...>
Date:   Fri Jun 20 11:18:03 2025 +0200

    tcl/board: Add config for TMS570LS12x development kit
    
    Tested on the corresponding hardware.
    
    Change-Id: Ic98141c450bb981cc7853c93b38195c7930bc7d3
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8969
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/board/ti/launchxl2-tms57012.cfg b/tcl/board/ti/launchxl2-tms57012.cfg
new file mode 100644
index 000000000..99cb26e20
--- /dev/null
+++ b/tcl/board/ti/launchxl2-tms57012.cfg
@@ -0,0 +1,10 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# Hercules TMS570LS12x LaunchPad Development Kit
+# https://www.ti.com/tool/LAUNCHXL2-TMS57012
+
+source [find interface/xds110.cfg]
+
+transport select jtag
+
+source [find target/ti_tms570ls1x.cfg]

commit c6f18633522e8cbc80e2abb5cf5e87da13440b92
Author: Marc Schink <de...@za...>
Date:   Fri Jun 20 10:47:23 2025 +0200

    target/armv4: Use command_print() instead of LOG_ERROR()
    
    Use command_print() in order to provide an error message to the caller.
    
    Change-Id: I9f1a2ef07a102e1d6e755f3680bed0f7183b5c9c
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8968
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 22cdba8ce..d90761569 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -842,7 +842,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
 	}
 
 	if (!is_arm_mode(arm->core_mode)) {
-		LOG_ERROR("not a valid arm core mode - communication failure?");
+		command_print(CMD, "not a valid arm core mode - communication failure?");
 		return ERROR_FAIL;
 	}
 
@@ -954,7 +954,7 @@ COMMAND_HANDLER(handle_arm_disassemble_command)
 	struct target *target = get_current_target(CMD_CTX);
 
 	if (!target) {
-		LOG_ERROR("No target selected");
+		command_print(CMD, "No target selected");
 		return ERROR_FAIL;
 	}
 

commit 56c24b9eb22c690f62fc173fe2fbd649070ae3d6
Author: Marc Schink <de...@za...>
Date:   Fri Jun 20 10:44:21 2025 +0200

    target/armv4: Use LOG_TARGET_xxx()
    
    Use LOG_TARGET_xxx() for log messages as it is used for other targets.
    
    While at it, rework the log messages. For example by removing spaces or
    punctuation marks at the end of the message.
    
    Change-Id: I295001876d40527ec8f35c2aec8d562a29e57b26
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8967
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index 597dc8990..22cdba8ce 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -437,7 +437,7 @@ const int armv4_5_core_reg_map[9][17] = {
 static const char *arm_core_state_string(struct arm *arm)
 {
 	if (arm->core_state > ARRAY_SIZE(arm_state_strings)) {
-		LOG_ERROR("core_state exceeds table size");
+		LOG_TARGET_ERROR(arm->target, "core_state exceeds table size");
 		return "Unknown";
 	}
 
@@ -483,20 +483,20 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
 
 	if (cpsr & (1 << 5)) {	/* T */
 		if (cpsr & (1 << 24)) {	/* J */
-			LOG_WARNING("ThumbEE -- incomplete support");
+			LOG_TARGET_WARNING(arm->target, "ThumbEE -- incomplete support");
 			state = ARM_STATE_THUMB_EE;
 		} else
 			state = ARM_STATE_THUMB;
 	} else {
 		if (cpsr & (1 << 24)) {	/* J */
-			LOG_ERROR("Jazelle state handling is BROKEN!");
+			LOG_TARGET_ERROR(arm->target, "Jazelle state handling is broken");
 			state = ARM_STATE_JAZELLE;
 		} else
 			state = ARM_STATE_ARM;
 	}
 	arm->core_state = state;
 
-	LOG_DEBUG("set CPSR %#8.8" PRIx32 ": %s mode, %s state", cpsr,
+	LOG_TARGET_DEBUG(arm->target, "set CPSR %#8.8" PRIx32 ": %s mode, %s state", cpsr,
 		arm_mode_name(mode),
 		arm_core_state_string(arm));
 }
@@ -521,7 +521,7 @@ struct reg *arm_reg_current(struct arm *arm, unsigned int regnum)
 		return NULL;
 
 	if (!arm->map) {
-		LOG_ERROR("Register map is not available yet, the target is not fully initialised");
+		LOG_TARGET_ERROR(arm->target, "Register map is not available yet, the target is not fully initialised");
 		r = arm->core_cache->reg_list + regnum;
 	} else
 		r = arm->core_cache->reg_list + arm->map[regnum];
@@ -530,7 +530,7 @@ struct reg *arm_reg_current(struct arm *arm, unsigned int regnum)
 	 * that doesn't support it...
 	 */
 	if (!r) {
-		LOG_ERROR("Invalid CPSR mode");
+		LOG_TARGET_ERROR(arm->target, "Invalid CPSR mode");
 		r = arm->core_cache->reg_list + regnum;
 	}
 
@@ -631,7 +631,7 @@ static int armv4_5_set_core_reg(struct reg *reg, uint8_t *buf)
 		 */
 		if (armv4_5_target->core_mode !=
 			(enum arm_mode)(value & 0x1f)) {
-			LOG_DEBUG("changing ARM core mode to '%s'",
+			LOG_TARGET_DEBUG(target, "changing ARM core mode to '%s'",
 				arm_mode_name(value & 0x1f));
 			value &= ~((1 << 24) | (1 << 5));
 			uint8_t t[4];
@@ -798,7 +798,7 @@ int arm_arch_state(struct target *target)
 	struct arm *arm = target_to_arm(target);
 
 	if (arm->common_magic != ARM_COMMON_MAGIC) {
-		LOG_ERROR("BUG: called for a non-ARM target");
+		LOG_TARGET_ERROR(target, "BUG: called for a non-ARM target");
 		return ERROR_FAIL;
 	}
 
@@ -806,7 +806,7 @@ int arm_arch_state(struct target *target)
 	if (target->semihosting && target->semihosting->hit_fileio)
 		return ERROR_OK;
 
-	LOG_USER("target halted in %s state due to %s, current mode: %s\n"
+	LOG_TARGET_USER(target, "target halted in %s state due to %s, current mode: %s\n"
 		"cpsr: 0x%8.8" PRIx32 " pc: 0x%8.8" PRIx32 "%s%s",
 		arm_core_state_string(arm),
 		debug_reason_name(target),
@@ -1291,7 +1291,7 @@ int arm_get_gdb_reg_list(struct target *target,
 	unsigned int i;
 
 	if (!is_arm_mode(arm->core_mode)) {
-		LOG_ERROR("not a valid arm core mode - communication failure?");
+		LOG_TARGET_ERROR(target, "not a valid arm core mode - communication failure?");
 		return ERROR_FAIL;
 	}
 
@@ -1362,7 +1362,7 @@ int arm_get_gdb_reg_list(struct target *target,
 		return ERROR_OK;
 
 	default:
-		LOG_ERROR("not a valid register class type in query.");
+		LOG_TARGET_ERROR(target, "not a valid register class type in query");
 		return ERROR_FAIL;
 	}
 }
@@ -1391,8 +1391,7 @@ static int armv4_5_run_algorithm_completion(struct target *target,
 
 	/* fast exit: ARMv5+ code can use BKPT */
 	if (exit_point && buf_get_u32(arm->pc->value, 0, 32) != exit_point) {
-		LOG_WARNING(
-			"target reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32 "",
+		LOG_TARGET_ERROR(target, "reentered debug state, but not at the desired exit point: 0x%4.4" PRIx32,
 			buf_get_u32(arm->pc->value, 0, 32));
 		return ERROR_TARGET_TIMEOUT;
 	}
@@ -1417,10 +1416,10 @@ int armv4_5_run_algorithm_inner(struct target *target,
 	int i;
 	int retval = ERROR_OK;
 
-	LOG_DEBUG("Running algorithm");
+	LOG_TARGET_DEBUG(target, "Running algorithm");
 
 	if (arm_algorithm_info->common_magic != ARM_COMMON_MAGIC) {
-		LOG_ERROR("current target isn't an ARMV4/5 target");
+		LOG_TARGET_ERROR(target, "current target isn't an ARMV4/5 target");
 		return ERROR_TARGET_INVALID;
 	}
 
@@ -1430,13 +1429,13 @@ int armv4_5_run_algorithm_inner(struct target *target,
 	}
 
 	if (!is_arm_mode(arm->core_mode)) {
-		LOG_ERROR("not a valid arm core mode - communication failure?");
+		LOG_TARGET_ERROR(target, "not a valid arm core mode - communication failure?");
 		return ERROR_FAIL;
 	}
 
 	/* armv5 and later can terminate with BKPT instruction; less overhead */
 	if (!exit_point && arm->arch == ARM_ARCH_V4) {
-		LOG_ERROR("ARMv4 target needs HW breakpoint location");
+		LOG_TARGET_ERROR(target, "ARMv4 target needs HW breakpoint location");
 		return ERROR_FAIL;
 	}
 
@@ -1470,12 +1469,12 @@ int armv4_5_run_algorithm_inner(struct target *target,
 
 		struct reg *reg = register_get_by_name(arm->core_cache, reg_params[i].reg_name, false);
 		if (!reg) {
-			LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+			LOG_TARGET_ERROR(target, "BUG: register '%s' not found", reg_params[i].reg_name);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
 
 		if (reg->size != reg_params[i].size) {
-			LOG_ERROR("BUG: register '%s' size doesn't match reg_params[i].size",
+			LOG_TARGET_ERROR(target, "BUG: register '%s' size doesn't match reg_params[i].size",
 				reg_params[i].reg_name);
 			return ERROR_COMMAND_SYNTAX_ERROR;
 		}
@@ -1491,12 +1490,12 @@ int armv4_5_run_algorithm_inner(struct target *target,
 	else if (arm->core_state == ARM_STATE_THUMB)
 		exit_breakpoint_size = 2;
 	else {
-		LOG_ERROR("BUG: can't execute algorithms when not in ARM or Thumb state");
+		LOG_TARGET_ERROR(target, "BUG: can't execute algorithms when not in ARM or Thumb state");
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	if (arm_algorithm_info->core_mode != ARM_MODE_ANY) {
-		LOG_DEBUG("setting core_mode: 0x%2.2x",
+		LOG_TARGET_DEBUG(target, "setting core_mode: 0x%2.2x",
 			arm_algorithm_info->core_mode);
 		buf_set_u32(arm->cpsr->value, 0, 5,
 			arm_algorithm_info->core_mode);
@@ -1509,7 +1508,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 		retval = breakpoint_add(target, exit_point,
 				exit_breakpoint_size, BKPT_HARD);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("can't add HW breakpoint to terminate algorithm");
+			LOG_TARGET_ERROR(target, "can't add HW breakpoint to terminate algorithm");
 			return ERROR_TARGET_FAILURE;
 		}
 	}
@@ -1542,13 +1541,13 @@ int armv4_5_run_algorithm_inner(struct target *target,
 					reg_params[i].reg_name,
 					false);
 			if (!reg) {
-				LOG_ERROR("BUG: register '%s' not found", reg_params[i].reg_name);
+				LOG_TARGET_ERROR(target, "BUG: register '%s' not found", reg_params[i].reg_name);
 				retval = ERROR_COMMAND_SYNTAX_ERROR;
 				continue;
 			}
 
 			if (reg->size != reg_params[i].size) {
-				LOG_ERROR(
+				LOG_TARGET_ERROR(target,
 					"BUG: register '%s' size doesn't match reg_params[i].size",
 					reg_params[i].reg_name);
 				retval = ERROR_COMMAND_SYNTAX_ERROR;
@@ -1667,7 +1666,7 @@ int arm_checksum_memory(struct target *target,
 	if (retval == ERROR_OK)
 		*checksum = buf_get_u32(reg_params[0].value, 0, 32);
 	else
-		LOG_ERROR("error executing ARM crc algorithm");
+		LOG_TARGET_ERROR(target, "error executing ARM CRC algorithm");
 
 	destroy_reg_param(&reg_params[0]);
 	destroy_reg_param(&reg_params[1]);
@@ -1702,7 +1701,7 @@ int arm_blank_check_memory(struct target *target,
 	assert(sizeof(check_code_le) % 4 == 0);
 
 	if (erased_value != 0xff) {
-		LOG_ERROR("Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
+		LOG_TARGET_ERROR(target, "Erase value 0x%02" PRIx8 " not yet supported for ARMv4/v5 targets",
 			erased_value);
 		return ERROR_FAIL;
 	}
@@ -1781,7 +1780,7 @@ static int arm_default_mrc(struct target *target, int cpnum,
 	uint32_t crn, uint32_t crm,
 	uint32_t *value)
 {
-	LOG_ERROR("%s doesn't implement MRC", target_type_name(target));
+	LOG_TARGET_ERROR(target, "%s doesn't implement MRC", target_type_name(target));
 	return ERROR_FAIL;
 }
 
@@ -1789,7 +1788,7 @@ static int arm_default_mrrc(struct target *target, int cpnum,
 	uint32_t op, uint32_t crm,
 	uint64_t *value)
 {
-	LOG_ERROR("%s doesn't implement MRRC", target_type_name(target));
+	LOG_TARGET_ERROR(target, "%s doesn't implement MRRC", target_type_name(target));
 	return ERROR_FAIL;
 }
 
@@ -1798,7 +1797,7 @@ static int arm_default_mcr(struct target *target, int cpnum,
 	uint32_t crn, uint32_t crm,
 	uint32_t value)
 {
-	LOG_ERROR("%s doesn't implement MCR", target_type_name(target));
+	LOG_TARGET_ERROR(target, "%s doesn't implement MCR", target_type_name(target));
 	return ERROR_FAIL;
 }
 
@@ -1806,7 +1805,7 @@ static int arm_default_mcrr(struct target *target, int cpnum,
 	uint32_t op, uint32_t crm,
 	uint64_t value)
 {
-	LOG_ERROR("%s doesn't implement MCRR", target_type_name(target));
+	LOG_TARGET_ERROR(target, "%s doesn't implement MCRR", target_type_name(target));
 	return ERROR_FAIL;
 }
 

commit 7fa8a5c257dcf3dbf072103f69959448e57dfa2c
Author: Marc Schink <de...@za...>
Date:   Fri Jun 20 10:30:03 2025 +0200

    target/armv7a: Use LOG_TARGET_xxx()
    
    Use LOG_TARGET_xxx() to indicate which target the message belongs to.
    
    Change-Id: Ic40c61a779c1a1ebdc96ebc56b27541fff5e6205
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8966
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 651241b77..2bbafd420 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -68,9 +68,9 @@ static void armv7a_show_fault_registers(struct target *target)
 	if (retval != ERROR_OK)
 		goto done;
 
-	LOG_USER("Data fault registers        DFSR: %8.8" PRIx32
+	LOG_TARGET_USER(target, "Data fault registers        DFSR: %8.8" PRIx32
 		", DFAR: %8.8" PRIx32, dfsr, dfar);
-	LOG_USER("Instruction fault registers IFSR: %8.8" PRIx32
+	LOG_TARGET_USER(target, "Instruction fault registers IFSR: %8.8" PRIx32
 		", IFAR: %8.8" PRIx32, ifsr, ifar);
 
 done:
@@ -134,7 +134,7 @@ int armv7a_read_ttbcr(struct target *target)
 	if (retval != ERROR_OK)
 		goto done;
 
-	LOG_DEBUG("ttbcr %" PRIx32, ttbcr);
+	LOG_TARGET_DEBUG(target, "ttbcr %" PRIx32, ttbcr);
 
 	ttbcr_n = ttbcr & 0x7;
 	armv7a->armv7a_mmu.ttbcr = ttbcr;
@@ -169,7 +169,7 @@ int armv7a_read_ttbcr(struct target *target)
 		armv7a->armv7a_mmu.ttbr_mask[0]  = 7 << (32 - ttbcr_n);
 	}
 
-	LOG_DEBUG("ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
+	LOG_TARGET_DEBUG(target, "ttbr1 %s, ttbr0_mask %" PRIx32 " ttbr1_mask %" PRIx32,
 		  (ttbcr_n != 0) ? "used" : "not used",
 		  armv7a->armv7a_mmu.ttbr_mask[0],
 		  armv7a->armv7a_mmu.ttbr_mask[1]);
@@ -248,14 +248,13 @@ static int armv7a_read_mpidr(struct target *target)
 
 	/* Is register in Multiprocessing Extensions register format? */
 	if (mpidr & MPIDR_MP_EXT) {
-		LOG_DEBUG("%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
+		LOG_TARGET_DEBUG(target, "%s: MPIDR 0x%" PRIx32, target_name(target), mpidr);
 		armv7a->multi_processor_system = (mpidr >> 30) & 1;
 		armv7a->multi_threading_processor = (mpidr >> 24) & 1;
 		armv7a->level2_id = (mpidr >> 16) & 0xf;
 		armv7a->cluster_id = (mpidr >> 8) & 0xf;
 		armv7a->cpu_id = mpidr & 0xf;
-		LOG_INFO("%s: MPIDR level2 %x, cluster %x, core %x, %s, %s",
-			target_name(target),
+		LOG_TARGET_INFO(target, "MPIDR level2 %x, cluster %x, core %x, %s, %s",
 			armv7a->level2_id,
 			armv7a->cluster_id,
 			armv7a->cpu_id,
@@ -263,7 +262,7 @@ static int armv7a_read_mpidr(struct target *target)
 			armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT");
 
 	} else
-		LOG_DEBUG("MPIDR not in multiprocessor format");
+		LOG_TARGET_DEBUG(target, "MPIDR not in multiprocessor format");
 
 done:
 	dpm->finish(dpm);
@@ -338,7 +337,7 @@ int armv7a_identify_cache(struct target *target)
 
 	cache->iminline = 4UL << (ctr & 0xf);
 	cache->dminline = 4UL << ((ctr & 0xf0000) >> 16);
-	LOG_DEBUG("ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
+	LOG_TARGET_DEBUG(target, "ctr %" PRIx32 " ctr.iminline %" PRIu32 " ctr.dminline %" PRIu32,
 		 ctr, cache->iminline, cache->dminline);
 
 	/*  retrieve CLIDR
@@ -350,7 +349,7 @@ int armv7a_identify_cache(struct target *target)
 		goto done;
 
 	cache->loc = (clidr & 0x7000000) >> 24;
-	LOG_DEBUG("Number of cache levels to PoC %" PRId32, cache->loc);
+	LOG_TARGET_DEBUG(target, "Number of cache levels to PoC %" PRId32, cache->loc);
 
 	/*  retrieve selected cache for later restore
 	 *  MRC p15, 2,<Rd>, c0, c0, 0; Read CSSELR */
@@ -378,13 +377,13 @@ int armv7a_identify_cache(struct target *target)
 				goto done;
 			cache->arch[cl].d_u_size = decode_cache_reg(cache_reg);
 
-			LOG_DEBUG("data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
+			LOG_TARGET_DEBUG(target, "data/unified cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
 					cache->arch[cl].d_u_size.index,
 					cache->arch[cl].d_u_size.index_shift,
 					cache->arch[cl].d_u_size.way,
 					cache->arch[cl].d_u_size.way_shift);
 
-			LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
+			LOG_TARGET_DEBUG(target, "cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
 					cache->arch[cl].d_u_size.linelen,
 					cache->arch[cl].d_u_size.cachesize,
 					cache->arch[cl].d_u_size.associativity);
@@ -398,13 +397,13 @@ int armv7a_identify_cache(struct target *target)
 				goto done;
 			cache->arch[cl].i_size = decode_cache_reg(cache_reg);
 
-			LOG_DEBUG("instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
+			LOG_TARGET_DEBUG(target, "instruction cache index %" PRIu32 " << %" PRIu32 ", way %" PRIu32 " << %" PRIu32,
 					cache->arch[cl].i_size.index,
 					cache->arch[cl].i_size.index_shift,
 					cache->arch[cl].i_size.way,
 					cache->arch[cl].i_size.way_shift);
 
-			LOG_DEBUG("cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
+			LOG_TARGET_DEBUG(target, "cacheline %" PRIu32 " bytes %" PRIu32 " KBytes asso %" PRIu32 " ways",
 					cache->arch[cl].i_size.linelen,
 					cache->arch[cl].i_size.cachesize,
 					cache->arch[cl].i_size.associativity);
@@ -445,7 +444,7 @@ static int armv7a_setup_semihosting(struct target *target, int enable)
 					 armv7a->debug_base + CPUDBG_VCR,
 					 &vcr);
 	if (ret < 0) {
-		LOG_ERROR("Failed to read VCR register\n");
+		LOG_TARGET_ERROR(target, "Failed to read VCR register");
 		return ret;
 	}
 
@@ -458,7 +457,7 @@ static int armv7a_setup_semihosting(struct target *target, int enable)
 					  armv7a->debug_base + CPUDBG_VCR,
 					  vcr);
 	if (ret < 0)
-		LOG_ERROR("Failed to write VCR register\n");
+		LOG_TARGET_ERROR(target, "Failed to write VCR register");
 
 	return ret;
 }
@@ -489,18 +488,18 @@ int armv7a_arch_state(struct target *target)
 	struct arm *arm = &armv7a->arm;
 
 	if (armv7a->common_magic != ARMV7_COMMON_MAGIC) {
-		LOG_ERROR("BUG: called for a non-ARMv7A target");
+		LOG_TARGET_ERROR(target, "BUG: called for a non-ARMv7A target");
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
 	arm_arch_state(target);
 
 	if (armv7a->is_armv7r) {
-		LOG_USER("D-Cache: %s, I-Cache: %s",
+		LOG_TARGET_USER(target, "D-Cache: %s, I-Cache: %s",
 			state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
 			state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);
 	} else {
-		LOG_USER("MMU: %s, D-Cache: %s, I-Cache: %s",
+		LOG_TARGET_USER(target, "MMU: %s, D-Cache: %s, I-Cache: %s",
 			state[armv7a->armv7a_mmu.mmu_enabled],
 			state[armv7a->armv7a_mmu.armv7a_cache.d_u_cache_enabled],
 			state[armv7a->armv7a_mmu.armv7a_cache.i_cache_enabled]);

-----------------------------------------------------------------------

Summary of changes:
 src/target/armv4_5.c                | 63 ++++++++++++++++++-------------------
 src/target/armv7a.c                 | 37 +++++++++++-----------
 tcl/board/ti/launchxl2-tms57012.cfg | 10 ++++++
 3 files changed, 59 insertions(+), 51 deletions(-)
 create mode 100644 tcl/board/ti/launchxl2-tms57012.cfg


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From: openocd-gerrit <ope...@us...> - 2025-06-29 07:36:06

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- Log -----------------------------------------------------------------
commit d008a02a74cb4edf18d99b0a6d7d1a698ccc4890
Author: Marc Schink <de...@za...>
Date:   Fri Jun 20 10:53:09 2025 +0200

    target/armv7a: Hide multiprocessing support message
    
    Print a debug message about missing multiprocessing support rather than
    an error message.
    
    Change-Id: Ia1581f7284747d8a92096d6f5515f891c8069f71
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8965
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/armv7a.c b/src/target/armv7a.c
index 4d353dec6..651241b77 100644
--- a/src/target/armv7a.c
+++ b/src/target/armv7a.c
@@ -263,7 +263,7 @@ static int armv7a_read_mpidr(struct target *target)
 			armv7a->multi_threading_processor == 1 ? "SMT" : "no SMT");
 
 	} else
-		LOG_ERROR("MPIDR not in multiprocessor format");
+		LOG_DEBUG("MPIDR not in multiprocessor format");
 
 done:
 	dpm->finish(dpm);

commit 4d56d580ce9e2f10e8659bd0d0c4e1b333efa45c
Author: Marc Schink <de...@za...>
Date:   Fri Jun 20 10:17:12 2025 +0200

    target/arm_dpm: Use LOG_TARGET_xxx()
    
    Use LOG_TARGET_xxx() to indicate which target the message belongs to.
    
    While at it, rework the log messages. For example, using correct format
    specifiers.
    
    Change-Id: I05031e0ae25fe9e7bc38dfb781b6623a967fd533
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8964
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c
index 0b2db77c5..8ab464d0a 100644
--- a/src/target/arm_dpm.c
+++ b/src/target/arm_dpm.c
@@ -50,9 +50,8 @@ static int dpm_mrc(struct target *target, int cpnum,
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("MRC p%d, %d, r0, c%d, c%d, %d", cpnum,
-		(int) op1, (int) crn,
-		(int) crm, (int) op2);
+	LOG_TARGET_DEBUG(target, "MRC p%d, %" PRId32 ", r0, c%" PRId32 ", c%" PRId32 ", %" PRId32,
+		cpnum, op1, crn, crm, op2);
 
 	/* read coprocessor register into R0; return via DCC */
 	retval = dpm->instr_read_data_r0(dpm,
@@ -74,8 +73,8 @@ static int dpm_mrrc(struct target *target, int cpnum,
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("MRRC p%d, %d, r0, r1, c%d", cpnum,
-		 (int)op, (int)crm);
+	LOG_TARGET_DEBUG(target, "MRRC p%d, %" PRId32 ", r0, r1, c%" PRId32,
+		cpnum, op, crm);
 
 	/* read coprocessor register into R0, R1; return via DCC */
 	retval = dpm->instr_read_data_r0_r1(dpm,
@@ -98,9 +97,8 @@ static int dpm_mcr(struct target *target, int cpnum,
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("MCR p%d, %d, r0, c%d, c%d, %d", cpnum,
-		(int) op1, (int) crn,
-		(int) crm, (int) op2);
+	LOG_TARGET_DEBUG(target, "MCR p%d, %" PRId32 ", r0, c%" PRId32 ", c%" PRId32 ", %" PRId32,
+		cpnum, op1, crn, crm, op2);
 
 	/* read DCC into r0; then write coprocessor register from R0 */
 	retval = dpm->instr_write_data_r0(dpm,
@@ -122,8 +120,8 @@ static int dpm_mcrr(struct target *target, int cpnum,
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("MCRR p%d, %d, r0, r1, c%d", cpnum,
-		(int)op, (int)crm);
+	LOG_TARGET_DEBUG(target, "MCRR p%d, %" PRId32 ", r0, r1, c%" PRId32,
+		cpnum, op, crm);
 
 	/* read DCC into r0, r1; then write coprocessor register from R0, R1 */
 	retval = dpm->instr_write_data_r0_r1(dpm,
@@ -198,7 +196,8 @@ static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int reg
 		buf_set_u32(r->value + 4, 0, 32, value_r1);
 		r->valid = true;
 		r->dirty = false;
-		LOG_DEBUG("READ: %s, %8.8" PRIx32 ", %8.8" PRIx32, r->name, value_r0, value_r1);
+		LOG_TARGET_DEBUG(dpm->arm->target, "READ: %s, %8.8" PRIx32 ", %8.8" PRIx32,
+			r->name, value_r0, value_r1);
 	}
 
 	return retval;
@@ -237,10 +236,10 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
 					break;
 				case ARM_STATE_JAZELLE:
 					/* core-specific ... ? */
-					LOG_WARNING("Jazelle PC adjustment unknown");
+					LOG_TARGET_WARNING(dpm->arm->target, "Jazelle PC adjustment unknown");
 					break;
 				default:
-					LOG_WARNING("unknown core state");
+					LOG_TARGET_WARNING(dpm->arm->target, "unknown core state");
 					break;
 			}
 			break;
@@ -265,7 +264,8 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
 		buf_set_u32(r->value, 0, 32, value);
 		r->valid = true;
 		r->dirty = false;
-		LOG_DEBUG("READ: %s, %8.8" PRIx32, r->name, value);
+		LOG_TARGET_DEBUG(dpm->arm->target, "READ: %s, %8.8" PRIx32, r->name,
+			value);
 	}
 
 	return retval;
@@ -301,7 +301,8 @@ static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int re
 
 	if (retval == ERROR_OK) {
 		r->dirty = false;
-		LOG_DEBUG("WRITE: %s, %8.8" PRIx32 ", %8.8" PRIx32, r->name, value_r0, value_r1);
+		LOG_TARGET_DEBUG(dpm->arm->target, "WRITE: %s, %8.8" PRIx32 ", %8.8" PRIx32,
+			r->name, value_r0, value_r1);
 	}
 
 	return retval;
@@ -349,7 +350,8 @@ static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum
 
 	if (retval == ERROR_OK) {
 		r->dirty = false;
-		LOG_DEBUG("WRITE: %s, %8.8" PRIx32, r->name, value);
+		LOG_TARGET_DEBUG(dpm->arm->target, "WRITE: %s, %8.8" PRIx32, r->name,
+			value);
 	}
 
 	return retval;
@@ -463,9 +465,8 @@ static int dpm_maybe_update_bpwp(struct arm_dpm *dpm, bool bpwp,
 				xp->address, xp->control);
 
 	if (retval != ERROR_OK)
-		LOG_ERROR("%s: can't %s HW %spoint %d",
+		LOG_TARGET_ERROR(dpm->arm->target, "can't %s HW %spoint %d",
 			disable ? "disable" : "enable",
-			target_name(dpm->arm->target),
 			(xp->number < 16) ? "break" : "watch",
 			xp->number & 0xf);
 done:
@@ -670,7 +671,7 @@ static enum arm_mode dpm_mapmode(struct arm *arm,
 		case ARM_VFP_V3_D0 ... ARM_VFP_V3_FPSCR:
 			return mode;
 		default:
-			LOG_WARNING("invalid register #%u", num);
+			LOG_TARGET_WARNING(arm->target, "invalid register #%u", num);
 			break;
 	}
 	return ARM_MODE_ANY;
@@ -885,7 +886,7 @@ static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
 			}
 		/* FALL THROUGH */
 		default:
-			LOG_ERROR("unsupported {break,watch}point length/alignment");
+			LOG_TARGET_ERROR(dpm->arm->target, "unsupported {break,watch}point length/alignment");
 			return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
@@ -899,7 +900,7 @@ static int dpm_bpwp_setup(struct arm_dpm *dpm, struct dpm_bpwp *xp,
 	xp->control = control;
 	xp->dirty = true;
 
-	LOG_DEBUG("BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
+	LOG_TARGET_DEBUG(dpm->arm->target, "BPWP: addr %8.8" PRIx32 ", control %" PRIx32 ", number %d",
 		xp->address, control, xp->number);
 
 	/* hardware is updated in write_dirty_registers() */
@@ -919,7 +920,7 @@ static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp)
 
 	/* FIXME we need a generic solution for software breakpoints. */
 	if (bp->type == BKPT_SOFT)
-		LOG_DEBUG("using HW bkpt, not SW...");
+		LOG_TARGET_DEBUG(dpm->arm->target, "using HW breakpoint instead of SW");
 
 	for (unsigned int i = 0; i < dpm->nbp; i++) {
 		if (!dpm->dbp[i].bp) {
@@ -963,7 +964,7 @@ static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t,
 
 	/* this hardware doesn't support data value matching or masking */
 	if (wp->mask != WATCHPOINT_IGNORE_DATA_VALUE_MASK) {
-		LOG_DEBUG("watchpoint values and masking not supported");
+		LOG_TARGET_ERROR(dpm->arm->target, "watchpoint values and masking not supported");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
@@ -1143,8 +1144,8 @@ int arm_dpm_setup(struct arm_dpm *dpm)
 		return ERROR_FAIL;
 	}
 
-	LOG_INFO("%s: hardware has %d breakpoints, %d watchpoints",
-		target_name(target), dpm->nbp, dpm->nwp);
+	LOG_TARGET_INFO(target, "hardware has %d breakpoints, %d watchpoints",
+		dpm->nbp, dpm->nwp);
 
 	/* REVISIT ... and some of those breakpoints could match
 	 * execution context IDs...
@@ -1172,8 +1173,7 @@ int arm_dpm_initialize(struct arm_dpm *dpm)
 			(void) dpm->bpwp_disable(dpm, 16 + i);
 		}
 	} else
-		LOG_WARNING("%s: can't disable breakpoints and watchpoints",
-			target_name(dpm->arm->target));
+		LOG_TARGET_WARNING(dpm->arm->target, "can't disable breakpoints and watchpoints");
 
 	return ERROR_OK;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/arm_dpm.c | 54 ++++++++++++++++++++++++++--------------------------
 src/target/armv7a.c  |  2 +-
 2 files changed, 28 insertions(+), 28 deletions(-)


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From: openocd-gerrit <ope...@us...> - 2025-06-29 07:34:21

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 46aa9c0e526f39c61b2c08ac1d21c998ad34259e
Author: Jan Matyas <jan...@co...>
Date:   Tue Jun 17 13:17:23 2025 +0200

    openocd.c: 'init' should fail if GDB service cannot be created
    
    If it is not possible to create a GDB service for a certain target
    (for example the given TCP port is already occupied), the "init"
    command should fail, but it currently does not.
    
    Fix this by checking the return code of gdb_target_add_all().
    
    Steps to reproduce:
    
    1) Make the port 3333/tcp occupied. For example by:
    
       nc -l 3333
    
    2) In another terminal, launch OpenOCD. Use the gdb_port
       3333 (which is the default). For example:
    
       path/to/your/openocd \
          -c "adapter driver ..." \
          -c "jtag newtap ..."
          -c "target create ..."
    
    3) Observe the outcome:
    
       Before this patch:
    
       Error "couldn't bind gdb to socket on port 3333: Address already in use"
       is displayed but OpenOCD keeps running.
    
       After this patch:
    
       The error message is displayed and OpenOCD exits - as expected.
    
    Change-Id: I63c283a9a1095167b78e69e9ee879c378a6b9f2a
    Signed-off-by: Jan Matyas <jan...@co...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8957
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/openocd.c b/src/openocd.c
index 3fbece395..e63a9661a 100644
--- a/src/openocd.c
+++ b/src/openocd.c
@@ -170,7 +170,8 @@ COMMAND_HANDLER(handle_init_command)
 	jtag_poll_unmask(save_poll_mask);
 
 	/* initialize telnet subsystem */
-	gdb_target_add_all(all_targets);
+	if (gdb_target_add_all(all_targets) != ERROR_OK)
+		return ERROR_FAIL;
 
 	target_register_event_callback(log_target_callback_event_handler, CMD_CTX);
 

-----------------------------------------------------------------------

Summary of changes:
 src/openocd.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)


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From: openocd-gerrit <ope...@us...> - 2025-06-29 07:33:03

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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 9b660bbd1957ffc1fd86485ceef5200f8968aeb6
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 15:07:50 2025 +0200

    rtos: sort the rtos by alphabetic order
    
    Add comments to require the list of rtos to be kept sorted.
    
    Change-Id: Iecf9250a14f6593d0a24a9f9b8930c0ec8d74bd2
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8953
    Tested-by: jenkins

diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 216129b97..2ccccf1b0 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -17,20 +17,22 @@
 #include "server/gdb_server.h"
 
 static const struct rtos_type *rtos_types[] = {
-	&threadx_rtos,
-	&freertos_rtos,
-	&ecos_rtos,
-	&linux_rtos,
+	// Keep in alphabetic order this list of rtos, except hwthread
 	&chibios_rtos,
 	&chromium_ec_rtos,
+	&ecos_rtos,
 	&embkernel_rtos,
+	&freertos_rtos,
+	&linux_rtos,
 	&mqx_rtos,
-	&ucos_iii_rtos,
 	&nuttx_rtos,
 	&riot_rtos,
-	&zephyr_rtos,
 	&rtkernel_rtos,
-	/* keep this as last, as it always matches with rtos auto */
+	&threadx_rtos,
+	&ucos_iii_rtos,
+	&zephyr_rtos,
+
+	// keep this as last, as it always matches with rtos auto
 	&hwthread_rtos,
 };
 
diff --git a/src/rtos/rtos.h b/src/rtos/rtos.h
index 05beab145..dbaa7e8ce 100644
--- a/src/rtos/rtos.h
+++ b/src/rtos/rtos.h
@@ -136,6 +136,7 @@ int rtos_read_buffer(struct target *target, target_addr_t address,
 int rtos_write_buffer(struct target *target, target_addr_t address,
 		uint32_t size, const uint8_t *buffer);
 
+// Keep in alphabetic order this list of rtos
 extern const struct rtos_type chibios_rtos;
 extern const struct rtos_type chromium_ec_rtos;
 extern const struct rtos_type ecos_rtos;

-----------------------------------------------------------------------

Summary of changes:
 src/rtos/rtos.c | 16 +++++++++-------
 src/rtos/rtos.h |  1 +
 2 files changed, 10 insertions(+), 7 deletions(-)


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From: openocd-gerrit <ope...@us...> - 2025-06-29 07:32:51

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       via  cd749419caae4f083daa2e0717fb2c6747ba033a (commit)
       via  c92cf66c6714ebf367d1ccb1ba59010491924063 (commit)
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- Log -----------------------------------------------------------------
commit df525290cb11ab40968253b7d4c5588b1aab7d82
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 15:02:04 2025 +0200

    target: use array size to constraint the loop
    
    Instead of using NULL terminated arrays to determine the last
    element of the array, use the size of the array.
    
    Change-Id: I3cdc0f6aef8a5110073aeef333c439e61fc54032
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8952
    Tested-by: jenkins
    Reviewed-by: Brandon Martin

diff --git a/src/target/target.c b/src/target/target.c
index 8bf654a27..995adbc9d 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -110,7 +110,6 @@ static struct target_type *target_types[] = {
 	&testee_target,
 	&xscale_target,
 	&xtensa_chip_target,
-	NULL,
 };
 
 struct target *all_targets;
@@ -5708,7 +5707,6 @@ static const struct command_registration target_instance_command_handlers[] = {
 COMMAND_HANDLER(handle_target_create)
 {
 	int retval = ERROR_OK;
-	int x;
 
 	if (CMD_ARGC < 2)
 		return ERROR_COMMAND_SYNTAX_ERROR;
@@ -5732,15 +5730,16 @@ COMMAND_HANDLER(handle_target_create)
 		LOG_INFO("The selected transport took over low-level target control. The results might differ compared to plain JTAG/SWD");
 	}
 	/* now does target type exist */
-	for (x = 0 ; target_types[x] ; x++) {
+	size_t x;
+	for (x = 0 ; x < ARRAY_SIZE(target_types) ; x++) {
 		if (strcmp(cp, target_types[x]->name) == 0) {
 			/* found */
 			break;
 		}
 	}
-	if (!target_types[x]) {
+	if (x == ARRAY_SIZE(target_types)) {
 		char *all = NULL;
-		for (x = 0 ; target_types[x] ; x++) {
+		for (x = 0 ; x < ARRAY_SIZE(target_types) ; x++) {
 			char *prev = all;
 			if (all)
 				all = alloc_printf("%s, %s", all, target_types[x]->name);
@@ -5942,7 +5941,7 @@ COMMAND_HANDLER(handle_target_types)
 	if (CMD_ARGC != 0)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	for (unsigned int x = 0; target_types[x]; x++)
+	for (size_t x = 0; x < ARRAY_SIZE(target_types); x++)
 		command_print(CMD, "%s", target_types[x]->name);
 
 	return ERROR_OK;

commit cd749419caae4f083daa2e0717fb2c6747ba033a
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 14:51:43 2025 +0200

    target: sort the targets by alphabetic order
    
    Add comments to require the list of targets to be kept sorted.
    
    Change-Id: Ie3d7e3f5d55a9f9214dc179c5c986b6682f59412
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8951
    Tested-by: jenkins

diff --git a/src/target/target.c b/src/target/target.c
index fd0e0116b..8bf654a27 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -71,44 +71,45 @@ static int target_gdb_fileio_end_default(struct target *target, int retcode,
 		int fileio_errno, bool ctrl_c);
 
 static struct target_type *target_types[] = {
+	// Keep in alphabetic order this list of targets
+	&aarch64_target,
+	&arcv2_target,
+	&arm11_target,
+	&arm720t_target,
 	&arm7tdmi_target,
-	&arm9tdmi_target,
 	&arm920t_target,
-	&arm720t_target,
-	&arm966e_target,
-	&arm946e_target,
 	&arm926ejs_target,
-	&fa526_target,
-	&feroceon_target,
-	&dragonite_target,
-	&xscale_target,
-	&xtensa_chip_target,
-	&cortexm_target,
+	&arm946e_target,
+	&arm966e_target,
+	&arm9tdmi_target,
+	&armv8r_target,
+	&avr32_ap7k_target,
+	&avr_target,
 	&cortexa_target,
+	&cortexm_target,
 	&cortexr4_target,
-	&arm11_target,
-	&ls1_sap_target,
-	&mips_m4k_target,
-	&avr_target,
+	&dragonite_target,
 	&dsp563xx_target,
 	&dsp5680xx_target,
-	&testee_target,
-	&avr32_ap7k_target,
-	&hla_target,
-	&esp32_target,
+	&esirisc_target,
 	&esp32s2_target,
 	&esp32s3_target,
+	&esp32_target,
+	&fa526_target,
+	&feroceon_target,
+	&hla_target,
+	&ls1_sap_target,
+	&mem_ap_target,
+	&mips_m4k_target,
+	&mips_mips64_target,
 	&or1k_target,
-	&quark_x10xx_target,
 	&quark_d20xx_target,
-	&stm8_target,
+	&quark_x10xx_target,
 	&riscv_target,
-	&mem_ap_target,
-	&esirisc_target,
-	&arcv2_target,
-	&aarch64_target,
-	&armv8r_target,
-	&mips_mips64_target,
+	&stm8_target,
+	&testee_target,
+	&xscale_target,
+	&xtensa_chip_target,
 	NULL,
 };
 
diff --git a/src/target/target_type.h b/src/target/target_type.h
index 5b0dc5a6c..a146fab76 100644
--- a/src/target/target_type.h
+++ b/src/target/target_type.h
@@ -307,6 +307,7 @@ struct target_type {
 	unsigned int (*data_bits)(struct target *target);
 };
 
+// Keep in alphabetic order this list of targets
 extern struct target_type aarch64_target;
 extern struct target_type arcv2_target;
 extern struct target_type arm11_target;

commit c92cf66c6714ebf367d1ccb1ba59010491924063
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 14:39:37 2025 +0200

    jtag: interfaces: sort the drivers by alphabetic order
    
    Add comments to require the list of drivers to be kept sorted.
    While there:
    - align the check on BUILD_PRESTO and BUILD_USB_BLASTER;
    - fix indentation of the closing parenthesis.
    
    Change-Id: Ic78281b1cdfb5bf72ea41427233e76516001b429
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8950
    Tested-by: jenkins

diff --git a/src/jtag/interface.h b/src/jtag/interface.h
index 475dbed36..834997361 100644
--- a/src/jtag/interface.h
+++ b/src/jtag/interface.h
@@ -371,6 +371,7 @@ int adapter_config_trace(bool enabled, enum tpiu_pin_protocol pin_protocol,
 		unsigned int traceclkin_freq, uint16_t *prescaler);
 int adapter_poll_trace(uint8_t *buf, size_t *size);
 
+// Keep in alphabetic order this list of drivers
 extern struct adapter_driver am335xgpio_adapter_driver;
 extern struct adapter_driver amt_jtagaccel_adapter_driver;
 extern struct adapter_driver angie_adapter_driver;
diff --git a/src/jtag/interfaces.c b/src/jtag/interfaces.c
index e49bd9e0f..834247245 100644
--- a/src/jtag/interfaces.c
+++ b/src/jtag/interfaces.c
@@ -36,125 +36,128 @@
  * drivers that were enabled by the @c configure script.
  */
 struct adapter_driver *adapter_drivers[] = {
-#if BUILD_PARPORT == 1
-		&parport_adapter_driver,
+		// Keep in alphabetic order this list of drivers
+
+#if BUILD_AM335XGPIO == 1
+		&am335xgpio_adapter_driver,
 #endif
-#if BUILD_DUMMY == 1
-		&dummy_adapter_driver,
+#if BUILD_AMTJTAGACCEL == 1
+		&amt_jtagaccel_adapter_driver,
 #endif
-#if BUILD_FTDI == 1
-		&ftdi_adapter_driver,
+#if BUILD_ANGIE == 1
+		&angie_adapter_driver,
 #endif
-#if BUILD_USB_BLASTER || BUILD_USB_BLASTER_2 == 1
-		&usb_blaster_adapter_driver,
+#if BUILD_ARMJTAGEW == 1
+		&armjtagew_adapter_driver,
 #endif
-#if BUILD_ESP_USB_JTAG == 1
-		&esp_usb_adapter_driver,
+#if BUILD_AT91RM9200 == 1
+		&at91rm9200_adapter_driver,
 #endif
-#if BUILD_JTAG_VPI == 1
-		&jtag_vpi_adapter_driver,
+#if BUILD_BCM2835GPIO == 1
+		&bcm2835gpio_adapter_driver,
 #endif
-#if BUILD_VDEBUG == 1
-		&vdebug_adapter_driver,
+#if BUILD_BUS_PIRATE == 1
+		&buspirate_adapter_driver,
 #endif
-#if BUILD_JTAG_DPI == 1
-		&jtag_dpi_adapter_driver,
+#if BUILD_CMSIS_DAP_USB == 1 || BUILD_CMSIS_DAP_HID == 1
+		&cmsis_dap_adapter_driver,
 #endif
-#if BUILD_FT232R == 1
-		&ft232r_adapter_driver,
+#if BUILD_DMEM == 1
+		&dmem_dap_adapter_driver,
 #endif
-#if BUILD_AMTJTAGACCEL == 1
-		&amt_jtagaccel_adapter_driver,
+#if BUILD_DUMMY == 1
+		&dummy_adapter_driver,
 #endif
 #if BUILD_EP93XX == 1
 		&ep93xx_adapter_driver,
 #endif
-#if BUILD_AT91RM9200 == 1
-		&at91rm9200_adapter_driver,
+#if BUILD_ESP_USB_JTAG == 1
+		&esp_usb_adapter_driver,
+#endif
+#if BUILD_FT232R == 1
+		&ft232r_adapter_driver,
+#endif
+#if BUILD_FTDI == 1
+		&ftdi_adapter_driver,
 #endif
 #if BUILD_GW16012 == 1
 		&gw16012_adapter_driver,
 #endif
-#if BUILD_PRESTO
-		&presto_adapter_driver,
-#endif
-#if BUILD_USBPROG == 1
-		&usbprog_adapter_driver,
+#if BUILD_HLADAPTER == 1
+		&hl_adapter_driver,
 #endif
-#if BUILD_OPENJTAG == 1
-		&openjtag_adapter_driver,
+#if BUILD_IMX_GPIO == 1
+		&imx_gpio_adapter_driver,
 #endif
 #if BUILD_JLINK == 1
 		&jlink_adapter_driver,
 #endif
-#if BUILD_VSLLINK == 1
-		&vsllink_adapter_driver,
-#endif
-#if BUILD_RLINK == 1
-		&rlink_adapter_driver,
+#if BUILD_JTAG_DPI == 1
+		&jtag_dpi_adapter_driver,
 #endif
-#if BUILD_ULINK == 1
-		&ulink_adapter_driver,
+#if BUILD_JTAG_VPI == 1
+		&jtag_vpi_adapter_driver,
 #endif
-#if BUILD_ANGIE == 1
-		&angie_adapter_driver,
+#if BUILD_KITPROG == 1
+		&kitprog_adapter_driver,
 #endif
-#if BUILD_ARMJTAGEW == 1
-		&armjtagew_adapter_driver,
+#if BUILD_LINUXGPIOD == 1
+		&linuxgpiod_adapter_driver,
 #endif
-#if BUILD_BUS_PIRATE == 1
-		&buspirate_adapter_driver,
+#if BUILD_LINUXSPIDEV == 1
+		&linuxspidev_adapter_driver,
 #endif
-#if BUILD_REMOTE_BITBANG == 1
-		&remote_bitbang_adapter_driver,
+#if BUILD_OPENDOUS == 1
+		&opendous_adapter_driver,
 #endif
-#if BUILD_HLADAPTER == 1
-		&hl_adapter_driver,
+#if BUILD_OPENJTAG == 1
+		&openjtag_adapter_driver,
 #endif
 #if BUILD_OSBDM == 1
 		&osbdm_adapter_driver,
 #endif
-#if BUILD_OPENDOUS == 1
-		&opendous_adapter_driver,
+#if BUILD_PARPORT == 1
+		&parport_adapter_driver,
 #endif
-#if BUILD_SYSFSGPIO == 1
-		&sysfsgpio_adapter_driver,
+#if BUILD_PRESTO == 1
+		&presto_adapter_driver,
 #endif
-#if BUILD_LINUXGPIOD == 1
-		&linuxgpiod_adapter_driver,
+#if BUILD_REMOTE_BITBANG == 1
+		&remote_bitbang_adapter_driver,
 #endif
-#if BUILD_LINUXSPIDEV == 1
-		&linuxspidev_adapter_driver,
+#if BUILD_RLINK == 1
+		&rlink_adapter_driver,
 #endif
-#if BUILD_XLNX_PCIE_XVC == 1
-		&xlnx_pcie_xvc_adapter_driver,
+#if BUILD_RSHIM == 1
+		&rshim_dap_adapter_driver,
 #endif
-#if BUILD_BCM2835GPIO == 1
-		&bcm2835gpio_adapter_driver,
+#if BUILD_HLADAPTER_STLINK == 1
+		&stlink_dap_adapter_driver,
 #endif
-#if BUILD_CMSIS_DAP_USB == 1 || BUILD_CMSIS_DAP_HID == 1
-		&cmsis_dap_adapter_driver,
+#if BUILD_SYSFSGPIO == 1
+		&sysfsgpio_adapter_driver,
 #endif
-#if BUILD_KITPROG == 1
-		&kitprog_adapter_driver,
+#if BUILD_ULINK == 1
+		&ulink_adapter_driver,
 #endif
-#if BUILD_IMX_GPIO == 1
-		&imx_gpio_adapter_driver,
+#if BUILD_USB_BLASTER == 1 || BUILD_USB_BLASTER_2 == 1
+		&usb_blaster_adapter_driver,
 #endif
-#if BUILD_XDS110 == 1
-		&xds110_adapter_driver,
+#if BUILD_USBPROG == 1
+		&usbprog_adapter_driver,
 #endif
-#if BUILD_HLADAPTER_STLINK == 1
-		&stlink_dap_adapter_driver,
+#if BUILD_VDEBUG == 1
+		&vdebug_adapter_driver,
 #endif
-#if BUILD_RSHIM == 1
-		&rshim_dap_adapter_driver,
+#if BUILD_VSLLINK == 1
+		&vsllink_adapter_driver,
 #endif
-#if BUILD_DMEM == 1
-		&dmem_dap_adapter_driver,
+#if BUILD_XDS110 == 1
+		&xds110_adapter_driver,
 #endif
-#if BUILD_AM335XGPIO == 1
-		&am335xgpio_adapter_driver,
+#if BUILD_XLNX_PCIE_XVC == 1
+		&xlnx_pcie_xvc_adapter_driver,
 #endif
+
 		NULL,
-	};
+};

commit 5d192a9f70a706f8639721a636156547875e9fa8
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 13:58:38 2025 +0200

    flash: nand: use array size to constraint the loop
    
    Instead of using NULL terminated arrays to determine the last
    element of the array, use the size of the array.
    
    Change-Id: I532a51a223061348e57bae3bd66ee6b346c1b070
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8949
    Tested-by: jenkins
    Reviewed-by: Brandon Martin

diff --git a/src/flash/nand/driver.c b/src/flash/nand/driver.c
index 69b3ba961..eda033b5b 100644
--- a/src/flash/nand/driver.c
+++ b/src/flash/nand/driver.c
@@ -10,6 +10,8 @@
 #ifdef HAVE_CONFIG_H
 #include <config.h>
 #endif
+
+#include <helper/types.h>
 #include "core.h"
 #include "driver.h"
 
@@ -29,12 +31,11 @@ static struct nand_flash_controller *nand_flash_controllers[] = {
 	&s3c2440_nand_controller,
 	&s3c2443_nand_controller,
 	&s3c6400_nand_controller,
-	NULL
 };
 
 struct nand_flash_controller *nand_driver_find_by_name(const char *name)
 {
-	for (unsigned int i = 0; nand_flash_controllers[i]; i++) {
+	for (size_t i = 0; i < ARRAY_SIZE(nand_flash_controllers); i++) {
 		struct nand_flash_controller *controller = nand_flash_controllers[i];
 		if (strcmp(name, controller->name) == 0)
 			return controller;
@@ -43,7 +44,7 @@ struct nand_flash_controller *nand_driver_find_by_name(const char *name)
 }
 int nand_driver_walk(nand_driver_walker_t f, void *x)
 {
-	for (unsigned int i = 0; nand_flash_controllers[i]; i++) {
+	for (size_t i = 0; i < ARRAY_SIZE(nand_flash_controllers); i++) {
 		int retval = (*f)(nand_flash_controllers[i], x);
 		if (retval != ERROR_OK)
 			return retval;

commit 6ab6d3475fb3758b60ad670b1b0d2cf3b2d10768
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 13:53:50 2025 +0200

    flash: nand: sort the drivers by alphabetic order
    
    Add comments to require the list of drivers to be kept sorted.
    
    Change-Id: I21b52cc1f5e679b0ebf7797e204248507f53557b
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8948
    Tested-by: jenkins

diff --git a/src/flash/nand/driver.c b/src/flash/nand/driver.c
index 5d99102c8..69b3ba961 100644
--- a/src/flash/nand/driver.c
+++ b/src/flash/nand/driver.c
@@ -14,20 +14,21 @@
 #include "driver.h"
 
 static struct nand_flash_controller *nand_flash_controllers[] = {
-	&nonce_nand_controller,
+	// Keep in alphabetic order the list of drivers
+	&at91sam9_nand_controller,
 	&davinci_nand_controller,
+	&imx31_nand_flash_controller,
 	&lpc3180_nand_controller,
 	&lpc32xx_nand_controller,
+	&mxc_nand_flash_controller,
+	&nonce_nand_controller,
+	&nuc910_nand_controller,
 	&orion_nand_controller,
 	&s3c2410_nand_controller,
 	&s3c2412_nand_controller,
 	&s3c2440_nand_controller,
 	&s3c2443_nand_controller,
 	&s3c6400_nand_controller,
-	&mxc_nand_flash_controller,
-	&imx31_nand_flash_controller,
-	&at91sam9_nand_controller,
-	&nuc910_nand_controller,
 	NULL
 };
 
diff --git a/src/flash/nand/driver.h b/src/flash/nand/driver.h
index 4e84f10fb..d26e77c75 100644
--- a/src/flash/nand/driver.h
+++ b/src/flash/nand/driver.h
@@ -89,6 +89,7 @@ typedef int (*nand_driver_walker_t)(struct nand_flash_controller *c, void *);
  */
 int nand_driver_walk(nand_driver_walker_t f, void *x);
 
+// Keep in alphabetic order the list of drivers
 extern struct nand_flash_controller at91sam9_nand_controller;
 extern struct nand_flash_controller davinci_nand_controller;
 extern struct nand_flash_controller imx31_nand_flash_controller;

commit fa0fa25764b4737b42fbceab9f56a467263e12b0
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 14:02:25 2025 +0200

    flash: nor: use array size to constraint the loop
    
    Instead of using NULL terminated arrays to determine the last
    element of the array, use the size of the array.
    
    Change-Id: Ia3d739b0a9f201ba2e7b1d1244d60c8e5546c9c1
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8947
    Reviewed-by: Brandon Martin
    Tested-by: jenkins

diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c
index 4f468848b..cb807ec62 100644
--- a/src/flash/nor/drivers.c
+++ b/src/flash/nor/drivers.c
@@ -7,6 +7,8 @@
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
+
+#include <helper/types.h>
 #include "imp.h"
 
 /**
@@ -89,12 +91,11 @@ static const struct flash_driver * const flash_drivers[] = {
 	&xcf_flash,
 	&xmc1xxx_flash,
 	&xmc4xxx_flash,
-	NULL,
 };
 
 const struct flash_driver *flash_driver_find_by_name(const char *name)
 {
-	for (unsigned int i = 0; flash_drivers[i]; i++) {
+	for (size_t i = 0; i < ARRAY_SIZE(flash_drivers); i++) {
 		if (strcmp(name, flash_drivers[i]->name) == 0)
 			return flash_drivers[i];
 	}

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nand/driver.c  |  18 +++---
 src/flash/nand/driver.h  |   1 +
 src/flash/nor/drivers.c  |   5 +-
 src/jtag/interface.h     |   1 +
 src/jtag/interfaces.c    | 153 ++++++++++++++++++++++++-----------------------
 src/target/target.c      |  64 ++++++++++----------
 src/target/target_type.h |   1 +
 7 files changed, 126 insertions(+), 117 deletions(-)


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Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1056-ga64ae963b

From: openocd-gerrit <ope...@us...> - 2025-06-29 07:32:35

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
       via  a64ae963be55a3a7e12d8f7a91c9787bf4047778 (commit)
      from  a9015ba79d73fcc68fac7b98e679e6d4818472ee (commit)

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- Log -----------------------------------------------------------------
commit a64ae963be55a3a7e12d8f7a91c9787bf4047778
Author: Antonio Borneo <bor...@gm...>
Date:   Sat Jun 14 12:36:07 2025 +0200

    flash: nor: sort the drivers by alphabetic order
    
    Add comments to require the list of drivers to be kept sorted.
    
    Change-Id: I57382605edc6a38d6c1ac18393421b18ae72215b
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8946
    Tested-by: jenkins

diff --git a/src/flash/nor/driver.h b/src/flash/nor/driver.h
index 3b57ef9ff..da649e783 100644
--- a/src/flash/nor/driver.h
+++ b/src/flash/nor/driver.h
@@ -237,6 +237,7 @@ struct flash_driver {
  */
 const struct flash_driver *flash_driver_find_by_name(const char *name);
 
+// Keep in alphabetic order this list of drivers
 extern const struct flash_driver aduc702x_flash;
 extern const struct flash_driver aducm360_flash;
 extern const struct flash_driver ambiqmicro_flash;
diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c
index 3770bfbd3..4f468848b 100644
--- a/src/flash/nor/drivers.c
+++ b/src/flash/nor/drivers.c
@@ -14,6 +14,7 @@
  * @todo Make this dynamically extendable with loadable modules.
  */
 static const struct flash_driver * const flash_drivers[] = {
+	// Keep in alphabetic order the list of drivers
 	&aduc702x_flash,
 	&aducm360_flash,
 	&ambiqmicro_flash,
@@ -27,8 +28,8 @@ static const struct flash_driver * const flash_drivers[] = {
 	&atsamv_flash,
 	&avr_flash,
 	&bluenrgx_flash,
-	&cc3220sf_flash,
 	&cc26xx_flash,
+	&cc3220sf_flash,
 	&cfi_flash,
 	&dsp5680xx_flash,
 	&dw_spi_flash,
@@ -37,9 +38,9 @@ static const struct flash_driver * const flash_drivers[] = {
 	&eneispif_flash,
 	&esirisc_flash,
 	&faux_flash,
+	&fespi_flash,
 	&fm3_flash,
 	&fm4_flash,
-	&fespi_flash,
 	&jtagspi_flash,
 	&kinetis_flash,
 	&kinetis_ke_flash,
@@ -54,40 +55,40 @@ static const struct flash_driver * const flash_drivers[] = {
 	&mspm0_flash,
 	&niietcm4_flash,
 	&npcx_flash,
-	&nrf5_flash,
 	&nrf51_flash,
+	&nrf5_flash,
 	&numicro_flash,
 	&ocl_flash,
 	&pic32mx_flash,
 	&psoc4_flash,
-	&psoc5lp_flash,
 	&psoc5lp_eeprom_flash,
+	&psoc5lp_flash,
 	&psoc5lp_nvl_flash,
 	&psoc6_flash,
 	&qn908x_flash,
 	&renesas_rpchf_flash,
 	&rp2xxx_flash,
+	&rsl10_flash,
 	&sh_qspi_flash,
 	&sim3x_flash,
 	&stellaris_flash,
 	&stm32f1x_flash,
 	&stm32f2x_flash,
-	&stm32lx_flash,
-	&stm32l4x_flash,
 	&stm32h7x_flash,
-	&stmsmi_flash,
+	&stm32l4x_flash,
+	&stm32lx_flash,
 	&stmqspi_flash,
+	&stmsmi_flash,
 	&str7x_flash,
 	&str9x_flash,
 	&str9xpec_flash,
 	&swm050_flash,
 	&tms470_flash,
 	&virtual_flash,
+	&w600_flash,
 	&xcf_flash,
 	&xmc1xxx_flash,
 	&xmc4xxx_flash,
-	&w600_flash,
-	&rsl10_flash,
 	NULL,
 };
 

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/driver.h  |  1 +
 src/flash/nor/drivers.c | 19 ++++++++++---------
 2 files changed, 11 insertions(+), 9 deletions(-)


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This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
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      from  1040bdec79d430440a31e77585547eb15c39966a (commit)

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- Log -----------------------------------------------------------------
commit a9015ba79d73fcc68fac7b98e679e6d4818472ee
Author: Marc Schink <de...@za...>
Date:   Thu Jun 19 10:28:36 2025 +0200

    tcl/target/lsch3_common: Remove 'mem2array'
    
    The 'mem2array' function is deprecated and replaced by 'read_memory'.
    
    Change-Id: Iea54a390d67978d20dbb99ab6f7f4178dda481c2
    Reported-by: Paul Fertser <fer...@gm...>
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8962
    Reviewed-by: Paul Fertser <fer...@gm...>
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/lsch3_common.cfg b/tcl/target/lsch3_common.cfg
index f48d59b9d..ad88b2e1b 100644
--- a/tcl/target/lsch3_common.cfg
+++ b/tcl/target/lsch3_common.cfg
@@ -51,8 +51,8 @@ proc release_cpu {cpu} {
 	}
 
 	# Release the cpu; it will start executing something bogus
-	mem2array regs 32 $RST_BRRL 1
-	mww $RST_BRRL [expr {$regs(0) | 1 << $cpu}]
+	set reg [read_memory $RST_BRRL 32 1]
+	mww $RST_BRRL [expr {$reg | 1 << $cpu}]
 
 	if {$not_halted} {
 		resume

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/lsch3_common.cfg | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1054-g1040bdec7

From: openocd-gerrit <ope...@us...> - 2025-06-21 07:38:45

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The branch, master has been updated
       via  1040bdec79d430440a31e77585547eb15c39966a (commit)
      from  99d642ca5b9c6c56c14325d6128a661cedae41a3 (commit)

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- Log -----------------------------------------------------------------
commit 1040bdec79d430440a31e77585547eb15c39966a
Author: Vitaly Cheptsov <vi...@pr...>
Date:   Sun May 18 08:49:30 2025 +0300

    jlink: add nickname support
    
    Using nicknames provides a human-readable alternative to serial
    numbers for convenience purposes. Allow matching adapter serial
    with device nickname.
    
    Change-Id: I03b8d28a6c89412a825d42f4f66b3b528f217d9c
    Signed-off-by: Vitaly Cheptsov <vi...@pr...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8886
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: zapb <de...@za...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 948372c7c..494042530 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2499,6 +2499,9 @@ If this command is not specified, serial strings are not checked.
 Only the following adapter drivers use the serial string from this command:
 arm-jtag-ew, cmsis_dap, esp_usb_jtag, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
 openjtag, osbdm, presto, rlink, st-link, usb_blaster (ublast2), usbprog, vsllink, xds110.
+
+For jlink adapters, the @var{serial_string} is also compared
+against the adapter's nickname.
 @end deffn
 
 @section Interface Drivers
diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c
index 9caf37f6f..f6bb3099d 100644
--- a/src/jtag/drivers/jlink.c
+++ b/src/jtag/drivers/jlink.c
@@ -23,6 +23,7 @@
 
 #include <stdint.h>
 #include <math.h>
+#include <string.h>
 
 #include <jtag/interface.h>
 #include <jtag/swd.h>
@@ -40,8 +41,6 @@ static struct jaylink_connection connlist[JAYLINK_MAX_CONNECTIONS];
 static enum jaylink_jtag_version jtag_command_version;
 static uint8_t caps[JAYLINK_DEV_EXT_CAPS_SIZE];
 
-static uint32_t serial_number;
-static bool use_serial_number;
 static bool use_usb_location;
 static enum jaylink_usb_address usb_address;
 static bool use_usb_address;
@@ -561,8 +560,9 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device)
 	}
 
 	use_usb_location = !!adapter_usb_get_location();
+	const char *adapter_serial = adapter_get_required_serial();
 
-	if (!use_serial_number && !use_usb_address && !use_usb_location && num_devices > 1) {
+	if (!adapter_serial && !use_usb_address && !use_usb_location && num_devices > 1) {
 		LOG_ERROR("Multiple devices found, specify the desired device");
 		LOG_INFO("Found devices:");
 		for (size_t i = 0; devs[i]; i++) {
@@ -575,7 +575,12 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device)
 					jaylink_strerror(ret));
 				continue;
 			}
-			LOG_INFO("Device %zu serial: %" PRIu32, i, serial);
+			char name[JAYLINK_NICKNAME_MAX_LENGTH];
+			int name_ret = jaylink_device_get_nickname(devs[i], name);
+			if (name_ret == JAYLINK_OK)
+				LOG_INFO("Device %zu serial: %" PRIu32 ", nickname %s", i, serial, name);
+			else
+				LOG_INFO("Device %zu serial: %" PRIu32, i, serial);
 		}
 
 		jaylink_free_devices(devs, true);
@@ -585,23 +590,39 @@ static int jlink_open_device(uint32_t ifaces, bool *found_device)
 
 	*found_device = false;
 
+	uint32_t serial_number;
+	ret = jaylink_parse_serial_number(adapter_serial, &serial_number);
+	if (ret != JAYLINK_OK)
+		serial_number = 0;
+
 	for (size_t i = 0; devs[i]; i++) {
 		struct jaylink_device *dev = devs[i];
 
-		if (use_serial_number) {
-			uint32_t tmp;
-			ret = jaylink_device_get_serial_number(dev, &tmp);
-
-			if (ret == JAYLINK_ERR_NOT_AVAILABLE) {
-				continue;
-			} else if (ret != JAYLINK_OK) {
-				LOG_WARNING("jaylink_device_get_serial_number() failed: %s",
-					jaylink_strerror(ret));
-				continue;
+		if (adapter_serial) {
+			/*
+			 * Treat adapter serial as a nickname first as it can also be numeric.
+			 * If it fails to match (optional) device nickname try to compare
+			 * adapter serial with the actual device serial number.
+			 */
+			char nickname[JAYLINK_NICKNAME_MAX_LENGTH];
+			ret = jaylink_device_get_nickname(dev, nickname);
+			if (ret != JAYLINK_OK || strcmp(nickname, adapter_serial) != 0) {
+				if (!serial_number)
+					continue;
+
+				uint32_t tmp;
+				ret = jaylink_device_get_serial_number(dev, &tmp);
+				if (ret == JAYLINK_ERR_NOT_AVAILABLE) {
+					continue;
+				} else if (ret != JAYLINK_OK) {
+					LOG_WARNING("jaylink_device_get_serial_number() failed: %s",
+						jaylink_strerror(ret));
+					continue;
+				}
+
+				if (serial_number != tmp)
+					continue;
 			}
-
-			if (serial_number != tmp)
-				continue;
 		}
 
 		if (use_usb_address) {
@@ -670,29 +691,15 @@ static int jlink_init(void)
 		return ERROR_JTAG_INIT_FAILED;
 	}
 
-	const char *serial = adapter_get_required_serial();
-	if (serial) {
-		ret = jaylink_parse_serial_number(serial, &serial_number);
-		if (ret == JAYLINK_ERR) {
-			LOG_ERROR("Invalid serial number: %s", serial);
-			jaylink_exit(jayctx);
-			return ERROR_JTAG_INIT_FAILED;
-		}
-		if (ret != JAYLINK_OK) {
-			LOG_ERROR("jaylink_parse_serial_number() failed: %s", jaylink_strerror(ret));
-			jaylink_exit(jayctx);
-			return ERROR_JTAG_INIT_FAILED;
-		}
-		use_serial_number = true;
+	if (adapter_get_required_serial())
 		use_usb_address = false;
-	}
 
 	bool found_device;
 	ret = jlink_open_device(JAYLINK_HIF_USB, &found_device);
 	if (ret != ERROR_OK)
 		return ret;
 
-	if (!found_device && use_serial_number) {
+	if (!found_device && adapter_get_required_serial()) {
 		ret = jlink_open_device(JAYLINK_HIF_TCP, &found_device);
 		if (ret != ERROR_OK)
 			return ret;

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi         |  3 ++
 src/jtag/drivers/jlink.c | 73 ++++++++++++++++++++++++++----------------------
 2 files changed, 43 insertions(+), 33 deletions(-)


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