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|
From: openocd-gerrit <ope...@us...> - 2025-12-19 21:18:15
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via e440b0648fd5a9ced8b3a05ff1a73b17c00cd144 (commit)
from 0e2f990c8703f1296a41815fafa2e0f73d249a8e (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit e440b0648fd5a9ced8b3a05ff1a73b17c00cd144
Author: Ryan QIAN <jia...@hp...>
Date: Mon Jan 27 12:06:50 2025 +0800
doc: add hpm_xpi flash driver description
- add description for hpm_xpi flash driver
Change-Id: I5336c11c8dbe5ab646d08e4e70aeef1ed6cbd970
Signed-off-by: Ryan QIAN <jia...@hp...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8726
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index f623d716e..4c2956334 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6225,6 +6225,22 @@ flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
@c "cfi part_id" disabled
@end deffn
+@deffn {Flash Driver} {hpm_xpi}
+All members of the HPMxxxx microcontroller family from HPMicro.
+Additional parameters are required to configure the driver: @option{io_base} is
+the base address of the configuration register interface, @option{opt0} and
+@option{opt1} are the options for the flash.
+
+@example
+flash bank $@{_FLASHNAME@}0 hpm_xpi base_address size_bytes 0 0 $_TARGETNAME \
+ io_base opt0 opt1
+@end example
+
+@deffn {Command} {hpm_xpi mass_erase} bank_id
+Erase all pages in data memory for the bank identified by @option{bank_id}.
+@end deffn
+@end deffn
+
@anchor{jtagspi}
@deffn {Flash Driver} {jtagspi}
@cindex Generic JTAG2SPI driver
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-12-19 21:17:59
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 0e2f990c8703f1296a41815fafa2e0f73d249a8e (commit)
from 26507adfad37ab81953fe1d37efead956a99de21 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 0e2f990c8703f1296a41815fafa2e0f73d249a8e
Author: Ryan QIAN <jia...@hp...>
Date: Tue Jan 7 15:21:02 2025 +0800
tcl: add config file for hpmicro devices and boards
- add board and device config files
- add interface config file for hpmicro evk boards
Change-Id: I8afb0b734b1064d71c4af3c118c7777d0ead9e6b
Signed-off-by: Ryan QIAN <jia...@hp...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8697
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/tcl/board/hpmicro/hpm5300evk.cfg b/tcl/board/hpmicro/hpm5300evk.cfg
new file mode 100644
index 000000000..70eacd36a
--- /dev/null
+++ b/tcl/board/hpmicro/hpm5300evk.cfg
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2023 HPMicro
+
+adapter speed 10000
+source [find interface/hpmicro/hpmicro_evk.cfg]
+source [find target/hpmicro/hpm5300.cfg]
+# openocd flash driver argument:
+# - option0:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+# [15:8] Dummy cycles
+# 0 - Auto-probed / detected / default value
+# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+# [7:4] Misc.
+# 0 - Not used
+# 1 - SPI mode
+# 2 - Internal loopback
+# 3 - External DQS
+# [3:0] Frequency option
+# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+# - option1:
+# [31:20] Reserved
+# [19:16] IO voltage
+# 0 - 3V / 1 - 1.8V
+# [15:12] Pin group
+# 0 - 1st group / 1 - 2nd group
+# [11:8] Connection selection
+# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+# [7:0] Drive Strength
+# 0 - Default value
+
+# xpi0 configs
+# - flash driver: hpm_xpi
+# - flash ctrl index: 0xF3000000
+# - base address: 0x80000000
+# - flash size: 0x2000000
+# - flash option0: 0x5
+# - flash option1: 0x1000
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3000000 0x5 0x1000
+
+proc init_clock {} {
+ mww 0xF4000800 0xFFFFFFFF
+ mww 0xF4000810 0xFFFFFFFF
+ mww 0xF4000820 0xFFFFFFFF
+ mww 0xF4000830 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+}
diff --git a/tcl/board/hpmicro/hpm5301evklite.cfg b/tcl/board/hpmicro/hpm5301evklite.cfg
new file mode 100644
index 000000000..effa50601
--- /dev/null
+++ b/tcl/board/hpmicro/hpm5301evklite.cfg
@@ -0,0 +1,66 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2023 HPMicro
+
+adapter speed 10000
+source [find interface/hpmicro/hpmicro_evk.cfg]
+source [find target/hpmicro/hpm5300.cfg]
+# openocd flash driver argument:
+# - option0:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+# [15:8] Dummy cycles
+# 0 - Auto-probed / detected / default value
+# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+# [7:4] Misc.
+# 0 - Not used
+# 1 - SPI mode
+# 2 - Internal loopback
+# 3 - External DQS
+# [3:0] Frequency option
+# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+# - option1:
+# [31:20] Reserved
+# [19:16] IO voltage
+# 0 - 3V / 1 - 1.8V
+# [15:12] Pin group
+# 0 - 1st group / 1 - 2nd group
+# [11:8] Connection selection
+# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+# [7:0] Drive Strength
+# 0 - Default value
+
+# xpi0 configs
+# - flash driver: hpm_xpi
+# - flash ctrl index: 0xF3000000
+# - base address: 0x80000000
+# - flash size: 0x2000000
+# - flash option0: 0x5
+# - flash option1: 0x1000
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000
+
+proc init_clock {} {
+ mww 0xF4000800 0xFFFFFFFF
+ mww 0xF4000810 0xFFFFFFFF
+ mww 0xF4000820 0xFFFFFFFF
+ mww 0xF4000830 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+}
diff --git a/tcl/board/hpmicro/hpm6200evk.cfg b/tcl/board/hpmicro/hpm6200evk.cfg
new file mode 100644
index 000000000..67cda4fed
--- /dev/null
+++ b/tcl/board/hpmicro/hpm6200evk.cfg
@@ -0,0 +1,64 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2023 HPMicro
+
+adapter speed 10000
+source [find interface/hpmicro/hpmicro_evk.cfg]
+source [find target/hpmicro/hpm6280-single-core.cfg]
+# openocd flash driver argument:
+# - option0:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+# [15:8] Dummy cycles
+# 0 - Auto-probed / detected / default value
+# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+# [7:4] Misc.
+# 0 - Not used
+# 1 - SPI mode
+# 2 - Internal loopback
+# 3 - External DQS
+# [3:0] Frequency option
+# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+# - option1:
+# [31:20] Reserved
+# [19:16] IO voltage
+# 0 - 3V / 1 - 1.8V
+# [15:12] Pin group
+# 0 - 1st group / 1 - 2nd group
+# [11:8] Connection selection
+# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+# [7:0] Drive Strength
+# 0 - Default value
+
+# xpi0 configs
+# - flash driver: hpm_xpi
+# - flash ctrl index: 0xF3040000
+# - base address: 0x80000000
+# - flash size: 0x1000000
+flash bank xpi0 hpm_xpi 0x80000000 0x1000000 0 0 $_TARGET0 0xF3040000
+
+proc init_clock {} {
+ mww 0xF4000800 0xFFFFFFFF
+ mww 0xF4000810 0xFFFFFFFF
+ mww 0xF4000820 0xFFFFFFFF
+ mww 0xF4000830 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+}
diff --git a/tcl/board/hpmicro/hpm6300evk.cfg b/tcl/board/hpmicro/hpm6300evk.cfg
new file mode 100644
index 000000000..5d0a71189
--- /dev/null
+++ b/tcl/board/hpmicro/hpm6300evk.cfg
@@ -0,0 +1,217 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2021 HPMicro
+
+adapter speed 10000
+source [find interface/hpmicro/hpmicro_evk.cfg]
+source [find target/hpmicro/hpm6360.cfg]
+# openocd flash driver argument:
+# - option0:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+# openocd flash driver argument:
+# - option0:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+# [15:8] Dummy cycles
+# 0 - Auto-probed / detected / default value
+# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+# [7:4] Misc.
+# 0 - Not used
+# 1 - SPI mode
+# 2 - Internal loopback
+# 3 - External DQS
+# [3:0] Frequency option
+# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+# - option1:
+# [31:20] Reserved
+# [19:16] IO voltage
+# 0 - 3V / 1 - 1.8V
+# [15:12] Pin group
+# 0 - 1st group / 1 - 2nd group
+# [11:8] Connection selection
+# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+# [7:0] Drive Strength
+# 0 - Default value
+
+# xpi0 configs
+# - flash driver: hpm_xpi
+# - flash ctrl index: 0xF3040000
+# - base address: 0x80000000
+# - flash size: 0x1000000
+flash bank xpi0 hpm_xpi 0x80000000 0x1000000 0 0 $_TARGET0 0xF3040000
+
+proc init_clock {} {
+ mww 0xF4000800 0xFFFFFFFF
+ mww 0xF4000810 0xFFFFFFFF
+ mww 0xF4000820 0xFFFFFFFF
+ mww 0xF4000830 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+proc init_sdram { } {
+# configure femc frequency
+# 166Mhz pll0_clk1: 333Mhz divide by 2
+ mww 0xF4001808 0x201
+
+ # PA25
+ mww 0xF40400C8 0xC
+ # PA26
+ mww 0xF40400D0 0xC
+ # PA27
+ mww 0xF40400D8 0xC
+ # PA28
+ mww 0xF40400E0 0xC
+ # PA29
+ mww 0xF40400E8 0xC
+ # PA30
+ mww 0xF40400F0 0xC
+ # PA31
+ mww 0xF40400F8 0xC
+ # PB00
+ mww 0xF4040100 0xC
+ # PB01
+ mww 0xF4040108 0xC
+ # PB02
+ mww 0xF4040110 0xC
+ # PB03
+ mww 0xF4040118 0xC
+ # PB04
+ mww 0xF4040120 0xC
+ # PB05
+ mww 0xF4040128 0xC
+ # PB06
+ mww 0xF4040130 0xC
+ # PB07
+ mww 0xF4040138 0xC
+ # PB08
+ mww 0xF4040140 0xC
+
+ # PB09
+ mww 0xF4040148 0xC
+ # PB10
+ mww 0xF4040150 0xC
+ # PB11
+ mww 0xF4040158 0xC
+ # PB12
+ mww 0xF4040160 0xC
+ # PB13
+ mww 0xF4040168 0xC
+ # PB14
+ mww 0xF4040170 0xC
+ # PB15
+ mww 0xF4040178 0xC
+ # PB16
+ mww 0xF4040180 0xC
+ # PB17
+ mww 0xF4040188 0xC
+ # PB18
+ mww 0xF4040190 0xC
+ # PB19
+ mww 0xF4040198 0xC
+ # PB20
+ mww 0xF40401A0 0xC
+
+ # PB21
+ mww 0xF40401A8 0xC
+ # PB22
+ mww 0xF40401B0 0xC
+ # PB23
+ mww 0xF40401B8 0xC
+ # PB24
+ mww 0xF40401C0 0xC
+ # PB25
+ mww 0xF40401C8 0xC
+ # PB26
+ mww 0xF40401D0 0xC
+ # PB27
+ mww 0xF40401D8 0xC
+ # PB28
+ mww 0xF40401E0 0xC
+ # PB29
+ mww 0xF40401E8 0xC
+ # PB30
+ mww 0xF40401F0 0xC
+ # PB31
+ mww 0xF40401F8 0xC
+
+ # femc configuration
+ mww 0xF3050000 0x1
+ sleep 10
+ mww 0xF3050000 0x2
+ mww 0xF3050008 0x30524
+ mww 0xF305000C 0x6030524
+ mww 0xF3050000 0x10000004
+
+ # 32MB
+ mww 0xF3050010 0x4000001b
+ mww 0xF3050014 0
+ # 16-bit
+ mww 0xF3050040 0xf31
+
+ # 166Mhz configuration
+ mww 0xF3050044 0x884e33
+ mww 0xF3050048 0x1020d0d
+ mww 0xF3050048 0x1020d0d
+ mww 0xF305004C 0x2020300
+
+ # config delay cell
+ mww 0xF3050150 0x2000
+ mww 0xF3050094 0
+ mww 0xF3050098 0
+
+ # precharge all
+ mww 0xF3050090 0x40000000
+ mww 0xF305009C 0xA55A000F
+ sleep 500
+ mww 0xF305003C 0x3
+ # auto refresh
+ mww 0xF305009C 0xA55A000C
+ sleep 500
+ mww 0xF305003C 0x3
+ mww 0xF305009C 0xA55A000C
+ sleep 500
+ mww 0xF305003C 0x3
+
+ # set mode
+ mww 0xF30500A0 0x33
+ mww 0xF305009C 0xA55A000A
+ sleep 500
+ mww 0xF305003C 0x3
+ mww 0xF305004C 0x2020301
+ echo "SDRAM has been initialized"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+ init_sdram
+}
diff --git a/tcl/board/hpmicro/hpm6750evk.cfg b/tcl/board/hpmicro/hpm6750evk.cfg
new file mode 100644
index 000000000..7cabef6dc
--- /dev/null
+++ b/tcl/board/hpmicro/hpm6750evk.cfg
@@ -0,0 +1,239 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2021 HPMicro
+
+adapter speed 10000
+source [find interface/hpmicro/hpmicro_evk.cfg]
+source [find target/hpmicro/hpm6750-single-core.cfg]
+# openocd flash driver argument:
+# - option0:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+# [15:8] Dummy cycles
+# 0 - Auto-probed / detected / default value
+# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+# [7:4] Misc.
+# 0 - Not used
+# 1 - SPI mode
+# 2 - Internal loopback
+# 3 - External DQS
+# [3:0] Frequency option
+# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+# - option1:
+# [31:20] Reserved
+# [19:16] IO voltage
+# 0 - 3V / 1 - 1.8V
+# [15:12] Pin group
+# 0 - 1st group / 1 - 2nd group
+# [11:8] Connection selection
+# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+# [7:0] Drive Strength
+# 0 - Default value
+
+# xpi0 configs
+# - flash driver: hpm_xpi
+# - flash ctrl index: 0xF3040000
+# - base address: 0x80000000
+# - flash size: 0x2000000
+# - flash option0: 0x7
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3040000 0x7
+
+proc init_clock {} {
+ mww 0xF4000800 0xFFFFFFFF
+ mww 0xF4000810 0xFFFFFFFF
+ mww 0xF4000820 0xFFFFFFFF
+ mww 0xF4000830 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+proc init_sdram { } {
+# configure femc frequency
+# 133Mhz pll1_clk0: 266Mhz divide by 2
+ #mww 0xF4001820 0x201
+# 166Mhz pll2_clk0: 333Mhz divide by 2
+ mww 0xF4001820 0x401
+ # PC01
+ mww 0xF4040208 0xC
+ # PC00
+ mww 0xF4040200 0xC
+ # PB31
+ mww 0xF40401F8 0xC
+ # PB30
+ mww 0xF40401F0 0xC
+ # PB29
+ mww 0xF40401E8 0xC
+ # PB28
+ mww 0xF40401E0 0xC
+ # PB27
+ mww 0xF40401D8 0xC
+ # PB26
+ mww 0xF40401D0 0xC
+ # PB25
+ mww 0xF40401C8 0xC
+ # PB24
+ mww 0xF40401C0 0xC
+ # PB23
+ mww 0xF40401B8 0xC
+ # PB22
+ mww 0xF40401B0 0xC
+ # PB21
+ mww 0xF40401A8 0xC
+ # PB20
+ mww 0xF40401A0 0xC
+ # PB19
+ mww 0xF4040198 0xC
+ # PB18
+ mww 0xF4040190 0xC
+
+ # PD13
+ mww 0xF4040368 0xC
+ # PD12
+ mww 0xF4040360 0xC
+ # PD10
+ mww 0xF4040350 0xC
+ # PD09
+ mww 0xF4040348 0xC
+ # PD08
+ mww 0xF4040340 0xC
+ # PD07
+ mww 0xF4040338 0xC
+ # PD06
+ mww 0xF4040330 0xC
+ # PD05
+ mww 0xF4040328 0xC
+ # PD04
+ mww 0xF4040320 0xC
+ # PD03
+ mww 0xF4040318 0xC
+ # PD02
+ mww 0xF4040310 0xC
+ # PD01
+ mww 0xF4040308 0xC
+ # PD00
+ mww 0xF4040300 0xC
+ # PC29
+ mww 0xF40402E8 0xC
+ # PC28
+ mww 0xF40402E0 0xC
+ # PC27
+ mww 0xF40402D8 0xC
+
+ # PC22
+ mww 0xF40402B0 0xC
+ # PC21
+ mww 0xF40402A8 0xC
+ # PC17
+ mww 0xF4040288 0xC
+ # PC15
+ mww 0xF4040278 0xC
+ # PC12
+ mww 0xF4040260 0xC
+ # PC11
+ mww 0xF4040258 0xC
+ # PC10
+ mww 0xF4040250 0xC
+ # PC09
+ mww 0xF4040248 0xC
+ # PC08
+ mww 0xF4040240 0xC
+ # PC07
+ mww 0xF4040238 0xC
+ # PC06
+ mww 0xF4040230 0xC
+ # PC05
+ mww 0xF4040228 0xC
+ # PC04
+ mww 0xF4040220 0xC
+
+ # PC14
+ mww 0xF4040270 0xC
+ # PC13
+ mww 0xF4040268 0xC
+ # PC16
+ # mww 0xF4040280 0x1000C
+ # PC26
+ mww 0xF40402D0 0xC
+ # PC25
+ mww 0xF40402C8 0xC
+ # PC19
+ mww 0xF4040298 0xC
+ # PC18
+ mww 0xF4040290 0xC
+ # PC23
+ mww 0xF40402B8 0xC
+ # PC24
+ mww 0xF40402C0 0xC
+ # PC30
+ mww 0xF40402F0 0xC
+ # PC31
+ mww 0xF40402F8 0xC
+ # PC02
+ mww 0xF4040210 0xC
+ # PC03
+ mww 0xF4040218 0xC
+
+ # femc configuration
+ mww 0xF3050000 0x1
+ sleep 10
+ mww 0xF3050000 0x2
+ mww 0xF3050008 0x30524
+ mww 0xF305000C 0x6030524
+ mww 0xF3050000 0x10000000
+ mww 0xF3050010 0x4000001b
+ mww 0xF3050014 0
+ mww 0xF3050040 0xf32
+
+ # 133Mhz configuration
+ #mww 0xF3050044 0x884e22
+ # 166Mhz configuration
+ mww 0xF3050044 0x884e33
+ mww 0xF3050048 0x1020d0d
+ mww 0xF3050048 0x1020d0d
+ mww 0xF305004C 0x2020300
+
+ # config delay cell
+ mww 0xF3050150 0x3b
+ mww 0xF3050150 0x203b
+ mww 0xF3050094 0
+ mww 0xF3050098 0
+
+ # precharge all
+ mww 0xF3050090 0x40000000
+ mww 0xF305009C 0xA55A000F
+ sleep 500
+ mww 0xF305003C 0x3
+ # auto refresh
+ mww 0xF305009C 0xA55A000C
+ sleep 500
+ mww 0xF305003C 0x3
+ mww 0xF305009C 0xA55A000C
+ sleep 500
+ mww 0xF305003C 0x3
+
+ # set mode
+ mww 0xF30500A0 0x33
+ mww 0xF305009C 0xA55A000A
+ sleep 500
+ mww 0xF305003C 0x3
+ mww 0xF305004C 0x2020301
+ echo "SDRAM has been initialized"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+ init_sdram
+}
diff --git a/tcl/board/hpmicro/hpm6750evk2.cfg b/tcl/board/hpmicro/hpm6750evk2.cfg
new file mode 100644
index 000000000..35fca3c37
--- /dev/null
+++ b/tcl/board/hpmicro/hpm6750evk2.cfg
@@ -0,0 +1,239 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2022 HPMicro
+
+adapter speed 10000
+source [find interface/hpmicro/hpmicro_evk.cfg]
+source [find target/hpmicro/hpm6750-single-core.cfg]
+# openocd flash driver argument:
+# - option0:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+# [15:8] Dummy cycles
+# 0 - Auto-probed / detected / default value
+# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+# [7:4] Misc.
+# 0 - Not used
+# 1 - SPI mode
+# 2 - Internal loopback
+# 3 - External DQS
+# [3:0] Frequency option
+# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+# - option1:
+# [31:20] Reserved
+# [19:16] IO voltage
+# 0 - 3V / 1 - 1.8V
+# [15:12] Pin group
+# 0 - 1st group / 1 - 2nd group
+# [11:8] Connection selection
+# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+# [7:0] Drive Strength
+# 0 - Default value
+
+# xpi0 configs
+# - flash driver: hpm_xpi
+# - flash ctrl index: 0xF3040000
+# - base address: 0x80000000
+# - flash size: 0x2000000
+# - flash option0: 0x7
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3040000 0x7
+
+proc init_clock {} {
+ mww 0xF4000800 0xFFFFFFFF
+ mww 0xF4000810 0xFFFFFFFF
+ mww 0xF4000820 0xFFFFFFFF
+ mww 0xF4000830 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+proc init_sdram { } {
+# configure femc frequency
+# 133Mhz pll1_clk0: 266Mhz divide by 2
+ #mww 0xF4001820 0x201
+# 166Mhz pll2_clk0: 333Mhz divide by 2
+ mww 0xF4001820 0x401
+ # PC01
+ mww 0xF4040208 0xC
+ # PC00
+ mww 0xF4040200 0xC
+ # PB31
+ mww 0xF40401F8 0xC
+ # PB30
+ mww 0xF40401F0 0xC
+ # PB29
+ mww 0xF40401E8 0xC
+ # PB28
+ mww 0xF40401E0 0xC
+ # PB27
+ mww 0xF40401D8 0xC
+ # PB26
+ mww 0xF40401D0 0xC
+ # PB25
+ mww 0xF40401C8 0xC
+ # PB24
+ mww 0xF40401C0 0xC
+ # PB23
+ mww 0xF40401B8 0xC
+ # PB22
+ mww 0xF40401B0 0xC
+ # PB21
+ mww 0xF40401A8 0xC
+ # PB20
+ mww 0xF40401A0 0xC
+ # PB19
+ mww 0xF4040198 0xC
+ # PB18
+ mww 0xF4040190 0xC
+
+ # PD13
+ mww 0xF4040368 0xC
+ # PD12
+ mww 0xF4040360 0xC
+ # PD10
+ mww 0xF4040350 0xC
+ # PD09
+ mww 0xF4040348 0xC
+ # PD08
+ mww 0xF4040340 0xC
+ # PD07
+ mww 0xF4040338 0xC
+ # PD06
+ mww 0xF4040330 0xC
+ # PD05
+ mww 0xF4040328 0xC
+ # PD04
+ mww 0xF4040320 0xC
+ # PD03
+ mww 0xF4040318 0xC
+ # PD02
+ mww 0xF4040310 0xC
+ # PD01
+ mww 0xF4040308 0xC
+ # PD00
+ mww 0xF4040300 0xC
+ # PC29
+ mww 0xF40402E8 0xC
+ # PC28
+ mww 0xF40402E0 0xC
+ # PC27
+ mww 0xF40402D8 0xC
+
+ # PC22
+ mww 0xF40402B0 0xC
+ # PC21
+ mww 0xF40402A8 0xC
+ # PC17
+ mww 0xF4040288 0xC
+ # PC15
+ mww 0xF4040278 0xC
+ # PC12
+ mww 0xF4040260 0xC
+ # PC11
+ mww 0xF4040258 0xC
+ # PC10
+ mww 0xF4040250 0xC
+ # PC09
+ mww 0xF4040248 0xC
+ # PC08
+ mww 0xF4040240 0xC
+ # PC07
+ mww 0xF4040238 0xC
+ # PC06
+ mww 0xF4040230 0xC
+ # PC05
+ mww 0xF4040228 0xC
+ # PC04
+ mww 0xF4040220 0xC
+
+ # PC14
+ mww 0xF4040270 0xC
+ # PC13
+ mww 0xF4040268 0xC
+ # PC16
+ #mww 0xF4040280 0x1000C
+ # PC26
+ mww 0xF40402D0 0xC
+ # PC25
+ mww 0xF40402C8 0xC
+ # PC19
+ mww 0xF4040298 0xC
+ # PC18
+ mww 0xF4040290 0xC
+ # PC23
+ mww 0xF40402B8 0xC
+ # PC24
+ mww 0xF40402C0 0xC
+ # PC30
+ mww 0xF40402F0 0xC
+ # PC31
+ mww 0xF40402F8 0xC
+ # PC02
+ mww 0xF4040210 0xC
+ # PC03
+ mww 0xF4040218 0xC
+
+ # femc configuration
+ mww 0xF3050000 0x1
+ sleep 10
+ mww 0xF3050000 0x2
+ mww 0xF3050008 0x30524
+ mww 0xF305000C 0x6030524
+ mww 0xF3050000 0x10000000
+ mww 0xF3050010 0x4000001b
+ mww 0xF3050014 0
+ mww 0xF3050040 0xf32
+
+ # 133Mhz configuration
+ #mww 0xF3050044 0x884e22
+ # 166Mhz configuration
+ mww 0xF3050044 0x884e33
+ mww 0xF3050048 0x1020d0d
+ mww 0xF3050048 0x1020d0d
+ mww 0xF305004C 0x2020300
+
+ # config delay cell
+ mww 0xF3050150 0x3b
+ mww 0xF3050150 0x203b
+ mww 0xF3050094 0
+ mww 0xF3050098 0
+
+ # precharge all
+ mww 0xF3050090 0x40000000
+ mww 0xF305009C 0xA55A000F
+ sleep 500
+ mww 0xF305003C 0x3
+ # auto refresh
+ mww 0xF305009C 0xA55A000C
+ sleep 500
+ mww 0xF305003C 0x3
+ mww 0xF305009C 0xA55A000C
+ sleep 500
+ mww 0xF305003C 0x3
+
+ # set mode
+ mww 0xF30500A0 0x33
+ mww 0xF305009C 0xA55A000A
+ sleep 500
+ mww 0xF305003C 0x3
+ mww 0xF305004C 0x2020301
+ echo "SDRAM has been initialized"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+ init_sdram
+}
diff --git a/tcl/board/hpmicro/hpm6750evkmini.cfg b/tcl/board/hpmicro/hpm6750evkmini.cfg
new file mode 100644
index 000000000..37b1ef83e
--- /dev/null
+++ b/tcl/board/hpmicro/hpm6750evkmini.cfg
@@ -0,0 +1,210 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2021 HPMicro
+
+adapter speed 10000
+source [find interface/hpmicro/hpmicro_evk.cfg]
+source [find target/hpmicro/hpm6750-single-core.cfg]
+# openocd flash driver argument:
+# - ARG7:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+# [15:8] Dummy cycles
+# 0 - Auto-probed / detected / default value
+# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+# [7:4] Misc.
+# 0 - Not used
+# 1 - SPI mode
+# 2 - Internal loopback
+# 3 - External DQS
+# [3:0] Frequency option
+# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+# - ARG8:
+# [31:20] Reserved
+# [19:16] IO voltage
+# 0 - 3V / 1 - 1.8V
+# [15:12] Pin group
+# 0 - 1st group / 1 - 2nd group
+# [11:8] Connection selection
+# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+# [7:0] Drive Strength
+# 0 - Default value
+
+# xpi0 configs
+# - flash driver: hpm_xpi
+# - flash ctrl index: 0xF3040000
+# - base address: 0x80000000
+# - flash size: 0x1000000
+# - flash option0: 0x7
+flash bank xpi0 hpm_xpi 0x80000000 0x1000000 1 1 $_TARGET0 0xF3040000 0x7
+
+proc init_clock {} {
+ mww 0xF4000800 0xFFFFFFFF
+ mww 0xF4000810 0xFFFFFFFF
+ mww 0xF4000820 0xFFFFFFFF
+ mww 0xF4000830 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+proc init_sdram { } {
+# configure femc frequency
+# 133Mhz pll1_clk0: 266Mhz divide by 2
+ #mww 0xF4001820 0x201
+# 166Mhz pll2_clk0: 333Mhz divide by 2
+ mww 0xF4001820 0x401
+
+ # PD13
+ mww 0xF4040368 0xC
+ # PD12
+ mww 0xF4040360 0xC
+ # PD10
+ mww 0xF4040350 0xC
+ # PD09
+ mww 0xF4040348 0xC
+ # PD08
+ mww 0xF4040340 0xC
+ # PD07
+ mww 0xF4040338 0xC
+ # PD06
+ mww 0xF4040330 0xC
+ # PD05
+ mww 0xF4040328 0xC
+ # PD04
+ mww 0xF4040320 0xC
+ # PD03
+ mww 0xF4040318 0xC
+ # PD02
+ mww 0xF4040310 0xC
+ # PD01
+ mww 0xF4040308 0xC
+ # PD00
+ mww 0xF4040300 0xC
+ # PC29
+ mww 0xF40402E8 0xC
+ # PC28
+ mww 0xF40402E0 0xC
+ # PC27
+ mww 0xF40402D8 0xC
+
+ # PC22
+ mww 0xF40402B0 0xC
+ # PC21
+ mww 0xF40402A8 0xC
+ # PC17
+ mww 0xF4040288 0xC
+ # PC15
+ mww 0xF4040278 0xC
+ # PC12
+ mww 0xF4040260 0xC
+ # PC11
+ mww 0xF4040258 0xC
+ # PC10
+ mww 0xF4040250 0xC
+ # PC09
+ mww 0xF4040248 0xC
+ # PC08
+ mww 0xF4040240 0xC
+ # PC07
+ mww 0xF4040238 0xC
+ # PC06
+ mww 0xF4040230 0xC
+ # PC05
+ mww 0xF4040228 0xC
+ # PC04
+ mww 0xF4040220 0xC
+
+ # PC14
+ mww 0xF4040270 0xC
+ # PC13
+ mww 0xF4040268 0xC
+ # PC16
+ #mww 0xF4040280 0x1000C
+ # PC26
+ mww 0xF40402D0 0xC
+ # PC25
+ mww 0xF40402C8 0xC
+ # PC19
+ mww 0xF4040298 0xC
+ # PC18
+ mww 0xF4040290 0xC
+ # PC23
+ mww 0xF40402B8 0xC
+ # PC24
+ mww 0xF40402C0 0xC
+ # PC30
+ mww 0xF40402F0 0xC
+ # PC31
+ mww 0xF40402F8 0xC
+ # PC02
+ mww 0xF4040210 0xC
+ # PC03
+ mww 0xF4040218 0xC
+
+ # femc configuration
+ mww 0xF3050000 0x1
+ sleep 10
+ mww 0xF3050000 0x2
+ mww 0xF3050008 0x30524
+ mww 0xF305000C 0x6030524
+ mww 0xF3050000 0x10000000
+
+ # 16MB
+ mww 0xF3050010 0x40000019
+ mww 0xF3050014 0
+ # 16-bit
+ mww 0xF3050040 0xf31
+
+ # 133Mhz configuration
+ #mww 0xF3050044 0x884e22
+ # 166Mhz configuration
+ mww 0xF3050044 0x884e33
+ mww 0xF3050048 0x1020d0d
+ mww 0xF3050048 0x1020d0d
+ mww 0xF305004C 0x2020300
+
+ # config delay cell
+ mww 0xF3050150 0x3b
+ mww 0xF3050150 0x203b
+ mww 0xF3050094 0
+ mww 0xF3050098 0
+
+ # precharge all
+ mww 0xF3050090 0x40000000
+ mww 0xF305009C 0xA55A000F
+ sleep 500
+ mww 0xF305003C 0x3
+ # auto refresh
+ mww 0xF305009C 0xA55A000C
+ sleep 500
+ mww 0xF305003C 0x3
+ mww 0xF305009C 0xA55A000C
+ sleep 500
+ mww 0xF305003C 0x3
+
+ # set mode
+ mww 0xF30500A0 0x33
+ mww 0xF305009C 0xA55A000A
+ sleep 500
+ mww 0xF305003C 0x3
+ mww 0xF305004C 0x2020301
+ echo "SDRAM has been initialized"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+ init_sdram
+}
diff --git a/tcl/board/hpmicro/hpm6800evk.cfg b/tcl/board/hpmicro/hpm6800evk.cfg
new file mode 100644
index 000000000..86b674f77
--- /dev/null
+++ b/tcl/board/hpmicro/hpm6800evk.cfg
@@ -0,0 +1,157 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2023 HPMicro
+
+adapter speed 10000
+source [find interface/hpmicro/hpmicro_evk.cfg]
+source [find target/hpmicro/hpm6880.cfg]
+# openocd flash driver argument:
+# - option0:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+# [15:8] Dummy cycles
+# 0 - Auto-probed / detected / default value
+# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+# [7:4] Misc.
+# 0 - Not used
+# 1 - SPI mode
+# 2 - Internal loopback
+# 3 - External DQS
+# [3:0] Frequency option
+# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+# - option1:
+# [31:20] Reserved
+# [19:16] IO voltage
+# 0 - 3V / 1 - 1.8V
+# [15:12] Pin group
+# 0 - 1st group / 1 - 2nd group
+# [11:8] Connection selection
+# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+# [7:0] Drive Strength
+# 0 - Default value
+
+# xpi0 configs
+# - flash driver: hpm_xpi
+# - flash ctrl index: 0xF3000000
+# - base address: 0x80000000
+# - flash size: 0x2000000
+# - flash option0: 0x7
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3000000 0x7
+
+proc init_clock {} {
+ mww 0xF4000800 0xFFFFFFFF
+ mww 0xF4000810 0xFFFFFFFF
+ mww 0xF4000820 0xFFFFFFFF
+ mww 0xF4000830 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+proc init_ddr3 {} {
+# ddr dcdc setup
+ mww 0xF4104080 0x10578
+
+# ddr3 setup
+ mww 0xF40C0180 0x30000019
+ mww 0xF400180C 0x09100401
+ mww 0xF4153000 0xF0000010
+ mww 0xF30101B0 0
+ mww 0xF4150040 0xf004641f
+ mww 0xF4153000 0xf0000011
+ mww 0xF3013000 0xf4000000
+ mww 0xF3010490 1
+ mww 0xF3010000 0x1040001
+ mww 0xF30100D0 0x4002004e
+ mww 0xF3010110 0x05010407
+ mww 0xF3010190 0x07040102
+ mww 0xF3010194 0x20404
+ mww 0xF30101A4 0x20008
+ mww 0xF3010240 0x06000600
+ mww 0xF3010200 0x1F1F1F
+ mww 0xF3010204 0x121212
+ mww 0xF3010208 0
+ mww 0xF301020C 0
+ mww 0xF3010210 0x1F1F
+ mww 0xF3010214 0x06030303
+ mww 0xF3010218 0x0F060606
+ mww 0xF3013000 0xFC000000
+ mww 0xF4150054 0xc70
+ mww 0xF4150058 0x6
+ mww 0xF415005c 0x18
+ mww 0xF4150048 0x919c8866
+ mww 0xF415004c 0x1a838360
+ mww 0xF415008c 0xf06d50
+ mww 0xF4150050 0x3002d200
+ mww 0xF30101b0 1
+ sleep 100
+ mww 0xF4150068 0x930035C7
+ mww 0xF4150004 0xFF81
+ sleep 200
+ echo "ddr3 has been enabled!"
+}
+
+proc init_dram {} {
+# ddr dcdc setup
+ mww 0xF4104080 0x10708
+
+# pll1 setup
+ mww 0xF40c0180 0xb0000016
+ mww 0xF40c0184 0
+ mww 0xF40c0188 0xe4e1c00
+
+#ddr setup
+ mww 0xF3010000 0x3040000
+ mww 0xF30101B0 0
+ mww 0xF4150044 0x40a
+ mww 0xF4150040 0xf004641f
+ mww 0xF4153000 0xf0000011
+ mww 0xF3013000 0xf4000000
+ mww 0xF3010490 1
+ mww 0xF3010000 0x1040000
+ mww 0xF3010190 0x07010101
+ mww 0xF3010194 0x20404
+ mww 0xF30101A4 0x20008
+ mww 0xF3010240 0x6000600
+ mww 0xF3010200 0x1f1f1f
+ mww 0xF3010204 0x70707
+ mww 0xF3010208 0
+ mww 0xF301020c 0
+ mww 0xF3010210 0x1f1f
+ mww 0xF3010214 0x6060606
+ mww 0xF3010218 0xf0f0606
+ mww 0xF3013000 0xfc000000
+ mww 0xF4150020 0x3000100
+ mww 0xF4150028 0x18002356
+ mww 0xF415002c 0x0aac4156
+ mww 0xF4150054 0xe73
+ mww 0xF4150058 0x5
+ mww 0xF415005c 0
+ mww 0xF4150048 0xf2adfe53
+ mww 0xF415004c 0x22820362
+ mww 0xF4150050 0x30020100
+ mww 0xF415008c 0xf06d50
+ mww 0xF30101b0 1
+ sleep 100
+ mww 0xF4150068 0x91003587
+ mww 0xF4150004 0xF501
+ sleep 200
+ echo "ddr has been enabled!"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+ init_ddr3
+}
diff --git a/tcl/board/hpmicro/hpm6e00evk.cfg b/tcl/board/hpmicro/hpm6e00evk.cfg
new file mode 100644
index 000000000..982db1d3c
--- /dev/null
+++ b/tcl/board/hpmicro/hpm6e00evk.cfg
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2024 HPMicro
+
+adapter speed 10000
+source [find interface/hpmicro/hpmicro_evk.cfg]
+source [find target/hpmicro/hpm6e80-single-core.cfg]
+# openocd flash driver argument:
+# - option0:
+# [31:28] Flash probe type
+# 0 - SFDP SDR / 1 - SFDP DDR
+# 2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+# 4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+# 6 - OctaBus DDR (SPI -> OPI DDR)
+# 8 - Xccela DDR (SPI -> OPI DDR)
+# 10 - EcoXiP DDR (SPI -> OPI DDR)
+# [27:24] Command Pads after Power-on Reset
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [23:20] Command Pads after Configuring FLASH
+# 0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+# [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+# 0 - Not needed
+# 1 - QE bit is at bit6 in Status Register 1
+# 2 - QE bit is at bit1 in Status Register 2
+# 3 - QE bit is at bit7 in Status Register 2
+# 4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+# [15:8] Dummy cycles
+# 0 - Auto-probed / detected / default value
+# Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+# [7:4] Misc.
+# 0 - Not used
+# 1 - SPI mode
+# 2 - Internal loopback
+# 3 - External DQS
+# [3:0] Frequency option
+# 1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+# - option1:
+# [31:20] Reserved
+# [19:16] IO voltage
+# 0 - 3V / 1 - 1.8V
+# [15:12] Pin group
+# 0 - 1st group / 1 - 2nd group
+# [11:8] Connection selection
+# 0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+# [7:0] Drive Strength
+# 0 - Default value
+
+# xpi0 configs
+# - flash driver: hpm_xpi
+# - flash ctrl index: 0xF3000000
+# - base address: 0x80000000
+# - flash size: 0x2000000
+# - flash option0: 0x7
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 0 0 $_TARGET0 0xF3000000 0x7
+
+proc init_clock {} {
+ mww 0xF4000800 0xFFFFFFFF
+ mww 0xF4000810 0xFFFFFFFF
+ mww 0xF4000820 0xFFFFFFFF
+ mww 0xF4000830 0xFFFFFFFF
+ echo "clocks has been enabled!"
+}
+
+$_TARGET0 configure -event reset-init {
+ init_clock
+}
diff --git a/tcl/interface/hpmicro/hpmicro_evk.cfg b/tcl/interface/hpmicro/hpmicro_evk.cfg
new file mode 100644
index 000000000..2d8e04fca
--- /dev/null
+++ b/tcl/interface/hpmicro/hpmicro_evk.cfg
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2021 HPMicro
+
+adapter driver ftdi
+ftdi_vid_pid 0x0403 0x6010
+
+ftdi_layout_init 0x0208 0x020b
+ftdi_layout_signal nTRST -data 0x0200 -noe 0x0400
+ftdi_layout_signal nSRST -data 0x0100 -noe 0x0800
diff --git a/tcl/target/hpmicro/hpm5300.cfg b/tcl/target/hpmicro/hpm5300.cfg
new file mode 100644
index 000000000..310c788bd
--- /dev/null
+++ b/tcl/target/hpmicro/hpm5300.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2021 HPMicro
+#
+# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251126/HPM5300DSV012.pdf
+
+if { [info exists CHIPNAME] } {
+ set _CHIP $CHIPNAME
+} else {
+ set _CHIP hpm5361
+}
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common.cfg]
+source [find target/hpmicro/hpm_common_csr_lite.cfg]
+
+proc reset_soc {} {
+ sba_write_mem 0xF410001C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6280-dual-core.cfg b/tcl/target/hpmicro/hpm6280-dual-core.cfg
new file mode 100644
index 000000000..a8cc33f5f
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6280-dual-core.cfg
@@ -0,0 +1,43 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2021 HPMicro
+#
+# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM6200DSV26.pdf
+
+if { [info exists CHIPNAME] } {
+ set _CHIP $CHIPNAME
+} else {
+ set _CHIP hpm6280
+}
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common.cfg]
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc release_core1 {} {
+ sba_write_mem 0xF4002C00 0x1000
+}
+
+set _TARGET1 $_CHIP.cpu1
+target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+$_TARGET1 configure -event examine-start {
+ release_core1
+}
+
+$_TARGET1 configure -event reset-deassert-pre {
+ $::_TARGET0 arp_poll
+ release_core1
+}
+
+proc reset_soc {} {
+ sba_write_mem 0xF40C001C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6280-single-core.cfg b/tcl/target/hpmicro/hpm6280-single-core.cfg
new file mode 100644
index 000000000..0e12c03af
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6280-single-core.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2021 HPMicro
+#
+# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM6200DSV26.pdf
+
+if { [info exists CHIPNAME] } {
+ set _CHIP $CHIPNAME
+} else {
+ set _CHIP hpm6280
+}
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common.cfg]
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc reset_soc {} {
+ sba_write_mem 0xF40C001C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6360.cfg b/tcl/target/hpmicro/hpm6360.cfg
new file mode 100644
index 000000000..abb6d9dbb
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6360.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2021 HPMicro
+#
+# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM6300DSV28-779.pdf:w
+
+if { [info exists CHIPNAME] } {
+ set _CHIP $CHIPNAME
+} else {
+ set _CHIP hpm6360
+}
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common.cfg]
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc reset_soc {} {
+ sba_write_mem 0xF40C001C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6750-dual-core.cfg b/tcl/target/hpmicro/hpm6750-dual-core.cfg
new file mode 100644
index 000000000..6beae150d
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6750-dual-core.cfg
@@ -0,0 +1,55 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2021 HPMicro
+#
+# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM67006400DSV27.pdf
+
+if { [info exists CHIPNAME] } {
+ set _CHIP $CHIPNAME
+} else {
+ set _CHIP hpm6750
+}
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common.cfg]
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc release_core1 {} {
+ set chip_rev [sba_read_mem 0x2001FF00]
+ if {$chip_rev != 0x56010100 } {
+ # set start point for core1
+ sba_write_mem 0xF4002C08 0x20016284
+ } else {
+ sba_write_mem 0xF4002C08 0x2001660c
+ }
+
+ # set boot flag for core1
+ sba_write_mem 0xF4002C0C 0xC1BEF1A9
+
+ # release core1
+ sba_write_mem 0xF4002C00 0x1000
+}
+
+set _TARGET1 $_CHIP.cpu1
+target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+$_TARGET1 configure -event examine-start {
+ release_core1
+}
+
+$_TARGET1 configure -event reset-deassert-pre {
+ $::_TARGET0 arp_poll
+ release_core1
+}
+
+proc reset_soc {} {
+ sba_write_mem 0xF40C001C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6750-single-core.cfg b/tcl/target/hpmicro/hpm6750-single-core.cfg
new file mode 100644
index 000000000..2566c8415
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6750-single-core.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2021 HPMicro
+#
+# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM67006400DSV27.pdf
+
+if { [info exists CHIPNAME] } {
+ set _CHIP $CHIPNAME
+} else {
+ set _CHIP hpm6750
+}
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common.cfg]
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc reset_soc {} {
+ sba_write_mem 0xF40C001C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6880.cfg b/tcl/target/hpmicro/hpm6880.cfg
new file mode 100644
index 000000000..591388f92
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6880.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2023 HPMicro
+#
+# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251128/HPM6800DSV12.pdf
+
+if { [info exists CHIPNAME] } {
+ set _CHIP $CHIPNAME
+} else {
+ set _CHIP hpm6880
+}
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common.cfg]
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc reset_soc {} {
+ sba_write_mem 0xF410001C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6e80-dual-core.cfg b/tcl/target/hpmicro/hpm6e80-dual-core.cfg
new file mode 100644
index 000000000..759cfd06a
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6e80-dual-core.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2024 HPMicro
+#
+# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM6E00DSV011.pdf
+
+if { [info exists CHIPNAME] } {
+ set _CHIP $CHIPNAME
+} else {
+ set _CHIP hpm6e00
+}
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common.cfg]
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc release_core1 {} {
+ sba_write_mem 0xF4002C00 0x1000
+}
+
+set _TARGET1 $_CHIP.cpu1
+target create $_TARGET1 riscv -chain-position $_CHIP.cpu -coreid 1
+$_TARGET1 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+$_TARGET1 configure -event examine-start {
+ release_core1
+}
+
+$_TARGET1 configure -event reset-deassert-pre {
+ $::_TARGET0 arp_poll
+ release_core1
+}
+
+$_TARGET0 configure -event reset-end {
+ sba_write_mem 0xF4002010 0x2
+}
+
+proc reset_soc {} {
+ sba_write_mem 0xF410001C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm6e80-single-core.cfg b/tcl/target/hpmicro/hpm6e80-single-core.cfg
new file mode 100644
index 000000000..7d62070fc
--- /dev/null
+++ b/tcl/target/hpmicro/hpm6e80-single-core.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2024 HPMicro
+#
+# datasheet: https://www.hpmicro.com/Public/Uploads/uploadfile/files/20251124/HPM6E00DSV011.pdf
+
+if { [info exists CHIPNAME] } {
+ set _CHIP $CHIPNAME
+} else {
+ set _CHIP hpm6e00
+}
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -chain-position $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common.cfg]
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc reset_soc {} {
+ sba_write_mem 0xF410001C 24000000
+}
diff --git a/tcl/target/hpmicro/hpm_common.cfg b/tcl/target/hpmicro/hpm_common.cfg
new file mode 100644
index 000000000..5f627cf65
--- /dev/null
+++ b/tcl/target/hpmicro/hpm_common.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2025 HPMicro
+
+source [find target/hpmicro/hpm_reset.cfg]
+
+set dmsbcs 0x38
+set dmsbaddress0 0x39
+set dmsbdata0 0x3C
+
+proc target0_dmi_write_reg {reg value} {
+ $::_TARGET0 riscv dmi_write ${reg} ${value}
+}
+
+proc target0_dmi_read_reg {reg} {
+ set v [$::_TARGET0 riscv dmi_read ${reg} $::dmsbdata0]
+ return ${v}
+}
+proc sba_write_mem {addr value} {
+ target0_dmi_write_reg $::dmsbaddress0 ${addr}
+ target0_dmi_write_reg $::dmsbdata0 ${value}
+}
+
+proc sba_read_mem {addr} {
+ set sbcs [expr { 0x100000 | [target0_dmi_read_reg $::dmsbcs] }]
+ target0_dmi_write_reg $::dmsbcs ${sbcs}
+ target0_dmi_write_reg $::dmsbaddress0 ${addr}
+ set value [target0_dmi_read_reg $::dmsbdata0]
+ return ${value}
+}
diff --git a/tcl/target/hpmicro/hpm_common_csr.cfg b/tcl/target/hpmicro/hpm_common_csr.cfg
new file mode 100644
index 000000000..5cf02305c
--- /dev/null
+++ b/tcl/target/hpmicro/hpm_common_csr.cfg
@@ -0,0 +1,104 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2024 HPMicro
+
+# expose non-standard csr registers
+# scounteren
+riscv expose_csrs 262
+# mcountinhibit
+riscv expose_csrs 800
+# milmb
+riscv expose_csrs 1984
+# mdlmb
+riscv expose_csrs 1985
+# mecc_code
+riscv expose_csrs 1986
+# mnvec
+riscv expose_csrs 1987
+# mxstatus
+riscv expose_csrs 1988
+# mpft_ctl
+riscv expose_csrs 1989
+# mhsp_ctl
+riscv expose_csrs 1990
+# msp_bound
+riscv expose_csrs 1991
+# msp_base
+riscv expose_csrs 1992
+# mdcause
+riscv expose_csrs 1993
+# mcache_ctl
+riscv expose_csrs 1994
+# mcctlbeginaddr
+riscv expose_csrs 1995
+# mcctlcommand
+riscv expose_csrs 1996
+# mcctldata
+riscv expose_csrs 1997
+# mcounterwen
+riscv expose_csrs 1998
+# mcounterinten
+riscv expose_csrs 1999
+# mmisc_ctl
+riscv expose_csrs 2000
+# mcountermask_m
+riscv expose_csrs 2001
+# mcountermask_s
+riscv expose_csrs 2002
+# mcountermask_u
+riscv expose_csrs 2003
+# mcounterovf
+riscv expose_csrs 2004
+# mslideleg
+riscv expose_csrs 2005
+# mclk_ctl
+riscv expose_csrs 2015
+# dexc2dbg
+riscv expose_csrs 2016
+# ddcause
+riscv expose_csrs 2017
+# uitb
+riscv expose_csrs 2048
+# ucode
+riscv expose_csrs 2049
+# udcause
+riscv expose_csrs 2057
+# ucctlbeginaddr
+riscv expose_csrs 2059
+# ucctlcommand
+riscv expose_csrs 2060
+# slie
+riscv expose_csrs 2500
+# slip
+riscv expose_csrs 2501
+# sdcause
+riscv expose_csrs 2505
+# scctldata
+riscv expose_csrs 2509
+# scounterinten
+riscv expose_csrs 2511
+# scountermask_m
+riscv expose_csrs 2513
+# scountermask_s
+riscv expose_csrs 2514
+# scountermask_u
+riscv expose_csrs 2515
+# scounterovf
+riscv expose_csrs 2516
+# scountinhibit
+riscv expose_csrs 2528
+# shpmevent3
+riscv expose_csrs 2531
+# shpmevent4
+riscv expose_csrs 2532
+# shpmevent5
+riscv expose_csrs 2533
+# shpmevent6
+riscv expose_csrs 2534
+# micm_cfg
+riscv expose_csrs 4032
+# mdcm_cfg
+riscv expose_csrs 4033
+# mmsc_cfg
+riscv expose_csrs 4034
+# mmsc_cfg2
+riscv expose_csrs 4035
diff --git a/tcl/target/hpmicro/hpm_common_csr_lite.cfg b/tcl/target/hpmicro/hpm_common_csr_lite.cfg
new file mode 100644
index 000000000..c0921f8f6
--- /dev/null
+++ b/tcl/target/hpmicro/hpm_common_csr_lite.cfg
@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2024 HPMicro
+
+# expose non-standard csr registers
+# mcountinhibit
+riscv expose_csrs 800
+# milmb
+riscv expose_csrs 1984
+# mdlmb
+riscv expose_csrs 1985
+# mecc_code
+riscv expose_csrs 1986
+# mnvec
+riscv expose_csrs 1987
+# mxstatus
+riscv expose_csrs 1988
+# mpft_ctl
+riscv expose_csrs 1989
+# mhsp_ctl
+riscv expose_csrs 1990
+# msp_bound
+riscv expose_csrs 1991
+# msp_base
+riscv expose_csrs 1992
+# mdcause
+riscv expose_csrs 1993
+# mcache_ctl
+riscv expose_csrs 1994
+# mcctlbeginaddr
+riscv expose_csrs 1995
+# mcctlcommand
+riscv expose_csrs 1996
+# mcctldata
+riscv expose_csrs 1997
+# mcounterwen
+riscv expose_csrs 1998
+# mcounterinten
+riscv expose_csrs 1999
+# mmisc_ctl
+riscv expose_csrs 2000
+# mcountermask_m
+riscv expose_csrs 2001
+# mcountermask_s
+riscv expose_csrs 2002
+# mcountermask_u
+riscv expose_csrs 2003
+# mcounterovf
+riscv expose_csrs 2004
+# dexc2dbg
+riscv expose_csrs 2016
+# ddcause
+riscv expose_csrs 2017
+# uitb
+riscv expose_csrs 2048
+# ucode
+riscv expose_csrs 2049
+# udcause
+riscv expose_csrs 2057
+# ucctlbeginaddr
+riscv expose_csrs 2059
+# ucctlcommand
+riscv expose_csrs 2060
+# micm_cfg
+riscv expose_csrs 4032
+# mdcm_cfg
+riscv expose_csrs 4033
+# mmsc_cfg
+riscv expose_csrs 4034
+# mmsc_cfg2
+riscv expose_csrs 4035
diff --git a/tcl/target/hpmicro/hpm_reset.cfg b/tcl/target/hpmicro/hpm_reset.cfg
new file mode 100644
index 000000000..0a0106a98
--- /dev/null
+++ b/tcl/target/hpmicro/hpm_reset.cfg
@@ -0,0 +1,13 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2025 HPMicro
+
+# As debug access needs to be released by bootrom after reset,
+# and halt request set along with reset will be ignored, it needs
+# a short period of time for bootrom to release the access,
+# so we request halt again in reset-deassert-pre event.
+$_TARGET0 configure -event reset-deassert-pre {
+ sleep 1
+ if {$halt} {
+ $::_TARGET0 arp_halt
+ }
+}
-----------------------------------------------------------------------
Summary of changes:
tcl/board/hpmicro/hpm5300evk.cfg | 66 ++++++++
tcl/board/hpmicro/hpm5301evklite.cfg | 66 ++++++++
tcl/board/hpmicro/hpm6200evk.cfg | 64 ++++++++
tcl/board/hpmicro/hpm6300evk.cfg | 217 ++++++++++++++++++++++++++
tcl/board/hpmicro/hpm6750evk.cfg | 239 +++++++++++++++++++++++++++++
tcl/board/hpmicro/hpm6750evk2.cfg | 239 +++++++++++++++++++++++++++++
tcl/board/hpmicro/hpm6750evkmini.cfg | 210 +++++++++++++++++++++++++
tcl/board/hpmicro/hpm6800evk.cfg | 157 +++++++++++++++++++
tcl/board/hpmicro/hpm6e00evk.cfg | 65 ++++++++
tcl/interface/hpmicro/hpmicro_evk.cfg | 9 ++
tcl/target/hpmicro/hpm5300.cfg | 24 +++
tcl/target/hpmicro/hpm6280-dual-core.cfg | 43 ++++++
tcl/target/hpmicro/hpm6280-single-core.cfg | 24 +++
tcl/target/hpmicro/hpm6360.cfg | 24 +++
tcl/target/hpmicro/hpm6750-dual-core.cfg | 55 +++++++
tcl/target/hpmicro/hpm6750-single-core.cfg | 24 +++
tcl/target/hpmicro/hpm6880.cfg | 24 +++
tcl/target/hpmicro/hpm6e80-dual-core.cfg | 47 ++++++
tcl/target/hpmicro/hpm6e80-single-core.cfg | 24 +++
tcl/target/hpmicro/hpm_common.cfg | 29 ++++
tcl/target/hpmicro/hpm_common_csr.cfg | 104 +++++++++++++
tcl/target/hpmicro/hpm_common_csr_lite.cfg | 70 +++++++++
tcl/target/hpmicro/hpm_reset.cfg | 13 ++
23 files changed, 1837 insertions(+)
create mode 100644 tcl/board/hpmicro/hpm5300evk.cfg
create mode 100644 tcl/board/hpmicro/hpm5301evklite.cfg
create mode 100644 tcl/board/hpmicro/hpm6200evk.cfg
create mode 100644 tcl/board/hpmicro/hpm6300evk.cfg
create mode 100644 tcl/board/hpmicro/hpm6750evk.cfg
create mode 100644 tcl/board/hpmicro/hpm6750evk2.cfg
create mode 100644 tcl/board/hpmicro/hpm6750evkmini.cfg
create mode 100644 tcl/board/hpmicro/hpm6800evk.cfg
create mode 100644 tcl/board/hpmicro/hpm6e00evk.cfg
create mode 100644 tcl/interface/hpmicro/hpmicro_evk.cfg
create mode 100644 tcl/target/hpmicro/hpm5300.cfg
create mode 100644 tcl/target/hpmicro/hpm6280-dual-core.cfg
create mode 100644 tcl/target/hpmicro/hpm6280-single-core.cfg
create mode 100644 tcl/target/hpmicro/hpm6360.cfg
create mode 100644 tcl/target/hpmicro/hpm6750-dual-core.cfg
create mode 100644 tcl/target/hpmicro/hpm6750-single-core.cfg
create mode 100644 tcl/target/hpmicro/hpm6880.cfg
create mode 100644 tcl/target/hpmicro/hpm6e80-dual-core.cfg
create mode 100644 tcl/target/hpmicro/hpm6e80-single-core.cfg
create mode 100644 tcl/target/hpmicro/hpm_common.cfg
create mode 100644 tcl/target/hpmicro/hpm_common_csr.cfg
create mode 100644 tcl/target/hpmicro/hpm_common_csr_lite.cfg
create mode 100644 tcl/target/hpmicro/hpm_reset.cfg
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-12-19 21:17:37
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 26507adfad37ab81953fe1d37efead956a99de21 (commit)
from 8e11797618a45a38a951e5482fc7d888edca21f5 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 26507adfad37ab81953fe1d37efead956a99de21
Author: Ryan QIAN <jia...@hp...>
Date: Tue Jan 7 15:10:08 2025 +0800
src/flash/nor: add hpmicro xpi support
- add hpmicro xpi support
Change-Id: I632558e72fa26cf1864614dd149985f09bcd9412
Signed-off-by: Ryan QIAN <jia...@hp...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8696
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index f40855900..7f8556c76 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -83,7 +83,8 @@ NOR_DRIVERS = \
%D%/w600.c \
%D%/xcf.c \
%D%/xmc1xxx.c \
- %D%/xmc4xxx.c
+ %D%/xmc4xxx.c \
+ %D%/hpm_xpi.c
NORHEADERS = \
%D%/artery.h \
diff --git a/src/flash/nor/driver.h b/src/flash/nor/driver.h
index 2bd204363..58f51d15f 100644
--- a/src/flash/nor/driver.h
+++ b/src/flash/nor/driver.h
@@ -265,6 +265,7 @@ extern const struct flash_driver faux_flash;
extern const struct flash_driver fespi_flash;
extern const struct flash_driver fm3_flash;
extern const struct flash_driver fm4_flash;
+extern const struct flash_driver hpm_xpi_flash;
extern const struct flash_driver jtagspi_flash;
extern const struct flash_driver kinetis_flash;
extern const struct flash_driver kinetis_ke_flash;
diff --git a/src/flash/nor/drivers.c b/src/flash/nor/drivers.c
index 6b0def681..3db75ab26 100644
--- a/src/flash/nor/drivers.c
+++ b/src/flash/nor/drivers.c
@@ -44,6 +44,7 @@ static const struct flash_driver * const flash_drivers[] = {
&fespi_flash,
&fm3_flash,
&fm4_flash,
+ &hpm_xpi_flash,
&jtagspi_flash,
&kinetis_flash,
&kinetis_ke_flash,
diff --git a/src/flash/nor/hpm_xpi.c b/src/flash/nor/hpm_xpi.c
new file mode 100644
index 000000000..3cb1f407a
--- /dev/null
+++ b/src/flash/nor/hpm_xpi.c
@@ -0,0 +1,523 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Copyright (c) 2025 hpmicro
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+#include "imp.h"
+#include <helper/bits.h>
+#include <helper/binarybuffer.h>
+#include <helper/time_support.h>
+#include <target/algorithm.h>
+#include <target/image.h>
+#include "target/riscv/program.h"
+
+#include "../../../contrib/loaders/flash/hpmicro/hpm_xpi_flash.h"
+static uint8_t flash_algo[] = {
+#include "../../../contrib/loaders/flash/hpmicro/hpm_xpi_flash.inc"
+};
+#define TIMEOUT_IN_MS (10000U)
+#define ERASE_CHIP_TIMEOUT_IN_MS (100000U)
+#define SECTOR_ERASE_TIMEOUT_IN_MS (100)
+#define TYPICAL_TIMEOUT_IN_MS (500U)
+#define BLOCK_SIZE (4096U)
+#define NOR_CFG_OPT_HEADER (0xFCF90000UL)
+
+struct hpm_flash_info {
+ uint32_t total_sz_in_bytes;
+ uint32_t sector_sz_in_bytes;
+};
+
+struct hpm_xpi_priv {
+ uint32_t io_base;
+ uint32_t header;
+ uint32_t opt0;
+ uint32_t opt1;
+ bool probed;
+};
+
+static int hpm_xpi_run_algo_flash_init(struct flash_bank *bank,
+ target_addr_t algo_entry)
+{
+ struct reg_param reg_params[6];
+ struct target *target = bank->target;
+ struct hpm_xpi_priv *xpi_priv = bank->driver_priv;
+
+ int xlen = riscv_xlen(target);
+ init_reg_param(®_params[0], "a0", xlen, PARAM_IN_OUT);
+ init_reg_param(®_params[1], "a1", xlen, PARAM_OUT);
+ init_reg_param(®_params[2], "a2", xlen, PARAM_OUT);
+ init_reg_param(®_params[3], "a3", xlen, PARAM_OUT);
+ init_reg_param(®_params[4], "a4", xlen, PARAM_OUT);
+ init_reg_param(®_params[5], "ra", xlen, PARAM_OUT);
+ buf_set_u64(reg_params[0].value, 0, xlen, bank->base);
+ buf_set_u64(reg_params[1].value, 0, xlen, xpi_priv->header);
+ buf_set_u64(reg_params[2].value, 0, xlen, xpi_priv->opt0);
+ buf_set_u64(reg_params[3].value, 0, xlen, xpi_priv->opt1);
+ buf_set_u64(reg_params[4].value, 0, xlen, xpi_priv->io_base);
+ buf_set_u64(reg_params[5].value, 0, xlen, algo_entry + FLASH_INIT + 4);
+ int retval = target_run_algorithm(target, 0, NULL, ARRAY_SIZE(reg_params), reg_params,
+ algo_entry, algo_entry + FLASH_INIT + 4, TYPICAL_TIMEOUT_IN_MS, NULL);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to execute run algorithm: %d", retval);
+ goto err;
+ }
+
+ uint32_t stat = buf_get_u32(reg_params[0].value, 0, xlen);
+ if (stat) {
+ retval = ERROR_TARGET_FAILURE;
+ LOG_ERROR("init flash failed on target: 0x%" PRIx32, retval);
+ goto err;
+ }
+
+err:
+ for (size_t k = 0; k < ARRAY_SIZE(reg_params); k++)
+ destroy_reg_param(®_params[k]);
+
+ return retval;
+}
+
+static int hpm_xpi_probe(struct flash_bank *bank)
+{
+ struct hpm_flash_info flash_info = {0};
+ struct working_area *data_wa = NULL;
+ struct flash_sector *sectors = NULL;
+ struct working_area *wa;
+ struct target *target = bank->target;
+
+ struct hpm_xpi_priv *xpi_priv = bank->driver_priv;
+
+ if (xpi_priv->probed) {
+ xpi_priv->probed = false;
+ bank->size = 0;
+ bank->num_sectors = 0;
+ free(bank->sectors);
+ bank->sectors = NULL;
+ }
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ int retval = target_alloc_working_area(target, sizeof(flash_algo), &wa);
+ if (retval != ERROR_OK) {
+ LOG_WARNING("Couldn't allocate %zd-byte working area",
+ sizeof(flash_algo));
+ return retval;
+ }
+
+ retval = target_write_buffer(target, wa->address,
+ sizeof(flash_algo), flash_algo);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to write code to 0x%" TARGET_PRIxADDR ": %d",
+ wa->address, retval);
+ target_free_working_area(target, wa);
+ return retval;
+ }
+
+ retval = hpm_xpi_run_algo_flash_init(bank, wa->address);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to run init flash algorithm: %d", retval);
+ return retval;
+ }
+
+ if (target_alloc_working_area(target, sizeof(flash_info),
+ &data_wa) != ERROR_OK) {
+ LOG_WARNING("Couldn't allocate %zd-byte working area",
+ sizeof(flash_info));
+ goto err;
+ }
+
+ int xlen = riscv_xlen(target);
+ struct reg_param reg_params[3];
+ init_reg_param(®_params[0], "a0", xlen, PARAM_IN_OUT);
+ init_reg_param(®_params[1], "a1", xlen, PARAM_OUT);
+ init_reg_param(®_params[2], "ra", xlen, PARAM_OUT);
+ buf_set_u64(reg_params[0].value, 0, xlen, bank->base);
+ buf_set_u64(reg_params[1].value, 0, xlen, data_wa->address);
+ buf_set_u64(reg_params[2].value, 0, xlen, wa->address + FLASH_GET_INFO + 4);
+
+ retval = target_run_algorithm(target, 0, NULL, ARRAY_SIZE(reg_params), reg_params,
+ wa->address + FLASH_GET_INFO, wa->address + FLASH_GET_INFO + 4, TYPICAL_TIMEOUT_IN_MS, NULL);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to run algorithm at: %d", retval);
+ goto err;
+ }
+
+ uint32_t stat = buf_get_u32(reg_params[0].value, 0, xlen);
+ if (stat) {
+ retval = ERROR_TARGET_FAILURE;
+ LOG_ERROR("flash get info failed on target: 0x%" PRIx32, retval);
+ goto err;
+ }
+
+ target_read_u32(target, data_wa->address, &flash_info.total_sz_in_bytes);
+ target_read_u32(target, data_wa->address + 4, &flash_info.sector_sz_in_bytes);
+
+ bank->size = flash_info.total_sz_in_bytes;
+ bank->num_sectors = flash_info.total_sz_in_bytes / flash_info.sector_sz_in_bytes;
+
+ /* create and fill sectors array */
+ sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
+ if (!sectors) {
+ LOG_ERROR("not enough memory");
+ retval = ERROR_FAIL;
+ goto err;
+ }
+
+ for (unsigned int sector = 0; sector < bank->num_sectors; sector++) {
+ sectors[sector].offset = sector * (flash_info.sector_sz_in_bytes);
+ sectors[sector].size = flash_info.sector_sz_in_bytes;
+ sectors[sector].is_erased = -1;
+ sectors[sector].is_protected = 0;
+ }
+
+ bank->sectors = sectors;
+ xpi_priv->probed = true;
+
+err:
+ for (size_t k = 0; k < ARRAY_SIZE(reg_params); k++)
+ destroy_reg_param(®_params[k]);
+ target_free_working_area(target, data_wa);
+ target_free_working_area(target, wa);
+ return retval;
+}
+
+static int hpm_xpi_auto_probe(struct flash_bank *bank)
+{
+ struct hpm_xpi_priv *xpi_priv = bank->driver_priv;
+ if (xpi_priv->probed)
+ return ERROR_OK;
+ return hpm_xpi_probe(bank);
+}
+
+static int hpm_xpi_write(struct flash_bank *bank, const uint8_t *buffer,
+ uint32_t offset, uint32_t count)
+{
+ struct working_area *data_wa = NULL;
+ struct working_area *wa = NULL;
+ uint32_t data_size = BLOCK_SIZE;
+ uint32_t left = count, i = 0;
+ struct target *target = bank->target;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ int retval = target_alloc_working_area(target, sizeof(flash_algo), &wa);
+ if (retval != ERROR_OK) {
+ LOG_WARNING("Couldn't allocate %zd-byte working area",
+ sizeof(flash_algo));
+ return retval;
+ }
+
+ retval = target_write_buffer(target, wa->address,
+ sizeof(flash_algo), flash_algo);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to write code to 0x%" TARGET_PRIxADDR ": %d",
+ wa->address, retval);
+ target_free_working_area(target, wa);
+ return retval;
+ }
+
+ retval = hpm_xpi_run_algo_flash_init(bank, wa->address);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to run init flash algorithm: %d", retval);
+ return retval;
+ }
+
+ /* memory buffer */
+ uint32_t avail_buffer_size;
+ avail_buffer_size = target_get_working_area_avail(target);
+ if (avail_buffer_size <= 256) {
+ /* we already allocated the writing code, but failed to get a
+ * buffer, free the algorithm */
+ target_free_working_area(target, wa);
+ LOG_WARNING("no large enough working area available, can't do block memory writes");
+ return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
+ }
+
+ data_size = MIN(data_size, avail_buffer_size);
+ retval = target_alloc_working_area(target, data_size, &data_wa);
+ if (retval != ERROR_OK) {
+ LOG_WARNING("Couldn't allocate %d-byte working area", data_size);
+ return retval;
+ }
+
+ int xlen = riscv_xlen(target);
+ struct reg_param reg_params[4];
+ init_reg_param(®_params[0], "a0", xlen, PARAM_IN_OUT);
+ init_reg_param(®_params[1], "a1", xlen, PARAM_OUT);
+ init_reg_param(®_params[2], "a2", xlen, PARAM_OUT);
+ init_reg_param(®_params[3], "a3", xlen, PARAM_OUT);
+
+ while (left) {
+ uint32_t trans_size = MIN(data_size, left);
+ retval = target_write_buffer(target, data_wa->address, trans_size, buffer + i * data_size);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to write buffer to 0x%" TARGET_PRIxADDR ": %d", data_wa->address, retval);
+ goto err;
+ }
+
+ buf_set_u32(reg_params[0].value, 0, xlen, bank->base);
+ buf_set_u32(reg_params[1].value, 0, xlen, offset + i * data_size);
+ buf_set_u32(reg_params[2].value, 0, xlen, data_wa->address);
+ buf_set_u32(reg_params[3].value, 0, xlen, trans_size);
+
+ retval = target_run_algorithm(target, 0, NULL, 4, reg_params,
+ wa->address + FLASH_PROGRAM, wa->address + FLASH_PROGRAM + 4, TIMEOUT_IN_MS, NULL);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to execute algorithm at 0x%" TARGET_PRIxADDR ": %d", wa->address, retval);
+ goto err;
+ }
+
+ uint32_t stat = buf_get_u32(reg_params[0].value, 0, xlen);
+ if (stat) {
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ LOG_ERROR("flash write failed on target: 0x%" PRIx32, retval);
+ goto err;
+ }
+ i++;
+ left -= trans_size;
+ }
+
+err:
+ if (data_wa)
+ target_free_working_area(target, data_wa);
+
+ for (size_t k = 0; k < ARRAY_SIZE(reg_params); k++)
+ destroy_reg_param(®_params[k]);
+
+ target_free_working_area(target, wa);
+ return retval;
+}
+
+static int hpm_xpi_erase(struct flash_bank *bank, unsigned int first, unsigned int last)
+{
+ struct target *target = bank->target;
+ struct working_area *wa = NULL;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ int retval = target_alloc_working_area(target, sizeof(flash_algo), &wa);
+ if (retval != ERROR_OK) {
+ LOG_WARNING("Couldn't allocate %zd-byte working area",
+ sizeof(flash_algo));
+ return retval;
+ }
+
+ retval = target_write_buffer(target, wa->address,
+ sizeof(flash_algo), flash_algo);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to write code to 0x%" TARGET_PRIxADDR ": %d",
+ wa->address, retval);
+ target_free_working_area(target, wa);
+ return retval;
+ }
+
+ retval = hpm_xpi_run_algo_flash_init(bank, wa->address);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to run init flash algorithm: %d", retval);
+ return retval;
+ }
+
+ LOG_DEBUG("from sector %u to sector %u", first, last);
+
+ int xlen = riscv_xlen(target);
+ struct reg_param reg_params[3];
+ init_reg_param(®_params[0], "a0", xlen, PARAM_IN_OUT);
+ init_reg_param(®_params[1], "a1", xlen, PARAM_OUT);
+ init_reg_param(®_params[2], "a2", xlen, PARAM_OUT);
+
+ buf_set_u32(reg_params[0].value, 0, xlen, bank->base);
+ buf_set_u32(reg_params[1].value, 0, xlen, first * bank->sectors[0].size);
+ buf_set_u32(reg_params[2].value, 0, xlen, (last - first + 1) * bank->sectors[0].size);
+
+ retval = target_run_algorithm(target, 0, NULL, ARRAY_SIZE(reg_params), reg_params,
+ wa->address + FLASH_ERASE, wa->address + FLASH_ERASE + 4,
+ SECTOR_ERASE_TIMEOUT_IN_MS * (last - first + 1), NULL);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to execute algorithm at 0x%" TARGET_PRIxADDR ": %d", wa->address, retval);
+ goto err;
+ }
+
+ uint32_t stat = buf_get_u32(reg_params[0].value, 0, xlen);
+ if (stat) {
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ LOG_ERROR("flash erase failed on target: 0x%" PRIx32, retval);
+ goto err;
+ }
+
+err:
+ target_free_working_area(target, wa);
+ for (size_t k = 0; k < ARRAY_SIZE(reg_params); k++)
+ destroy_reg_param(®_params[k]);
+ return retval;
+}
+
+static int hpm_xpi_erase_chip(struct flash_bank *bank)
+{
+ struct target *target = bank->target;
+ struct working_area *wa = NULL;
+
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ int retval = target_alloc_working_area(target, sizeof(flash_algo), &wa);
+ if (retval != ERROR_OK) {
+ LOG_WARNING("Couldn't allocate %zd-byte working area",
+ sizeof(flash_algo));
+ return retval;
+ }
+
+ retval = target_write_buffer(target, wa->address,
+ sizeof(flash_algo), flash_algo);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to write code to 0x%" TARGET_PRIxADDR ": %d",
+ wa->address, retval);
+ target_free_working_area(target, wa);
+ return retval;
+ }
+
+ retval = hpm_xpi_run_algo_flash_init(bank, wa->address);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to run init flash algorithm: %d", retval);
+ return retval;
+ }
+
+ int xlen = riscv_xlen(target);
+ struct reg_param reg_params[1];
+ init_reg_param(®_params[0], "a0", xlen, PARAM_IN_OUT);
+ buf_set_u64(reg_params[0].value, 0, xlen, bank->base);
+
+ retval = target_run_algorithm(target, 0, NULL, ARRAY_SIZE(reg_params), reg_params,
+ wa->address + FLASH_ERASE_CHIP, wa->address + FLASH_ERASE_CHIP + 4, ERASE_CHIP_TIMEOUT_IN_MS, NULL);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Failed to execute algorithm at 0x%" TARGET_PRIxADDR ": %d", wa->address, retval);
+ goto err;
+ }
+
+ uint32_t stat = buf_get_u32(reg_params[0].value, 0, xlen);
+ if (stat) {
+ retval = ERROR_FLASH_OPERATION_FAILED;
+ LOG_ERROR("flash erase chip failed on target: 0x%" PRIx32, retval);
+ goto err;
+ }
+
+err:
+ target_free_working_area(target, wa);
+ for (size_t k = 0; k < ARRAY_SIZE(reg_params); k++)
+ destroy_reg_param(®_params[k]);
+ return retval;
+}
+
+COMMAND_HANDLER(hpm_xpi_handle_erase_chip_command)
+{
+ int retval;
+ struct flash_bank *bank;
+ struct target *target;
+ retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+ if (retval != ERROR_OK)
+ return retval;
+
+ target = bank->target;
+ if (target->state != TARGET_HALTED) {
+ LOG_ERROR("Target not halted");
+ return ERROR_TARGET_NOT_HALTED;
+ }
+
+ return hpm_xpi_erase_chip(bank);
+}
+
+static const struct command_registration hpm_xpi_exec_command_handlers[] = {
+ {
+ .name = "mass_erase",
+ .handler = hpm_xpi_handle_erase_chip_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "erase entire flash device",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+const struct command_registration hpm_xpi_command_handlers[] = {
+ {
+ .name = "hpm_xpi",
+ .mode = COMMAND_ANY,
+ .help = "hpm_xpi command group",
+ .usage = "",
+ .chain = hpm_xpi_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+FLASH_BANK_COMMAND_HANDLER(hpm_xpi_flash_bank_command)
+{
+ struct hpm_xpi_priv *xpi_priv;
+ uint32_t io_base;
+ uint32_t header;
+ uint32_t opt0;
+ uint32_t opt1;
+
+ if (CMD_ARGC < 7)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[6], io_base);
+
+ switch (CMD_ARGC) {
+ case 7:
+ header = NOR_CFG_OPT_HEADER + 1;
+ opt1 = 0;
+ opt0 = 7;
+ break;
+ case 8:
+ header = NOR_CFG_OPT_HEADER + 1;
+ opt1 = 0;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], opt0);
+ break;
+ case 9:
+ header = NOR_CFG_OPT_HEADER + 2;
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[7], opt0);
+ COMMAND_PARSE_NUMBER(u32, CMD_ARGV[8], opt1);
+ break;
+ default:
+ return ERROR_COMMAND_SYNTAX_ERROR;
+ }
+ xpi_priv = malloc(sizeof(struct hpm_xpi_priv));
+ if (!xpi_priv) {
+ LOG_ERROR("not enough memory");
+ return ERROR_FAIL;
+ }
+
+ bank->driver_priv = xpi_priv;
+ xpi_priv->io_base = io_base;
+ xpi_priv->header = header;
+ xpi_priv->opt0 = opt0;
+ xpi_priv->opt1 = opt1;
+ xpi_priv->probed = false;
+
+ return ERROR_OK;
+}
+
+const struct flash_driver hpm_xpi_flash = {
+ .name = "hpm_xpi",
+ .flash_bank_command = hpm_xpi_flash_bank_command,
+ .commands = hpm_xpi_command_handlers,
+ .erase = hpm_xpi_erase,
+ .write = hpm_xpi_write,
+ .read = default_flash_read,
+ .verify = default_flash_verify,
+ .probe = hpm_xpi_probe,
+ .auto_probe = hpm_xpi_auto_probe,
+ .erase_check = default_flash_blank_check,
+ .free_driver_priv = default_flash_free_driver_priv,
+};
-----------------------------------------------------------------------
Summary of changes:
src/flash/nor/Makefile.am | 3 +-
src/flash/nor/driver.h | 1 +
src/flash/nor/drivers.c | 1 +
src/flash/nor/hpm_xpi.c | 523 ++++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 527 insertions(+), 1 deletion(-)
create mode 100644 src/flash/nor/hpm_xpi.c
hooks/post-receive
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Main OpenOCD repository
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From: openocd-gerrit <ope...@us...> - 2025-12-19 21:17:11
|
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 8e11797618a45a38a951e5482fc7d888edca21f5
Author: Ryan QIAN <jia...@hp...>
Date: Tue Jan 7 15:09:18 2025 +0800
contrib/loaders/flash/hpmicro: add hpmicro device xpi support
- add xpi flash support for hpmicro devices
Change-Id: I3531fdf20a34561c6f3fe6ac0b9af988d483aae7
Signed-off-by: Ryan QIAN <jia...@hp...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8695
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/contrib/loaders/flash/hpmicro/Makefile b/contrib/loaders/flash/hpmicro/Makefile
new file mode 100644
index 000000000..304363171
--- /dev/null
+++ b/contrib/loaders/flash/hpmicro/Makefile
@@ -0,0 +1,51 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2023 HPMicro
+#
+BIN2C = ../../../../src/helper/bin2char.sh
+
+
+PROJECT=hpm_xpi_flash
+CROSS_COMPILE ?= riscv32-unknown-elf-
+CC=$(CROSS_COMPILE)gcc
+AS=$(CROSS_COMPILE)gcc
+OBJCOPY=$(CROSS_COMPILE)objcopy
+OBJDUMP=$(CROSS_COMPILE)objdump
+LD=$(CROSS_COMPILE)ld
+LDSCRIPT=linker.ld
+
+OPT=-O3
+
+ASFLAGS=
+CFLAGS=$(OPT) -fomit-frame-pointer -Wall
+LDFLAGS=-nostartfiles -T$(LDSCRIPT) -Wl,-Map=$(PROJECT).map -static -Wl,--gc-sections
+OBJS=$(ASRC:.S=.o) $(SRC:.c=.o)
+
+SRC=openocd_flash_algo.c
+ASRC=func_table.S
+
+all: $(OBJS) $(PROJECT).elf $(PROJECT).bin $(PROJECT).lst $(PROJECT).inc
+
+%o: %c
+ @$(CC) -c $(CFLAGS) -I . $< -o $@
+
+%o: %S
+ @$(AS) -c $(ASFLAGS) -I . $< -o $@
+
+%elf: $(OBJS)
+ @$(CC) $(OBJS) $(LDFLAGS) -o $@
+
+%lst: %elf
+ @$(OBJDUMP) -h -S $< > $@
+
+%bin: %elf
+ @$(OBJCOPY) -Obinary $< $@
+
+%inc: %bin
+ $(BIN2C) < $< > $@
+
+clean:
+ @-rm -f *.o *.elf *.lst *.bin *.inc
+
+.PHONY: all clean
+
+.INTERMEDIATE: $(patsubst %.S,%.o,$(SRCS)) $(patsubst %.S,%.elf,$(SRCS)) $(patsubst %.S,%.bin,$(SRCS))
diff --git a/contrib/loaders/flash/hpmicro/README b/contrib/loaders/flash/hpmicro/README
new file mode 100644
index 000000000..a6c047a11
--- /dev/null
+++ b/contrib/loaders/flash/hpmicro/README
@@ -0,0 +1,7 @@
+The loader relies on the romapi provided by HPMicro devices.
+
+- hpm_common.h and all the hpm_romapi_*.c/h are reused from hpm_sdk
+(v1.9.0 https://github.com/hpmicro/hpm_sdk/releases).
+
+Due to different coding rules, these source code needs to be updated
+accordingly to pass the coding rule check for openocd.
diff --git a/contrib/loaders/flash/hpmicro/func_table.S b/contrib/loaders/flash/hpmicro/func_table.S
new file mode 100644
index 000000000..d5f34265e
--- /dev/null
+++ b/contrib/loaders/flash/hpmicro/func_table.S
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 HPMicro
+ */
+ .section .func_table, "ax"
+ .global _init
+_init:
+ jal flash_init
+ ebreak
+ jal flash_erase
+ ebreak
+ jal flash_program
+ ebreak
+ jal flash_read
+ ebreak
+ jal flash_get_info
+ ebreak
+ jal flash_erase_chip
+ ebreak
+ jal flash_deinit
+ ebreak
diff --git a/contrib/loaders/flash/hpmicro/hpm_common.h b/contrib/loaders/flash/hpmicro/hpm_common.h
new file mode 100644
index 000000000..8190fbfed
--- /dev/null
+++ b/contrib/loaders/flash/hpmicro/hpm_common.h
@@ -0,0 +1,203 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ */
+
+#ifndef _HPM_COMMON_H
+#define _HPM_COMMON_H
+
+#include <assert.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdlib.h>
+
+/**
+ *
+ * @brief COMMON driver APIs
+ * @defgroup common_interface COMMON driver APIs
+ * @{
+ *
+ */
+
+#define __R volatile const /* Define "read-only" permission */
+#define __RW volatile /* Define "read-write" permission */
+#define __W volatile /* Define "write-only" permission */
+
+#ifndef __I
+#define __I __R
+#endif
+
+#ifndef __IO
+#define __IO __RW
+#endif
+
+#ifndef __O
+#define __O __W
+#endif
+
+#ifndef ARRAY_SIZE
+#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
+#endif
+
+#define HPM_BITSMASK(val, offset) ((uint32_t)(val) << (offset))
+#define IS_HPM_BITMASK_SET(val, mask) (((uint32_t)(val) & (uint32_t)(mask)) != 0U)
+#define IS_HPM_BIT_SET(val, offset) (((uint32_t)(val) & (1UL << (offset))) != 0U)
+#define IS_HPM_BITMASK_CLR(val, mask) (((uint32_t)(val) & (uint32_t)(mask)) == 0U)
+#define IS_HPM_BIT_CLR(val, offset) (((uint32_t)(val) & (1UL << (offset))) == 0U)
+
+#define HPM_BREAK_IF(cond) do {if (cond) break; } while (0)
+#define HPM_CONTINUE_IF(cond) do {if (cond) continue; } while (0)
+
+#define HPM_CHECK_RET(x) \
+ do { \
+ stat = (x); \
+ if (status_success != stat) { \
+ return stat; \
+ } \
+ } while (false)
+
+#define SIZE_1KB (1024UL)
+#define SIZE_1MB (1048576UL)
+
+typedef uint32_t hpm_stat_t;
+
+/* @brief Enum definition for the Status group
+ * Rule:
+ * [Group] 0-999 for the SoC driver and the corresponding components
+ * 1000 or above for the application status group
+ * [Code] Valid value: 0-999
+ *
+ */
+#define MAKE_STATUS(group, code) ((uint32_t)(group) * 1000U + (uint32_t)(code))
+/* @brief System status group definitions */
+enum {
+ status_group_common = 0,
+ status_group_uart = 1,
+ status_group_i2c = 2,
+ status_group_spi = 3,
+ status_group_usb = 4,
+ status_group_i2s = 5,
+ status_group_xpi = 6,
+ status_group_l1c,
+ status_group_dma,
+ status_group_femc,
+ status_group_sdp,
+ status_group_xpi_nor,
+ status_group_otp,
+ status_group_lcdc,
+ status_group_mbx,
+ status_group_rng,
+ status_group_pdma,
+ status_group_wdg,
+ status_group_pmic_sec,
+ status_group_can,
+ status_group_sdxc,
+ status_group_pcfg,
+ status_group_clk,
+ status_group_pllctl,
+ status_group_pllctlv2,
+ status_group_ffa,
+ status_group_mcan,
+
+ status_group_middleware_start = 500,
+ status_group_sdmmc = status_group_middleware_start,
+ status_group_audio_codec,
+ status_group_dma_manager,
+};
+
+/* @brief Common status code definitions */
+enum {
+ status_success = MAKE_STATUS(status_group_common, 0),
+ status_fail = MAKE_STATUS(status_group_common, 1),
+ status_invalid_argument = MAKE_STATUS(status_group_common, 2),
+ status_timeout = MAKE_STATUS(status_group_common, 3),
+};
+
+#if defined(__GNUC__)
+
+/* alway_inline */
+#define ATTR_ALWAYS_INLINE __attribute__((always_inline))
+
+/* weak */
+#define ATTR_WEAK __attribute__((weak))
+
+/* alignment */
+#define ATTR_ALIGN(alignment) __attribute__((aligned(alignment)))
+
+/* place var_declare at section_name, e.x. PLACE_AT(".target_section", var); */
+#define ATTR_PLACE_AT(section_name) __attribute__((section(section_name)))
+
+#define ATTR_PLACE_AT_WITH_ALIGNMENT(section_name, alignment) \
+ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment)
+
+#define ATTR_PLACE_AT_NONCACHEABLE ATTR_PLACE_AT(".noncacheable.bss")
+#define ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(alignment) \
+ ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment)
+
+#define ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_PLACE_AT(".noncacheable.bss")
+#define ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(alignment) \
+ ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_ALIGN(alignment)
+
+/* initialize variable x with y using PLACE_AT_NONCACHEABLE_INIT(x) = {y}; */
+#define ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_PLACE_AT(".noncacheable.init")
+#define ATTR_PLACE_AT_NONCACHEABLE_INIT_WITH_ALIGNMENT(alignment) \
+ ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_ALIGN(alignment)
+
+#define ATTR_RAMFUNC ATTR_PLACE_AT(".fast")
+#define ATTR_RAMFUNC_WITH_ALIGNMENT(alignment) \
+ ATTR_RAMFUNC ATTR_ALIGN(alignment)
+
+#define ATTR_SHARE_MEM ATTR_PLACE_AT(".sh_mem")
+
+#define NOP() __asm volatile("nop")
+#define WFI() __asm volatile("wfi")
+
+#define HPM_ATTR_MACHINE_INTERRUPT __attribute__ ((section(".isr_vector"), interrupt("machine"), aligned(4)))
+
+#elif defined(__ICCRISCV__)
+
+/* alway_inline */
+#define ATTR_ALWAYS_INLINE __attribute__((always_inline))
+
+/* weak */
+#define ATTR_WEAK __weak
+
+/* alignment */
+#define ATTR_ALIGN(alignment) __attribute__((aligned(alignment)))
+
+/* place var_declare at section_name, e.x. PLACE_AT(".target_section", var); */
+#define ATTR_PLACE_AT(section_name) __attribute__((section(section_name)))
+
+#define ATTR_PLACE_AT_WITH_ALIGNMENT(section_name, alignment) \
+ATTR_PLACE_AT(section_name) ATTR_ALIGN(alignment)
+
+#define ATTR_PLACE_AT_NONCACHEABLE ATTR_PLACE_AT(".noncacheable.bss")
+#define ATTR_PLACE_AT_NONCACHEABLE_WITH_ALIGNMENT(alignment) \
+ ATTR_PLACE_AT_NONCACHEABLE ATTR_ALIGN(alignment)
+
+#define ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_PLACE_AT(".noncacheable.bss")
+#define ATTR_PLACE_AT_NONCACHEABLE_BSS_WITH_ALIGNMENT(alignment) \
+ ATTR_PLACE_AT_NONCACHEABLE_BSS ATTR_ALIGN(alignment)
+
+/* initialize variable x with y using PLACE_AT_NONCACHEABLE_INIT(x) = {y}; */
+#define ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_PLACE_AT(".noncacheable.init")
+#define ATTR_PLACE_AT_NONCACHEABLE_INIT_WITH_ALIGNMENT(alignment) \
+ ATTR_PLACE_AT_NONCACHEABLE_INIT ATTR_ALIGN(alignment)
+
+#define ATTR_RAMFUNC ATTR_PLACE_AT(".fast")
+#define ATTR_RAMFUNC_WITH_ALIGNMENT(alignment) \
+ ATTR_RAMFUNC ATTR_ALIGN(alignment)
+
+#define ATTR_SHARE_MEM ATTR_PLACE_AT(".sh_mem")
+
+#define NOP() __asm volatile("nop")
+#define WFI() __asm volatile("wfi")
+
+#define HPM_ATTR_MACHINE_INTERRUPT __machine __interrupt
+
+#else
+#error Unknown toolchain
+#endif
+#endif /* _HPM_COMMON_H */
diff --git a/contrib/loaders/flash/hpmicro/hpm_romapi.h b/contrib/loaders/flash/hpmicro/hpm_romapi.h
new file mode 100644
index 000000000..d19f55199
--- /dev/null
+++ b/contrib/loaders/flash/hpmicro/hpm_romapi.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Copyright (c) 2021-2023 HPMicro
+ */
+
+#ifndef HPM_ROMAPI_H
+#define HPM_ROMAPI_H
+
+/**
+ * @brief ROM APIs
+ * @defgroup romapi_interface ROM APIs
+ * @{
+ */
+
+#include "hpm_common.h"
+#include "hpm_romapi_xpi_def.h"
+#include "hpm_romapi_xpi_soc_def.h"
+#include "hpm_romapi_xpi_nor_def.h"
+
+/***********************************************************************************************************************
+ *
+ *
+ * Definitions
+ *
+ *
+ **********************************************************************************************************************/
+
+/**
+ * @brief Bootloader API table
+ */
+struct bootloader_api_table_t {
+ /**< Bootloader API table: version */
+ const uint32_t version;
+ /**< Bootloader API table: copyright string address */
+ const char *copyright;
+ /**< Bootloader API table: run_bootloader API */
+ const uint32_t reserved0;
+ /**< Bootloader API table: otp driver interface address */
+ const uint32_t reserved1;
+ /**< Bootloader API table: xpi driver interface address */
+ const struct xpi_driver_interface_t *xpi_driver_if;
+ /**< Bootloader API table: xpi nor driver interface address */
+ const struct xpi_nor_driver_interface_t *xpi_nor_driver_if;
+ /**< Bootloader API table: xpi ram driver interface address */
+ const uint32_t reserved2;
+};
+
+/**< Bootloader API table Root */
+#define ROM_API_TABLE_ROOT ((const struct bootloader_api_table_t *)0x2001FF00U)
+
+#endif /* HPM_ROMAPI_H */
diff --git a/contrib/loaders/flash/hpmicro/hpm_romapi_xpi_def.h b/contrib/loaders/flash/hpmicro/hpm_romapi_xpi_def.h
new file mode 100644
index 000000000..b4d73bd10
--- /dev/null
+++ b/contrib/loaders/flash/hpmicro/hpm_romapi_xpi_def.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Copyright (c) 2021 HPMicro
+ */
+#ifndef HPM_ROMAPI_XPI_DEF_H
+#define HPM_ROMAPI_XPI_DEF_H
+
+/**
+ * @brief XPI ROM APIs
+ * @defgroup xpi_interface XPI driver APIs
+ * @{
+ */
+
+#include "hpm_common.h"
+
+/**
+ * @brief XPI Read Sample Clock source options
+ */
+enum xpi_rxclksrc_type_t {
+ xpi_rxclksrc_internal_loopback = 0, /**< Internal loopback */
+ xpi_rxclksrc_dqs_loopback = 1, /**< Loopback from DQS pad */
+ xpi_rxclksrc_external_dqs = 3, /**< Read is driven by External DQS pad */
+};
+
+/**
+ * @brief XPI pad definitions
+ */
+#define XPI_1PAD (0U) /**< Single pad */
+#define XPI_2PADS (1U) /**< Dual pads */
+#define XPI_4PADS (2U) /**< Quad pads */
+#define XPI_8PADS (3U) /**< Octal pads */
+
+/**
+ * @brief XPI IO pin group options
+ */
+enum xpi_io_group_t {
+ xpi_io_1st_group, /**< First/Primary group */
+ xpi_io_2nd_group, /**< Second/Secondary group */
+};
+
+/**
+ * @brief XPI Transfer Channel type definitions
+ */
+enum xpi_xfer_channel_t {
+ xpi_xfer_channel_a1, /**< The address is based on the device connected to Channel A1 */
+ xpi_xfer_channel_a2, /**< The address is based on the device connected to Channel A2 */
+ xpi_xfer_channel_b1, /**< The address is based on the device connected to Channel B1 */
+ xpi_xfer_channel_b2, /**< The address is based on the device connected to Channel B2 */
+ xpi_xfer_channel_auto, /**< The channel is auto determined */
+};
+
+/**
+ * @brief XPI Channel definitions
+ */
+enum xpi_channel_t {
+ xpi_channel_a1, /**< Port: Channel A1 */
+ xpi_channel_a2, /**< Port: Channel A2 */
+ xpi_channel_b1, /**< Port: Channel B1 */
+ xpi_channel_b2, /**< Port: Channel B2 */
+};
+
+/**
+ * @brief XPI APB Transfer type
+ */
+enum xpi_apb_xfer_type_t {
+ xpi_apb_xfer_type_cmd, /**< APB Command Type: Command only */
+ xpi_apb_xfer_type_config, /**< APB Command Type: Configuration */
+ xpi_apb_xfer_type_read, /**< APB Command Type: Read */
+ xpi_apb_xfer_type_write, /**< APB Command Type: Write */
+};
+
+/**
+ * @brief XPI Xfer Mode
+ */
+enum xpi_xfer_mode_t {
+ xpi_xfer_mode_polling, /**< Transfer mode: Polling */
+ xpi_xfer_mode_dma, /**< Transfer mode: DMA */
+ xpi_xfer_mode_interrupt, /**< Transfer mode: Interrupt */
+};
+
+/**
+ * @brief XPI Xfer context
+ */
+struct xpi_xfer_ctx_t {
+ uint32_t addr; /**< device address for XPI transfer */
+ uint8_t channel; /**< channel for XPI transfer */
+ uint8_t cmd_type; /**< command type for XPI transfer */
+ uint8_t seq_idx; /**< Sequence index for XPI transfer */
+ uint8_t seq_num; /**< Sequence number for XPI transfer */
+ uint32_t *buf; /**< Buffer for XPI transfer */
+ uint32_t xfer_size; /**< Transfer size in bytes */
+};
+
+/**
+ * @brief XPI instruction sequence
+ */
+struct xpi_instr_seq_t {
+ uint32_t entry[4];
+};
+
+/**
+ * @brief XPI Phase definitions
+ */
+#define XPI_PHASE_STOP (0x00U) /**< Phase: Stop */
+#define XPI_PHASE_CMD_SDR (0x01U) /**< Phase: Send CMD in SDR mode */
+#define XPI_PHASE_RADDR_SDR (0x02U) /**< Phase: Send Row Address in SDR Mode */
+#define XPI_PHASE_CADDR_SDR (0x03U) /**< Phase: Send Column Address in SDR Mode */
+#define XPI_PHASE_MODE4_SDR (0x06U) /**< Phase: Send Mode 4 in SDR Mode */
+#define XPI_PHASE_MODE8_SDR (0x07U) /**< Phase: Send Mode 8 in SDR Mode */
+#define XPI_PHASE_WRITE_SDR (0x08U) /**< Phase: Write data in SDR Mode */
+#define XPI_PHASE_READ_SDR (0x09U) /**< Phase: Read data in SDR Mode */
+#define XPI_PHASE_DUMMY_SDR (0X0CU) /**< Phase: Send Dummy in SDR Mode */
+#define XPI_PHASE_DUMMY_RWDS_SDR (0x0DU) /**< Phase: Send Dummy RWDS in SDR Mode */
+
+#define XPI_PHASE_CMD_DDR (0x21U) /**< Phase: Send CMD in DDR Mode */
+#define XPI_PHASE_RADDR_DDR (0x22U) /**< Phase: Send Raw Address in DDR Mode */
+#define XPI_PHASE_CADDR_DDR (0x23U) /**< Phase: Send Column address in DDR Mode */
+#define XPI_PHASE_MODE4_DDR (0x26U) /**< Phase: Send Mode 4 in DDR Mode */
+#define XPI_PHASE_MODE8_DDR (0x27U) /**< Phase: Send Mode 8 in DDR Mode */
+#define XPI_PHASE_WRITE_DDR (0x28U) /**< Phase: Write data in DDR Mode */
+#define XPI_PHASE_READ_DDR (0x29U) /**< Phase: Read data in SDR Mode */
+#define XPI_PHASE_DUMMY_DDR (0x2CU) /**< Phase: Send DUMMY in DDR Mode */
+#define XPI_PHASE_DUMMY_RWDS_DDR (0x2DU) /**< Phase: Send DUMMY RWDS in DDR Mode */
+
+/**
+ * @brief XPI API command error codes
+ */
+enum {
+ status_xpi_apb_jump_on_cs = MAKE_STATUS(status_group_xpi, 1),
+ status_xpi_apb_unknown_inst = MAKE_STATUS(status_group_xpi, 2),
+ status_xpi_apb_dummy_sdr_in_ddr_seq = MAKE_STATUS(status_group_xpi, 3),
+ status_xpi_apb_dummy_ddr_in_sdr_seq = MAKE_STATUS(status_group_xpi, 4),
+ status_xpi_apb_exceed_addr_range = MAKE_STATUS(status_group_xpi, 5),
+ status_xpi_apb_seq_timeout = MAKE_STATUS(status_group_xpi, 6),
+ status_xpi_apb_cross_boundary = MAKE_STATUS(status_group_xpi, 7),
+};
+
+/**
+ * @brief Delay line definitions
+ */
+enum {
+ xpi_dll_half_cycle = 0xFU,
+ xpi_dll_quarter_cycle = 0x7U,
+ xpi_dll_sdr_default_cycle = xpi_dll_half_cycle,
+ xpi_dll_ddr_default_cycle = xpi_dll_quarter_cycle,
+};
+
+/**
+ * @brief XPI configuration structure
+ */
+struct xpi_config_t {
+ uint8_t rxclk_src; /**< Read sample clock source */
+ uint8_t reserved0[7]; /**< Reserved */
+ uint8_t tx_watermark_in_dwords; /**< Tx watermark in double words */
+ uint8_t rx_watermark_in_dwords; /**< Rx watermark in double words */
+ uint8_t enable_differential_clk; /**< Enable differential clock */
+ uint8_t reserved1[5]; /**< Reserved */
+ uint32_t access_flags; /**< Access flags */
+};
+
+/**
+ * @brief XPI Device Configuration structure
+ */
+struct xpi_device_config_t {
+ uint32_t size_in_kbytes; /**< Device size in kbytes */
+ uint32_t serial_root_clk_freq; /**< XPI serial root clock frequency */
+
+ uint8_t enable_write_mask; /**< Enable write mask, typically for PSRAM/HyperRAM */
+ uint8_t data_valid_time; /**< Data valid time, Unit 0.1ns */
+ uint8_t reserved0[2];
+
+ uint8_t cs_hold_time; /**< CS hold time, cycles in terms of FLASH clock */
+ uint8_t cs_setup_time; /**< CS setup time, cycles in terms of FLASH clock */
+ uint16_t cs_interval; /**< CS interval, cycles in terms of FLASH clock */
+
+ uint8_t reserved1;
+ uint8_t column_addr_size; /**< Column address bits */
+ uint8_t enable_word_address; /**< Enable word address, for HyperFLASH/HyperRAM */
+ uint8_t dly_target; /**< Delay target */
+
+ uint8_t ahb_write_seq_idx; /**< AHB write sequence index */
+ uint8_t ahb_write_seq_num; /**< AHB write sequence number */
+ uint8_t ahb_read_seq_idx; /**< AHB read sequence index */
+ uint8_t ahb_read_seq_num; /**< AHB read sequence number */
+
+ uint8_t ahb_write_wait_interval; /**< AHB write wait interval, in terms of FLASH clock */
+ uint8_t reserved2[3];
+};
+
+/**
+ * @brief SUB Instruction
+ * @param [in] phase Name
+ * @param [in] pad Pad for Phase
+ * @param [in] op Operand for Phase
+ */
+#define SUB_INSTR(phase, pad, op) ((uint32_t)(((uint16_t)(phase) << 10) | ((uint16_t)(pad) << 8) | ((uint16_t)(op))))
+/**
+ * @brief Generate a single word INSTRUCTION sequence word
+ * @note Here intentionally use the MACRO because when the arguments are constant value, the compiler
+ * can generate the const entry word during pre-processing
+ */
+#define XPI_INSTR_SEQ(phase0, pad0, op0, phase1, pad1, op1) \
+ (SUB_INSTR(phase0, pad0, op0) | (SUB_INSTR(phase1, pad1, op1) << 16))
+
+struct xpi_ahb_buffer_cfg_t {
+ struct {
+ uint8_t priority; /* Offset: 0x00 */
+ uint8_t master_idx; /* Offset: 0x01 */
+ uint8_t buf_size_in_dword; /* Offset: 0x02 */
+ bool enable_prefetch; /* Offset: 0x03 */
+ } entry[8];
+};
+
+/**
+ * @brief XPI driver interface
+ */
+struct xpi_driver_interface_t {
+ /**< XPI driver interface: version */
+ uint32_t version;
+ /**< XPI driver interface: get default configuration */
+ hpm_stat_t (*get_default_config)(struct xpi_config_t *xpi_config);
+ /**< XPI driver interface: get default device configuration */
+ hpm_stat_t (*get_default_device_config)(struct xpi_device_config_t *dev_config);
+ /**< XPI driver interface: initialize the XPI using xpi_config */
+ hpm_stat_t (*init)(uint32_t *base, struct xpi_config_t *xpi_config);
+ /**< XPI driver interface: configure the AHB buffer */
+ hpm_stat_t (*config_ahb_buffer)(uint32_t *base, struct xpi_ahb_buffer_cfg_t *ahb_buf_cfg);
+ /**< XPI driver interface: configure the device */
+ hpm_stat_t (*config_device)(uint32_t *base, struct xpi_device_config_t *dev_cfg, enum xpi_channel_t channel);
+ /**< XPI driver interface: update instruction talbe */
+ hpm_stat_t (*update_instr_table)(uint32_t *base, const uint32_t *inst_base, uint32_t seq_idx, uint32_t num);
+ /**< XPI driver interface: transfer command/data using block interface */
+ hpm_stat_t (*transfer_blocking)(uint32_t *base, struct xpi_xfer_ctx_t *xfer);
+ /**< Software reset the XPI controller */
+ void (*software_reset)(uint32_t *base);
+ /**< XPI driver interface: Check whether IP is idle */
+ bool (*is_idle)(uint32_t *base);
+ /**< XPI driver interface: update delay line setting */
+ void (*update_dllcr)(uint32_t *base,
+ uint32_t serial_root_clk_freq,
+ uint32_t data_valid_time,
+ enum xpi_channel_t channel,
+ uint32_t dly_target);
+ /**< XPI driver interface: Get absolute address for APB transfer */
+ hpm_stat_t
+ (*get_abs_apb_xfer_addr)(uint32_t *base, enum xpi_xfer_channel_t channel, uint32_t in_addr, uint32_t *out_addr);
+};
+
+/**
+ * @}
+ */
+
+#endif /* HPM_ROMAPI_XPI_DEF_H */
diff --git a/contrib/loaders/flash/hpmicro/hpm_romapi_xpi_nor_def.h b/contrib/loaders/flash/hpmicro/hpm_romapi_xpi_nor_def.h
new file mode 100644
index 000000000..edde8402f
--- /dev/null
+++ b/contrib/loaders/flash/hpmicro/hpm_romapi_xpi_nor_def.h
@@ -0,0 +1,426 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Copyright (c) 2021 HPMicro
+ */
+#ifndef HPM_ROMAPI_XPI_NOR_DEF_H
+#define HPM_ROMAPI_XPI_NOR_DEF_H
+
+/**
+ * @brief XPI NOR ROM APIs
+ * @defgroup xpi_nor_interface XPI NOR driver APIs
+ * @ingroup romapi_interfaces
+ * @{
+ */
+
+#include "hpm_common.h"
+#include "hpm_romapi_xpi_def.h"
+
+#define XPI_NOR_CFG_TAG 0x524f4E58U /**< ASCII: "XNOR" */
+
+/**
+ * @brief XPI NOR properties
+ */
+enum {
+ xpi_nor_property_total_size, /**< Total size in bytes */
+ xpi_nor_property_page_size, /**< Page size in bytes */
+ xpi_nor_property_sector_size, /**<sector size in bytes */
+ xpi_nor_property_block_size, /**< block size in bytes */
+ xpi_nor_property_max = xpi_nor_property_block_size,
+};
+
+/**
+ * @brief XPI NOR safe frequency option
+ */
+enum {
+ xpi_nor_clk_safe_clk_freq = 1,
+};
+
+/**
+ * @brief XPI NOR miscellaneous options
+ */
+enum {
+ xpi_nor_option_misc_spi_only = 1, /**< SPI only */
+ xpi_nor_option_misc_internal_loopback = 2, /**< Internal loopback mode */
+ xpi_nor_option_misc_ext_dqs = 3, /**< External DQS pin */
+};
+
+/**
+ * @brief XPI NOR connection option
+ */
+enum {
+ xpi_nor_connection_sel_chna_cs0, /**< Channel A, CS0 */
+ xpi_nor_connection_sel_chnb_cs0, /**< Channel B, CS0 */
+ xpi_nor_connection_sel_chna_cs0_chnb_cs0, /**< Channel A + Channel B, CS0 */
+ xpi_nor_connection_sel_chna_cs0_cs1, /**< Channel A, CS0 + CS1 */
+ xpi_nor_connection_sel_chnb_cs0_cs1 /**< Channel B, CS0 + CS1 */
+};
+
+/**
+ * @brief QE bit enable sequence option
+ */
+enum xpi_nor_quad_enable_seq_t {
+ xpi_nor_quad_en_auto_or_ignore = 0U, /**< Auto enable or ignore */
+ xpi_nor_quad_en_set_bit6_in_status_reg1 = 1U, /**< QE bit is at bit6 in Status register 1 */
+ xpi_nor_quad_en_set_bit1_in_status_reg2 = 2U, /**< QE bit is at bit1 in Status register 2 register 2 */
+ xpi_nor_quad_en_set_bit7_in_status_reg2 = 3U, /**< QE bit is at bit7 in Status register 2 */
+ xpi_nor_quad_en_set_bi1_in_status_reg2_via_0x31_cmd = 4U, /**< QE bit is in status register 2 via CMD 0x31 */
+};
+
+/**
+ * @brief XPI working mode
+ */
+enum xpi_working_mode_t {
+ xpi_working_mode_extend_spi, /**< XPI works in extended SPI mode, including 1-1-1, 1-2-2, 1-4-4, 1-8-8 */
+ xpi_working_mode_xpi, /**< XPI works in XPI mode, including, 1-1-1, 2-2-2, 4-4-4, 8-8-8 */
+ xpi_working_mode_hyperbus, /**< XPI works in HyperBus mode */
+};
+
+/**
+ * @brief XPI NOR configuration command type
+ */
+enum xpi_nor_cfg_cmd_type_t {
+ xpi_nor_cfg_cmd_type_no_cfg = 0U, /**< No configuration */
+ xpi_nor_cfg_cmd_type_generic = 1U, /**< Generic configuration */
+ xpi_nor_cfg_cmd_type_spi2xpi = 2U, /**< SPI to XPI mode */
+ xpi_nor_cfg_cmd_type_xpi2spi = 3U, /**< XPI to SPI mode */
+};
+
+/**
+ * @brief XPI NOR probe options
+ */
+enum xpi_nor_probe_t {
+ xpi_nor_probe_sfdp_sdr = 0U, /**< Probe FLASH using SFDP and set FLASH to SDR mode */
+ xpi_nor_probe_sfdp_ddr = 1U, /**< Probe FLASH using SDP and set FLASH to DDR mode */
+ xpi_nor_quad_read_0xeb = 2U, /**< Set FLASH to default Quad I/O read in SDR mode */
+ xpi_nor_dual_read_0xbb = 3U, /**< Set FLASH to default Dual I/O read in SDR mode */
+ xpi_nor_hyperbus_1v8 = 4U, /**< Probe FLASH using HyperBus in 1.8V voltage */
+ xpi_nor_hyperbus_3v0 = 5U, /**< Probe FLASH using HyperBus in 3.0V voltage */
+ xpi_nor_octabus_ddr = 6U, /**< Probe FLASH using Macronix OctaBus and configure FLASH to OPI DDR mode */
+ xpi_nor_octabus_sdr = 7U, /**< Probe FLASH using Macronix OctaBus and configure FLASH to OPI SDR mode */
+ xpi_nor_xccela_ddr = 8U, /**< Probe FLASH using Xccela Protocol and configure FLASH to OPI DDR mode */
+ xpi_nor_xccela_sdr = 9U, /**< Probe FLASH using Xccela Protocol and configure FLASH to SDR mode */
+ xpi_nor_ecoxip_ddr = 10U, /**< Probe FLASH using EcoXiP Protocol and configure FLASH to OPI DDR mode */
+ xpi_nor_ecoxip_sdr = 11U, /**< Probe FLASH using EcoXiP Protocol and configure FLASH to SDR mode */
+};
+
+/**
+ * @brief Standard XPI NOR seuqnce index definitions
+ */
+enum xpi_std_nor_instr_idx_t {
+ xpi_std_nor_seq_idx_read = 0U, /**< 0 - Read */
+ xpi_std_nor_seq_idx_page_program = 1U, /**< 1 - Page Program */
+ xpi_std_nor_seq_idx_read_status = 2U, /**< 2 - Read Status */
+ xpi_std_nor_seq_idx_read_status_xpi = 3U, /**< 3 - Read Status in xSPI mode */
+ xpi_std_nor_seq_idx_write_enable = 4U, /**< 4 - Write Enable */
+ xpi_std_nor_seq_idx_write_enable_xpi = 5U, /**< 5 - Write Enable in xSPI mode */
+ xpi_std_nor_seq_idx_erase_sector = 6U, /**< 6 - Erase sector */
+ xpi_std_nor_seq_idx_erase_block = 7U, /**< 7 - Erase block */
+ xpi_std_nor_seq_idx_erase_chip = 8U, /**< 8 - Erase full chip */
+ xpi_std_nor_seq_idx_max = 9, /**< 9 */
+};
+
+/**
+ * @brief XPI NOR option tag
+ */
+#define XPI_NOR_CFG_OPTION_TAG (0xfcf90U)
+
+/**
+ * @brief XPI NOR configuration option
+ * The ROM SW can detect the FLASH configuration based on the following structure specified by the end-user
+ */
+struct xpi_nor_config_option_t {
+ union {
+ struct {
+ uint32_t words: 4; /**< Option words, exclude the header itself */
+ uint32_t reserved: 8; /**< Reserved for future use */
+ uint32_t tag: 20; /**< Must be 0xfcf90 */
+ };
+ uint32_t U;
+ } header;
+ union {
+ struct {
+ uint32_t freq_opt: 4; /**< 1 - 30MHz, others, SoC specific setting */
+ uint32_t misc: 4; /**< Not used for now */
+ uint32_t dummy_cycles: 8; /**< 0 - Auto detected/ use predefined value, others: by end-user */
+ uint32_t quad_enable_seq: 4; /**< See the xpi_nor_quad_enable_seq_t definitions for more details */
+ uint32_t cmd_pads_after_init: 4; /**< See the xpi_data_pad_t definitions for more details */
+ uint32_t cmd_pads_after_por: 4; /**< See the xpi_data_pad_t definitions for more details */
+ uint32_t probe_type: 4; /**< See the xpi_nor_probe_t definitions for more details */
+ };
+ uint32_t U;
+ } option0;
+ union {
+ struct {
+ uint32_t drive_strength: 8; /**< IO drive strength, 0 - pre-defined, Others - specified by end-user */
+ uint32_t connection_sel: 4; /**< Device connection selection: 0 - PORTA, 1 - PORTB, 2 - Parallel mode */
+ uint32_t pin_group_sel: 4; /**< Pin group selection, 0 - 1st group, 1 - 2nd group, default, 1st group */
+ uint32_t io_voltage: 4; /**< SoC pad voltage, 0 - 3.0V, 1-1.8V */
+ uint32_t reserved: 12; /**< Reserved for future use */
+ };
+ uint32_t U;
+ } option1;
+ union {
+ struct {
+ uint32_t flash_size_option:8; /**< FLASH size option */
+ uint32_t flash_sector_size_option:4; /**< FLASH sector size option */
+ uint32_t flash_sector_erase_cmd_option:4; /**< Sector Erase command option */
+ uint32_t reserved:20;
+ };
+ uint32_t U;
+ } option2;
+};
+
+/**
+ * @brief Sector size options
+ */
+enum {
+ serial_nor_sector_size_4kb, /**< Sector size: 4KB */
+ serial_nor_sector_size_32kb, /**< Sector size: 32KB */
+ serial_nor_sector_size_64kb, /**< Sector size: 64KB */
+ serial_nor_sector_size_256kb, /**< Sector size: 256KB */
+};
+
+/**
+ * @brief Sector erase command options
+ */
+enum {
+ serial_nor_erase_type_4kb, /**< Sector erase command: 4KB Erase */
+ serial_nor_erase_type_32kb, /**< Sector erase command: 32KB Erase */
+ serial_nor_erase_type_64kb, /**< Sector erase command: 64KB Erase */
+ serial_nor_erase_type_256kb, /**< Sector erase command: 256KB Erase */
+};
+
+/**
+ * @brief FLASH size options
+ */
+enum {
+ flash_size_4mb, /**< FLASH size: 4MB */
+ flash_size_8mb, /**< FLASH size: 8MB */
+ flash_size_16mb, /**< FLASH size: 16MB */
+};
+
+/**
+ * @brief Device Mode configuration structure
+ */
+struct device_mode_cfg_t {
+ uint8_t cfg_cmd_type; /**< Configuration command type */
+ uint8_t param_size; /**< Size for parameter */
+};
+
+/**
+ * @brief Device mode parameter structure
+ */
+struct device_mode_param_t {
+ uint32_t instr_seq[4]; /**< Command Instruction sequence*/
+ uint32_t param; /**< Parameter */
+};
+
+/**
+ * @brief XPI NOR device information structure
+ */
+struct xpi_device_info_t {
+ uint32_t size_in_kbytes; /**< Device Size in Kilobytes, offset 0x00 */
+ uint16_t page_size; /**< Page size, offset 0x04 */
+ uint16_t sector_size_kbytes; /**< Sector size in kilobytes, offset 0x06 */
+ uint16_t block_size_kbytes; /**< Block size in kilobytes, offset 0x08 */
+ uint8_t busy_offset; /**< Busy offset, offset 0x0a */
+ uint8_t busy_polarity; /**< Busy polarity, offset 0x0b */
+ uint8_t data_pads; /**< Device Size in Kilobytes, offset 0x0c */
+ uint8_t en_ddr_mode; /**< Enable DDR mode, offset 0x0d */
+ uint8_t clk_freq_for_device_cfg; /**< Clk frequency for device configuration offset 0x0e */
+ uint8_t working_mode_por; /**< Working mode after POR reset offset 0x0f */
+ uint8_t working_mode; /**< The device working mode, offset 0x10 */
+ uint8_t en_diff_clk; /**< Enable Differential clock, offset 0x11 */
+ uint8_t data_valid_time; /**< Data valid time, in 0.1ns, offset 0x12 */
+ uint8_t en_half_clk_for_non_read_cmd; /**< Enable half clock for non-read command, offset 0x13 */
+ uint8_t clk_freq_for_non_read_cmd; /**< Enable safe clock for non-read command, offset 0x14 */
+ uint8_t dll_dly_target; /**< XPI DLL Delay Target, offset 0x15 */
+ uint8_t io_voltage; /**< IO voltage, offset 0x16 */
+ uint8_t reserved0; /**< Reserved for future use, offset 0x17 */
+ uint8_t cs_hold_time; /**< CS hold time, 0 - default, others - user specified, offset 0x18 */
+ uint8_t cs_setup_time; /**< CS setup time, 0 - default, others - user specified, offset 0x19 */
+ uint8_t cs_interval; /**< CS interval, intervals between to CS active, offset 0x1a */
+ uint8_t en_dev_mode_cfg; /**< Enable device mode configuration, offset 0x1b */
+ uint32_t flash_state_ctx; /**< Flash state context, offset 0x1c */
+ struct device_mode_cfg_t mode_cfg_list[2]; /**< Mode configuration sequences, offset 0x20 */
+ uint32_t mode_cfg_param[2]; /**< Mode configuration parameters, offset 0x24 */
+ uint32_t reserved1; /**< Reserved for future use, offset 0x2C */
+ struct {
+ uint32_t entry[4];
+ } cfg_instr_seq[2]; /**< Mode Configuration Instruction sequence, offset 0x30 */
+};
+
+/**
+ * @brief XPI NOR configuration structure
+ */
+struct xpi_nor_config_t {
+ uint32_t tag; /**< Must be "XNOR", offset 0x000 */
+ uint32_t reserved0; /**< Reserved for future use, offset 0x004 */
+ uint8_t rxclk_src; /**< RXCLKSRC value, offset 0x008 */
+ uint8_t clk_freq; /**< Clock frequency, offset 0x009 */
+ uint8_t drive_strength; /**< Drive strength, offset 0x0a */
+ uint8_t column_addr_size; /**< Column address size, offset 0x0b */
+ uint8_t rxclk_src_for_init; /**< RXCLKSRC during FLASH initialization, offset 0x0c */
+ uint8_t config_in_progress; /**< Indicate whether device configuration is in progress, offset: 0x0d */
+ uint8_t reserved[2]; /**< Reserved for future use, offset 0x00f */
+ struct {
+ uint8_t enable; /**< Port enable flag, 0 - not enabled, 1 - enabled */
+ uint8_t group; /**< 0 - 1st IO group, 1 - 2nd IO group */
+ uint8_t reserved[2];
+ } chn_info[4]; /**< Device connection information */
+ struct xpi_device_info_t device_info; /**< Device info, offset 0x20 */
+ struct xpi_instr_seq_t instr_set[xpi_std_nor_seq_idx_max];/**< Standard instruction sequence table, offset 0x70 */
+};
+
+/**
+ * @brief FLASH runtime context structure
+ */
+union flash_run_context_t {
+ struct {
+ uint32_t wait_time: 7; /**< Wait time */
+ uint32_t wait_time_unit: 1; /**< 0 - 10us, 1 - 1ms */
+ uint32_t reset_gpio: 8; /**<Reset GPIO */
+ uint32_t restore_sequence: 4; /**<Restore sequence */
+ uint32_t exit_no_cmd_sequence: 4; /**< Exit no-cmd sequence */
+ uint32_t current_mode: 4; /**< Current FLASH mode */
+ uint32_t por_mode: 4; /**< FLASH mode upon Power-on Reset */
+ };
+ uint32_t U;
+};
+
+/**
+ * @brief XPI NOR API error codes
+ */
+enum {
+ status_xpi_nor_sfdp_not_found = MAKE_STATUS(status_group_xpi_nor, 0), /**< SFDP table was not found */
+ status_xpi_nor_ddr_read_dummy_cycle_probe_failed =
+ MAKE_STATUS(status_group_xpi_nor, 1), /**< Probing Dummy cyles for DDR read failed */
+ status_xpi_nor_flash_not_found = MAKE_STATUS(status_group_xpi_nor, 2), /**< FLASH was not detected */
+};
+
+/**
+ * @brief XPI NOR driver interface
+ */
+struct xpi_nor_driver_interface_t {
+ /**< XPI NOR driver interface: API version */
+ uint32_t version;
+ /**< XPI NOR driver interface: Get FLASH configuration */
+ hpm_stat_t (*get_config)(uint32_t *base,
+ struct xpi_nor_config_t *nor_cfg,
+ struct xpi_nor_config_option_t *cfg_option);
+ /**< XPI NOR driver interface: initialize FLASH */
+ hpm_stat_t (*init)(uint32_t *base, struct xpi_nor_config_t *nor_config);
+ /**< XPI NOR driver interface: Enable write access to FLASH */
+ hpm_stat_t
+ (*enable_write)(uint32_t *base, enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config, uint32_t addr);
+ /**< XPI NOR driver interface: Get FLASH status register */
+ hpm_stat_t (*get_status)(uint32_t *base,
+ enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config,
+ uint32_t addr,
+ uint16_t *out_status);
+ /**< XPI NOR driver interface: Wait when FLASH is still busy */
+ hpm_stat_t
+ (*wait_busy)(uint32_t *base, enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config, uint32_t addr);
+ /**< XPI NOR driver interface: erase a specified FLASH region */
+ hpm_stat_t (*erase)(uint32_t *base,
+ enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config,
+ uint32_t start,
+ uint32_t length);
+ /**< XPI NOR driver interface: Erase the whole FLASH */
+ hpm_stat_t (*erase_chip)(uint32_t *base, enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config);
+ /**< XPI NOR driver interface: Erase specified FLASH sector */
+ hpm_stat_t
+ (*erase_sector)(uint32_t *base, enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config, uint32_t addr);
+ /**< XPI NOR driver interface: Erase specified FLASH block */
+ hpm_stat_t
+ (*erase_block)(uint32_t *base, enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config, uint32_t addr);
+ /**< XPI NOR driver interface: Program data to specified FLASH address */
+ hpm_stat_t (*program)(uint32_t *base,
+ enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config,
+ const uint32_t *src,
+ uint32_t dst_addr,
+ uint32_t length);
+ /**< XPI NOR driver interface: read data from specified FLASH address */
+ hpm_stat_t (*read)(uint32_t *base,
+ enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config,
+ uint32_t *dst,
+ uint32_t start,
+ uint32_t length);
+ /**< XPI NOR driver interface: program FLASH page using nonblocking interface */
+ hpm_stat_t (*page_program_nonblocking)(uint32_t *base,
+ enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config,
+ const uint32_t *src,
+ uint32_t dst_addr,
+ uint32_t length);
+ /**< XPI NOR driver interface: erase FLASH sector using nonblocking interface */
+ hpm_stat_t (*erase_sector_nonblocking)(uint32_t *base,
+ enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config,
+ uint32_t addr);
+ /**< XPI NOR driver interface: erase FLASH block using nonblocking interface */
+ hpm_stat_t (*erase_block_nonblocking)(uint32_t *base,
+ enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config,
+ uint32_t addr);
+ /**< XPI NOR driver interface: erase the whole FLASh using nonblocking interface */
+ hpm_stat_t (*erase_chip_nonblocking)(uint32_t *base,
+ enum xpi_xfer_channel_t channel,
+ const struct xpi_nor_config_t *nor_config);
+
+ uint32_t reserved0[3];
+
+ /**< XPI NOR driver interface: automatically configuration flash based on the cfg_option setting */
+ hpm_stat_t (*auto_config)(uint32_t *base, struct xpi_nor_config_t *nor_cfg,
+ struct xpi_nor_config_option_t *cfg_option);
+
+ /**< XPI NOR driver interface: Get FLASH properties */
+ hpm_stat_t (*get_property)(uint32_t *base, struct xpi_nor_config_t *nor_cfg, uint32_t property_id, uint32_t *value);
+
+ uint32_t reserved1;
+
+ /**< Post Erase Sector Nonblocking operation: For Hybrid mode only */
+ hpm_stat_t (*post_erase_sector_nonblocking)(uint32_t *base, enum xpi_xfer_channel_t chn,
+ struct xpi_nor_config_t *nor_cfg, uint32_t addr);
+
+ /**< Post Erase Block Nonblocking operation: For Hybrid mode only */
+ hpm_stat_t (*post_erase_block_nonblocking)(uint32_t *base, enum xpi_xfer_channel_t chn,
+ struct xpi_nor_config_t *nor_cfg, uint32_t addr);
+
+ /**< Post Erase Chip Nonblocking operation: For Hybrid mode only */
+ hpm_stat_t (*post_erase_chip_nonblocking)(uint32_t *base, enum xpi_xfer_channel_t chn,
+ struct xpi_nor_config_t *nor_cfg);
+
+ /**< Post Page Program Nonblocking operation: For Hybrid mode only */
+ hpm_stat_t (*post_page_program_nonblocking)(uint32_t *base, enum xpi_xfer_channel_t chn,
+ struct xpi_nor_config_t *nor_config,
+ const uint32_t *src, uint32_t dst_addr, uint32_t length);
+ /**< Turn on the power for Internal FLASH */
+ void (*sip_flash_power_on)(uint32_t *base);
+
+ /**< Turn off the power for Internal FLASH */
+ void (*sip_flash_power_off)(uint32_t *base);
+
+ /**< Enable Hybrid mode */
+ void (*enable_hybrid_xpi)(uint32_t *base);
+
+ /**< Disable Hybrid mode */
+ void (*disable_hybrid_xpi)(uint32_t *base);
+
+};
+
+/**
+ * @}
+ */
+
+#endif /* HPM_ROMAPI_XPI_NOR_DEF_H */
diff --git a/contrib/loaders/flash/hpmicro/hpm_romapi_xpi_soc_def.h b/contrib/loaders/flash/hpmicro/hpm_romapi_xpi_soc_def.h
new file mode 100644
index 000000000..959f0a36b
--- /dev/null
+++ b/contrib/loaders/flash/hpmicro/hpm_romapi_xpi_soc_def.h
@@ -0,0 +1,69 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Copyright (c) 2021 HPMicro
+ */
+
+#ifndef HPM_ROMAPI_XPI_SOC_DEF_H
+#define HPM_ROMAPI_XPI_SOC_DEF_H
+
+#include "hpm_common.h"
+#include "hpm_romapi_xpi_def.h"
+
+/***********************************************************************************************************************
+ * Definitions
+ **********************************************************************************************************************/
+
+#define XPI_CLK_OUT_FREQ_OPTION_30MHZ (1U)
+#define XPI_CLK_OUT_FREQ_OPTION_50MHZ (2U)
+#define XPI_CLK_OUT_FREQ_OPTION_66MHZ (3U)
+#define XPI_CLK_OUT_FREQ_OPTION_80MHZ (4U)
+#define XPI_CLK_OUT_FREQ_OPTION_104MHZ (5U)
+#define XPI_CLK_OUT_FREQ_OPTION_120MHZ (6U)
+#define XPI_CLK_OUT_FREQ_OPTION_133MHZ (7U)
+#define XPI_CLK_OUT_FREQ_OPTION_166MHZ (8U)
+#define XPI_CLK_OUT_FREQ_OPTION_200MHZ (9U)
+
+struct xpi_io_config_t {
+ uint8_t data_pads;
+ enum xpi_channel_t channel;
+ enum xpi_io_group_t io_group;
+ uint8_t drive_strength;
+ bool enable_dqs;
+ bool enable_diff_clk;
+};
+
+enum clk_freq_type_t {
+ xpi_freq_type_typical,
+ xpi_freq_type_mhz,
+};
+
+enum xpi_clk_src_t {
+ xpi_clk_src_auto,
+ xpi_clk_src_osc,
+ xpi_clk_src_pll0clk0,
+ xpi_clk_src_pll1clk0,
+ xpi_clk_src_pll1clk1,
+ xpi_clk_src_pll2clk0,
+ xpi_clk_src_pll2clk1,
+ xpi_clk_src_pll3clk0,
+ xpi_clk_src_pll4clk0,
+};
+
+union xpi_clk_config_t {
+ struct {
+ uint8_t freq;
+ bool enable_ddr;
+ enum xpi_clk_src_t clk_src;
+ enum clk_freq_type_t freq_type;
+ };
+ uint32_t freq_opt;
+};
+
+enum xpi_clock_t {
+ xpi_clock_bus,
+ xpi_clock_serial_root,
+ xpi_clock_serial,
+};
+
+#endif /* HPM_ROMAPI_XPI_SOC_DEF_H */
diff --git a/contrib/loaders/flash/hpmicro/hpm_xpi_flash.h b/contrib/loaders/flash/hpmicro/hpm_xpi_flash.h
new file mode 100644
index 000000000..462b374bc
--- /dev/null
+++ b/contrib/loaders/flash/hpmicro/hpm_xpi_flash.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+
+/*
+ * Copyright (c) 2021 hpmicro
+ */
+
+#ifndef HPM_XPI_FLASH_H
+#define HPM_XPI_FLASH_H
+
+#define FLASH_INIT (0)
+#define FLASH_ERASE (0x6)
+#define FLASH_PROGRAM (0xc)
+#define FLASH_READ (0x12)
+#define FLASH_GET_INFO (0x18)
+#define FLASH_ERASE_CHIP (0x1e)
+
+#endif
diff --git a/contrib/loaders/flash/hpmicro/hpm_xpi_flash.inc b/contrib/loaders/flash/hpmicro/hpm_xpi_flash.inc
new file mode 100644
index 000000000..410d3679f
--- /dev/null
+++ b/contrib/loaders/flash/hpmicro/hpm_xpi_flash.inc
@@ -0,0 +1,72 @@
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+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
+0x3d,0x43,0x2a,0x87,0x63,0x73,0xc3,0x02,0x93,0x77,0xf7,0x00,0xbd,0xef,0xad,0xe5,
+0x93,0x76,0x06,0xff,0x3d,0x8a,0xba,0x96,0x0c,0xc3,0x4c,0xc3,0x0c,0xc7,0x4c,0xc7,
+0x41,0x07,0xe3,0x6b,0xd7,0xfe,0x11,0xe2,0x82,0x80,0xb3,0x06,0xc3,0x40,0x8a,0x06,
+0x97,0x02,0x00,0x00,0x96,0x96,0x67,0x80,0xa6,0x00,0x23,0x07,0xb7,0x00,0xa3,0x06,
+0xb7,0x00,0x23,0x06,0xb7,0x00,0xa3,0x05,0xb7,0x00,0x23,0x05,0xb7,0x00,0xa3,0x04,
+0xb7,0x00,0x23,0x04,0xb7,0x00,0xa3,0x03,0xb7,0x00,0x23,0x03,0xb7,0x00,0xa3,0x02,
+0xb7,0x00,0x23,0x02,0xb7,0x00,0xa3,0x01,0xb7,0x00,0x23,0x01,0xb7,0x00,0xa3,0x00,
+0xb7,0x00,0x23,0x00,0xb7,0x00,0x82,0x80,0x93,0xf5,0xf5,0x0f,0x93,0x96,0x85,0x00,
+0xd5,0x8d,0x93,0x96,0x05,0x01,0xd5,0x8d,0x61,0xb7,0x93,0x96,0x27,0x00,0x97,0x02,
+0x00,0x00,0x96,0x96,0x86,0x82,0xe7,0x80,0x86,0xfa,0x96,0x80,0xc1,0x17,0x1d,0x8f,
+0x3e,0x96,0xe3,0x74,0xc3,0xf8,0xa5,0xb7,
diff --git a/contrib/loaders/flash/hpmicro/linker.ld b/contrib/loaders/flash/hpmicro/linker.ld
new file mode 100644
index 000000000..9697fb967
--- /dev/null
+++ b/contrib/loaders/flash/hpmicro/linker.ld
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: BSD-3-Clause */
+/*
+ * Copyright (c) 2021 HPMicro
+ */
+ENTRY(_init)
+
+SECTIONS
+{
+ .text : {
+ *(.func_table)
+ KEEP(*(.flash_algo.text*))
+ KEEP(*(.rodata))
+ KEEP(*(.rodata*))
+ KEEP(*(.flash_algo.data*))
+ *(.text)
+ *(.text*)
+ __etext = .;
+ }
+ .discard : {
+ __noncacheable_start__ = .;
+ __noncacheable_bss_start__ = .;
+ __bss_start__ = .;
+ __bss_end__ = .;
+ __noncacheable_bss_end__ = .;
+ _end = .;
+ __noncacheable_init_start__ = .;
+ __data_start__ = .;
+ __data_end__ = .;
+ __noncacheable_init_end__ = .;
+ __noncacheable_end__ = .;
+ __heap_start__ = .;
+ __heap_end__ = .;
+ __ramfunc_start__ = .;
+ __ramfunc_end__ = .;
+ __noncacheable_bss_start__ = .;
+ __noncacheable_bss_end__ = .;
+ __noncacheable_init_start__ = .;
+ __noncacheable_init_end__ = .;
+ __tdata_start__ = .;
+ __tdata_end__ = .;
+ __tbss_start__ = .;
+ __tbss_end__ = .;
+ __data_load_addr__ = .;
+ __fast_load_addr__ = .;
+ __tdata_load_addr__ = .;
+ __noncacheable_init_load_addr__ = .;
+ }
+}
diff --git a/contrib/loaders/flash/hpmicro/openocd_flash_algo.c b/contrib/loaders/flash/hpmicro/openocd_flash_algo.c
new file mode 100644
index 000000000..16b66d55d
--- /dev/null
+++ b/contrib/loaders/flash/hpmicro/openocd_flash_algo.c
@@ -0,0 +1,154 @@
+// SPDX-License-Identifier: BSD-3-Clause
+
+/*
+ * Copyright (c) 2024 HPMicro
+ */
+
+#include "hpm_romapi.h"
+
+#define CSR_MCACHE_CTL (0x7CA)
+#define HPM_MCACHE_CTL_DC_EN_MASK (0x2UL)
+
+#define XPI_USE_PORT_B_MASK (0x100)
+#define XPI_USE_PORT_A_MASK (0)
+#define XPI_USE_PORT_SHIFT (0x8)
+
+#define ROMAPI_SUPPORTS_HYBRIDXPI() (ROM_API_TABLE_ROOT->xpi_nor_driver_if->version >= 0x56010300)
+
+struct hpm_flash_info_t {
+ uint32_t total_sz_in_bytes;
+ uint32_t sector_sz_in_bytes;
+};
+
+__attribute__ ((section(".flash_algo.data"))) struct xpi_nor_config_t nor_config;
+__attribute__ ((section(".flash_algo.data"))) bool xpi_inited = false;
+__attribute__ ((section(".flash_algo.data"))) uint32_t channel = xpi_channel_a1;
+__attribute__ ((section(".flash_algo.data"))) uint32_t *xpi_base;
+
+__attribute__ ((section(".flash_algo.text"))) void refresh_device_size(uint32_t *base,
+ struct xpi_nor_config_option_t *option)
+{
+ volatile uint32_t *dev_size = (volatile uint32_t *)((uint32_t)base + 0x60);
+ bool enable_channelb = false;
+ if (option->header.words > 1)
+ enable_channelb = option->option1.connection_sel == xpi_nor_connection_sel_chnb_cs0;
+ if (enable_channelb) {
+ dev_size[0] = 0;
+ dev_size[1] = 0;
+ }
+}
+
+__attribute__ ((section(".flash_algo.text"))) uint32_t flash_init(uint32_t flash_base, uint32_t header,
+ uint32_t opt0, uint32_t opt1, uint32_t xpi_base_addr)
+{
+ uint32_t i = 0;
+ struct xpi_nor_config_option_t cfg_option;
+ hpm_stat_t stat = status_success;
+
+ xpi_base = (uint32_t *)xpi_base_addr;
+ if (xpi_inited)
+ return stat;
+
+ __asm volatile("csrc %0, %1" : : "i"(CSR_MCACHE_CTL), "r"(HPM_MCACHE_CTL_DC_EN_MASK));
+ for (i = 0; i < sizeof(cfg_option); i++)
+ *((uint8_t *)&cfg_option + i) = 0;
+ for (i = 0; i < sizeof(nor_config); i++)
+ *((uint8_t *)&nor_config + i) = 0;
+
+ cfg_option.header.U = header;
+ cfg_option.option0.U = opt0;
+ cfg_option.option1.U = opt1;
+
+ if (opt1 & XPI_USE_PORT_B_MASK)
+ channel = xpi_channel_b1;
+ else
+ channel = xpi_channel_a1;
+
+ stat = ROM_API_TABLE_ROOT->xpi_nor_driver_if->auto_config(xpi_base, &nor_config, &cfg_option);
+ if (stat)
+ return stat;
+
+ if (ROMAPI_SUPPORTS_HYBRIDXPI())
+ ROM_API_TABLE_ROOT->xpi_nor_driver_if->enable_hybrid_xpi(xpi_base);
+
+ refresh_device_size(xpi_base, &cfg_option);
+
+ nor_config.device_info.clk_freq_for_non_read_cmd = 0;
+ if (!xpi_inited)
+ xpi_inited = true;
+ return stat;
+}
+
+__attribute__ ((section(".flash_algo.text"))) uint32_t flash_erase(uint32_t flash_base, uint32_t address, uint32_t size)
+{
+ hpm_stat_t stat = status_success;
+ uint32_t left, start, block_size, align;
+
+ left = size;
+ start = address;
+ if (ROMAPI_SUPPORTS_HYBRIDXPI())
+ start += flash_base;
+ block_size = nor_config.device_info.block_size_kbytes * 1024;
+ if (left >= block_size) {
+ align = block_size - (start % block_size);
+ if (align != block_size) {
+ stat = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(xpi_base, channel, &nor_config, start, align);
+ if (stat != status_success)
+ return stat;
+ left -= align;
+ start += align;
+ }
+ while (left > block_size) {
+ stat = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_block(xpi_base, channel, &nor_config, start);
+ if (stat != status_success)
+ break;
+ left -= block_size;
+ start += block_size;
+ }
+ }
+ if (stat == status_success && left)
+ stat = ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase(xpi_base, channel, &nor_config, start, left);
+ return stat;
+}
+
+__attribute__ ((section(".flash_algo.text"))) uint32_t flash_program(uint32_t flash_base, uint32_t address,
+ uint32_t *buf, uint32_t size)
+{
+ hpm_stat_t stat;
+
+ if (ROMAPI_SUPPORTS_HYBRIDXPI())
+ address += flash_base;
+ stat = ROM_API_TABLE_ROOT->xpi_nor_driver_if->program(xpi_base, channel, &nor_config, buf, address, size);
+ return stat;
+}
+
+__attribute__ ((section(".flash_algo.text"))) uint32_t flash_read(uint32_t flash_base, uint32_t *buf,
+ uint32_t address, uint32_t size)
+{
+ hpm_stat_t stat;
+
+ if (ROMAPI_SUPPORTS_HYBRIDXPI())
+ address += flash_base;
+ stat = ROM_API_TABLE_ROOT->xpi_nor_driver_if->read(xpi_base, channel, &nor_config, buf, address, size);
+ return stat;
+}
+
+__attribute__ ((section(".flash_algo.text"))) uint32_t flash_get_info(uint32_t flash_base,
+ struct hpm_flash_info_t *flash_info)
+{
+ if (!flash_info)
+ return status_invalid_argument;
+
+ flash_info->total_sz_in_bytes = nor_config.device_info.size_in_kbytes << 10;
+ flash_info->sector_sz_in_bytes = nor_config.device_info.sector_size_kbytes << 10;
+ return status_success;
+}
+
+__attribute__ ((section(".flash_algo.text"))) uint32_t flash_erase_chip(uint32_t flash_base)
+{
+ return ROM_API_TABLE_ROOT->xpi_nor_driver_if->erase_chip(xpi_base, channel, &nor_config);
+}
+
+__attribute__ ((section(".flash_algo.text"))) void flash_deinit(void)
+{
+}
-----------------------------------------------------------------------
Summary of changes:
contrib/loaders/flash/hpmicro/Makefile | 51 +++
contrib/loaders/flash/hpmicro/README | 7 +
contrib/loaders/flash/hpmicro/func_table.S | 21 +
contrib/loaders/flash/hpmicro/hpm_common.h | 203 ++++++++++
contrib/loaders/flash/hpmicro/hpm_romapi.h | 52 +++
contrib/loaders/flash/hpmicro/hpm_romapi_xpi_def.h | 254 ++++++++++++
.../loaders/flash/hpmicro/hpm_romapi_xpi_nor_def.h | 426 +++++++++++++++++++++
.../loaders/flash/hpmicro/hpm_romapi_xpi_soc_def.h | 69 ++++
contrib/loaders/flash/hpmicro/hpm_xpi_flash.h | 17 +
contrib/loaders/flash/hpmicro/hpm_xpi_flash.inc | 72 ++++
contrib/loaders/flash/hpmicro/linker.ld | 48 +++
contrib/loaders/flash/hpmicro/openocd_flash_algo.c | 154 ++++++++
12 files changed, 1374 insertions(+)
create mode 100644 contrib/loaders/flash/hpmicro/Makefile
create mode 100644 contrib/loaders/flash/hpmicro/README
create mode 100644 contrib/loaders/flash/hpmicro/func_table.S
create mode 100644 contrib/loaders/flash/hpmicro/hpm_common.h
create mode 100644 contrib/loaders/flash/hpmicro/hpm_romapi.h
create mode 100644 contrib/loaders/flash/hpmicro/hpm_romapi_xpi_def.h
create mode 100644 contrib/loaders/flash/hpmicro/hpm_romapi_xpi_nor_def.h
create mode 100644 contrib/loaders/flash/hpmicro/hpm_romapi_xpi_soc_def.h
create mode 100644 contrib/loaders/flash/hpmicro/hpm_xpi_flash.h
create mode 100644 contrib/loaders/flash/hpmicro/hpm_xpi_flash.inc
create mode 100644 contrib/loaders/flash/hpmicro/linker.ld
create mode 100644 contrib/loaders/flash/hpmicro/openocd_flash_algo.c
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-12-14 20:54:09
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 41e165eee2c95ec01de3dc5f0794fec2ce9eab75 (commit)
from 517fd8e4b51c6e162f15452b9852ccb0a2b0e867 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 41e165eee2c95ec01de3dc5f0794fec2ce9eab75
Author: Maximilian Schneider <ma...@sc...>
Date: Fri Dec 5 21:31:39 2025 +0100
Change default WORKAREASIZE to 12kbytes for stm32f3x.
stm32f334k8 only has 12kbytes of SRAM and
flashing with the default WORKAREA of 16kbytes
will fail for images > 12k.
Change-Id: If9be0b0e7cd6e4ba15a130d8e06c74e4a0e22a61
Signed-off-by: Maximilian Schneider <ma...@sc...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9283
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg
index aa978d9c8..840ddff3f 100644
--- a/tcl/target/stm32f3x.cfg
+++ b/tcl/target/stm32f3x.cfg
@@ -17,11 +17,11 @@ if { [info exists CHIPNAME] } {
set _ENDIAN little
# Work-area is a space in RAM used for flash programming
-# By default use 16kB
+# By default use 12kB
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
- set _WORKAREASIZE 0x4000
+ set _WORKAREASIZE 0x3000
}
# Allow overriding the Flash bank size
-----------------------------------------------------------------------
Summary of changes:
tcl/target/stm32f3x.cfg | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-12-13 17:21:35
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 517fd8e4b51c6e162f15452b9852ccb0a2b0e867 (commit)
from 4e3ec2474a29d0270108990b509469c085ff7f1f (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 517fd8e4b51c6e162f15452b9852ccb0a2b0e867
Author: Antonio Borneo <bor...@gm...>
Date: Sun Nov 30 09:32:38 2025 +0100
tcl: file_renaming: add missing rename ti_beaglebone-base
Add the file renaming still not covered.
Change-Id: I74e22b3b66a27b9618356272553331ef3ada50cb
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9280
Tested-by: jenkins
Reviewed-by: Nishanth Menon <nm...@ti...>
Reviewed-by: Marc Schink <de...@za...>
diff --git a/tcl/file_renaming.cfg b/tcl/file_renaming.cfg
index 3a5294c3f..a522471f9 100644
--- a/tcl/file_renaming.cfg
+++ b/tcl/file_renaming.cfg
@@ -20,6 +20,7 @@ set _file_renaming {
board/sifive-hifive1-revb.cfg board/sifive/hifive1-rev-b.cfg
board/ti_beagleboard.cfg board/beagle/beagleboard.cfg
board/ti_beagleboard_xm.cfg board/beagle/beagleboard-xm.cfg
+ board/ti_beaglebone-base.cfg board/beagle/beaglebone-base.cfg
board/ti_beaglebone_black.cfg board/beagle/beaglebone-black.cfg
board/ti_beaglebone.cfg board/beagle/beaglebone.cfg
interface/chameleon.cfg interface/parport/chameleon.cfg
-----------------------------------------------------------------------
Summary of changes:
tcl/file_renaming.cfg | 1 +
1 file changed, 1 insertion(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-12-13 17:21:16
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 4e3ec2474a29d0270108990b509469c085ff7f1f (commit)
via 5b4557c6f29375cf48ec615aa7d5ecd496561c92 (commit)
from f8501461c1e96dfa7f3e37ff4e8c311683b97cea (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 4e3ec2474a29d0270108990b509469c085ff7f1f
Author: Antonio Borneo <bor...@gm...>
Date: Sun Nov 30 09:29:20 2025 +0100
tcl: file_renaming: drop automatic replecement check
With 'proc find' able to handle the replacement of '_' to '-',
drop the now unnecessary hardcoded renames.
Change-Id: I67fe3b5de8bad7611b2229fed8d2eefee848eb81
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9279
Tested-by: jenkins
Reviewed-by: Nishanth Menon <nm...@ti...>
diff --git a/tcl/file_renaming.cfg b/tcl/file_renaming.cfg
index 1603e2321..3a5294c3f 100644
--- a/tcl/file_renaming.cfg
+++ b/tcl/file_renaming.cfg
@@ -14,28 +14,14 @@
# board, chip, cpld, cpu, fpga, interface, target, test, tools
set _file_renaming {
- board/nordic_nrf51822_mkit.cfg board/nordic/nrf51822-mkit.cfg
- board/nordic_nrf51_dk.cfg board/nordic/nrf51-dk.cfg
- board/nordic_nrf52_dk.cfg board/nordic/nrf52-dk.cfg
board/omap2420_h4.cfg board/ti/omap2420-h4.cfg
board/stm32mp13x_dk.cfg board/st/stm32mp135f-dk.cfg
board/stm32mp15x_dk2.cfg board/st/stm32mp157f-dk2.cfg
board/sifive-hifive1-revb.cfg board/sifive/hifive1-rev-b.cfg
- board/ti_am437x_idk.cfg board/ti/am437x-idk.cfg
- board/ti_am43xx_evm.cfg board/ti/am43xx-evm.cfg
board/ti_beagleboard.cfg board/beagle/beagleboard.cfg
board/ti_beagleboard_xm.cfg board/beagle/beagleboard-xm.cfg
board/ti_beaglebone_black.cfg board/beagle/beaglebone-black.cfg
board/ti_beaglebone.cfg board/beagle/beaglebone.cfg
- board/ti_cc13x0_launchpad.cfg board/ti/cc13x0-launchpad.cfg
- board/ti_cc13x2_launchpad.cfg board/ti/cc13x2-launchpad.cfg
- board/ti_cc26x0_launchpad.cfg board/ti/cc26x0-launchpad.cfg
- board/ti_cc26x2_launchpad.cfg board/ti/cc26x2-launchpad.cfg
- board/ti_cc3200_launchxl.cfg board/ti/cc3200-launchxl.cfg
- board/ti_cc3220sf_launchpad.cfg board/ti/cc3220sf-launchpad.cfg
- board/ti_cc32xx_launchpad.cfg board/ti/cc32xx-launchpad.cfg
- board/ti_msp432_launchpad.cfg board/ti/msp432-launchpad.cfg
- board/ti_pandaboard_es.cfg board/ti/pandaboard-es.cfg
interface/chameleon.cfg interface/parport/chameleon.cfg
interface/flashlink.cfg interface/parport/flashlink.cfg
}
commit 5b4557c6f29375cf48ec615aa7d5ecd496561c92
Author: Antonio Borneo <bor...@gm...>
Date: Sun Nov 30 09:25:48 2025 +0100
startup.tcl: extend the file search among rename
The renaming of boards and targets is often requiring the simple
replacement of '_' with '-'.
To avoid listing such replacements in 'tcl/file_renaming.cfg', add
the automatic check in 'proc find' allowing till two replacements
of '_' with '-'.
Change-Id: I2623ea78d9c61d86189afcae2553c2910bda8389
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9278
Reviewed-by: Marc Schink <de...@za...>
Reviewed-by: Nishanth Menon <nm...@ti...>
Tested-by: jenkins
diff --git a/src/helper/startup.tcl b/src/helper/startup.tcl
index 89ed71b90..be01d71b3 100644
--- a/src/helper/startup.tcl
+++ b/src/helper/startup.tcl
@@ -31,23 +31,39 @@ proc find {filename} {
# - path/to/a/certain/vendor_config_file
# - path/to/a/certain/vendor-config_file
- # replaced with
+ # replaced either with
# - path/to/a/certain/vendor/config_file
+ # or
+ # - path/to/a/certain/vendor/config-file
regsub {([/\\])([^/\\_-]*)[_-]([^/\\]*$)} $filename "\\1\\2\\1\\3" f
if {[catch {_find_internal $f} t]==0} {
echo "WARNING: '$filename' is deprecated, use '$f' instead"
return $t
}
+ regsub {([/\\])([^/\\_]*)_([^/\\]*$)} $f "\\1\\2-\\3" f
+ regsub {([/\\])([^/\\_]*)_([^/\\]*$)} $f "\\1\\2-\\3" f
+ if {[catch {_find_internal $f} t]==0} {
+ echo "WARNING: '$filename' is deprecated, use '$f' instead"
+ return $t
+ }
foreach vendor {nordic ti sifive st} {
# - path/to/a/certain/config_file
- # replaced with
+ # replaced either with
# - path/to/a/certain/${vendor}/config_file
+ # or
+ # - path/to/a/certain/${vendor}/config-file
regsub {([/\\])([^/\\]*$)} $filename "\\1$vendor\\1\\2" f
if {[catch {_find_internal $f} t]==0} {
echo "WARNING: '$filename' is deprecated, use '$f' instead"
return $t
}
+ regsub {([/\\])([^/\\_]*)_([^/\\]*$)} $f "\\1\\2-\\3" f
+ regsub {([/\\])([^/\\_]*)_([^/\\]*$)} $f "\\1\\2-\\3" f
+ if {[catch {_find_internal $f} t]==0} {
+ echo "WARNING: '$filename' is deprecated, use '$f' instead"
+ return $t
+ }
}
# at last, check for explicit renaming
-----------------------------------------------------------------------
Summary of changes:
src/helper/startup.tcl | 20 ++++++++++++++++++--
tcl/file_renaming.cfg | 14 --------------
2 files changed, 18 insertions(+), 16 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-12-13 17:21:00
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via f8501461c1e96dfa7f3e37ff4e8c311683b97cea (commit)
via 6a5e4dc2a37c2dd0386a0495c89763b1bdd1b03c (commit)
from 13a082fc7ed6619c979fdf33a4a860760ba6d55d (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit f8501461c1e96dfa7f3e37ff4e8c311683b97cea
Author: Nishanth Menon <nm...@ti...>
Date: Wed Nov 12 07:20:55 2025 -0600
tcl/board/ti/*: Rename files using "-" separator
Replace "_" file separator with "-" file separator as recommended by
coding standards guidelines. While doing this, add the files that were
present in previous v0.12.0 release to file_renaming.cfg for this
non-trivial rename.
Signed-off-by: Nishanth Menon <nm...@ti...>
Change-Id: I88685f08f4a0cc580fa3b03f6db0d85061d65b94
Reviewed-on: https://review.openocd.org/c/openocd/+/9236
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/tcl/board/ti/am243_launchpad.cfg b/tcl/board/ti/am243-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/am243_launchpad.cfg
rename to tcl/board/ti/am243-launchpad.cfg
diff --git a/tcl/board/ti/am261_launchpad.cfg b/tcl/board/ti/am261-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/am261_launchpad.cfg
rename to tcl/board/ti/am261-launchpad.cfg
diff --git a/tcl/board/ti/am263_launchpad.cfg b/tcl/board/ti/am263-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/am263_launchpad.cfg
rename to tcl/board/ti/am263-launchpad.cfg
diff --git a/tcl/board/ti/am263p_launchpad.cfg b/tcl/board/ti/am263p-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/am263p_launchpad.cfg
rename to tcl/board/ti/am263p-launchpad.cfg
diff --git a/tcl/board/ti/am273_launchpad.cfg b/tcl/board/ti/am273-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/am273_launchpad.cfg
rename to tcl/board/ti/am273-launchpad.cfg
diff --git a/tcl/board/ti/am437x_idk.cfg b/tcl/board/ti/am437x-idk.cfg
similarity index 100%
rename from tcl/board/ti/am437x_idk.cfg
rename to tcl/board/ti/am437x-idk.cfg
diff --git a/tcl/board/ti/am43xx_evm.cfg b/tcl/board/ti/am43xx-evm.cfg
similarity index 100%
rename from tcl/board/ti/am43xx_evm.cfg
rename to tcl/board/ti/am43xx-evm.cfg
diff --git a/tcl/board/ti/cc13x0_launchpad.cfg b/tcl/board/ti/cc13x0-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/cc13x0_launchpad.cfg
rename to tcl/board/ti/cc13x0-launchpad.cfg
diff --git a/tcl/board/ti/cc13x2_launchpad.cfg b/tcl/board/ti/cc13x2-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/cc13x2_launchpad.cfg
rename to tcl/board/ti/cc13x2-launchpad.cfg
diff --git a/tcl/board/ti/cc26x0_launchpad.cfg b/tcl/board/ti/cc26x0-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/cc26x0_launchpad.cfg
rename to tcl/board/ti/cc26x0-launchpad.cfg
diff --git a/tcl/board/ti/cc26x2_launchpad.cfg b/tcl/board/ti/cc26x2-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/cc26x2_launchpad.cfg
rename to tcl/board/ti/cc26x2-launchpad.cfg
diff --git a/tcl/board/ti/cc26x2x7_launchpad.cfg b/tcl/board/ti/cc26x2x7-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/cc26x2x7_launchpad.cfg
rename to tcl/board/ti/cc26x2x7-launchpad.cfg
diff --git a/tcl/board/ti/cc3200_launchxl.cfg b/tcl/board/ti/cc3200-launchxl.cfg
similarity index 100%
rename from tcl/board/ti/cc3200_launchxl.cfg
rename to tcl/board/ti/cc3200-launchxl.cfg
diff --git a/tcl/board/ti/cc3220sf_launchpad.cfg b/tcl/board/ti/cc3220sf-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/cc3220sf_launchpad.cfg
rename to tcl/board/ti/cc3220sf-launchpad.cfg
diff --git a/tcl/board/ti/cc32xx_launchpad.cfg b/tcl/board/ti/cc32xx-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/cc32xx_launchpad.cfg
rename to tcl/board/ti/cc32xx-launchpad.cfg
diff --git a/tcl/board/ti/msp432_launchpad.cfg b/tcl/board/ti/msp432-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/msp432_launchpad.cfg
rename to tcl/board/ti/msp432-launchpad.cfg
diff --git a/tcl/board/ti/mspm0_launchpad.cfg b/tcl/board/ti/mspm0-launchpad.cfg
similarity index 100%
rename from tcl/board/ti/mspm0_launchpad.cfg
rename to tcl/board/ti/mspm0-launchpad.cfg
diff --git a/tcl/board/ti/omap2420_h4.cfg b/tcl/board/ti/omap2420-h4.cfg
similarity index 100%
rename from tcl/board/ti/omap2420_h4.cfg
rename to tcl/board/ti/omap2420-h4.cfg
diff --git a/tcl/board/ti/pandaboard_es.cfg b/tcl/board/ti/pandaboard-es.cfg
similarity index 100%
rename from tcl/board/ti/pandaboard_es.cfg
rename to tcl/board/ti/pandaboard-es.cfg
diff --git a/tcl/file_renaming.cfg b/tcl/file_renaming.cfg
index 0a80d8033..1603e2321 100644
--- a/tcl/file_renaming.cfg
+++ b/tcl/file_renaming.cfg
@@ -17,13 +17,25 @@ set _file_renaming {
board/nordic_nrf51822_mkit.cfg board/nordic/nrf51822-mkit.cfg
board/nordic_nrf51_dk.cfg board/nordic/nrf51-dk.cfg
board/nordic_nrf52_dk.cfg board/nordic/nrf52-dk.cfg
+ board/omap2420_h4.cfg board/ti/omap2420-h4.cfg
board/stm32mp13x_dk.cfg board/st/stm32mp135f-dk.cfg
board/stm32mp15x_dk2.cfg board/st/stm32mp157f-dk2.cfg
board/sifive-hifive1-revb.cfg board/sifive/hifive1-rev-b.cfg
+ board/ti_am437x_idk.cfg board/ti/am437x-idk.cfg
+ board/ti_am43xx_evm.cfg board/ti/am43xx-evm.cfg
board/ti_beagleboard.cfg board/beagle/beagleboard.cfg
board/ti_beagleboard_xm.cfg board/beagle/beagleboard-xm.cfg
board/ti_beaglebone_black.cfg board/beagle/beaglebone-black.cfg
board/ti_beaglebone.cfg board/beagle/beaglebone.cfg
+ board/ti_cc13x0_launchpad.cfg board/ti/cc13x0-launchpad.cfg
+ board/ti_cc13x2_launchpad.cfg board/ti/cc13x2-launchpad.cfg
+ board/ti_cc26x0_launchpad.cfg board/ti/cc26x0-launchpad.cfg
+ board/ti_cc26x2_launchpad.cfg board/ti/cc26x2-launchpad.cfg
+ board/ti_cc3200_launchxl.cfg board/ti/cc3200-launchxl.cfg
+ board/ti_cc3220sf_launchpad.cfg board/ti/cc3220sf-launchpad.cfg
+ board/ti_cc32xx_launchpad.cfg board/ti/cc32xx-launchpad.cfg
+ board/ti_msp432_launchpad.cfg board/ti/msp432-launchpad.cfg
+ board/ti_pandaboard_es.cfg board/ti/pandaboard-es.cfg
interface/chameleon.cfg interface/parport/chameleon.cfg
interface/flashlink.cfg interface/parport/flashlink.cfg
}
commit 6a5e4dc2a37c2dd0386a0495c89763b1bdd1b03c
Author: Nishanth Menon <nm...@ti...>
Date: Mon Nov 3 11:39:34 2025 -0600
board/ti: Rename _swd_native.cfg as -self-hosted.cfg
Rename the _swd_native.cfg files as -self-hosted.cfg files as a better
representation of what we are using the configuration files to be.
Change-Id: I4eb469a219b83de6a9e7a8dfef5607306f59a7cd
Suggested-by: Antonio Borneo <bor...@gm...>
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9206
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 9f5ec2ff3..f623d716e 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3869,7 +3869,7 @@ device configuration, this function may be blocked out. Typical behavior
observed in such cases is a firewall exception report on the security
controller and armv8 processor reporting a system error.
-See @file{tcl/board/ti/am625_swd_native.cfg} for a sample configuration
+See @file{tcl/board/ti/am625-self-hosted.cfg} for a sample configuration
file.
@deffn {Command} {dmem info}
diff --git a/tcl/board/ti/am625_swd_native.cfg b/tcl/board/ti/am625-self-hosted.cfg
similarity index 100%
rename from tcl/board/ti/am625_swd_native.cfg
rename to tcl/board/ti/am625-self-hosted.cfg
diff --git a/tcl/board/ti/am62a7_swd_native.cfg b/tcl/board/ti/am62a7-self-hosted.cfg
similarity index 100%
rename from tcl/board/ti/am62a7_swd_native.cfg
rename to tcl/board/ti/am62a7-self-hosted.cfg
diff --git a/tcl/board/ti/am62p_swd_native.cfg b/tcl/board/ti/am62p-self-hosted.cfg
similarity index 100%
rename from tcl/board/ti/am62p_swd_native.cfg
rename to tcl/board/ti/am62p-self-hosted.cfg
diff --git a/tcl/board/ti/am64xx_swd_native.cfg b/tcl/board/ti/am64xx-self-hosted.cfg
similarity index 100%
rename from tcl/board/ti/am64xx_swd_native.cfg
rename to tcl/board/ti/am64xx-self-hosted.cfg
diff --git a/tcl/board/ti/j721e_swd_native.cfg b/tcl/board/ti/j721e-self-hosted.cfg
similarity index 100%
rename from tcl/board/ti/j721e_swd_native.cfg
rename to tcl/board/ti/j721e-self-hosted.cfg
diff --git a/tcl/board/ti/j722s_swd_native.cfg b/tcl/board/ti/j722s-self-hosted.cfg
similarity index 100%
rename from tcl/board/ti/j722s_swd_native.cfg
rename to tcl/board/ti/j722s-self-hosted.cfg
diff --git a/tcl/board/ti/j784s4_swd_native.cfg b/tcl/board/ti/j784s4-self-hosted.cfg
similarity index 100%
rename from tcl/board/ti/j784s4_swd_native.cfg
rename to tcl/board/ti/j784s4-self-hosted.cfg
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 2 +-
tcl/board/ti/{am243_launchpad.cfg => am243-launchpad.cfg} | 0
tcl/board/ti/{am261_launchpad.cfg => am261-launchpad.cfg} | 0
tcl/board/ti/{am263_launchpad.cfg => am263-launchpad.cfg} | 0
tcl/board/ti/{am263p_launchpad.cfg => am263p-launchpad.cfg} | 0
tcl/board/ti/{am273_launchpad.cfg => am273-launchpad.cfg} | 0
tcl/board/ti/{am437x_idk.cfg => am437x-idk.cfg} | 0
tcl/board/ti/{am43xx_evm.cfg => am43xx-evm.cfg} | 0
tcl/board/ti/{am625_swd_native.cfg => am625-self-hosted.cfg} | 0
.../ti/{am62a7_swd_native.cfg => am62a7-self-hosted.cfg} | 0
tcl/board/ti/{am62p_swd_native.cfg => am62p-self-hosted.cfg} | 0
.../ti/{am64xx_swd_native.cfg => am64xx-self-hosted.cfg} | 0
tcl/board/ti/{cc13x0_launchpad.cfg => cc13x0-launchpad.cfg} | 0
tcl/board/ti/{cc13x2_launchpad.cfg => cc13x2-launchpad.cfg} | 0
tcl/board/ti/{cc26x0_launchpad.cfg => cc26x0-launchpad.cfg} | 0
tcl/board/ti/{cc26x2_launchpad.cfg => cc26x2-launchpad.cfg} | 0
.../ti/{cc26x2x7_launchpad.cfg => cc26x2x7-launchpad.cfg} | 0
tcl/board/ti/{cc3200_launchxl.cfg => cc3200-launchxl.cfg} | 0
.../ti/{cc3220sf_launchpad.cfg => cc3220sf-launchpad.cfg} | 0
tcl/board/ti/{cc32xx_launchpad.cfg => cc32xx-launchpad.cfg} | 0
tcl/board/ti/{j721e_swd_native.cfg => j721e-self-hosted.cfg} | 0
tcl/board/ti/{j722s_swd_native.cfg => j722s-self-hosted.cfg} | 0
.../ti/{j784s4_swd_native.cfg => j784s4-self-hosted.cfg} | 0
tcl/board/ti/{msp432_launchpad.cfg => msp432-launchpad.cfg} | 0
tcl/board/ti/{mspm0_launchpad.cfg => mspm0-launchpad.cfg} | 0
tcl/board/ti/{omap2420_h4.cfg => omap2420-h4.cfg} | 0
tcl/board/ti/{pandaboard_es.cfg => pandaboard-es.cfg} | 0
tcl/file_renaming.cfg | 12 ++++++++++++
28 files changed, 13 insertions(+), 1 deletion(-)
rename tcl/board/ti/{am243_launchpad.cfg => am243-launchpad.cfg} (100%)
rename tcl/board/ti/{am261_launchpad.cfg => am261-launchpad.cfg} (100%)
rename tcl/board/ti/{am263_launchpad.cfg => am263-launchpad.cfg} (100%)
rename tcl/board/ti/{am263p_launchpad.cfg => am263p-launchpad.cfg} (100%)
rename tcl/board/ti/{am273_launchpad.cfg => am273-launchpad.cfg} (100%)
rename tcl/board/ti/{am437x_idk.cfg => am437x-idk.cfg} (100%)
rename tcl/board/ti/{am43xx_evm.cfg => am43xx-evm.cfg} (100%)
rename tcl/board/ti/{am625_swd_native.cfg => am625-self-hosted.cfg} (100%)
rename tcl/board/ti/{am62a7_swd_native.cfg => am62a7-self-hosted.cfg} (100%)
rename tcl/board/ti/{am62p_swd_native.cfg => am62p-self-hosted.cfg} (100%)
rename tcl/board/ti/{am64xx_swd_native.cfg => am64xx-self-hosted.cfg} (100%)
rename tcl/board/ti/{cc13x0_launchpad.cfg => cc13x0-launchpad.cfg} (100%)
rename tcl/board/ti/{cc13x2_launchpad.cfg => cc13x2-launchpad.cfg} (100%)
rename tcl/board/ti/{cc26x0_launchpad.cfg => cc26x0-launchpad.cfg} (100%)
rename tcl/board/ti/{cc26x2_launchpad.cfg => cc26x2-launchpad.cfg} (100%)
rename tcl/board/ti/{cc26x2x7_launchpad.cfg => cc26x2x7-launchpad.cfg} (100%)
rename tcl/board/ti/{cc3200_launchxl.cfg => cc3200-launchxl.cfg} (100%)
rename tcl/board/ti/{cc3220sf_launchpad.cfg => cc3220sf-launchpad.cfg} (100%)
rename tcl/board/ti/{cc32xx_launchpad.cfg => cc32xx-launchpad.cfg} (100%)
rename tcl/board/ti/{j721e_swd_native.cfg => j721e-self-hosted.cfg} (100%)
rename tcl/board/ti/{j722s_swd_native.cfg => j722s-self-hosted.cfg} (100%)
rename tcl/board/ti/{j784s4_swd_native.cfg => j784s4-self-hosted.cfg} (100%)
rename tcl/board/ti/{msp432_launchpad.cfg => msp432-launchpad.cfg} (100%)
rename tcl/board/ti/{mspm0_launchpad.cfg => mspm0-launchpad.cfg} (100%)
rename tcl/board/ti/{omap2420_h4.cfg => omap2420-h4.cfg} (100%)
rename tcl/board/ti/{pandaboard_es.cfg => pandaboard-es.cfg} (100%)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-12-13 17:20:39
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 13a082fc7ed6619c979fdf33a4a860760ba6d55d (commit)
via 19f5e2071579c4c0ff09e9cf510f807246794d6d (commit)
from 2f8ddc0835d67ff8ab5e3ca57ccd8c39b349d95e (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 13a082fc7ed6619c979fdf33a4a860760ba6d55d
Author: Nishanth Menon <nm...@ti...>
Date: Mon Nov 3 11:31:12 2025 -0600
board/ti_*.cfg: Move TI evm platform configurations to board/ti folder
As part of the cfg file cleanups, let us move the TI evms, launchpads
and other development platform configuration files to board/ti folder.
While at this, drop the "ti_" prefix as the folder structure gives us
the details anyways.
Change-Id: I929b88e0cf6527f3181820ad0b9b4744185eabaf
Suggested-by: Antonio Borneo <bor...@gm...>
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9205
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 533290382..9f5ec2ff3 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -3869,7 +3869,7 @@ device configuration, this function may be blocked out. Typical behavior
observed in such cases is a firewall exception report on the security
controller and armv8 processor reporting a system error.
-See @file{tcl/interface/ti_k3_am625-swd-native.cfg} for a sample configuration
+See @file{tcl/board/ti/am625_swd_native.cfg} for a sample configuration
file.
@deffn {Command} {dmem info}
diff --git a/tcl/board/dk-tm4c129.cfg b/tcl/board/dk-tm4c129.cfg
index 27bd432ce..2c5b5b151 100644
--- a/tcl/board/dk-tm4c129.cfg
+++ b/tcl/board/dk-tm4c129.cfg
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-echo "WARNING: board/dk-tm4c129.cfg is deprecated, please switch to board/ti_dk-tm4c129.cfg"
+echo "WARNING: board/dk-tm4c129.cfg is deprecated, please switch to board/ti/dk-tm4c129.cfg"
-source [find board/ti_dk-tm4c129.cfg]
+source [find board/ti/dk-tm4c129.cfg]
diff --git a/tcl/board/ek-tm4c123gxl.cfg b/tcl/board/ek-tm4c123gxl.cfg
index d569e58cd..b808731a6 100644
--- a/tcl/board/ek-tm4c123gxl.cfg
+++ b/tcl/board/ek-tm4c123gxl.cfg
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-echo "WARNING: board/ek-tm4c123gxl.cfg is deprecated, please switch to board/ti_ek-tm4c123gxl.cfg"
+echo "WARNING: board/ek-tm4c123gxl.cfg is deprecated, please switch to board/ti/ek-tm4c123gxl.cfg"
-source [find board/ti_ek-tm4c123gxl.cfg]
+source [find board/ti/ek-tm4c123gxl.cfg]
diff --git a/tcl/board/ek-tm4c1294xl.cfg b/tcl/board/ek-tm4c1294xl.cfg
index 5c1167451..0e8837c4e 100644
--- a/tcl/board/ek-tm4c1294xl.cfg
+++ b/tcl/board/ek-tm4c1294xl.cfg
@@ -1,5 +1,5 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-echo "WARNING: board/ek-tm4c1294xl.cfg is deprecated, please switch to board/ti_ek-tm4c1294xl.cfg"
+echo "WARNING: board/ek-tm4c1294xl.cfg is deprecated, please switch to board/ti/ek-tm4c1294xl.cfg"
-source [find board/ti_ek-tm4c1294xl.cfg]
+source [find board/ti/ek-tm4c1294xl.cfg]
diff --git a/tcl/board/ti_am243_launchpad.cfg b/tcl/board/ti/am243_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_am243_launchpad.cfg
rename to tcl/board/ti/am243_launchpad.cfg
diff --git a/tcl/board/ti_am261_launchpad.cfg b/tcl/board/ti/am261_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_am261_launchpad.cfg
rename to tcl/board/ti/am261_launchpad.cfg
diff --git a/tcl/board/ti_am263_launchpad.cfg b/tcl/board/ti/am263_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_am263_launchpad.cfg
rename to tcl/board/ti/am263_launchpad.cfg
diff --git a/tcl/board/ti_am263p_launchpad.cfg b/tcl/board/ti/am263p_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_am263p_launchpad.cfg
rename to tcl/board/ti/am263p_launchpad.cfg
diff --git a/tcl/board/ti_am273_launchpad.cfg b/tcl/board/ti/am273_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_am273_launchpad.cfg
rename to tcl/board/ti/am273_launchpad.cfg
diff --git a/tcl/board/ti_am335xevm.cfg b/tcl/board/ti/am335xevm.cfg
similarity index 100%
rename from tcl/board/ti_am335xevm.cfg
rename to tcl/board/ti/am335xevm.cfg
diff --git a/tcl/board/am3517evm.cfg b/tcl/board/ti/am3517evm.cfg
similarity index 100%
rename from tcl/board/am3517evm.cfg
rename to tcl/board/ti/am3517evm.cfg
diff --git a/tcl/board/ti_am437x_idk.cfg b/tcl/board/ti/am437x_idk.cfg
similarity index 100%
rename from tcl/board/ti_am437x_idk.cfg
rename to tcl/board/ti/am437x_idk.cfg
diff --git a/tcl/board/ti_am43xx_evm.cfg b/tcl/board/ti/am43xx_evm.cfg
similarity index 100%
rename from tcl/board/ti_am43xx_evm.cfg
rename to tcl/board/ti/am43xx_evm.cfg
diff --git a/tcl/board/ti_am625_swd_native.cfg b/tcl/board/ti/am625_swd_native.cfg
similarity index 100%
rename from tcl/board/ti_am625_swd_native.cfg
rename to tcl/board/ti/am625_swd_native.cfg
diff --git a/tcl/board/ti_am625evm.cfg b/tcl/board/ti/am625evm.cfg
similarity index 100%
rename from tcl/board/ti_am625evm.cfg
rename to tcl/board/ti/am625evm.cfg
diff --git a/tcl/board/ti_am62a7_swd_native.cfg b/tcl/board/ti/am62a7_swd_native.cfg
similarity index 100%
rename from tcl/board/ti_am62a7_swd_native.cfg
rename to tcl/board/ti/am62a7_swd_native.cfg
diff --git a/tcl/board/ti_am62a7evm.cfg b/tcl/board/ti/am62a7evm.cfg
similarity index 100%
rename from tcl/board/ti_am62a7evm.cfg
rename to tcl/board/ti/am62a7evm.cfg
diff --git a/tcl/board/ti_am62levm.cfg b/tcl/board/ti/am62levm.cfg
similarity index 100%
rename from tcl/board/ti_am62levm.cfg
rename to tcl/board/ti/am62levm.cfg
diff --git a/tcl/board/ti_am62p_swd_native.cfg b/tcl/board/ti/am62p_swd_native.cfg
similarity index 100%
rename from tcl/board/ti_am62p_swd_native.cfg
rename to tcl/board/ti/am62p_swd_native.cfg
diff --git a/tcl/board/ti_am62pevm.cfg b/tcl/board/ti/am62pevm.cfg
similarity index 100%
rename from tcl/board/ti_am62pevm.cfg
rename to tcl/board/ti/am62pevm.cfg
diff --git a/tcl/board/ti_am642evm.cfg b/tcl/board/ti/am642evm.cfg
similarity index 100%
rename from tcl/board/ti_am642evm.cfg
rename to tcl/board/ti/am642evm.cfg
diff --git a/tcl/board/ti_am64xx_swd_native.cfg b/tcl/board/ti/am64xx_swd_native.cfg
similarity index 100%
rename from tcl/board/ti_am64xx_swd_native.cfg
rename to tcl/board/ti/am64xx_swd_native.cfg
diff --git a/tcl/board/ti_am654evm.cfg b/tcl/board/ti/am654evm.cfg
similarity index 100%
rename from tcl/board/ti_am654evm.cfg
rename to tcl/board/ti/am654evm.cfg
diff --git a/tcl/board/ti_blaze.cfg b/tcl/board/ti/blaze.cfg
similarity index 100%
rename from tcl/board/ti_blaze.cfg
rename to tcl/board/ti/blaze.cfg
diff --git a/tcl/board/ti_cc13x0_launchpad.cfg b/tcl/board/ti/cc13x0_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_cc13x0_launchpad.cfg
rename to tcl/board/ti/cc13x0_launchpad.cfg
diff --git a/tcl/board/ti_cc13x2_launchpad.cfg b/tcl/board/ti/cc13x2_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_cc13x2_launchpad.cfg
rename to tcl/board/ti/cc13x2_launchpad.cfg
diff --git a/tcl/board/ti_cc26x0_launchpad.cfg b/tcl/board/ti/cc26x0_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_cc26x0_launchpad.cfg
rename to tcl/board/ti/cc26x0_launchpad.cfg
diff --git a/tcl/board/ti_cc26x2_launchpad.cfg b/tcl/board/ti/cc26x2_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_cc26x2_launchpad.cfg
rename to tcl/board/ti/cc26x2_launchpad.cfg
diff --git a/tcl/board/ti_cc26x2x7_launchpad.cfg b/tcl/board/ti/cc26x2x7_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_cc26x2x7_launchpad.cfg
rename to tcl/board/ti/cc26x2x7_launchpad.cfg
diff --git a/tcl/board/ti_cc3200_launchxl.cfg b/tcl/board/ti/cc3200_launchxl.cfg
similarity index 100%
rename from tcl/board/ti_cc3200_launchxl.cfg
rename to tcl/board/ti/cc3200_launchxl.cfg
diff --git a/tcl/board/ti_cc3220sf_launchpad.cfg b/tcl/board/ti/cc3220sf_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_cc3220sf_launchpad.cfg
rename to tcl/board/ti/cc3220sf_launchpad.cfg
diff --git a/tcl/board/ti_cc32xx_launchpad.cfg b/tcl/board/ti/cc32xx_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_cc32xx_launchpad.cfg
rename to tcl/board/ti/cc32xx_launchpad.cfg
diff --git a/tcl/board/da850evm.cfg b/tcl/board/ti/da850evm.cfg
similarity index 85%
rename from tcl/board/da850evm.cfg
rename to tcl/board/ti/da850evm.cfg
index 736467cf6..eff7cf4e8 100644
--- a/tcl/board/da850evm.cfg
+++ b/tcl/board/ti/da850evm.cfg
@@ -9,4 +9,4 @@ source [find target/ti/omapl138.cfg]
reset_config trst_and_srst separate
#currently any pinmux/timing must be setup by UBL before openocd can do debug
-#TODO: implement pinmux/timing on reset like in board/dm365evm.cfg
+#TODO: implement pinmux/timing on reset like in board/ti/dm365evm.cfg
diff --git a/tcl/board/ti_dk-tm4c129.cfg b/tcl/board/ti/dk-tm4c129.cfg
similarity index 100%
rename from tcl/board/ti_dk-tm4c129.cfg
rename to tcl/board/ti/dk-tm4c129.cfg
diff --git a/tcl/board/dm355evm.cfg b/tcl/board/ti/dm355evm.cfg
similarity index 100%
rename from tcl/board/dm355evm.cfg
rename to tcl/board/ti/dm355evm.cfg
diff --git a/tcl/board/dm365evm.cfg b/tcl/board/ti/dm365evm.cfg
similarity index 100%
rename from tcl/board/dm365evm.cfg
rename to tcl/board/ti/dm365evm.cfg
diff --git a/tcl/board/dm6446evm.cfg b/tcl/board/ti/dm6446evm.cfg
similarity index 100%
rename from tcl/board/dm6446evm.cfg
rename to tcl/board/ti/dm6446evm.cfg
diff --git a/tcl/board/ek-lm3s1968.cfg b/tcl/board/ti/ek-lm3s1968.cfg
similarity index 100%
rename from tcl/board/ek-lm3s1968.cfg
rename to tcl/board/ti/ek-lm3s1968.cfg
diff --git a/tcl/board/ek-lm3s3748.cfg b/tcl/board/ti/ek-lm3s3748.cfg
similarity index 100%
rename from tcl/board/ek-lm3s3748.cfg
rename to tcl/board/ti/ek-lm3s3748.cfg
diff --git a/tcl/board/ek-lm3s6965.cfg b/tcl/board/ti/ek-lm3s6965.cfg
similarity index 100%
rename from tcl/board/ek-lm3s6965.cfg
rename to tcl/board/ti/ek-lm3s6965.cfg
diff --git a/tcl/board/ek-lm3s811-revb.cfg b/tcl/board/ti/ek-lm3s811-revb.cfg
similarity index 92%
rename from tcl/board/ek-lm3s811-revb.cfg
rename to tcl/board/ti/ek-lm3s811-revb.cfg
index 2006992b3..baa4d63ab 100644
--- a/tcl/board/ek-lm3s811-revb.cfg
+++ b/tcl/board/ti/ek-lm3s811-revb.cfg
@@ -7,7 +7,7 @@
#
# NOTE: newer 811-EK boards (rev C and above) shouldn't use this.
-# use board/ek-lm3s811.cfg
+# use board/ti/ek-lm3s811.cfg
source [find interface/ftdi/luminary-lm3s811.cfg]
# include the target config
diff --git a/tcl/board/ek-lm3s811.cfg b/tcl/board/ti/ek-lm3s811.cfg
similarity index 100%
rename from tcl/board/ek-lm3s811.cfg
rename to tcl/board/ti/ek-lm3s811.cfg
diff --git a/tcl/board/ek-lm3s8962.cfg b/tcl/board/ti/ek-lm3s8962.cfg
similarity index 100%
rename from tcl/board/ek-lm3s8962.cfg
rename to tcl/board/ti/ek-lm3s8962.cfg
diff --git a/tcl/board/ek-lm3s9b9x.cfg b/tcl/board/ti/ek-lm3s9b9x.cfg
similarity index 100%
rename from tcl/board/ek-lm3s9b9x.cfg
rename to tcl/board/ti/ek-lm3s9b9x.cfg
diff --git a/tcl/board/ek-lm3s9d92.cfg b/tcl/board/ti/ek-lm3s9d92.cfg
similarity index 100%
rename from tcl/board/ek-lm3s9d92.cfg
rename to tcl/board/ti/ek-lm3s9d92.cfg
diff --git a/tcl/board/ek-lm4f120xl.cfg b/tcl/board/ti/ek-lm4f120xl.cfg
similarity index 100%
rename from tcl/board/ek-lm4f120xl.cfg
rename to tcl/board/ti/ek-lm4f120xl.cfg
diff --git a/tcl/board/ek-lm4f232.cfg b/tcl/board/ti/ek-lm4f232.cfg
similarity index 100%
rename from tcl/board/ek-lm4f232.cfg
rename to tcl/board/ti/ek-lm4f232.cfg
diff --git a/tcl/board/ti_ek-tm4c123gxl.cfg b/tcl/board/ti/ek-tm4c123gxl.cfg
similarity index 100%
rename from tcl/board/ti_ek-tm4c123gxl.cfg
rename to tcl/board/ti/ek-tm4c123gxl.cfg
diff --git a/tcl/board/ti_ek-tm4c1294xl.cfg b/tcl/board/ti/ek-tm4c1294xl.cfg
similarity index 100%
rename from tcl/board/ti_ek-tm4c1294xl.cfg
rename to tcl/board/ti/ek-tm4c1294xl.cfg
diff --git a/tcl/board/ti_j7200evm.cfg b/tcl/board/ti/j7200evm.cfg
similarity index 100%
rename from tcl/board/ti_j7200evm.cfg
rename to tcl/board/ti/j7200evm.cfg
diff --git a/tcl/board/ti_j721e_swd_native.cfg b/tcl/board/ti/j721e_swd_native.cfg
similarity index 100%
rename from tcl/board/ti_j721e_swd_native.cfg
rename to tcl/board/ti/j721e_swd_native.cfg
diff --git a/tcl/board/ti_j721evm.cfg b/tcl/board/ti/j721evm.cfg
similarity index 100%
rename from tcl/board/ti_j721evm.cfg
rename to tcl/board/ti/j721evm.cfg
diff --git a/tcl/board/ti_j721s2evm.cfg b/tcl/board/ti/j721s2evm.cfg
similarity index 100%
rename from tcl/board/ti_j721s2evm.cfg
rename to tcl/board/ti/j721s2evm.cfg
diff --git a/tcl/board/ti_j722s_swd_native.cfg b/tcl/board/ti/j722s_swd_native.cfg
similarity index 100%
rename from tcl/board/ti_j722s_swd_native.cfg
rename to tcl/board/ti/j722s_swd_native.cfg
diff --git a/tcl/board/ti_j722sevm.cfg b/tcl/board/ti/j722sevm.cfg
similarity index 100%
rename from tcl/board/ti_j722sevm.cfg
rename to tcl/board/ti/j722sevm.cfg
diff --git a/tcl/board/ti_j784s4_swd_native.cfg b/tcl/board/ti/j784s4_swd_native.cfg
similarity index 100%
rename from tcl/board/ti_j784s4_swd_native.cfg
rename to tcl/board/ti/j784s4_swd_native.cfg
diff --git a/tcl/board/ti_j784s4evm.cfg b/tcl/board/ti/j784s4evm.cfg
similarity index 100%
rename from tcl/board/ti_j784s4evm.cfg
rename to tcl/board/ti/j784s4evm.cfg
diff --git a/tcl/board/ti_msp432_launchpad.cfg b/tcl/board/ti/msp432_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_msp432_launchpad.cfg
rename to tcl/board/ti/msp432_launchpad.cfg
diff --git a/tcl/board/ti_mspm0_launchpad.cfg b/tcl/board/ti/mspm0_launchpad.cfg
similarity index 100%
rename from tcl/board/ti_mspm0_launchpad.cfg
rename to tcl/board/ti/mspm0_launchpad.cfg
diff --git a/tcl/board/omap2420_h4.cfg b/tcl/board/ti/omap2420_h4.cfg
similarity index 100%
rename from tcl/board/omap2420_h4.cfg
rename to tcl/board/ti/omap2420_h4.cfg
diff --git a/tcl/board/osk5912.cfg b/tcl/board/ti/osk5912.cfg
similarity index 100%
rename from tcl/board/osk5912.cfg
rename to tcl/board/ti/osk5912.cfg
diff --git a/tcl/board/ti_pandaboard.cfg b/tcl/board/ti/pandaboard.cfg
similarity index 100%
rename from tcl/board/ti_pandaboard.cfg
rename to tcl/board/ti/pandaboard.cfg
diff --git a/tcl/board/ti_pandaboard_es.cfg b/tcl/board/ti/pandaboard_es.cfg
similarity index 100%
rename from tcl/board/ti_pandaboard_es.cfg
rename to tcl/board/ti/pandaboard_es.cfg
diff --git a/tcl/board/ti_tmdx570ls20susb.cfg b/tcl/board/ti/tmdx570ls20susb.cfg
similarity index 100%
rename from tcl/board/ti_tmdx570ls20susb.cfg
rename to tcl/board/ti/tmdx570ls20susb.cfg
diff --git a/tcl/board/ti_tmdx570ls31usb.cfg b/tcl/board/ti/tmdx570ls31usb.cfg
similarity index 100%
rename from tcl/board/ti_tmdx570ls31usb.cfg
rename to tcl/board/ti/tmdx570ls31usb.cfg
commit 19f5e2071579c4c0ff09e9cf510f807246794d6d
Author: Nishanth Menon <nm...@ti...>
Date: Mon Nov 3 11:25:15 2025 -0600
tcl/board/ti_beagle* move to board/beagle/ folder
Move the BeagleBoard.org Foundation boards to it's own folder. This
allows additional support such as BeagleV-Fire and other non TI SoC
vendor support to be subsequently added.
While doing this,
* Use "-" as separator for the file names as recommended
by coding standards.
* To maintain compatibility, add the non-trivial renames to
file_renaming.cfg
Change-Id: Ie916c9bf81fc3922bf19ed9ed2db841549d29ca9
Suggested-by: Antonio Borneo <bor...@gm...>
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9204
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/tcl/board/ti_beagleboard_xm.cfg b/tcl/board/beagle/beagleboard-xm.cfg
similarity index 100%
rename from tcl/board/ti_beagleboard_xm.cfg
rename to tcl/board/beagle/beagleboard-xm.cfg
diff --git a/tcl/board/ti_beagleboard.cfg b/tcl/board/beagle/beagleboard.cfg
similarity index 100%
rename from tcl/board/ti_beagleboard.cfg
rename to tcl/board/beagle/beagleboard.cfg
diff --git a/tcl/board/ti_beaglebone-base.cfg b/tcl/board/beagle/beaglebone-base.cfg
similarity index 100%
rename from tcl/board/ti_beaglebone-base.cfg
rename to tcl/board/beagle/beaglebone-base.cfg
diff --git a/tcl/board/ti_beaglebone_black.cfg b/tcl/board/beagle/beaglebone-black.cfg
similarity index 76%
rename from tcl/board/ti_beaglebone_black.cfg
rename to tcl/board/beagle/beaglebone-black.cfg
index d72bf09dd..89928d76f 100644
--- a/tcl/board/ti_beaglebone_black.cfg
+++ b/tcl/board/beagle/beaglebone-black.cfg
@@ -7,4 +7,4 @@ adapter speed 1000
reset_config trst_and_srst
-source [find board/ti_beaglebone-base.cfg]
+source [find board/beagle/beaglebone-base.cfg]
diff --git a/tcl/board/ti_beaglebone.cfg b/tcl/board/beagle/beaglebone.cfg
similarity index 83%
rename from tcl/board/ti_beaglebone.cfg
rename to tcl/board/beagle/beaglebone.cfg
index d96e45f6a..f09b51e86 100644
--- a/tcl/board/ti_beaglebone.cfg
+++ b/tcl/board/beagle/beaglebone.cfg
@@ -10,4 +10,4 @@ adapter speed 16000
reset_config trst_and_srst
-source [find board/ti_beaglebone-base.cfg]
+source [find board/beagle/beaglebone-base.cfg]
diff --git a/tcl/file_renaming.cfg b/tcl/file_renaming.cfg
index 79932473e..0a80d8033 100644
--- a/tcl/file_renaming.cfg
+++ b/tcl/file_renaming.cfg
@@ -20,6 +20,10 @@ set _file_renaming {
board/stm32mp13x_dk.cfg board/st/stm32mp135f-dk.cfg
board/stm32mp15x_dk2.cfg board/st/stm32mp157f-dk2.cfg
board/sifive-hifive1-revb.cfg board/sifive/hifive1-rev-b.cfg
+ board/ti_beagleboard.cfg board/beagle/beagleboard.cfg
+ board/ti_beagleboard_xm.cfg board/beagle/beagleboard-xm.cfg
+ board/ti_beaglebone_black.cfg board/beagle/beaglebone-black.cfg
+ board/ti_beaglebone.cfg board/beagle/beaglebone.cfg
interface/chameleon.cfg interface/parport/chameleon.cfg
interface/flashlink.cfg interface/parport/flashlink.cfg
}
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 2 +-
tcl/board/{ti_beagleboard_xm.cfg => beagle/beagleboard-xm.cfg} | 0
tcl/board/{ti_beagleboard.cfg => beagle/beagleboard.cfg} | 0
tcl/board/{ti_beaglebone-base.cfg => beagle/beaglebone-base.cfg} | 0
tcl/board/{ti_beaglebone_black.cfg => beagle/beaglebone-black.cfg} | 2 +-
tcl/board/{ti_beaglebone.cfg => beagle/beaglebone.cfg} | 2 +-
tcl/board/dk-tm4c129.cfg | 4 ++--
tcl/board/ek-tm4c123gxl.cfg | 4 ++--
tcl/board/ek-tm4c1294xl.cfg | 4 ++--
tcl/board/{ti_am243_launchpad.cfg => ti/am243_launchpad.cfg} | 0
tcl/board/{ti_am261_launchpad.cfg => ti/am261_launchpad.cfg} | 0
tcl/board/{ti_am263_launchpad.cfg => ti/am263_launchpad.cfg} | 0
tcl/board/{ti_am263p_launchpad.cfg => ti/am263p_launchpad.cfg} | 0
tcl/board/{ti_am273_launchpad.cfg => ti/am273_launchpad.cfg} | 0
tcl/board/{ti_am335xevm.cfg => ti/am335xevm.cfg} | 0
tcl/board/{ => ti}/am3517evm.cfg | 0
tcl/board/{ti_am437x_idk.cfg => ti/am437x_idk.cfg} | 0
tcl/board/{ti_am43xx_evm.cfg => ti/am43xx_evm.cfg} | 0
tcl/board/{ti_am625_swd_native.cfg => ti/am625_swd_native.cfg} | 0
tcl/board/{ti_am625evm.cfg => ti/am625evm.cfg} | 0
tcl/board/{ti_am62a7_swd_native.cfg => ti/am62a7_swd_native.cfg} | 0
tcl/board/{ti_am62a7evm.cfg => ti/am62a7evm.cfg} | 0
tcl/board/{ti_am62levm.cfg => ti/am62levm.cfg} | 0
tcl/board/{ti_am62p_swd_native.cfg => ti/am62p_swd_native.cfg} | 0
tcl/board/{ti_am62pevm.cfg => ti/am62pevm.cfg} | 0
tcl/board/{ti_am642evm.cfg => ti/am642evm.cfg} | 0
tcl/board/{ti_am64xx_swd_native.cfg => ti/am64xx_swd_native.cfg} | 0
tcl/board/{ti_am654evm.cfg => ti/am654evm.cfg} | 0
tcl/board/{ti_blaze.cfg => ti/blaze.cfg} | 0
tcl/board/{ti_cc13x0_launchpad.cfg => ti/cc13x0_launchpad.cfg} | 0
tcl/board/{ti_cc13x2_launchpad.cfg => ti/cc13x2_launchpad.cfg} | 0
tcl/board/{ti_cc26x0_launchpad.cfg => ti/cc26x0_launchpad.cfg} | 0
tcl/board/{ti_cc26x2_launchpad.cfg => ti/cc26x2_launchpad.cfg} | 0
tcl/board/{ti_cc26x2x7_launchpad.cfg => ti/cc26x2x7_launchpad.cfg} | 0
tcl/board/{ti_cc3200_launchxl.cfg => ti/cc3200_launchxl.cfg} | 0
tcl/board/{ti_cc3220sf_launchpad.cfg => ti/cc3220sf_launchpad.cfg} | 0
tcl/board/{ti_cc32xx_launchpad.cfg => ti/cc32xx_launchpad.cfg} | 0
tcl/board/{ => ti}/da850evm.cfg | 2 +-
tcl/board/{ti_dk-tm4c129.cfg => ti/dk-tm4c129.cfg} | 0
tcl/board/{ => ti}/dm355evm.cfg | 0
tcl/board/{ => ti}/dm365evm.cfg | 0
tcl/board/{ => ti}/dm6446evm.cfg | 0
tcl/board/{ => ti}/ek-lm3s1968.cfg | 0
tcl/board/{ => ti}/ek-lm3s3748.cfg | 0
tcl/board/{ => ti}/ek-lm3s6965.cfg | 0
tcl/board/{ => ti}/ek-lm3s811-revb.cfg | 2 +-
tcl/board/{ => ti}/ek-lm3s811.cfg | 0
tcl/board/{ => ti}/ek-lm3s8962.cfg | 0
tcl/board/{ => ti}/ek-lm3s9b9x.cfg | 0
tcl/board/{ => ti}/ek-lm3s9d92.cfg | 0
tcl/board/{ => ti}/ek-lm4f120xl.cfg | 0
tcl/board/{ => ti}/ek-lm4f232.cfg | 0
tcl/board/{ti_ek-tm4c123gxl.cfg => ti/ek-tm4c123gxl.cfg} | 0
tcl/board/{ti_ek-tm4c1294xl.cfg => ti/ek-tm4c1294xl.cfg} | 0
tcl/board/{ti_j7200evm.cfg => ti/j7200evm.cfg} | 0
tcl/board/{ti_j721e_swd_native.cfg => ti/j721e_swd_native.cfg} | 0
tcl/board/{ti_j721evm.cfg => ti/j721evm.cfg} | 0
tcl/board/{ti_j721s2evm.cfg => ti/j721s2evm.cfg} | 0
tcl/board/{ti_j722s_swd_native.cfg => ti/j722s_swd_native.cfg} | 0
tcl/board/{ti_j722sevm.cfg => ti/j722sevm.cfg} | 0
tcl/board/{ti_j784s4_swd_native.cfg => ti/j784s4_swd_native.cfg} | 0
tcl/board/{ti_j784s4evm.cfg => ti/j784s4evm.cfg} | 0
tcl/board/{ti_msp432_launchpad.cfg => ti/msp432_launchpad.cfg} | 0
tcl/board/{ti_mspm0_launchpad.cfg => ti/mspm0_launchpad.cfg} | 0
tcl/board/{ => ti}/omap2420_h4.cfg | 0
tcl/board/{ => ti}/osk5912.cfg | 0
tcl/board/{ti_pandaboard.cfg => ti/pandaboard.cfg} | 0
tcl/board/{ti_pandaboard_es.cfg => ti/pandaboard_es.cfg} | 0
tcl/board/{ti_tmdx570ls20susb.cfg => ti/tmdx570ls20susb.cfg} | 0
tcl/board/{ti_tmdx570ls31usb.cfg => ti/tmdx570ls31usb.cfg} | 0
tcl/file_renaming.cfg | 4 ++++
71 files changed, 15 insertions(+), 11 deletions(-)
rename tcl/board/{ti_beagleboard_xm.cfg => beagle/beagleboard-xm.cfg} (100%)
rename tcl/board/{ti_beagleboard.cfg => beagle/beagleboard.cfg} (100%)
rename tcl/board/{ti_beaglebone-base.cfg => beagle/beaglebone-base.cfg} (100%)
rename tcl/board/{ti_beaglebone_black.cfg => beagle/beaglebone-black.cfg} (76%)
rename tcl/board/{ti_beaglebone.cfg => beagle/beaglebone.cfg} (83%)
rename tcl/board/{ti_am243_launchpad.cfg => ti/am243_launchpad.cfg} (100%)
rename tcl/board/{ti_am261_launchpad.cfg => ti/am261_launchpad.cfg} (100%)
rename tcl/board/{ti_am263_launchpad.cfg => ti/am263_launchpad.cfg} (100%)
rename tcl/board/{ti_am263p_launchpad.cfg => ti/am263p_launchpad.cfg} (100%)
rename tcl/board/{ti_am273_launchpad.cfg => ti/am273_launchpad.cfg} (100%)
rename tcl/board/{ti_am335xevm.cfg => ti/am335xevm.cfg} (100%)
rename tcl/board/{ => ti}/am3517evm.cfg (100%)
rename tcl/board/{ti_am437x_idk.cfg => ti/am437x_idk.cfg} (100%)
rename tcl/board/{ti_am43xx_evm.cfg => ti/am43xx_evm.cfg} (100%)
rename tcl/board/{ti_am625_swd_native.cfg => ti/am625_swd_native.cfg} (100%)
rename tcl/board/{ti_am625evm.cfg => ti/am625evm.cfg} (100%)
rename tcl/board/{ti_am62a7_swd_native.cfg => ti/am62a7_swd_native.cfg} (100%)
rename tcl/board/{ti_am62a7evm.cfg => ti/am62a7evm.cfg} (100%)
rename tcl/board/{ti_am62levm.cfg => ti/am62levm.cfg} (100%)
rename tcl/board/{ti_am62p_swd_native.cfg => ti/am62p_swd_native.cfg} (100%)
rename tcl/board/{ti_am62pevm.cfg => ti/am62pevm.cfg} (100%)
rename tcl/board/{ti_am642evm.cfg => ti/am642evm.cfg} (100%)
rename tcl/board/{ti_am64xx_swd_native.cfg => ti/am64xx_swd_native.cfg} (100%)
rename tcl/board/{ti_am654evm.cfg => ti/am654evm.cfg} (100%)
rename tcl/board/{ti_blaze.cfg => ti/blaze.cfg} (100%)
rename tcl/board/{ti_cc13x0_launchpad.cfg => ti/cc13x0_launchpad.cfg} (100%)
rename tcl/board/{ti_cc13x2_launchpad.cfg => ti/cc13x2_launchpad.cfg} (100%)
rename tcl/board/{ti_cc26x0_launchpad.cfg => ti/cc26x0_launchpad.cfg} (100%)
rename tcl/board/{ti_cc26x2_launchpad.cfg => ti/cc26x2_launchpad.cfg} (100%)
rename tcl/board/{ti_cc26x2x7_launchpad.cfg => ti/cc26x2x7_launchpad.cfg} (100%)
rename tcl/board/{ti_cc3200_launchxl.cfg => ti/cc3200_launchxl.cfg} (100%)
rename tcl/board/{ti_cc3220sf_launchpad.cfg => ti/cc3220sf_launchpad.cfg} (100%)
rename tcl/board/{ti_cc32xx_launchpad.cfg => ti/cc32xx_launchpad.cfg} (100%)
rename tcl/board/{ => ti}/da850evm.cfg (85%)
rename tcl/board/{ti_dk-tm4c129.cfg => ti/dk-tm4c129.cfg} (100%)
rename tcl/board/{ => ti}/dm355evm.cfg (100%)
rename tcl/board/{ => ti}/dm365evm.cfg (100%)
rename tcl/board/{ => ti}/dm6446evm.cfg (100%)
rename tcl/board/{ => ti}/ek-lm3s1968.cfg (100%)
rename tcl/board/{ => ti}/ek-lm3s3748.cfg (100%)
rename tcl/board/{ => ti}/ek-lm3s6965.cfg (100%)
rename tcl/board/{ => ti}/ek-lm3s811-revb.cfg (92%)
rename tcl/board/{ => ti}/ek-lm3s811.cfg (100%)
rename tcl/board/{ => ti}/ek-lm3s8962.cfg (100%)
rename tcl/board/{ => ti}/ek-lm3s9b9x.cfg (100%)
rename tcl/board/{ => ti}/ek-lm3s9d92.cfg (100%)
rename tcl/board/{ => ti}/ek-lm4f120xl.cfg (100%)
rename tcl/board/{ => ti}/ek-lm4f232.cfg (100%)
rename tcl/board/{ti_ek-tm4c123gxl.cfg => ti/ek-tm4c123gxl.cfg} (100%)
rename tcl/board/{ti_ek-tm4c1294xl.cfg => ti/ek-tm4c1294xl.cfg} (100%)
rename tcl/board/{ti_j7200evm.cfg => ti/j7200evm.cfg} (100%)
rename tcl/board/{ti_j721e_swd_native.cfg => ti/j721e_swd_native.cfg} (100%)
rename tcl/board/{ti_j721evm.cfg => ti/j721evm.cfg} (100%)
rename tcl/board/{ti_j721s2evm.cfg => ti/j721s2evm.cfg} (100%)
rename tcl/board/{ti_j722s_swd_native.cfg => ti/j722s_swd_native.cfg} (100%)
rename tcl/board/{ti_j722sevm.cfg => ti/j722sevm.cfg} (100%)
rename tcl/board/{ti_j784s4_swd_native.cfg => ti/j784s4_swd_native.cfg} (100%)
rename tcl/board/{ti_j784s4evm.cfg => ti/j784s4evm.cfg} (100%)
rename tcl/board/{ti_msp432_launchpad.cfg => ti/msp432_launchpad.cfg} (100%)
rename tcl/board/{ti_mspm0_launchpad.cfg => ti/mspm0_launchpad.cfg} (100%)
rename tcl/board/{ => ti}/omap2420_h4.cfg (100%)
rename tcl/board/{ => ti}/osk5912.cfg (100%)
rename tcl/board/{ti_pandaboard.cfg => ti/pandaboard.cfg} (100%)
rename tcl/board/{ti_pandaboard_es.cfg => ti/pandaboard_es.cfg} (100%)
rename tcl/board/{ti_tmdx570ls20susb.cfg => ti/tmdx570ls20susb.cfg} (100%)
rename tcl/board/{ti_tmdx570ls31usb.cfg => ti/tmdx570ls31usb.cfg} (100%)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-12-13 17:20:23
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 2f8ddc0835d67ff8ab5e3ca57ccd8c39b349d95e (commit)
from 5479c58d23771c31d6f034a63b3f01b83ed5129a (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 2f8ddc0835d67ff8ab5e3ca57ccd8c39b349d95e
Author: Nishanth Menon <nm...@ti...>
Date: Mon Nov 3 11:02:57 2025 -0600
tcl/target: Move TI targets to ti folder
Move the ti targets to a TI folder. Since the folder is ti, we can
drop the "ti" prefix from the files themselves.
Done via the following script:
mkdir target/ti
FILES=`ls target/ti*.cfg target/omap*.cfg target/am335x.cfg
target/amdm37x.cfg target/icepick.cfg target/stellaris.cfg
target/davinci.cfg`
for cname in $FILES
do
bname=`basename $cname`
nname=`echo $bname|sed -e "s/^ti-//g"|sed -e "s/ti_//g"`
npath="target/ti/$nname"
echo "$cname => $npath"
fref=`git grep $cname .|cut -d ':' -f1|sort -u`
sed -i -e "s&$cname&$npath&g" $fref
git mv $cname $npath
done
Change-Id: I9f94dc6bb01f73721d4ff96be92cb51de2cbf0e2
Suggested-by: Antonio Borneo <bor...@gm...>
Signed-off-by: Nishanth Menon <nm...@ti...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9203
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/README b/README
index 73aa3a630..b99c6d813 100644
--- a/README
+++ b/README
@@ -38,7 +38,7 @@ e.g.:
```
openocd -f interface/ftdi/jtagkey2.cfg -c "transport select jtag" \
- -f target/ti_calypso.cfg
+ -f target/ti/calypso.cfg
```
```
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 82d2a9416..533290382 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1771,10 +1771,10 @@ There are more complex examples too, with chips that have
multiple TAPs. Ones worth looking at include:
@itemize
-@item @file{target/omap3530.cfg} -- with disabled ARM and DSP,
+@item @file{target/ti/omap3530.cfg} -- with disabled ARM and DSP,
plus a JRC to enable them
@item @file{target/str912.cfg} -- with flash, CPU, and boundary scan
-@item @file{target/ti_dm355.cfg} -- with ETM, ARM, and JRC (this JRC
+@item @file{target/ti/dm355.cfg} -- with ETM, ARM, and JRC (this JRC
is not currently used)
@end itemize
diff --git a/tcl/board/am3517evm.cfg b/tcl/board/am3517evm.cfg
index 0b19be68b..c76516608 100644
--- a/tcl/board/am3517evm.cfg
+++ b/tcl/board/am3517evm.cfg
@@ -13,7 +13,7 @@
# http://processors.wiki.ti.com/index.php?title=How_to_Find_the_Silicon_Revision_of_your_OMAP35x
set CHIPTYPE "am35x"
-source [find target/amdm37x.cfg]
+source [find target/ti/amdm37x.cfg]
# The TI-14 JTAG connector does not have srst. CPU reset is handled in
# hardware.
diff --git a/tcl/board/da850evm.cfg b/tcl/board/da850evm.cfg
index 12de3a7e3..736467cf6 100644
--- a/tcl/board/da850evm.cfg
+++ b/tcl/board/da850evm.cfg
@@ -4,7 +4,7 @@
# http://focus.ti.com/dsp/docs/thirdparty/catalog/devtoolsproductfolder.tsp?actionPerformed=productFolder&productId=5939
# http://www.logicpd.com/products/development-kits/zoom-omap-l138-evm-development-kit
-source [find target/omapl138.cfg]
+source [find target/ti/omapl138.cfg]
reset_config trst_and_srst separate
diff --git a/tcl/board/dm355evm.cfg b/tcl/board/dm355evm.cfg
index 0dbffa839..d7102b372 100644
--- a/tcl/board/dm355evm.cfg
+++ b/tcl/board/dm355evm.cfg
@@ -4,7 +4,7 @@
# http://focus.ti.com/docs/toolsw/folders/print/tmdsevm355.html
# http://c6000.spectrumdigital.com/evmdm355/
-source [find target/ti_dm355.cfg]
+source [find target/ti/dm355.cfg]
reset_config trst_and_srst separate
diff --git a/tcl/board/dm365evm.cfg b/tcl/board/dm365evm.cfg
index 15db24c20..113a4a3d1 100644
--- a/tcl/board/dm365evm.cfg
+++ b/tcl/board/dm365evm.cfg
@@ -4,7 +4,7 @@
# http://focus.ti.com/docs/toolsw/folders/print/tmdxevm365.html
# http://support.spectrumdigital.com/boards/evmdm365
-source [find target/ti_dm365.cfg]
+source [find target/ti/dm365.cfg]
# NOTE: in Rev C boards, the CPLD ignores SRST from the ARM-20 JTAG
# connector, so it doesn't affect generation of the reset signal.
diff --git a/tcl/board/dm6446evm.cfg b/tcl/board/dm6446evm.cfg
index 1236b8622..7f1b5b052 100644
--- a/tcl/board/dm6446evm.cfg
+++ b/tcl/board/dm6446evm.cfg
@@ -6,7 +6,7 @@
# EVM is just the board; buy that at Spectrum.
# The "kit" from TI also has: video camera, LCD video monitor, more.
-source [find target/ti_dm6446.cfg]
+source [find target/ti/dm6446.cfg]
# J4 controls what CS2 hooks up to, usually NOR or NAND flash.
# S3.1/S3.2 controls boot mode, which may force J4 and S3.3 settings.
diff --git a/tcl/board/ek-lm3s1968.cfg b/tcl/board/ek-lm3s1968.cfg
index c794a17a0..382865340 100644
--- a/tcl/board/ek-lm3s1968.cfg
+++ b/tcl/board/ek-lm3s1968.cfg
@@ -18,4 +18,4 @@ source [find interface/ftdi/luminary.cfg]
# include the target config
set WORKAREASIZE 0x2000
set CHIPNAME lm3s1968
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/ek-lm3s3748.cfg b/tcl/board/ek-lm3s3748.cfg
index 705cb64ce..c72af120f 100644
--- a/tcl/board/ek-lm3s3748.cfg
+++ b/tcl/board/ek-lm3s3748.cfg
@@ -13,4 +13,4 @@ source [find interface/ftdi/luminary.cfg]
# 20k working area
set WORKAREASIZE 0x4000
set CHIPNAME lm3s3748
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/ek-lm3s6965.cfg b/tcl/board/ek-lm3s6965.cfg
index ee4e15f8a..3ce2c5167 100644
--- a/tcl/board/ek-lm3s6965.cfg
+++ b/tcl/board/ek-lm3s6965.cfg
@@ -14,4 +14,4 @@ source [find interface/ftdi/luminary.cfg]
set WORKAREASIZE 0x5000
set CHIPNAME lm3s6965
# include the target config
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/ek-lm3s811-revb.cfg b/tcl/board/ek-lm3s811-revb.cfg
index f968eece5..2006992b3 100644
--- a/tcl/board/ek-lm3s811-revb.cfg
+++ b/tcl/board/ek-lm3s811-revb.cfg
@@ -13,4 +13,4 @@ source [find interface/ftdi/luminary-lm3s811.cfg]
# include the target config
set WORKAREASIZE 0x2000
set CHIPNAME lm3s811
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/ek-lm3s811.cfg b/tcl/board/ek-lm3s811.cfg
index 0cf36c284..9a36221ea 100644
--- a/tcl/board/ek-lm3s811.cfg
+++ b/tcl/board/ek-lm3s811.cfg
@@ -14,4 +14,4 @@ source [find interface/ftdi/luminary.cfg]
# include the target config
set WORKAREASIZE 0x2000
set CHIPNAME lm3s811
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/ek-lm3s8962.cfg b/tcl/board/ek-lm3s8962.cfg
index 71a1b1090..f58147edd 100644
--- a/tcl/board/ek-lm3s8962.cfg
+++ b/tcl/board/ek-lm3s8962.cfg
@@ -14,4 +14,4 @@ source [find interface/ftdi/luminary.cfg]
set WORKAREASIZE 0x10000
set CHIPNAME lm3s8962
# include the target config
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/ek-lm3s9b9x.cfg b/tcl/board/ek-lm3s9b9x.cfg
index 289a2cc09..b823b56cd 100644
--- a/tcl/board/ek-lm3s9b9x.cfg
+++ b/tcl/board/ek-lm3s9b9x.cfg
@@ -13,4 +13,4 @@ source [find interface/ftdi/luminary-icdi.cfg]
set WORKAREASIZE 0x4000
set CHIPNAME lm3s9b9x
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/ek-lm3s9d92.cfg b/tcl/board/ek-lm3s9d92.cfg
index 08bbbdb58..9f4dcaa35 100644
--- a/tcl/board/ek-lm3s9d92.cfg
+++ b/tcl/board/ek-lm3s9d92.cfg
@@ -13,4 +13,4 @@ source [find interface/ftdi/luminary-icdi.cfg]
# 64k working area
set WORKAREASIZE 0x10000
set CHIPNAME lm3s9d92
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/ek-lm4f120xl.cfg b/tcl/board/ek-lm4f120xl.cfg
index 44b1b1ea1..b1ab98668 100644
--- a/tcl/board/ek-lm4f120xl.cfg
+++ b/tcl/board/ek-lm4f120xl.cfg
@@ -16,4 +16,4 @@ transport select jtag
set WORKAREASIZE 0x8000
set CHIPNAME lm4f120h5qr
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/ek-lm4f232.cfg b/tcl/board/ek-lm4f232.cfg
index bb7f9ea5b..1fd05bb75 100644
--- a/tcl/board/ek-lm4f232.cfg
+++ b/tcl/board/ek-lm4f232.cfg
@@ -16,4 +16,4 @@ transport select jtag
set WORKAREASIZE 0x8000
set CHIPNAME lm4f23x
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/linksys-wag200g.cfg b/tcl/board/linksys-wag200g.cfg
index 26900a7d7..2150baf89 100644
--- a/tcl/board/linksys-wag200g.cfg
+++ b/tcl/board/linksys-wag200g.cfg
@@ -22,7 +22,7 @@ set partition_list {
adam2env { "Adam2 environment" 0x903f0000 0x00010000 }
}
-source [find target/ti-ar7.cfg]
+source [find target/ti/ar7.cfg]
# External 4MB MXIC 29LV320MBTC Flash (Manufacturer/Device: 0x00c2 0x227e)
set _FLASHNAME $_CHIPNAME.flash
diff --git a/tcl/board/netgear-dg834v3.cfg b/tcl/board/netgear-dg834v3.cfg
index a9938889c..4292ac406 100644
--- a/tcl/board/netgear-dg834v3.cfg
+++ b/tcl/board/netgear-dg834v3.cfg
@@ -12,7 +12,7 @@ set partition_list {
config { "Bootloader config space" 0x903f0000 0x00010000 }
}
-source [find target/ti-ar7.cfg]
+source [find target/ti/ar7.cfg]
# External 16MB SDRAM - disabled as we use internal sram
#$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 0x00001000
diff --git a/tcl/board/omap2420_h4.cfg b/tcl/board/omap2420_h4.cfg
index ec169654f..b3e9d7dab 100644
--- a/tcl/board/omap2420_h4.cfg
+++ b/tcl/board/omap2420_h4.cfg
@@ -2,7 +2,7 @@
# OMAP2420 SDP board ("H4")
-source [find target/omap2420.cfg]
+source [find target/ti/omap2420.cfg]
# NOTE: this assumes you're *NOT* using a TI-14 connector.
reset_config trst_and_srst separate
diff --git a/tcl/board/osk5912.cfg b/tcl/board/osk5912.cfg
index 0759a27ac..1f94c67a2 100644
--- a/tcl/board/osk5912.cfg
+++ b/tcl/board/osk5912.cfg
@@ -2,7 +2,7 @@
# http://omap.spectrumdigital.com/osk5912/
-source [find target/omap5912.cfg]
+source [find target/ti/omap5912.cfg]
# NOTE: this assumes you're using the ARM 20-pin ("Multi-ICE")
# JTAG connector, and accordingly have J1 connecting pins 1 & 2.
diff --git a/tcl/board/phone_se_j100i.cfg b/tcl/board/phone_se_j100i.cfg
index 70387ee15..09ea703c8 100644
--- a/tcl/board/phone_se_j100i.cfg
+++ b/tcl/board/phone_se_j100i.cfg
@@ -6,7 +6,7 @@
# more information can be found on
# http://bb.osmocom.org/trac/wiki/SonyEricssonJ100i
#
-source [find target/ti_calypso.cfg]
+source [find target/ti/calypso.cfg]
# external flash
diff --git a/tcl/board/ti/launchxl2-tms57012.cfg b/tcl/board/ti/launchxl2-tms57012.cfg
index 99cb26e20..ba305f691 100644
--- a/tcl/board/ti/launchxl2-tms57012.cfg
+++ b/tcl/board/ti/launchxl2-tms57012.cfg
@@ -7,4 +7,4 @@ source [find interface/xds110.cfg]
transport select jtag
-source [find target/ti_tms570ls1x.cfg]
+source [find target/ti/tms570ls1x.cfg]
diff --git a/tcl/board/ti_am243_launchpad.cfg b/tcl/board/ti_am243_launchpad.cfg
index aa75dda88..6833cdd67 100644
--- a/tcl/board/ti_am243_launchpad.cfg
+++ b/tcl/board/ti_am243_launchpad.cfg
@@ -20,6 +20,6 @@ if { ![info exists SOC] } {
set SOC am243
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 250
diff --git a/tcl/board/ti_am261_launchpad.cfg b/tcl/board/ti_am261_launchpad.cfg
index c6c4609ed..0a99d8b1e 100644
--- a/tcl/board/ti_am261_launchpad.cfg
+++ b/tcl/board/ti_am261_launchpad.cfg
@@ -20,6 +20,6 @@ if { ![info exists SOC] } {
set SOC am261
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 250
diff --git a/tcl/board/ti_am263_launchpad.cfg b/tcl/board/ti_am263_launchpad.cfg
index a07a21b3d..7d603d386 100644
--- a/tcl/board/ti_am263_launchpad.cfg
+++ b/tcl/board/ti_am263_launchpad.cfg
@@ -20,6 +20,6 @@ if { ![info exists SOC] } {
set SOC am263
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 250
diff --git a/tcl/board/ti_am263p_launchpad.cfg b/tcl/board/ti_am263p_launchpad.cfg
index 96e06fab6..25ae80d63 100644
--- a/tcl/board/ti_am263p_launchpad.cfg
+++ b/tcl/board/ti_am263p_launchpad.cfg
@@ -20,6 +20,6 @@ if { ![info exists SOC] } {
set SOC am263p
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 250
diff --git a/tcl/board/ti_am273_launchpad.cfg b/tcl/board/ti_am273_launchpad.cfg
index c17170bf1..6f10b6b62 100644
--- a/tcl/board/ti_am273_launchpad.cfg
+++ b/tcl/board/ti_am273_launchpad.cfg
@@ -20,6 +20,6 @@ if { ![info exists SOC] } {
set SOC am273
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 250
diff --git a/tcl/board/ti_am335xevm.cfg b/tcl/board/ti_am335xevm.cfg
index af058ecf7..cc64d5877 100644
--- a/tcl/board/ti_am335xevm.cfg
+++ b/tcl/board/ti_am335xevm.cfg
@@ -7,6 +7,6 @@
#
jtag_rclk 6000
-source [find target/am335x.cfg]
+source [find target/ti/am335x.cfg]
reset_config trst_and_srst
diff --git a/tcl/board/ti_am437x_idk.cfg b/tcl/board/ti_am437x_idk.cfg
index b4277628e..30f2580f6 100644
--- a/tcl/board/ti_am437x_idk.cfg
+++ b/tcl/board/ti_am437x_idk.cfg
@@ -8,7 +8,7 @@ source [find interface/ftdi/xds100v2.cfg]
transport select jtag
adapter speed 30000
-source [find target/am437x.cfg]
+source [find target/ti/am437x.cfg]
$_TARGETNAME configure -event reset-init { init_platform 0x61a11b32 }
reset_config trst_and_srst
diff --git a/tcl/board/ti_am43xx_evm.cfg b/tcl/board/ti_am43xx_evm.cfg
index 005421f42..1c3961820 100644
--- a/tcl/board/ti_am43xx_evm.cfg
+++ b/tcl/board/ti_am43xx_evm.cfg
@@ -4,6 +4,6 @@
transport select jtag
adapter speed 16000
-source [find target/am437x.cfg]
+source [find target/ti/am437x.cfg]
reset_config trst_and_srst
diff --git a/tcl/board/ti_am625_swd_native.cfg b/tcl/board/ti_am625_swd_native.cfg
index 65314fe5d..8891e021a 100644
--- a/tcl/board/ti_am625_swd_native.cfg
+++ b/tcl/board/ti_am625_swd_native.cfg
@@ -20,4 +20,4 @@ if { ![info exists SOC] } {
set SOC am625
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
diff --git a/tcl/board/ti_am625evm.cfg b/tcl/board/ti_am625evm.cfg
index 4906fd096..2df13cdae 100644
--- a/tcl/board/ti_am625evm.cfg
+++ b/tcl/board/ti_am625evm.cfg
@@ -20,6 +20,6 @@ if { ![info exists SOC] } {
set SOC am625
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 2500
diff --git a/tcl/board/ti_am62a7_swd_native.cfg b/tcl/board/ti_am62a7_swd_native.cfg
index 3d5e89228..4d5512688 100644
--- a/tcl/board/ti_am62a7_swd_native.cfg
+++ b/tcl/board/ti_am62a7_swd_native.cfg
@@ -20,4 +20,4 @@ if { ![info exists SOC] } {
set SOC am62a7
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
diff --git a/tcl/board/ti_am62a7evm.cfg b/tcl/board/ti_am62a7evm.cfg
index e40790950..1c90be8b1 100644
--- a/tcl/board/ti_am62a7evm.cfg
+++ b/tcl/board/ti_am62a7evm.cfg
@@ -20,6 +20,6 @@ if { ![info exists SOC] } {
set SOC am62a7
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 2500
diff --git a/tcl/board/ti_am62levm.cfg b/tcl/board/ti_am62levm.cfg
index 6debdd49f..53ac7a5a0 100644
--- a/tcl/board/ti_am62levm.cfg
+++ b/tcl/board/ti_am62levm.cfg
@@ -20,6 +20,6 @@ if { ![info exists SOC] } {
set SOC am62l
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 2500
diff --git a/tcl/board/ti_am62p_swd_native.cfg b/tcl/board/ti_am62p_swd_native.cfg
index a8c6bd120..55e6ea3d7 100644
--- a/tcl/board/ti_am62p_swd_native.cfg
+++ b/tcl/board/ti_am62p_swd_native.cfg
@@ -20,4 +20,4 @@ if { ![info exists SOC] } {
set SOC am62p
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
diff --git a/tcl/board/ti_am62pevm.cfg b/tcl/board/ti_am62pevm.cfg
index 2322b3d94..6c7f99a33 100644
--- a/tcl/board/ti_am62pevm.cfg
+++ b/tcl/board/ti_am62pevm.cfg
@@ -19,6 +19,6 @@ if { ![info exists SOC] } {
set SOC am62p
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 2500
diff --git a/tcl/board/ti_am642evm.cfg b/tcl/board/ti_am642evm.cfg
index e97fdcf13..a6cfacd80 100644
--- a/tcl/board/ti_am642evm.cfg
+++ b/tcl/board/ti_am642evm.cfg
@@ -19,6 +19,6 @@ if { ![info exists SOC] } {
set SOC am642
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 250
diff --git a/tcl/board/ti_am64xx_swd_native.cfg b/tcl/board/ti_am64xx_swd_native.cfg
index d3727149e..65e9e7c56 100644
--- a/tcl/board/ti_am64xx_swd_native.cfg
+++ b/tcl/board/ti_am64xx_swd_native.cfg
@@ -20,4 +20,4 @@ if { ![info exists SOC] } {
set SOC am642
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
diff --git a/tcl/board/ti_am654evm.cfg b/tcl/board/ti_am654evm.cfg
index a661f6068..e812feb6c 100644
--- a/tcl/board/ti_am654evm.cfg
+++ b/tcl/board/ti_am654evm.cfg
@@ -19,6 +19,6 @@ if { ![info exists SOC] } {
set SOC am654
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 2500
diff --git a/tcl/board/ti_beagleboard.cfg b/tcl/board/ti_beagleboard.cfg
index 6767bd6df..735708e80 100644
--- a/tcl/board/ti_beagleboard.cfg
+++ b/tcl/board/ti_beagleboard.cfg
@@ -6,7 +6,7 @@
# Fall back to 6MHz if RTCK is not supported
jtag_rclk 6000
-source [find target/omap3530.cfg]
+source [find target/ti/omap3530.cfg]
# TI-14 JTAG connector
reset_config trst_only
diff --git a/tcl/board/ti_beagleboard_xm.cfg b/tcl/board/ti_beagleboard_xm.cfg
index fd176a001..cd9a53c5f 100644
--- a/tcl/board/ti_beagleboard_xm.cfg
+++ b/tcl/board/ti_beagleboard_xm.cfg
@@ -4,7 +4,7 @@
# http://beagleboard.org
set CHIPTYPE "dm37x"
-source [find target/amdm37x.cfg]
+source [find target/ti/amdm37x.cfg]
# The TI-14 JTAG connector does not have srst. CPU reset is handled in
# hardware.
diff --git a/tcl/board/ti_beaglebone-base.cfg b/tcl/board/ti_beaglebone-base.cfg
index 566f0a4b3..db8432f4c 100644
--- a/tcl/board/ti_beaglebone-base.cfg
+++ b/tcl/board/ti_beaglebone-base.cfg
@@ -3,4 +3,4 @@
# AM335x Beaglebone family base configuration
# http://beagleboard.org/bone
-source [find target/am335x.cfg]
+source [find target/ti/am335x.cfg]
diff --git a/tcl/board/ti_blaze.cfg b/tcl/board/ti_blaze.cfg
index e28b05b83..e54903527 100644
--- a/tcl/board/ti_blaze.cfg
+++ b/tcl/board/ti_blaze.cfg
@@ -2,6 +2,6 @@
jtag_rclk 6000
-source [find target/omap4430.cfg]
+source [find target/ti/omap4430.cfg]
reset_config trst_and_srst
diff --git a/tcl/board/ti_cc13x0_launchpad.cfg b/tcl/board/ti_cc13x0_launchpad.cfg
index f6dfbcda3..e6904456c 100644
--- a/tcl/board/ti_cc13x0_launchpad.cfg
+++ b/tcl/board/ti_cc13x0_launchpad.cfg
@@ -6,4 +6,4 @@
source [find interface/xds110.cfg]
transport select jtag
adapter speed 5500
-source [find target/ti_cc13x0.cfg]
+source [find target/ti/cc13x0.cfg]
diff --git a/tcl/board/ti_cc13x2_launchpad.cfg b/tcl/board/ti_cc13x2_launchpad.cfg
index 900842a2f..1653224d1 100644
--- a/tcl/board/ti_cc13x2_launchpad.cfg
+++ b/tcl/board/ti_cc13x2_launchpad.cfg
@@ -6,4 +6,4 @@
source [find interface/xds110.cfg]
adapter speed 5500
transport select jtag
-source [find target/ti_cc13x2.cfg]
+source [find target/ti/cc13x2.cfg]
diff --git a/tcl/board/ti_cc26x0_launchpad.cfg b/tcl/board/ti_cc26x0_launchpad.cfg
index 431383db1..8e57cf2a4 100644
--- a/tcl/board/ti_cc26x0_launchpad.cfg
+++ b/tcl/board/ti_cc26x0_launchpad.cfg
@@ -6,4 +6,4 @@
source [find interface/xds110.cfg]
adapter speed 5500
transport select jtag
-source [find target/ti_cc26x0.cfg]
+source [find target/ti/cc26x0.cfg]
diff --git a/tcl/board/ti_cc26x2_launchpad.cfg b/tcl/board/ti_cc26x2_launchpad.cfg
index 133f57e07..931270e21 100644
--- a/tcl/board/ti_cc26x2_launchpad.cfg
+++ b/tcl/board/ti_cc26x2_launchpad.cfg
@@ -6,4 +6,4 @@
source [find interface/xds110.cfg]
adapter speed 5500
transport select jtag
-source [find target/ti_cc26x2.cfg]
+source [find target/ti/cc26x2.cfg]
diff --git a/tcl/board/ti_cc26x2x7_launchpad.cfg b/tcl/board/ti_cc26x2x7_launchpad.cfg
index 9e6e72e89..c1b6e059a 100644
--- a/tcl/board/ti_cc26x2x7_launchpad.cfg
+++ b/tcl/board/ti_cc26x2x7_launchpad.cfg
@@ -6,4 +6,4 @@
source [find interface/xds110.cfg]
adapter speed 5500
transport select jtag
-source [find target/ti_cc26x2x7.cfg]
+source [find target/ti/cc26x2x7.cfg]
diff --git a/tcl/board/ti_cc3200_launchxl.cfg b/tcl/board/ti_cc3200_launchxl.cfg
index 5f39b8a83..ca78cd19e 100644
--- a/tcl/board/ti_cc3200_launchxl.cfg
+++ b/tcl/board/ti_cc3200_launchxl.cfg
@@ -17,7 +17,7 @@ if { [info exists TRANSPORT] } {
adapter speed 2500
set WORKAREASIZE 0x40000
-source [find target/ti_cc32xx.cfg]
+source [find target/ti/cc32xx.cfg]
reset_config srst_only
adapter srst delay 1100
diff --git a/tcl/board/ti_cc3220sf_launchpad.cfg b/tcl/board/ti_cc3220sf_launchpad.cfg
index fe34554df..560e3ee25 100644
--- a/tcl/board/ti_cc3220sf_launchpad.cfg
+++ b/tcl/board/ti_cc3220sf_launchpad.cfg
@@ -6,4 +6,4 @@
source [find interface/xds110.cfg]
adapter speed 8500
transport select swd
-source [find target/ti_cc3220sf.cfg]
+source [find target/ti/cc3220sf.cfg]
diff --git a/tcl/board/ti_cc32xx_launchpad.cfg b/tcl/board/ti_cc32xx_launchpad.cfg
index 343da485d..41da72c3c 100644
--- a/tcl/board/ti_cc32xx_launchpad.cfg
+++ b/tcl/board/ti_cc32xx_launchpad.cfg
@@ -6,7 +6,7 @@
source [find interface/xds110.cfg]
adapter speed 8500
transport select swd
-source [find target/ti_cc32xx.cfg]
+source [find target/ti/cc32xx.cfg]
reset_config srst_only
adapter srst delay 1100
diff --git a/tcl/board/ti_dk-tm4c129.cfg b/tcl/board/ti_dk-tm4c129.cfg
index e0574fa87..d01b55966 100644
--- a/tcl/board/ti_dk-tm4c129.cfg
+++ b/tcl/board/ti_dk-tm4c129.cfg
@@ -13,4 +13,4 @@ transport select jtag
set WORKAREASIZE 0x8000
set CHIPNAME tm4c129xnczad
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/ti_ek-tm4c123gxl.cfg b/tcl/board/ti_ek-tm4c123gxl.cfg
index 7b8fc267f..2d1c1a771 100644
--- a/tcl/board/ti_ek-tm4c123gxl.cfg
+++ b/tcl/board/ti_ek-tm4c123gxl.cfg
@@ -12,4 +12,4 @@ transport select jtag
set WORKAREASIZE 0x8000
set CHIPNAME tm4c123gh6pm
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/ti_ek-tm4c1294xl.cfg b/tcl/board/ti_ek-tm4c1294xl.cfg
index 8cceb49c9..38e8f023b 100644
--- a/tcl/board/ti_ek-tm4c1294xl.cfg
+++ b/tcl/board/ti_ek-tm4c1294xl.cfg
@@ -13,4 +13,4 @@ transport select jtag
set WORKAREASIZE 0x8000
set CHIPNAME tm4c1294ncpdt
-source [find target/stellaris.cfg]
+source [find target/ti/stellaris.cfg]
diff --git a/tcl/board/ti_j7200evm.cfg b/tcl/board/ti_j7200evm.cfg
index cc70056fb..7edeb3678 100644
--- a/tcl/board/ti_j7200evm.cfg
+++ b/tcl/board/ti_j7200evm.cfg
@@ -19,6 +19,6 @@ if { ![info exists SOC] } {
set SOC j7200
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 2500
diff --git a/tcl/board/ti_j721e_swd_native.cfg b/tcl/board/ti_j721e_swd_native.cfg
index 38316387a..7b3f6060f 100644
--- a/tcl/board/ti_j721e_swd_native.cfg
+++ b/tcl/board/ti_j721e_swd_native.cfg
@@ -19,4 +19,4 @@ transport select swd
if { ![info exists SOC] } {
set SOC j721e
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
diff --git a/tcl/board/ti_j721evm.cfg b/tcl/board/ti_j721evm.cfg
index d0c4b7496..92e88234e 100644
--- a/tcl/board/ti_j721evm.cfg
+++ b/tcl/board/ti_j721evm.cfg
@@ -19,6 +19,6 @@ if { ![info exists SOC] } {
set SOC j721e
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 2500
diff --git a/tcl/board/ti_j721s2evm.cfg b/tcl/board/ti_j721s2evm.cfg
index 72418b57b..f8e12b875 100644
--- a/tcl/board/ti_j721s2evm.cfg
+++ b/tcl/board/ti_j721s2evm.cfg
@@ -20,6 +20,6 @@ if { ![info exists SOC] } {
set SOC j721s2
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 2500
diff --git a/tcl/board/ti_j722s_swd_native.cfg b/tcl/board/ti_j722s_swd_native.cfg
index a171ec358..1bc60968c 100644
--- a/tcl/board/ti_j722s_swd_native.cfg
+++ b/tcl/board/ti_j722s_swd_native.cfg
@@ -21,4 +21,4 @@ if { ![info exists SOC] } {
set SOC j722s
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
diff --git a/tcl/board/ti_j722sevm.cfg b/tcl/board/ti_j722sevm.cfg
index 6a5c2d9cd..c43e7abe5 100644
--- a/tcl/board/ti_j722sevm.cfg
+++ b/tcl/board/ti_j722sevm.cfg
@@ -19,6 +19,6 @@ if { ![info exists SOC] } {
set SOC j722s
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 2500
diff --git a/tcl/board/ti_j784s4_swd_native.cfg b/tcl/board/ti_j784s4_swd_native.cfg
index 13b2ac3b8..dd534248f 100644
--- a/tcl/board/ti_j784s4_swd_native.cfg
+++ b/tcl/board/ti_j784s4_swd_native.cfg
@@ -19,4 +19,4 @@ transport select swd
if { ![info exists SOC] } {
set SOC j784s4
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
diff --git a/tcl/board/ti_j784s4evm.cfg b/tcl/board/ti_j784s4evm.cfg
index d23dc8ce6..a8a5af2e0 100644
--- a/tcl/board/ti_j784s4evm.cfg
+++ b/tcl/board/ti_j784s4evm.cfg
@@ -20,6 +20,6 @@ if { ![info exists SOC] } {
set SOC j784s4
}
-source [find target/ti_k3.cfg]
+source [find target/ti/k3.cfg]
adapter speed 2500
diff --git a/tcl/board/ti_msp432_launchpad.cfg b/tcl/board/ti_msp432_launchpad.cfg
index 4832b837b..455d5a362 100644
--- a/tcl/board/ti_msp432_launchpad.cfg
+++ b/tcl/board/ti_msp432_launchpad.cfg
@@ -6,4 +6,4 @@
source [find interface/xds110.cfg]
adapter speed 10000
transport select swd
-source [find target/ti_msp432.cfg]
+source [find target/ti/msp432.cfg]
diff --git a/tcl/board/ti_mspm0_launchpad.cfg b/tcl/board/ti_mspm0_launchpad.cfg
index 132fdc2a3..30632f2b5 100644
--- a/tcl/board/ti_mspm0_launchpad.cfg
+++ b/tcl/board/ti_mspm0_launchpad.cfg
@@ -11,4 +11,4 @@
source [find interface/xds110.cfg]
adapter speed 10000
-source [find target/ti_mspm0.cfg]
+source [find target/ti/mspm0.cfg]
diff --git a/tcl/board/ti_pandaboard.cfg b/tcl/board/ti_pandaboard.cfg
index 45092e067..7e15f07bd 100644
--- a/tcl/board/ti_pandaboard.cfg
+++ b/tcl/board/ti_pandaboard.cfg
@@ -2,6 +2,6 @@
jtag_rclk 6000
-source [find target/omap4430.cfg]
+source [find target/ti/omap4430.cfg]
reset_config trst_only
diff --git a/tcl/board/ti_pandaboard_es.cfg b/tcl/board/ti_pandaboard_es.cfg
index f83735844..cd8a2f80b 100644
--- a/tcl/board/ti_pandaboard_es.cfg
+++ b/tcl/board/ti_pandaboard_es.cfg
@@ -2,6 +2,6 @@
jtag_rclk 6000
-source [find target/omap4460.cfg]
+source [find target/ti/omap4460.cfg]
reset_config trst_only
diff --git a/tcl/board/ti_tmdx570ls20susb.cfg b/tcl/board/ti_tmdx570ls20susb.cfg
index 9c5ef74ea..ccf649d8f 100644
--- a/tcl/board/ti_tmdx570ls20susb.cfg
+++ b/tcl/board/ti_tmdx570ls20susb.cfg
@@ -8,7 +8,7 @@
source [find interface/ftdi/xds100v2.cfg]
# Processor is TMS570LS20216
-source [find target/ti_tms570ls20xxx.cfg]
+source [find target/ti/tms570ls20xxx.cfg]
reset_config trst_only
diff --git a/tcl/board/ti_tmdx570ls31usb.cfg b/tcl/board/ti_tmdx570ls31usb.cfg
index 324f003d3..b2d5d8119 100644
--- a/tcl/board/ti_tmdx570ls31usb.cfg
+++ b/tcl/board/ti_tmdx570ls31usb.cfg
@@ -3,6 +3,6 @@
adapter speed 1500
source [find interface/ftdi/xds100v2.cfg]
-source [find target/ti_tms570.cfg]
+source [find target/ti/tms570.cfg]
reset_config trst_only
diff --git a/tcl/target/am335x.cfg b/tcl/target/ti/am335x.cfg
similarity index 97%
rename from tcl/target/am335x.cfg
rename to tcl/target/ti/am335x.cfg
index 208ebf561..9388f76fb 100644
--- a/tcl/target/am335x.cfg
+++ b/tcl/target/ti/am335x.cfg
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-source [find target/icepick.cfg]
+source [find target/ti/icepick.cfg]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
@@ -84,7 +84,7 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x4000
# when putting the target into 'reset halt', we need to disable the watchdog as
# it would otherwise trigger while we're in JTAG
-# FIXME: unify with target/am437x.cfg
+# FIXME: unify with target/ti/am437x.cfg
source [find mem_helper.tcl]
set WDT1_BASE_ADDR 0x44e35000
set WDT1_W_PEND_WSPR [expr {$WDT1_BASE_ADDR + 0x0034}]
diff --git a/tcl/target/am437x.cfg b/tcl/target/ti/am437x.cfg
similarity index 99%
rename from tcl/target/am437x.cfg
rename to tcl/target/ti/am437x.cfg
index 535092758..5470f164b 100644
--- a/tcl/target/am437x.cfg
+++ b/tcl/target/ti/am437x.cfg
@@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-source [find target/icepick.cfg]
+source [find target/ti/icepick.cfg]
source [find mem_helper.tcl]
###############################################################################
diff --git a/tcl/target/amdm37x.cfg b/tcl/target/ti/amdm37x.cfg
similarity index 99%
rename from tcl/target/amdm37x.cfg
rename to tcl/target/ti/amdm37x.cfg
index d9adae904..635d94c1c 100644
--- a/tcl/target/amdm37x.cfg
+++ b/tcl/target/ti/amdm37x.cfg
@@ -59,7 +59,7 @@ adapter speed 10
# can be read about this module in sprugn4r in chapter 27: "Debug and
# Emulation". The module is used to route the JTAG chain to the various
# subsystems in the chip.
-source [find target/icepick.cfg]
+source [find target/ti/icepick.cfg]
# The TAP order should be described from the TDO connection in OpenOCD to the
# TDI pin. The OpenOCD FAQ describes this in more detail:
diff --git a/tcl/target/ti-ar7.cfg b/tcl/target/ti/ar7.cfg
similarity index 100%
rename from tcl/target/ti-ar7.cfg
rename to tcl/target/ti/ar7.cfg
diff --git a/tcl/target/ti_calypso.cfg b/tcl/target/ti/calypso.cfg
similarity index 100%
rename from tcl/target/ti_calypso.cfg
rename to tcl/target/ti/calypso.cfg
diff --git a/tcl/target/ti_cc13x0.cfg b/tcl/target/ti/cc13x0.cfg
similarity index 84%
rename from tcl/target/ti_cc13x0.cfg
rename to tcl/target/ti/cc13x0.cfg
index f1c43a689..7f33edb80 100644
--- a/tcl/target/ti_cc13x0.cfg
+++ b/tcl/target/ti/cc13x0.cfg
@@ -10,4 +10,4 @@ set CHIPNAME cc13x0
set JRC_TAPID 0x0B9BE02F
set WORKAREASIZE 0x4000
-source [find target/ti_cc26x0.cfg]
+source [find target/ti/cc26x0.cfg]
diff --git a/tcl/target/ti_cc13x2.cfg b/tcl/target/ti/cc13x2.cfg
similarity index 84%
rename from tcl/target/ti_cc13x2.cfg
rename to tcl/target/ti/cc13x2.cfg
index c85081685..2dadb9ce0 100644
--- a/tcl/target/ti_cc13x2.cfg
+++ b/tcl/target/ti/cc13x2.cfg
@@ -10,4 +10,4 @@ set CHIPNAME cc13x2
set JRC_TAPID 0x0BB4102F
set WORKAREASIZE 0x7000
-source [find target/ti_cc26x0.cfg]
+source [find target/ti/cc26x0.cfg]
diff --git a/tcl/target/cc2538.cfg b/tcl/target/ti/cc2538.cfg
similarity index 94%
rename from tcl/target/cc2538.cfg
rename to tcl/target/ti/cc2538.cfg
index e4fb02ad4..f0fd34b05 100644
--- a/tcl/target/cc2538.cfg
+++ b/tcl/target/ti/cc2538.cfg
@@ -5,8 +5,8 @@
adapter speed 100
-source [find target/icepick.cfg]
-source [find target/ti-cjtag.cfg]
+source [find target/ti/icepick.cfg]
+source [find target/ti/cjtag.cfg]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/ti_cc26x0.cfg b/tcl/target/ti/cc26x0.cfg
similarity index 95%
rename from tcl/target/ti_cc26x0.cfg
rename to tcl/target/ti/cc26x0.cfg
index b9ccf3123..246c1fd97 100644
--- a/tcl/target/ti_cc26x0.cfg
+++ b/tcl/target/ti/cc26x0.cfg
@@ -6,8 +6,8 @@
# http://www.ti.com
#
-source [find target/icepick.cfg]
-source [find target/ti-cjtag.cfg]
+source [find target/ti/icepick.cfg]
+source [find target/ti/cjtag.cfg]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/ti_cc26x2.cfg b/tcl/target/ti/cc26x2.cfg
similarity index 84%
rename from tcl/target/ti_cc26x2.cfg
rename to tcl/target/ti/cc26x2.cfg
index 62c91c339..14b586921 100644
--- a/tcl/target/ti_cc26x2.cfg
+++ b/tcl/target/ti/cc26x2.cfg
@@ -10,4 +10,4 @@ set CHIPNAME cc26x2
set JRC_TAPID 0x0BB4102F
set WORKAREASIZE 0x7000
-source [find target/ti_cc26x0.cfg]
+source [find target/ti/cc26x0.cfg]
diff --git a/tcl/target/ti_cc26x2x7.cfg b/tcl/target/ti/cc26x2x7.cfg
similarity index 84%
rename from tcl/target/ti_cc26x2x7.cfg
rename to tcl/target/ti/cc26x2x7.cfg
index 91c1a8059..80ecdd450 100644
--- a/tcl/target/ti_cc26x2x7.cfg
+++ b/tcl/target/ti/cc26x2x7.cfg
@@ -10,4 +10,4 @@ set CHIPNAME cc26x2x7
set JRC_TAPID 0x1BB7702F
set WORKAREASIZE 0x7000
-source [find target/ti_cc26x0.cfg]
+source [find target/ti/cc26x0.cfg]
diff --git a/tcl/target/ti_cc3220sf.cfg b/tcl/target/ti/cc3220sf.cfg
similarity index 93%
rename from tcl/target/ti_cc3220sf.cfg
rename to tcl/target/ti/cc3220sf.cfg
index cf4336376..7b242ab8a 100644
--- a/tcl/target/ti_cc3220sf.cfg
+++ b/tcl/target/ti/cc3220sf.cfg
@@ -7,8 +7,8 @@
#
source [find target/swj-dp.tcl]
-source [find target/icepick.cfg]
-source [find target/ti_cc32xx.cfg]
+source [find target/ti/icepick.cfg]
+source [find target/ti/cc32xx.cfg]
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
diff --git a/tcl/target/ti_cc32xx.cfg b/tcl/target/ti/cc32xx.cfg
similarity index 97%
rename from tcl/target/ti_cc32xx.cfg
rename to tcl/target/ti/cc32xx.cfg
index 9eb03eb2f..d081360bd 100644
--- a/tcl/target/ti_cc32xx.cfg
+++ b/tcl/target/ti/cc32xx.cfg
@@ -8,7 +8,7 @@
#
source [find target/swj-dp.tcl]
-source [find target/icepick.cfg]
+source [find target/ti/icepick.cfg]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
diff --git a/tcl/target/ti-cjtag.cfg b/tcl/target/ti/cjtag.cfg
similarity index 100%
rename from tcl/target/ti-cjtag.cfg
rename to tcl/target/ti/cjtag.cfg
diff --git a/tcl/target/davinci.cfg b/tcl/target/ti/davinci.cfg
similarity index 100%
rename from tcl/target/davinci.cfg
rename to tcl/target/ti/davinci.cfg
diff --git a/tcl/target/ti_dm355.cfg b/tcl/target/ti/dm355.cfg
similarity index 97%
rename from tcl/target/ti_dm355.cfg
rename to tcl/target/ti/dm355.cfg
index 42923733e..198d1eb50 100644
--- a/tcl/target/ti_dm355.cfg
+++ b/tcl/target/ti/dm355.cfg
@@ -17,7 +17,7 @@ set EMU01 "-disable"
# needing any ICEpick interaction.
#set EMU01 "-enable"
-source [find target/icepick.cfg]
+source [find target/ti/icepick.cfg]
#
# Also note: when running without RTCK before the PLLs are set up, you
@@ -80,7 +80,7 @@ dict set dm355 uart0 0x01c20000
dict set dm355 uart1 0x01c20400
dict set dm355 uart2 0x01e06000
-source [find target/davinci.cfg]
+source [find target/ti/davinci.cfg]
################
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
diff --git a/tcl/target/ti_dm365.cfg b/tcl/target/ti/dm365.cfg
similarity index 97%
rename from tcl/target/ti_dm365.cfg
rename to tcl/target/ti/dm365.cfg
index e19efd7ee..8f4510e3b 100644
--- a/tcl/target/ti_dm365.cfg
+++ b/tcl/target/ti/dm365.cfg
@@ -17,7 +17,7 @@ set EMU01 "-disable"
# needing any ICEpick interaction.
#set EMU01 "-enable"
-source [find target/icepick.cfg]
+source [find target/ti/icepick.cfg]
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID] } {
@@ -72,7 +72,7 @@ dict set dm365 a_emif_cs1 0x04000000
dict set dm365 ddr_emif 0x20000000
dict set dm365 ddr 0x80000000
-source [find target/davinci.cfg]
+source [find target/ti/davinci.cfg]
################
# GDB target: the ARM, using SRAM1 for scratch. SRAM0 (also 16K)
diff --git a/tcl/target/ti_dm6446.cfg b/tcl/target/ti/dm6446.cfg
similarity index 98%
rename from tcl/target/ti_dm6446.cfg
rename to tcl/target/ti/dm6446.cfg
index 8938234c3..23218c4ab 100644
--- a/tcl/target/ti_dm6446.cfg
+++ b/tcl/target/ti/dm6446.cfg
@@ -17,7 +17,7 @@ set EMU01 "-disable"
# needing any ICEpick interaction.
#set EMU01 "-enable"
-source [find target/icepick.cfg]
+source [find target/ti/icepick.cfg]
# Subsidiary TAP: unknown ... must enable via ICEpick
jtag newtap $_CHIPNAME unknown -irlen 8 -disable
diff --git a/tcl/target/icepick.cfg b/tcl/target/ti/icepick.cfg
similarity index 100%
rename from tcl/target/icepick.cfg
rename to tcl/target/ti/icepick.cfg
diff --git a/tcl/target/ti_k3.cfg b/tcl/target/ti/k3.cfg
similarity index 100%
rename from tcl/target/ti_k3.cfg
rename to tcl/target/ti/k3.cfg
diff --git a/tcl/target/ti_msp432.cfg b/tcl/target/ti/msp432.cfg
similarity index 100%
rename from tcl/target/ti_msp432.cfg
rename to tcl/target/ti/msp432.cfg
diff --git a/tcl/target/ti_mspm0.cfg b/tcl/target/ti/mspm0.cfg
similarity index 100%
rename from tcl/target/ti_mspm0.cfg
rename to tcl/target/ti/mspm0.cfg
diff --git a/tcl/target/omap2420.cfg b/tcl/target/ti/omap2420.cfg
similarity index 100%
rename from tcl/target/omap2420.cfg
rename to tcl/target/ti/omap2420.cfg
diff --git a/tcl/target/omap3530.cfg b/tcl/target/ti/omap3530.cfg
similarity index 98%
rename from tcl/target/omap3530.cfg
rename to tcl/target/ti/omap3530.cfg
index c1921b437..5ae003b39 100644
--- a/tcl/target/omap3530.cfg
+++ b/tcl/target/ti/omap3530.cfg
@@ -11,7 +11,7 @@ if { [info exists CHIPNAME] } {
}
# ICEpick-C ... used to route Cortex, DSP, and more not shown here
-source [find target/icepick.cfg]
+source [find target/ti/icepick.cfg]
# Subsidiary TAP: C64x+ DSP ... must enable via ICEpick
jtag newtap $_CHIPNAME dsp -irlen 38 -ircapture 0x25 -irmask 0x3f -disable
diff --git a/tcl/target/omap4430.cfg b/tcl/target/ti/omap4430.cfg
similarity index 98%
rename from tcl/target/omap4430.cfg
rename to tcl/target/ti/omap4430.cfg
index 4bc7fe1bf..f1b87f147 100644
--- a/tcl/target/omap4430.cfg
+++ b/tcl/target/ti/omap4430.cfg
@@ -12,7 +12,7 @@ if { [info exists CHIPNAME] } {
# Although the OMAP4430 supposedly has an ICEpick-D, only the
# ICEpick-C router commands seem to work.
# See http://processors.wiki.ti.com/index.php/ICEPICK
-source [find target/icepick.cfg]
+source [find target/ti/icepick.cfg]
#
diff --git a/tcl/target/omap4460.cfg b/tcl/target/ti/omap4460.cfg
similarity index 98%
rename from tcl/target/omap4460.cfg
rename to tcl/target/ti/omap4460.cfg
index 85ba96c51..b9e414061 100644
--- a/tcl/target/omap4460.cfg
+++ b/tcl/target/ti/omap4460.cfg
@@ -12,7 +12,7 @@ if { [info exists CHIPNAME] } {
# Although the OMAP4430 supposedly has an ICEpick-D, only the
# ICEpick-C router commands seem to work.
# See http://processors.wiki.ti.com/index.php/ICEPICK
-source [find target/icepick.cfg]
+source [find target/ti/icepick.cfg]
#
diff --git a/tcl/target/omap5912.cfg b/tcl/target/ti/omap5912.cfg
similarity index 100%
rename from tcl/target/omap5912.cfg
rename to tcl/target/ti/omap5912.cfg
diff --git a/tcl/target/omapl138.cfg b/tcl/target/ti/omapl138.cfg
similarity index 98%
rename from tcl/target/omapl138.cfg
rename to tcl/target/ti/omapl138.cfg
index 9d89429a8..166317f1d 100644
--- a/tcl/target/omapl138.cfg
+++ b/tcl/target/ti/omapl138.cfg
@@ -9,7 +9,7 @@ if { [info exists CHIPNAME] } {
set _CHIPNAME omapl138
}
-source [find target/icepick.cfg]
+source [find target/ti/icepick.cfg]
# Subsidiary TAP: ARM ETB11, with scan chain for 4K of ETM trace buffer
if { [info exists ETB_TAPID] } {
diff --git a/tcl/target/ti_rm4x.cfg b/tcl/target/ti/rm4x.cfg
similarity index 56%
rename from tcl/target/ti_rm4x.cfg
rename to tcl/target/ti/rm4x.cfg
index 715aa5b70..9103d4462 100644
--- a/tcl/target/ti_rm4x.cfg
+++ b/tcl/target/ti/rm4x.cfg
@@ -1,3 +1,3 @@
# SPDX-License-Identifier: GPL-2.0-or-later
-source [find target/ti_tms570.cfg]
+source [find target/ti/tms570.cfg]
diff --git a/tcl/target/stellaris.cfg b/tcl/target/ti/stellaris.cfg
similarity index 100%
rename from tcl/target/stellaris.cfg
rename to tcl/target/ti/stellaris.cfg
diff --git a/tcl/target/ti_tms570.cfg b/tcl/target/ti/tms570.cfg
similarity index 97%
rename from tcl/target/ti_tms570.cfg
rename to tcl/target/ti/tms570.cfg
index 18e0d8294..3b0639b5d 100644
--- a/tcl/target/ti_tms570.cfg
+++ b/tcl/target/ti/tms570.cfg
@@ -15,7 +15,7 @@ if { [info exists ENDIAN] } {
}
# TMS570 has an ICEpick-C on which we need the router commands.
-source [find target/icepick.cfg]
+source [find target/ti/icepick.cfg]
# Main DAP
# DAP_TAPID should be set before source-ing this file
diff --git a/tcl/target/ti_tms570lc43xx.cfg b/tcl/target/ti/tms570lc43xx.cfg
similarity index 73%
rename from tcl/target/ti_tms570lc43xx.cfg
rename to tcl/target/ti/tms570lc43xx.cfg
index ffda989f9..677132a89 100644
--- a/tcl/target/ti_tms570lc43xx.cfg
+++ b/tcl/target/ti/tms570lc43xx.cfg
@@ -3,4 +3,4 @@
set DAP_TAPID 0x0B95A02F
set JRC_TAPID 0x0B95A02F
-source [find target/ti_tms570.cfg]
+source [find target/ti/tms570.cfg]
diff --git a/tcl/target/ti_tms570ls1x.cfg b/tcl/target/ti/tms570ls1x.cfg
similarity index 82%
rename from tcl/target/ti_tms570ls1x.cfg
rename to tcl/target/ti/tms570ls1x.cfg
index 3c2577757..8eace9c52 100644
--- a/tcl/target/ti_tms570ls1x.cfg
+++ b/tcl/target/ti/tms570ls1x.cfg
@@ -5,4 +5,4 @@
set DAP_TAPID 0x0B95502F
set JRC_TAPID 0x0B95502F
-source [find target/ti_tms570.cfg]
+source [find target/ti/tms570.cfg]
diff --git a/tcl/target/ti_tms570ls20xxx.cfg b/tcl/target/ti/tms570ls20xxx.cfg
similarity index 84%
rename from tcl/target/ti_tms570ls20xxx.cfg
rename to tcl/target/ti/tms570ls20xxx.cfg
index cc2bbd690..4581dbf30 100644
--- a/tcl/target/ti_tms570ls20xxx.cfg
+++ b/tcl/target/ti/tms570ls20xxx.cfg
@@ -5,4 +5,4 @@
set DAP_TAPID 0x0B7B302F
set JRC_TAPID 0x0B7B302F
-source [find target/ti_tms570.cfg]
+source [find target/ti/tms570.cfg]
diff --git a/tcl/target/ti_tms570ls3137.cfg b/tcl/target/ti/tms570ls3137.cfg
similarity index 76%
rename from tcl/target/ti_tms570ls3137.cfg
rename to tcl/target/ti/tms570ls3137.cfg
index ebe2cfc65..2cbbde84f 100644
--- a/tcl/target/ti_tms570ls3137.cfg
+++ b/tcl/target/ti/tms570ls3137.cfg
@@ -4,4 +4,4 @@
set DAP_TAPID 0x0B8A002F
set JRC_TAPID 0x0B8A002F
-source [find target/ti_tms570.cfg]
+source [find target/ti/tms570.cfg]
-----------------------------------------------------------------------
Summary of changes:
README | 2 +-
doc/openocd.texi | 4 ++--
tcl/board/am3517evm.cfg | 2 +-
tcl/board/da850evm.cfg | 2 +-
tcl/board/dm355evm.cfg | 2 +-
tcl/board/dm365evm.cfg | 2 +-
tcl/board/dm6446evm.cfg | 2 +-
tcl/board/ek-lm3s1968.cfg | 2 +-
tcl/board/ek-lm3s3748.cfg | 2 +-
tcl/board/ek-lm3s6965.cfg | 2 +-
tcl/board/ek-lm3s811-revb.cfg | 2 +-
tcl/board/ek-lm3s811.cfg | 2 +-
tcl/board/ek-lm3s8962.cfg | 2 +-
tcl/board/ek-lm3s9b9x.cfg | 2 +-
tcl/board/ek-lm3s9d92.cfg | 2 +-
tcl/board/ek-lm4f120xl.cfg | 2 +-
tcl/board/ek-lm4f232.cfg | 2 +-
tcl/board/linksys-wag200g.cfg | 2 +-
tcl/board/netgear-dg834v3.cfg | 2 +-
tcl/board/omap2420_h4.cfg | 2 +-
tcl/board/osk5912.cfg | 2 +-
tcl/board/phone_se_j100i.cfg | 2 +-
tcl/board/ti/launchxl2-tms57012.cfg | 2 +-
tcl/board/ti_am243_launchpad.cfg | 2 +-
tcl/board/ti_am261_launchpad.cfg | 2 +-
tcl/board/ti_am263_launchpad.cfg | 2 +-
tcl/board/ti_am263p_launchpad.cfg | 2 +-
tcl/board/ti_am273_launchpad.cfg | 2 +-
tcl/board/ti_am335xevm.cfg | 2 +-
tcl/board/ti_am437x_idk.cfg | 2 +-
tcl/board/ti_am43xx_evm.cfg | 2 +-
tcl/board/ti_am625_swd_native.cfg | 2 +-
tcl/board/ti_am625evm.cfg | 2 +-
tcl/board/ti_am62a7_swd_native.cfg | 2 +-
tcl/board/ti_am62a7evm.cfg | 2 +-
tcl/board/ti_am62levm.cfg | 2 +-
tcl/board/ti_am62p_swd_native.cfg | 2 +-
tcl/board/ti_am62pevm.cfg | 2 +-
tcl/board/ti_am642evm.cfg | 2 +-
tcl/board/ti_am64xx_swd_native.cfg | 2 +-
tcl/board/ti_am654evm.cfg | 2 +-
tcl/board/ti_beagleboard.cfg | 2 +-
tcl/board/ti_beagleboard_xm.cfg | 2 +-
tcl/board/ti_beaglebone-base.cfg | 2 +-
tcl/board/ti_blaze.cfg | 2 +-
tcl/board/ti_cc13x0_launchpad.cfg | 2 +-
tcl/board/ti_cc13x2_launchpad.cfg | 2 +-
tcl/board/ti_cc26x0_launchpad.cfg | 2 +-
tcl/board/ti_cc26x2_launchpad.cfg | 2 +-
tcl/board/ti_cc26x2x7_launchpad.cfg | 2 +-
tcl/board/ti_cc3200_launchxl.cfg | 2 +-
tcl/board/ti_cc3220sf_launchpad.cfg | 2 +-
tcl/board/ti_cc32xx_launchpad.cfg | 2 +-
tcl/board/ti_dk-tm4c129.cfg | 2 +-
tcl/board/ti_ek-tm4c123gxl.cfg | 2 +-
tcl/board/ti_ek-tm4c1294xl.cfg | 2 +-
tcl/board/ti_j7200evm.cfg | 2 +-
tcl/board/ti_j721e_swd_native.cfg | 2 +-
tcl/board/ti_j721evm.cfg | 2 +-
tcl/board/ti_j721s2evm.cfg | 2 +-
tcl/board/ti_j722s_swd_native.cfg | 2 +-
tcl/board/ti_j722sevm.cfg | 2 +-
tcl/board/ti_j784s4_swd_native.cfg | 2 +-
tcl/board/ti_j784s4evm.cfg | 2 +-
tcl/board/ti_msp432_launchpad.cfg | 2 +-
tcl/board/ti_mspm0_launchpad.cfg | 2 +-
tcl/board/ti_pandaboard.cfg | 2 +-
tcl/board/ti_pandaboard_es.cfg | 2 +-
tcl/board/ti_tmdx570ls20susb.cfg | 2 +-
tcl/board/ti_tmdx570ls31usb.cfg | 2 +-
tcl/target/{ => ti}/am335x.cfg | 4 ++--
tcl/target/{ => ti}/am437x.cfg | 2 +-
tcl/target/{ => ti}/amdm37x.cfg | 2 +-
tcl/target/{ti-ar7.cfg => ti/ar7.cfg} | 0
tcl/target/{ti_calypso.cfg => ti/calypso.cfg} | 0
tcl/target/{ti_cc13x0.cfg => ti/cc13x0.cfg} | 2 +-
tcl/target/{ti_cc13x2.cfg => ti/cc13x2.cfg} | 2 +-
tcl/target/{ => ti}/cc2538.cfg | 4 ++--
tcl/target/{ti_cc26x0.cfg => ti/cc26x0.cfg} | 4 ++--
tcl/target/{ti_cc26x2.cfg => ti/cc26x2.cfg} | 2 +-
tcl/target/{ti_cc26x2x7.cfg => ti/cc26x2x7.cfg} | 2 +-
tcl/target/{ti_cc3220sf.cfg => ti/cc3220sf.cfg} | 4 ++--
tcl/target/{ti_cc32xx.cfg => ti/cc32xx.cfg} | 2 +-
tcl/target/{ti-cjtag.cfg => ti/cjtag.cfg} | 0
tcl/target/{ => ti}/davinci.cfg | 0
tcl/target/{ti_dm355.cfg => ti/dm355.cfg} | 4 ++--
tcl/target/{ti_dm365.cfg => ti/dm365.cfg} | 4 ++--
tcl/target/{ti_dm6446.cfg => ti/dm6446.cfg} | 2 +-
tcl/target/{ => ti}/icepick.cfg | 0
tcl/target/{ti_k3.cfg => ti/k3.cfg} | 0
tcl/target/{ti_msp432.cfg => ti/msp432.cfg} | 0
tcl/target/{ti_mspm0.cfg => ti/mspm0.cfg} | 0
tcl/target/{ => ti}/omap2420.cfg | 0
tcl/target/{ => ti}/omap3530.cfg | 2 +-
tcl/target/{ => ti}/omap4430.cfg | 2 +-
tcl/target/{ => ti}/omap4460.cfg | 2 +-
tcl/target/{ => ti}/omap5912.cfg | 0
tcl/target/{ => ti}/omapl138.cfg | 2 +-
tcl/target/{ti_rm4x.cfg => ti/rm4x.cfg} | 2 +-
tcl/target/{ => ti}/stellaris.cfg | 0
tcl/target/{ti_tms570.cfg => ti/tms570.cfg} | 2 +-
tcl/target/{ti_tms570lc43xx.cfg => ti/tms570lc43xx.cfg} | 2 +-
tcl/target/{ti_tms570ls1x.cfg => ti/tms570ls1x.cfg} | 2 +-
tcl/target/{ti_tms570ls20xxx.cfg => ti/tms570ls20xxx.cfg} | 2 +-
tcl/target/{ti_tms570ls3137.cfg => ti/tms570ls3137.cfg} | 2 +-
105 files changed, 101 insertions(+), 101 deletions(-)
rename tcl/target/{ => ti}/am335x.cfg (97%)
rename tcl/target/{ => ti}/am437x.cfg (99%)
rename tcl/target/{ => ti}/amdm37x.cfg (99%)
rename tcl/target/{ti-ar7.cfg => ti/ar7.cfg} (100%)
rename tcl/target/{ti_calypso.cfg => ti/calypso.cfg} (100%)
rename tcl/target/{ti_cc13x0.cfg => ti/cc13x0.cfg} (84%)
rename tcl/target/{ti_cc13x2.cfg => ti/cc13x2.cfg} (84%)
rename tcl/target/{ => ti}/cc2538.cfg (94%)
rename tcl/target/{ti_cc26x0.cfg => ti/cc26x0.cfg} (95%)
rename tcl/target/{ti_cc26x2.cfg => ti/cc26x2.cfg} (84%)
rename tcl/target/{ti_cc26x2x7.cfg => ti/cc26x2x7.cfg} (84%)
rename tcl/target/{ti_cc3220sf.cfg => ti/cc3220sf.cfg} (93%)
rename tcl/target/{ti_cc32xx.cfg => ti/cc32xx.cfg} (97%)
rename tcl/target/{ti-cjtag.cfg => ti/cjtag.cfg} (100%)
rename tcl/target/{ => ti}/davinci.cfg (100%)
rename tcl/target/{ti_dm355.cfg => ti/dm355.cfg} (97%)
rename tcl/target/{ti_dm365.cfg => ti/dm365.cfg} (97%)
rename tcl/target/{ti_dm6446.cfg => ti/dm6446.cfg} (98%)
rename tcl/target/{ => ti}/icepick.cfg (100%)
rename tcl/target/{ti_k3.cfg => ti/k3.cfg} (100%)
rename tcl/target/{ti_msp432.cfg => ti/msp432.cfg} (100%)
rename tcl/target/{ti_mspm0.cfg => ti/mspm0.cfg} (100%)
rename tcl/target/{ => ti}/omap2420.cfg (100%)
rename tcl/target/{ => ti}/omap3530.cfg (98%)
rename tcl/target/{ => ti}/omap4430.cfg (98%)
rename tcl/target/{ => ti}/omap4460.cfg (98%)
rename tcl/target/{ => ti}/omap5912.cfg (100%)
rename tcl/target/{ => ti}/omapl138.cfg (98%)
rename tcl/target/{ti_rm4x.cfg => ti/rm4x.cfg} (56%)
rename tcl/target/{ => ti}/stellaris.cfg (100%)
rename tcl/target/{ti_tms570.cfg => ti/tms570.cfg} (97%)
rename tcl/target/{ti_tms570lc43xx.cfg => ti/tms570lc43xx.cfg} (73%)
rename tcl/target/{ti_tms570ls1x.cfg => ti/tms570ls1x.cfg} (82%)
rename tcl/target/{ti_tms570ls20xxx.cfg => ti/tms570ls20xxx.cfg} (84%)
rename tcl/target/{ti_tms570ls3137.cfg => ti/tms570ls3137.cfg} (76%)
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From: openocd-gerrit <ope...@us...> - 2025-12-12 19:14:57
|
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generated because a ref change was pushed to the repository containing
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commit 5479c58d23771c31d6f034a63b3f01b83ed5129a
Author: Niklas Gürtler <pro...@gm...>
Date: Wed Dec 3 12:03:11 2025 +0100
tcl/target/stm32l4, tcl/target/stm32w*: Fix clock configuration
For stm32l4, stm32wbx, stm32wlx the target tcl scripts try to change the
MSI oscillator's speed to 24 MHz before boosting the interface
frequency, but don't clear the RCC_CR_MSIRANGE field correctly before.
This causes the register write access to fail and leaves the clock
frequency unchanged. For the stm32wlx, the script also neglects to set
the MSIRGSEL bit, such that the frequency setting is not actually
applied.
The issue appears to not cause a problem when using an ST-Link adapter.
When using an FT4232HP, communication to the target fails after the
reset-init event, possibly because this adapter actually supports the
higher interface frequency.
This commit fixes the register accesses to make sure the RCC_CR_MSIRANGE
is cleared to zero before OR-ing the new value. For the stm32wlx, also
set the MSIRGSEL bit. Just to be safe, also fix the write access to the
FLASH_ACR_LATENCY field to clear it before OR-ing, even though it should
be zero at reset anyways.
Change-Id: Ie8320fa6ee2086981c0b1f3c18f51e171709078d
Signed-off-by: Niklas Gürtler <pro...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9282
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
diff --git a/tcl/target/stm32l4x.cfg b/tcl/target/stm32l4x.cfg
index 9a696736c..1666b2549 100644
--- a/tcl/target/stm32l4x.cfg
+++ b/tcl/target/stm32l4x.cfg
@@ -143,8 +143,8 @@ $_TARGETNAME configure -event reset-init {
# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 6 (4 MHz).
# Use MSI 24 MHz clock, compliant even with VOS == 2.
# 3 WS compliant with VOS == 2 and 24 MHz.
- mww 0x40022000 0x00000103 ;# FLASH_ACR = PRFTBE | 3(Latency)
- mww 0x40021000 0x00000099 ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
+ mmw 0x40022000 0x00000103 0x00000007 ;# FLASH_ACR = PRFTBE | 3(Latency)
+ mmw 0x40021000 0x00000099 0x000000F0 ;# RCC_CR = MSI_ON | MSIRGSEL | MSI Range 9
# Boost JTAG frequency
adapter speed 4000
diff --git a/tcl/target/stm32wbx.cfg b/tcl/target/stm32wbx.cfg
index 737b1447c..d11c5fb8c 100644
--- a/tcl/target/stm32wbx.cfg
+++ b/tcl/target/stm32wbx.cfg
@@ -76,8 +76,8 @@ $_TARGETNAME configure -event reset-init {
# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
# 2 WS compliant with VOS=Range1 and 24 MHz.
- mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTBE | 2(Latency)
- mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+ mmw 0x58004000 0x00000102 0x00000007 ;# FLASH_ACR |= PRFTBE | 2(Latency)
+ mmw 0x58000000 0x00000091 0x000000F0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
# Boost JTAG frequency
adapter speed 4000
}
diff --git a/tcl/target/stm32wlx.cfg b/tcl/target/stm32wlx.cfg
index 39c897fc5..ddf760d45 100644
--- a/tcl/target/stm32wlx.cfg
+++ b/tcl/target/stm32wlx.cfg
@@ -91,8 +91,8 @@ $_CHIPNAME.cpu0 configure -event reset-init {
# CPU comes out of reset with MSI_ON | MSI_RDY | MSI Range 4 MHz.
# Configure system to use MSI 24 MHz clock, compliant with VOS default Range1.
# 2 WS compliant with VOS=Range1 and 24 MHz.
- mmw 0x58004000 0x00000102 0 ;# FLASH_ACR |= PRFTEN | 2(Latency)
- mmw 0x58000000 0x00000091 0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz
+ mmw 0x58004000 0x00000102 0x00000007 ;# FLASH_ACR |= PRFTEN | 2(Latency)
+ mmw 0x58000000 0x00000099 0x000000F0 ;# RCC_CR = MSI_ON | MSI Range 24 MHz | MSIRGSEL
# Boost JTAG frequency
adapter speed 4000
}
-----------------------------------------------------------------------
Summary of changes:
tcl/target/stm32l4x.cfg | 4 ++--
tcl/target/stm32wbx.cfg | 4 ++--
tcl/target/stm32wlx.cfg | 4 ++--
3 files changed, 6 insertions(+), 6 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2025-12-12 17:42:00
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
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- Log -----------------------------------------------------------------
commit 8115c286637eabfbc48712e41d901f3d1090f408
Author: Thomas Hebb <tom...@gm...>
Date: Fri Apr 29 23:26:00 2022 -0700
tcl/target/gd32vf103: copy a few minor settings from riscv-openocd
These changes bring over some lines from the independently-developed
gd32vf103.cfg that I contributed[1] to the riscv-openocd fork of
OpenOCD. They're all minor, so I'm squashing them into one review. The
changes are as follows:
- Add boundary scan TAP.
- Mention inconsistency of CPU ID between vendor SDK and real hardware.
- Specify that there's no MMU so we don't look for one at runtime.
Signed-off-by: Thomas Hebb <tom...@gm...>
Change-Id: Ie8033eff436d6dbdc3eab156769a8908ccb547f6
Reviewed-on: https://review.openocd.org/c/openocd/+/6959
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/tcl/target/gd32vf103.cfg b/tcl/target/gd32vf103.cfg
index 54a74e8cc..5941dc66d 100644
--- a/tcl/target/gd32vf103.cfg
+++ b/tcl/target/gd32vf103.cfg
@@ -23,11 +23,20 @@ if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE 0x1800
}
+# Example OpenOCD configurations from GigaDevice/Nuclei expect a cpu IDCODE of
+# 0x1e200a6d instead. It's unclear if any units with that IDCODE exist in the
+# wild. Please report a bug if you have such a unit.
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x1000563d
+jtag newtap $_CHIPNAME bs -irlen 5 -expected-id 0x790007a3
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+# Disable virtual address translation since we don't have an MMU. Nothing will
+# break without this line, but OpenOCD will do a few unnecessary register reads
+# to figure it out on its own.
+$_TARGETNAME riscv virt2phys_mode off
+
proc default_mem_access {} {
riscv set_mem_access progbuf
}
-----------------------------------------------------------------------
Summary of changes:
tcl/target/gd32vf103.cfg | 9 +++++++++
1 file changed, 9 insertions(+)
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From: openocd-gerrit <ope...@us...> - 2025-12-04 11:20:15
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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- Log -----------------------------------------------------------------
commit aa9ff8dc5ec60c46134f57a2f858149bb083036e
Author: Tomas Vanek <va...@fb...>
Date: Mon Oct 13 18:35:37 2025 +0200
target/esirisc_trace: drop macro BIT_MASK() conflicting with bits.h
The esirisc_trace.c uses macro BIT_MASK(), same name as a macro
from helper/bits.h
Drop the macro definition and use GENMASK() instead.
Change-Id: I0cc6a58e5aff3f48fa9a79a99bd28124f334c4e2
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9168
Tested-by: jenkins
Reviewed-by: Evgeniy Naydanov <eu...@gm...>
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/target/esirisc_trace.c b/src/target/esirisc_trace.c
index 2dc08e5d2..42bc37d30 100644
--- a/src/target/esirisc_trace.c
+++ b/src/target/esirisc_trace.c
@@ -10,6 +10,7 @@
#endif
#include <helper/binarybuffer.h>
+#include <helper/bits.h>
#include <helper/command.h>
#include <helper/fileio.h>
#include <helper/log.h>
@@ -18,8 +19,6 @@
#include "esirisc.h"
-#define BIT_MASK(x) ((1 << (x)) - 1)
-
/* Control Fields */
#define CONTROL_ST (1<<0) /* Start */
#define CONTROL_SP (1<<1) /* Stop */
@@ -483,7 +482,7 @@ static int esirisc_trace_analyze_simple(struct command_invocation *cmd, uint8_t
struct target *target = get_current_target(cmd->ctx);
struct esirisc_common *esirisc = target_to_esirisc(target);
struct esirisc_trace *trace_info = &esirisc->trace_info;
- const uint32_t end_of_trace = BIT_MASK(trace_info->pc_bits) << 1;
+ const uint32_t end_of_trace = GENMASK(trace_info->pc_bits, 1);
const uint32_t num_bits = size * 8;
int retval;
-----------------------------------------------------------------------
Summary of changes:
src/target/esirisc_trace.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2025-11-30 10:25:11
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
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commit ac6972ba16b471cb46a2d862fb24d54b98b4bb61
Author: Marc Schink <de...@za...>
Date: Tue Nov 11 17:39:23 2025 +0100
adapter/gpio: Use command_print() instead of LOG_ERROR()
Use command_print() in order to provide an error message to the caller.
While at it, fix the return values.
Change-Id: I0f8d3466ab2729d8cca6cf4c1cff51d67982c373
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9267
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/adapter.c b/src/jtag/adapter.c
index c30a26c87..3f94ffec7 100644
--- a/src/jtag/adapter.c
+++ b/src/jtag/adapter.c
@@ -957,8 +957,8 @@ COMMAND_HANDLER(adapter_gpio_config_handler)
int gpio_idx = get_gpio_index(CMD_ARGV[0]);
if (gpio_idx == -1) {
- LOG_ERROR("adapter has no gpio named %s", CMD_ARGV[0]);
- return ERROR_COMMAND_SYNTAX_ERROR;
+ command_print(CMD, "adapter has no gpio named %s", CMD_ARGV[0]);
+ return ERROR_COMMAND_ARGUMENT_INVALID;
}
if (CMD_ARGC == 1) {
@@ -1077,9 +1077,9 @@ COMMAND_HANDLER(adapter_gpio_config_handler)
}
}
- LOG_ERROR("illegal option for adapter %s %s: %s",
+ command_print(CMD, "illegal option for adapter %s %s: %s",
CMD_NAME, gpio_map[gpio_idx].name, CMD_ARGV[i]);
- return ERROR_COMMAND_SYNTAX_ERROR;
+ return ERROR_COMMAND_ARGUMENT_INVALID;
}
/* Force swdio_dir init state to be compatible with swdio init state */
-----------------------------------------------------------------------
Summary of changes:
src/jtag/adapter.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2025-11-30 10:24:49
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commit 171454fffad3573bdf0870769ae7d82bf07bb8dc
Author: Antonio Borneo <bor...@gm...>
Date: Sat Nov 22 22:03:10 2025 +0100
server: fix a new double free()
By reorganizing the free() of the service and its subfields, the
patch reported in 'fixes' exposes a new double free().
Issue detected by 'scan-build'.
Fix it.
Fixes: 5ff384be086a ("semihosting: fix memory leak and double free")
Change-Id: Ief4262e98c9ecdca39d4e2d77e7a0ea87cfa198c
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9266
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/server/server.c b/src/server/server.c
index 494fd9da3..81d79d41b 100644
--- a/src/server/server.c
+++ b/src/server/server.c
@@ -378,7 +378,6 @@ int remove_service(const char *name, const char *port)
if (tmp->type != CONNECTION_STDINOUT)
close_socket(tmp->fd);
- free(tmp->priv);
free_service(tmp);
return ERROR_OK;
-----------------------------------------------------------------------
Summary of changes:
src/server/server.c | 1 -
1 file changed, 1 deletion(-)
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From: openocd-gerrit <ope...@us...> - 2025-11-30 10:24:27
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commit fc8f939d95e0b02e5d5dc70023a0ca48fde7aa5d
Author: Antonio Borneo <bor...@gm...>
Date: Sat Jul 26 12:17:46 2025 +0200
Support two-wire cJTAG OSCAN1 and JScan3 using FTDI adapters
cJTAG OSCAN1, in lieu of 4-wire JTAG, is starting to be a configuration
option for some SiFive hardware. An FTDI-based adapter that can be
configured to drive the bidirectional pin TMSC is assumed for this
topology. Specifically, the Olimex ARM-USB-TINY-H with the ARM-JTAG-SWD
adapter, connected to a SiFive cJTAG-enabled target board is the only
known concrete topology, currently. But in theory, other FTDI based
devices that can drive a two-wire bidirectional signaling pattern could
be made to work in this scheme in the future.
These code changes are offered as a way to drive that topology. It's
translating IR/DR and JTAG traversal commands to the two-wire clocking
and signaling.
See:
- https://github.com/riscv-collab/riscv-openocd/pull/320
- https://github.com/riscv-collab/riscv-openocd/pull/736
Signed-off-by: Greg Savin <gre...@si...>
Signed-off-by: mrv96 <mr...@us...>
Signed-off-by: Tim Newsome <ti...@si...>
Signed-off-by: Antonio Borneo <bor...@gm...>
Change-Id: Ia1daa2c01227c4b0005be947b2bb0de81a800874
Reviewed-on: https://review.openocd.org/c/openocd/+/6981
Tested-by: jenkins
diff --git a/configure.ac b/configure.ac
index 6efcf24f2..d563f2b66 100644
--- a/configure.ac
+++ b/configure.ac
@@ -130,6 +130,7 @@ m4_define([ADAPTER_OPT], [m4_translit(ADAPTER_ARG($1), [_], [-])])
m4_define([USB1_ADAPTERS],
[[[ftdi], [MPSSE mode of FTDI based devices], [FTDI]],
+ [[ftdi_cjtag], [cJTAG (OScan1, JScan3) tunneled thru MPSSE], [FTDI_CJTAG]],
[[ch347], [CH347 based devices], [CH347]],
[[stlink], [ST-Link Programmer], [HLADAPTER_STLINK]],
[[ti_icdi], [TI ICDI JTAG Programmer], [HLADAPTER_ICDI]],
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 09bbd3dd9..82d2a9416 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2781,6 +2781,35 @@ minimal impact on the target system. Avoid floating inputs, conflicting outputs
and initially asserted reset signals.
@end deffn
+@deffn {Command} {ftdi oscan1_mode} on|off
+Enable or disable OScan1 mode. This mode is intended for use with an adapter,
+such as the ARM-JTAG-SWD by Olimex, that sits in between the FTDI chip and the
+target. The cJTAG prococol is composed of two wires: TCKC (clock) and TMSC (data).
+TMSC is a bidirectional signal which is time-multiplexed alternating TDI, TMS and
+TDO. The multiplexing is achieved by a tri-state buffer which puts TMSC in Hi-Z
+when the device is supposed to take the control of the line (TDO phase).
+
+The ARM-JTAG-SWD adapter uses standard TRST and TMS signals to control TMSC
+direction. TRST is used by the adapter as selector for the multiplexers which set
+the JTAG probe in 2-wire mode. Whatever signal is used for this purpose, it must
+be defined with the name JTAG_SEL using @command{ftdi layout_signal}. JTAG_SEL is
+set to 0 during OScan1 initialization.
+
+Some JTAG probes like the Digilent JTAG-HS2, support cJTAG by using a
+separate pin to control when TMS is driven onto TMSC. You can use such
+probes by defining the signal TMSC_EN using
+@command{ftdi layout_signal TMSC_EN -data <mask>}.
+@end deffn
+
+@deffn {Command} {ftdi jscan3_mode} on|off
+Enable or disable JScan3 mode. This mode uses the classic 4-wire JTAG protocol
+in chips whose JTAG port is only compliant with the cJTAG standard (IEEE 1149.7).
+
+Since cJTAG needs a 2-wire escape sequence to select the operating mode,
+a cJTAG adapter like ARM-JTAG-SWD by Olimex is still required. This means
+that a cJTAG probe configuration script must be used too.
+@end deffn
+
@deffn {Command} {ftdi layout_signal} name [@option{-data}|@option{-ndata} data_mask] [@option{-input}|@option{-ninput} input_mask] [@option{-oe}|@option{-noe} oe_mask] [@option{-alias}|@option{-nalias} name]
Creates a signal with the specified @var{name}, controlled by one or more FTDI
GPIO pins via a range of possible buffer connections. The masks are FTDI GPIO
diff --git a/src/jtag/drivers/ftdi.c b/src/jtag/drivers/ftdi.c
index 00b3d198b..c57972cce 100644
--- a/src/jtag/drivers/ftdi.c
+++ b/src/jtag/drivers/ftdi.c
@@ -75,6 +75,16 @@
/* FTDI access library includes */
#include "mpsse.h"
+#if BUILD_FTDI_CJTAG == 1
+#define DO_CLOCK_DATA clock_data
+#define DO_CLOCK_TMS_CS clock_tms_cs
+#define DO_CLOCK_TMS_CS_OUT clock_tms_cs_out
+#else
+#define DO_CLOCK_DATA mpsse_clock_data
+#define DO_CLOCK_TMS_CS mpsse_clock_tms_cs
+#define DO_CLOCK_TMS_CS_OUT mpsse_clock_tms_cs_out
+#endif
+
#define JTAG_MODE (LSB_FIRST | POS_EDGE_IN | NEG_EDGE_OUT)
#define JTAG_MODE_ALT (LSB_FIRST | NEG_EDGE_IN | NEG_EDGE_OUT)
#define SWD_MODE (LSB_FIRST | POS_EDGE_IN | NEG_EDGE_OUT)
@@ -85,6 +95,39 @@ static uint8_t ftdi_jtag_mode = JTAG_MODE;
static bool swd_mode;
+#if BUILD_FTDI_CJTAG == 1
+#define ESCAPE_SEQ_OAC_BIT2 28
+
+static void cjtag_reset_online_activate(void);
+
+/*
+ The cJTAG 2-wire OScan1 protocol, in lieu of 4-wire JTAG, is a configuration option
+ for some SoCs. An FTDI-based adapter that can be configured to appropriately drive
+ the bidirectional pin TMSC is able to drive OScan1 protocol. For example, an Olimex
+ ARM-USB-TINY-H with the ARM-JTAG-SWD adapter, connected to a cJTAG-enabled
+ target board is such a topology. A TCK cycle with TMS=1/TDI=N translates to a TMSC
+ output of N, and a TCK cycle with TMS=0 translates to a TMSC input from the target back
+ to the adapter/probe. The OScan1 protocol uses 3 TCK cycles to generate the data flow
+ that is equivalent to that of a single TCK cycle in 4-wire JTAG. The OScan1-related
+ code in this module translates IR/DR scan commanads and JTAG state traversal commands
+ to the two-wire clocking and signaling of OScan1 protocol, if placed into OScan1 mode
+ during initialization.
+*/
+static void oscan1_mpsse_clock_data(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, uint8_t *in,
+ unsigned int in_offset, unsigned int length, uint8_t mode);
+static void oscan1_mpsse_clock_tms_cs(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, uint8_t *in,
+ unsigned int in_offset, unsigned int length, bool tdi, uint8_t mode);
+static void oscan1_mpsse_clock_tms_cs_out(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset,
+ unsigned int length, bool tdi, uint8_t mode);
+
+static bool oscan1_mode;
+
+/*
+ The cJTAG 4-wire JScan3 allows to use standard JTAG protocol with cJTAG hardware
+*/
+static bool jscan3_mode;
+#endif
+
#define MAX_USB_IDS 8
/* vid = pid = 0 marks the end of the list */
static uint16_t ftdi_vid[MAX_USB_IDS + 1] = { 0 };
@@ -230,6 +273,35 @@ static int ftdi_get_signal(const struct signal *s, uint16_t *value_out)
return ERROR_OK;
}
+#if BUILD_FTDI_CJTAG == 1
+static void clock_data(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, uint8_t *in,
+ unsigned int in_offset, unsigned int length, uint8_t mode)
+{
+ if (oscan1_mode)
+ oscan1_mpsse_clock_data(ctx, out, out_offset, in, in_offset, length, mode);
+ else
+ mpsse_clock_data(ctx, out, out_offset, in, in_offset, length, mode);
+}
+
+static void clock_tms_cs(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, uint8_t *in,
+ unsigned int in_offset, unsigned int length, bool tdi, uint8_t mode)
+{
+ if (oscan1_mode)
+ oscan1_mpsse_clock_tms_cs(ctx, out, out_offset, in, in_offset, length, tdi, mode);
+ else
+ mpsse_clock_tms_cs(ctx, out, out_offset, in, in_offset, length, tdi, mode);
+}
+
+static void clock_tms_cs_out(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset,
+ unsigned int length, bool tdi, uint8_t mode)
+{
+ if (oscan1_mode)
+ oscan1_mpsse_clock_tms_cs_out(ctx, out, out_offset, length, tdi, mode);
+ else
+ mpsse_clock_tms_cs_out(ctx, out, out_offset, length, tdi, mode);
+}
+#endif
+
/**
* Function move_to_state
* moves the TAP controller from the current state to a
@@ -258,7 +330,7 @@ static void move_to_state(enum tap_state goal_state)
for (int i = 0; i < tms_count; i++)
tap_set_state(tap_state_transition(tap_get_state(), (tms_bits >> i) & 1));
- mpsse_clock_tms_cs_out(mpsse_ctx,
+ DO_CLOCK_TMS_CS_OUT(mpsse_ctx,
&tms_bits,
0,
tms_count,
@@ -325,7 +397,7 @@ static void ftdi_execute_runtest(struct jtag_command *cmd)
while (i > 0) {
/* there are no state transitions in this code, so omit state tracking */
unsigned int this_len = i > 7 ? 7 : i;
- mpsse_clock_tms_cs_out(mpsse_ctx, &zero, 0, this_len, false, ftdi_jtag_mode);
+ DO_CLOCK_TMS_CS_OUT(mpsse_ctx, &zero, 0, this_len, false, ftdi_jtag_mode);
i -= this_len;
}
@@ -360,7 +432,7 @@ static void ftdi_execute_tms(struct jtag_command *cmd)
LOG_DEBUG_IO("TMS: %u bits", cmd->cmd.tms->num_bits);
/* TODO: Missing tap state tracking, also missing from ft2232.c! */
- mpsse_clock_tms_cs_out(mpsse_ctx,
+ DO_CLOCK_TMS_CS_OUT(mpsse_ctx,
cmd->cmd.tms->bits,
0,
cmd->cmd.tms->num_bits,
@@ -407,7 +479,7 @@ static void ftdi_execute_pathmove(struct jtag_command *cmd)
state_count++;
if (bit_count == 7 || num_states == 0) {
- mpsse_clock_tms_cs_out(mpsse_ctx,
+ DO_CLOCK_TMS_CS_OUT(mpsse_ctx,
&tms_byte,
0,
bit_count,
@@ -461,7 +533,7 @@ static void ftdi_execute_scan(struct jtag_command *cmd)
if (i == cmd->cmd.scan->num_fields - 1 && tap_get_state() != tap_get_end_state()) {
/* Last field, and we're leaving IRSHIFT/DRSHIFT. Clock last bit during tap
* movement. This last field can't have length zero, it was checked above. */
- mpsse_clock_data(mpsse_ctx,
+ DO_CLOCK_DATA(mpsse_ctx,
field->out_value,
0,
field->in_value,
@@ -476,7 +548,7 @@ static void ftdi_execute_scan(struct jtag_command *cmd)
* Otherwise, clock out 1-0 (->EXIT1 ->PAUSE)
*/
uint8_t tms_bits = 0x03;
- mpsse_clock_tms_cs(mpsse_ctx,
+ DO_CLOCK_TMS_CS(mpsse_ctx,
&tms_bits,
0,
field->in_value,
@@ -486,7 +558,7 @@ static void ftdi_execute_scan(struct jtag_command *cmd)
ftdi_jtag_mode);
tap_set_state(tap_state_transition(tap_get_state(), 1));
if (tap_get_end_state() == TAP_IDLE) {
- mpsse_clock_tms_cs_out(mpsse_ctx,
+ DO_CLOCK_TMS_CS_OUT(mpsse_ctx,
&tms_bits,
1,
2,
@@ -495,7 +567,7 @@ static void ftdi_execute_scan(struct jtag_command *cmd)
tap_set_state(tap_state_transition(tap_get_state(), 1));
tap_set_state(tap_state_transition(tap_get_state(), 0));
} else {
- mpsse_clock_tms_cs_out(mpsse_ctx,
+ DO_CLOCK_TMS_CS_OUT(mpsse_ctx,
&tms_bits,
2,
1,
@@ -504,7 +576,7 @@ static void ftdi_execute_scan(struct jtag_command *cmd)
tap_set_state(tap_state_transition(tap_get_state(), 0));
}
} else
- mpsse_clock_data(mpsse_ctx,
+ DO_CLOCK_DATA(mpsse_ctx,
field->out_value,
0,
field->in_value,
@@ -585,7 +657,7 @@ static void ftdi_execute_stableclocks(struct jtag_command *cmd)
while (num_cycles > 0) {
/* there are no state transitions in this code, so omit state tracking */
unsigned int this_len = num_cycles > 7 ? 7 : num_cycles;
- mpsse_clock_tms_cs_out(mpsse_ctx, &tms, 0, this_len, false, ftdi_jtag_mode);
+ DO_CLOCK_TMS_CS_OUT(mpsse_ctx, &tms, 0, this_len, false, ftdi_jtag_mode);
num_cycles -= this_len;
}
@@ -597,10 +669,19 @@ static void ftdi_execute_stableclocks(struct jtag_command *cmd)
static void ftdi_execute_command(struct jtag_command *cmd)
{
switch (cmd->type) {
+#if BUILD_FTDI_CJTAG == 1
+ case JTAG_RESET:
+ if (cmd->cmd.reset->trst)
+ cjtag_reset_online_activate(); /* put the target (back) into selected cJTAG mode */
+ break;
+#endif
case JTAG_RUNTEST:
ftdi_execute_runtest(cmd);
break;
case JTAG_TLR_RESET:
+#if BUILD_FTDI_CJTAG == 1
+ cjtag_reset_online_activate(); /* put the target (back) into selected cJTAG mode */
+#endif
ftdi_execute_statemove(cmd);
break;
case JTAG_PATHMOVE:
@@ -675,6 +756,21 @@ static int ftdi_initialize(void)
/* A dummy SWD_EN would have zero mask */
if (sig->data_mask)
ftdi_set_signal(sig, '1');
+#if BUILD_FTDI_CJTAG == 1
+ } else if (oscan1_mode || jscan3_mode) {
+ struct signal *sig = find_signal_by_name("JTAG_SEL");
+ if (!sig) {
+ LOG_ERROR("A cJTAG mode is active but JTAG_SEL signal is not defined");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+ /* A dummy JTAG_SEL would have zero mask */
+ if (sig->data_mask) {
+ ftdi_set_signal(sig, '0');
+ } else if (jscan3_mode) {
+ LOG_ERROR("In JScan3 mode JTAG_SEL signal cannot be dummy, data mask needed");
+ return ERROR_JTAG_INIT_FAILED;
+ }
+#endif
}
mpsse_set_data_bits_low_byte(mpsse_ctx, output & 0xff, direction & 0xff);
@@ -706,6 +802,286 @@ static int ftdi_quit(void)
return ERROR_OK;
}
+#if BUILD_FTDI_CJTAG == 1
+static void oscan1_mpsse_clock_data(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, uint8_t *in,
+ unsigned int in_offset, unsigned int length, uint8_t mode)
+{
+ static const uint8_t zero;
+ static const uint8_t one = 1;
+
+ struct signal *tmsc_en = find_signal_by_name("TMSC_EN");
+
+ LOG_DEBUG_IO("%sout %d bits", in ? "in" : "", length);
+
+ for (unsigned int i = 0; i < length; i++) {
+ int bitnum;
+ uint8_t bit;
+
+ /* OScan1 uses 3 separate clocks */
+
+ /* drive TMSC to the *negation* of the desired TDI value */
+ bitnum = out_offset + i;
+ bit = out ? ((out[bitnum / 8] >> (bitnum % 8)) & 0x1) : 0;
+
+ /* Try optimized case first: if desired TDI bit is 1, then we
+ can fuse what would otherwise be the first two MPSSE commands */
+ if (bit) {
+ const uint8_t tmsbits = 0x3; /* 1, 1 */
+ mpsse_clock_tms_cs_out(mpsse_ctx, &tmsbits, 0, 2, false, mode);
+ } else {
+ /* Can't fuse because TDI varies; less efficient */
+ mpsse_clock_tms_cs_out(mpsse_ctx, &one, 0, 1, bit ? 0 : 1, mode);
+
+ /* drive TMSC to desired TMS value (always zero in this context) */
+ mpsse_clock_tms_cs_out(mpsse_ctx, &one, 0, 1, false, mode);
+ }
+
+ if (tmsc_en)
+ ftdi_set_signal(tmsc_en, '0'); /* put TMSC in high impedance */
+
+ /* drive another TCK without driving TMSC (TDO cycle) */
+ mpsse_clock_tms_cs(mpsse_ctx, &zero, 0, in, in_offset + i, 1, false, mode);
+
+ if (tmsc_en)
+ ftdi_set_signal(tmsc_en, '1'); /* drive again TMSC */
+ }
+}
+
+static void oscan1_mpsse_clock_tms_cs(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset, uint8_t *in,
+ unsigned int in_offset, unsigned int length, bool tdi, uint8_t mode)
+{
+ static const uint8_t zero;
+ static const uint8_t one = 1;
+
+ struct signal *tmsc_en = find_signal_by_name("TMSC_EN");
+
+ LOG_DEBUG_IO("%sout %d bits, tdi=%d", in ? "in" : "", length, tdi);
+
+ for (unsigned int i = 0; i < length; i++) {
+ int bitnum;
+ uint8_t tmsbit;
+ uint8_t tdibit;
+
+ /* OScan1 uses 3 separate clocks */
+
+ /* drive TMSC to the *negation* of the desired TDI value */
+ tdibit = tdi ? 0 : 1;
+
+ /* drive TMSC to desired TMS value */
+ bitnum = out_offset + i;
+ tmsbit = ((out[bitnum / 8] >> (bitnum % 8)) & 0x1);
+
+ if (tdibit == tmsbit) {
+ /* Can squash into a single MPSSE command */
+ const uint8_t tmsbits = 0x3;
+ mpsse_clock_tms_cs_out(mpsse_ctx, &tmsbits, 0, 2, tdibit, mode);
+ } else {
+ /* Unoptimized case, can't formulate with a single command */
+ mpsse_clock_tms_cs_out(mpsse_ctx, &one, 0, 1, tdibit, mode);
+ mpsse_clock_tms_cs_out(mpsse_ctx, &one, 0, 1, (tmsbit != 0), mode);
+ }
+
+ if (tmsc_en)
+ ftdi_set_signal(tmsc_en, '0'); /* put TMSC in high impedance */
+
+ /* drive another TCK without driving TMSC (TDO cycle) */
+ mpsse_clock_tms_cs(mpsse_ctx, &zero, 0, in, in_offset + i, 1, false, mode);
+
+ if (tmsc_en)
+ ftdi_set_signal(tmsc_en, '1'); /* drive again TMSC */
+ }
+}
+
+static void oscan1_mpsse_clock_tms_cs_out(struct mpsse_ctx *ctx, const uint8_t *out, unsigned int out_offset,
+ unsigned int length, bool tdi, uint8_t mode)
+{
+ oscan1_mpsse_clock_tms_cs(ctx, out, out_offset, 0, 0, length, tdi, mode);
+}
+
+static void cjtag_set_tck_tms_tdi(struct signal *tck, char tckvalue, struct signal *tms,
+ char tmsvalue, struct signal *tdi, char tdivalue)
+{
+ ftdi_set_signal(tms, tmsvalue);
+ ftdi_set_signal(tdi, tdivalue);
+ ftdi_set_signal(tck, tckvalue);
+}
+
+static void cjtag_reset_online_activate(void)
+{
+ /* After TAP reset, the cJTAG-to-JTAG adapter is in offline and
+ non-activated state. Escape sequences are needed to bring the
+ TAP online and activated into the desired working mode. */
+
+ struct signal *tck = find_signal_by_name("TCK");
+ struct signal *tdi = find_signal_by_name("TDI");
+ struct signal *tms = find_signal_by_name("TMS");
+ struct signal *tdo = find_signal_by_name("TDO");
+ struct signal *tmsc_en = find_signal_by_name("TMSC_EN");
+ uint16_t tdovalue;
+
+ static struct {
+ int8_t tck;
+ int8_t tms;
+ int8_t tdi;
+ } sequence[] = {
+ /* TCK=0, TMS=1, TDI=0 (drive TMSC to 0 baseline) */
+ {'0', '1', '0'},
+
+ /* Drive cJTAG escape sequence for TAP reset - 8 TMSC edges */
+ /* TCK=1, TMS=1, TDI=0 (rising edge of TCK with TMSC still 0) */
+ {'1', '1', '0'},
+ /* TCK=1, TMS=1, TDI=1 (drive rising TMSC edge) */
+ {'1', '1', '1'},
+ /* TCK=1, TMS=1, TDI=0 (drive falling TMSC edge) */
+ {'1', '1', '0'},
+ /* TCK=1, TMS=1, TDI=1 (drive rising TMSC edge) */
+ {'1', '1', '1'},
+ /* TCK=1, TMS=1, TDI=0 (drive falling TMSC edge) */
+ {'1', '1', '0'},
+ /* TCK=1, TMS=1, TDI=1 (drive rising TMSC edge) */
+ {'1', '1', '1'},
+ /* TCK=1, TMS=1, TDI=0 (drive falling TMSC edge) */
+ {'1', '1', '0'},
+ /* TCK=1, TMS=1, TDI=1 (drive rising TMSC edge) */
+ {'1', '1', '1'},
+ /* TCK=1, TMS=1, TDI=0 (drive falling TMSC edge) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=0 (falling edge TCK with TMSC still 0) */
+ {'0', '1', '0'},
+
+ /* 3 TCK pulses for padding */
+ /* TCK=1, TMS=1, TDI=0 (drive rising TCK edge) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=0 (drive falling TCK edge) */
+ {'0', '1', '0'},
+ /* TCK=1, TMS=1, TDI=0 (drive rising TCK edge) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=0 (drive falling TCK edge) */
+ {'0', '1', '0'},
+ /* TCK=1, TMS=1, TDI=0 (drive rising TCK edge) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=0 (drive falling TCK edge) */
+ {'0', '1', '0'},
+
+ /* Drive cJTAG escape sequence for SELECT */
+ /* TCK=1, TMS=1, TDI=0 (rising edge of TCK with TMSC still 0, TAP reset that was just setup occurs here too) */
+ {'1', '1', '0'},
+ /* TCK=1, TMS=1, TDI=1 (drive rising TMSC edge) */
+ {'1', '1', '1'},
+ /* TCK=1, TMS=1, TDI=0 (drive falling TMSC edge) */
+ {'1', '1', '0'},
+ /* TCK=1, TMS=1, TDI=1 (drive rising TMSC edge) */
+ {'1', '1', '1'},
+ /* TCK=1, TMS=1, TDI=0 (drive falling TMSC edge) */
+ {'1', '1', '0'},
+ /* TCK=1, TMS=1, TDI=1 (drive rising TMSC edge) */
+ {'1', '1', '1'},
+ /* TCK=1, TMS=1, TDI=0 (drive falling TMSC edge) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=0 (falling edge TCK with TMSC still 0) */
+ {'0', '1', '0'},
+
+ /* Drive cJTAG escape sequence for OScan1 activation -- OAC = 1100 -> 2 wires -- */
+ /* TCK=1, TMS=1, TDI=0 (rising edge TCK with TMSC still 0... online mode activated... also OAC bit0==0) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=0 (falling edge TCK) */
+ {'0', '1', '0'},
+ /* TCK=1, TMS=1, TDI=0 (rising edge TCK... OAC bit1==0) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=1 (falling edge TCK) */
+ {'0', '1', '1'},
+ /* TCK=1, TMS=1, TDI=1 (rising edge TCK... OAC bit2==1) */
+ {'1', '1', '1'},
+ /* TCK=0, TMS=1, TDI=1 (falling edge TCK, TMSC stays high) */
+ {'0', '1', '1'},
+ /* TCK=1, TMS=1, TDI=1 (rising edge TCK... OAC bit3==1) */
+ {'1', '1', '1'},
+ /* TCK=0, TMS=1, TDI=0 (falling edge TCK) */
+ {'0', '1', '0'},
+ /* TCK=1, TMS=1, TDI=0 (rising edge TCK... EC bit0==0) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=0 (falling edge TCK) */
+ {'0', '1', '0'},
+ /* TCK=1, TMS=1, TDI=0 (rising edge TCK... EC bit1==0) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=0 (falling edge TCK) */
+ {'0', '1', '0'},
+ /* TCK=1, TMS=1, TDI=0 (rising edge TCK... EC bit2==0) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=1 (falling edge TCK) */
+ {'0', '1', '1'},
+ /* TCK=1, TMS=1, TDI=1 (rising edge TCK... EC bit3==1) */
+ {'1', '1', '1'},
+ /* TCK=0, TMS=1, TDI=0 (falling edge TCK) */
+ {'0', '1', '0'},
+ /* TCK=1, TMS=1, TDI=0 (rising edge TCK... CP bit0==0) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=0 (falling edge TCK) */
+ {'0', '1', '0'},
+ /* TCK=1, TMS=1, TDI=0 (rising edge TCK... CP bit1==0) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=0 (falling edge TCK) */
+ {'0', '1', '0'},
+ /* TCK=1, TMS=1, TDI=0 (rising edge TCK... CP bit2==0) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=0 (falling edge TCK) */
+ {'0', '1', '0'},
+ /* TCK=1, TMS=1, TDI=0 (rising edge TCK... CP bit3==0) */
+ {'1', '1', '0'},
+ /* TCK=0, TMS=1, TDI=0 (falling edge TCK) */
+ {'0', '1', '0'},
+ };
+
+ if (!oscan1_mode && !jscan3_mode)
+ return; /* Nothing to do */
+
+ if (oscan1_mode && jscan3_mode) {
+ LOG_ERROR("Both oscan1_mode and jscan3_mode are \"on\". At most one of them can be enabled.");
+ return;
+ }
+
+ if (!tck) {
+ LOG_ERROR("Can't run cJTAG online/activate escape sequences: TCK signal is not defined");
+ return;
+ }
+
+ if (!tdi) {
+ LOG_ERROR("Can't run cJTAG online/activate escape sequences: TDI signal is not defined");
+ return;
+ }
+
+ if (!tms) {
+ LOG_ERROR("Can't run cJTAG online/activate escape sequences: TMS signal is not defined");
+ return;
+ }
+
+ if (!tdo) {
+ LOG_ERROR("Can't run cJTAG online/activate escape sequences: TDO signal is not defined");
+ return;
+ }
+
+ if (jscan3_mode) {
+ /* Update the sequence above to enable JScan3 instead of OScan1 */
+ sequence[ESCAPE_SEQ_OAC_BIT2].tdi = '0';
+ sequence[ESCAPE_SEQ_OAC_BIT2 + 1].tdi = '0';
+ }
+
+ /* if defined TMSC_EN, replace tms with it */
+ if (tmsc_en)
+ tms = tmsc_en;
+
+ /* Send the sequence to the adapter */
+ for (size_t i = 0; i < ARRAY_SIZE(sequence); i++)
+ cjtag_set_tck_tms_tdi(tck, sequence[i].tck, tms, sequence[i].tms, tdi, sequence[i].tdi);
+
+ /* If JScan3 mode, configure cJTAG adapter to 4-wire */
+ if (jscan3_mode)
+ ftdi_set_signal(find_signal_by_name("JTAG_SEL"), '1');
+
+ ftdi_get_signal(tdo, &tdovalue); /* Just to force a flush */
+}
+#endif /* #if BUILD_FTDI_CJTAG == 1 */
+
COMMAND_HANDLER(ftdi_handle_device_desc_command)
{
if (CMD_ARGC == 1) {
@@ -917,6 +1293,32 @@ COMMAND_HANDLER(ftdi_handle_tdo_sample_edge_command)
return ERROR_OK;
}
+#if BUILD_FTDI_CJTAG == 1
+COMMAND_HANDLER(ftdi_handle_oscan1_mode_command)
+{
+ if (CMD_ARGC > 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_ON_OFF(CMD_ARGV[0], oscan1_mode);
+
+ command_print(CMD, "oscan1 mode: %s.", oscan1_mode ? "on" : "off");
+ return ERROR_OK;
+}
+
+COMMAND_HANDLER(ftdi_handle_jscan3_mode_command)
+{
+ if (CMD_ARGC > 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ if (CMD_ARGC == 1)
+ COMMAND_PARSE_ON_OFF(CMD_ARGV[0], jscan3_mode);
+
+ command_print(CMD, "jscan3 mode: %s.", jscan3_mode ? "on" : "off");
+ return ERROR_OK;
+}
+#endif
+
static const struct command_registration ftdi_subcommand_handlers[] = {
{
.name = "device_desc",
@@ -978,6 +1380,22 @@ static const struct command_registration ftdi_subcommand_handlers[] = {
"allow signalling speed increase)",
.usage = "(rising|falling)",
},
+#if BUILD_FTDI_CJTAG == 1
+ {
+ .name = "oscan1_mode",
+ .handler = &ftdi_handle_oscan1_mode_command,
+ .mode = COMMAND_ANY,
+ .help = "set to 'on' to use OScan1 mode for signaling, otherwise 'off' (default is 'off')",
+ .usage = "(on|off)",
+ },
+ {
+ .name = "jscan3_mode",
+ .handler = &ftdi_handle_jscan3_mode_command,
+ .mode = COMMAND_ANY,
+ .help = "set to 'on' to use JScan3 mode for signaling, otherwise 'off' (default is 'off')",
+ .usage = "(on|off)",
+ },
+#endif
COMMAND_REGISTRATION_DONE
};
diff --git a/tcl/interface/ftdi/olimex-arm-jtag-cjtag.cfg b/tcl/interface/ftdi/olimex-arm-jtag-cjtag.cfg
new file mode 100644
index 000000000..25addb0ca
--- /dev/null
+++ b/tcl/interface/ftdi/olimex-arm-jtag-cjtag.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM JTAG SWD adapter
+# https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-SWD/
+#
+
+#
+# Olimex ARM-USB-TINY-H
+#
+# http://www.olimex.com/dev/arm-usb-tiny-h.html
+#
+
+interface ftdi
+ftdi oscan1_mode on
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi vid_pid 0x15ba 0x002a
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+# oscan1_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
+
+# These signals are used for cJTAG escape sequence on initialization only
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
diff --git a/tcl/interface/ftdi/olimex-arm-usb-ocd-h-cjtag.cfg b/tcl/interface/ftdi/olimex-arm-usb-ocd-h-cjtag.cfg
new file mode 100644
index 000000000..85d66ef01
--- /dev/null
+++ b/tcl/interface/ftdi/olimex-arm-usb-ocd-h-cjtag.cfg
@@ -0,0 +1,24 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM-USB-OCD-H (using cJTAG)
+#
+# http://www.olimex.com/dev/arm-usb-ocd-h.html
+#
+
+interface ftdi
+ftdi oscan1_mode on
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-OCD-H"
+ftdi vid_pid 0x15ba 0x002b
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+# oscan1_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
+
+# These signals are used for cJTAG escape sequence on initialization only
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
diff --git a/tcl/interface/ftdi/olimex-arm-usb-tiny-h-cjtag.cfg b/tcl/interface/ftdi/olimex-arm-usb-tiny-h-cjtag.cfg
new file mode 100644
index 000000000..ee09e81e2
--- /dev/null
+++ b/tcl/interface/ftdi/olimex-arm-usb-tiny-h-cjtag.cfg
@@ -0,0 +1,29 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Olimex ARM JTAG SWD adapter
+# https://www.olimex.com/Products/ARM/JTAG/ARM-JTAG-SWD/
+#
+
+#
+# Olimex ARM-USB-TINY-H (using cJTAG)
+#
+# http://www.olimex.com/dev/arm-usb-tiny-h.html
+#
+
+interface ftdi
+ftdi oscan1_mode on
+ftdi device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi vid_pid 0x15ba 0x002a
+
+ftdi layout_init 0x0808 0x0a1b
+ftdi layout_signal nSRST -oe 0x0200
+# oscan1_ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi layout_signal LED -data 0x0800
+
+# These signals are used for cJTAG escape sequence on initialization only
+ftdi layout_signal TCK -data 0x0001
+ftdi layout_signal TDI -data 0x0002
+ftdi layout_signal TDO -input 0x0004
+ftdi layout_signal TMS -data 0x0008
+ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
-----------------------------------------------------------------------
Summary of changes:
configure.ac | 1 +
doc/openocd.texi | 29 ++
src/jtag/drivers/ftdi.c | 438 ++++++++++++++++++++-
tcl/interface/ftdi/olimex-arm-jtag-cjtag.cfg | 29 ++
tcl/interface/ftdi/olimex-arm-usb-ocd-h-cjtag.cfg | 24 ++
tcl/interface/ftdi/olimex-arm-usb-tiny-h-cjtag.cfg | 29 ++
6 files changed, 540 insertions(+), 10 deletions(-)
create mode 100644 tcl/interface/ftdi/olimex-arm-jtag-cjtag.cfg
create mode 100644 tcl/interface/ftdi/olimex-arm-usb-ocd-h-cjtag.cfg
create mode 100644 tcl/interface/ftdi/olimex-arm-usb-tiny-h-cjtag.cfg
hooks/post-receive
--
Main OpenOCD repository
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|
From: openocd-gerrit <ope...@us...> - 2025-11-30 10:23:27
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 181547327f11ea56d24b1d15989df81355b2b7d0 (commit)
from eef37df3aaeab98ac8df4ad6447680228d2a9772 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.
- Log -----------------------------------------------------------------
commit 181547327f11ea56d24b1d15989df81355b2b7d0
Author: Kulyatskaya Alexandra <a.k...@sy...>
Date: Tue Jun 24 15:37:48 2025 +0300
target/breakpoints.c: add breakpoint intersection detection
Modify the breakpoint insertion logic to include intersection detection
between breakpoints.
Change-Id: I294bea83b18335c2f304ddd99361872eadaaa684
Signed-off-by: Kulyatskaya Alexandra <a.k...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9146
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/helper/util.c b/src/helper/util.c
index 2e9f6155e..1ced8bd5f 100644
--- a/src/helper/util.c
+++ b/src/helper/util.c
@@ -40,3 +40,26 @@ int util_init(struct command_context *cmd_ctx)
{
return register_commands(cmd_ctx, NULL, util_command_handlers);
}
+
+bool is_memory_regions_overlap(target_addr_t start1,
+ unsigned int size1,
+ target_addr_t start2,
+ unsigned int size2)
+{
+ /* Two memory regions: [S1,E1] and [S2,E2] where:
+ * E1 = S1 + size1 - 1, E2 = S2 + size2 - 1
+ *
+ * After normalization:
+ * Region 1: [0, size1 - 1]
+ * Region 2: [start2 - start1, (start2 - start1) + size2 - 1]
+ *
+ * Intersection cases:
+ * 1. Normalized region 2 wraps around 0 (unsigned overflow)
+ * 2. Start of normalized region 2 is within region 1
+ */
+ start2 -= start1;
+ target_addr_t end1 = size1 - 1;
+ target_addr_t end2 = start2 + size2 - 1;
+
+ return start2 > end2 || start2 <= end1;
+}
diff --git a/src/helper/util.h b/src/helper/util.h
index 3ccdc4fdf..c10135678 100644
--- a/src/helper/util.h
+++ b/src/helper/util.h
@@ -10,5 +10,7 @@
struct command_context;
int util_init(struct command_context *cmd_ctx);
+bool is_memory_regions_overlap(target_addr_t start1, unsigned int size1,
+ target_addr_t start2, unsigned int size2);
#endif /* OPENOCD_HELPER_UTIL_H */
diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index 753c343c5..d260009f5 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -16,6 +16,7 @@
#include <helper/log.h>
#include "breakpoints.h"
#include "smp.h"
+#include "helper/util.h"
enum breakpoint_watchpoint {
BREAKPOINT,
@@ -56,6 +57,13 @@ static int breakpoint_add_internal(struct target *target,
address, breakpoint->unique_id);
return ERROR_TARGET_DUPLICATE_BREAKPOINT;
}
+ if (type == BKPT_SOFT &&
+ is_memory_regions_overlap(address, length, breakpoint->address, breakpoint->length)) {
+ LOG_TARGET_ERROR(target, "Breakpoint intersects with another one at " TARGET_ADDR_FMT
+ " of length %u (BP %" PRIu32 ")", breakpoint->address,
+ breakpoint->length, breakpoint->unique_id);
+ return ERROR_TARGET_INTERSECT_BREAKPOINT;
+ }
breakpoint_p = &breakpoint->next;
breakpoint = breakpoint->next;
}
diff --git a/src/target/target.h b/src/target/target.h
index 94e6aa335..3e202ffa6 100644
--- a/src/target/target.h
+++ b/src/target/target.h
@@ -796,6 +796,7 @@ int target_profiling_default(struct target *target, uint32_t *samples, uint32_t
#define ERROR_TARGET_SIZE_NOT_SUPPORTED (-314)
#define ERROR_TARGET_PACKING_NOT_SUPPORTED (-315)
#define ERROR_TARGET_HALTED_DO_RESUME (-316) /* used to workaround incorrect debug halt */
+#define ERROR_TARGET_INTERSECT_BREAKPOINT (-317)
extern bool get_target_reset_nag(void);
-----------------------------------------------------------------------
Summary of changes:
src/helper/util.c | 23 +++++++++++++++++++++++
src/helper/util.h | 2 ++
src/target/breakpoints.c | 8 ++++++++
src/target/target.h | 1 +
4 files changed, 34 insertions(+)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-11-30 10:22:37
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via eef37df3aaeab98ac8df4ad6447680228d2a9772 (commit)
from 37dcf4359bd22025aaa809a8559b129ed6607195 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit eef37df3aaeab98ac8df4ad6447680228d2a9772
Author: Antonio Borneo <bor...@gm...>
Date: Wed Nov 5 14:45:29 2025 +0100
target: cortex-m: defer cache identification on Cortex-M7 under reset
On Cortex-M7 only, several registers in System Control Space (SCS)
are not accessible when the CPU is under reset, generating a bus
error.
This causes OpenOCD to fail examining the CPU when the board reset
button is pressed or when the flag 'connect_assert_srst' is used
on 'reset_config' command.
Introduce a deferred identification of the cache and run it during
polling and at target halted (just in case of polling disabled).
Change-Id: Ia5c582ae95f825c5fb8c2dcfb320142f7ac04a9f
Signed-off-by: Antonio Borneo <bor...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9232
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
diff --git a/src/target/armv7m_cache.c b/src/target/armv7m_cache.c
index cc0c9d140..f07ac142f 100644
--- a/src/target/armv7m_cache.c
+++ b/src/target/armv7m_cache.c
@@ -68,7 +68,7 @@ static struct armv7m_cache_size decode_ccsidr(uint32_t ccsidr)
return size;
}
-int armv7m_identify_cache(struct target *target)
+static int armv7m_identify_cache_internal(struct target *target)
{
struct armv7m_common *armv7m = target_to_armv7m(target);
struct armv7m_cache_common *cache = &armv7m->armv7m_cache;
@@ -191,6 +191,54 @@ int armv7m_identify_cache(struct target *target)
return ERROR_OK;
}
+/*
+ * On Cortex-M7 only, when the CPU is kept in reset, several registers of the
+ * System Control Space (SCS) are not accessible and return bus error.
+ * The list of accessible registers is:
+ * - 0xE000ED00
+ * - 0xE000ED30
+ * - 0xE000EDF0 ... 0xE000EEFC
+ * - 0xE000EF40 ... 0xE000EF48
+ * - 0xE000EFD0 ... 0xE000EFFC
+ * This makes impossible detecting the cache during the reset.
+ * Use a deferred mechanism to detect the cache during polling or when the
+ * Cortex-M7 halts.
+ */
+int armv7m_identify_cache(struct target *target)
+{
+ struct cortex_m_common *cortex_m = target_to_cm(target);
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct armv7m_cache_common *cache = &armv7m->armv7m_cache;
+
+ if (cache->info_valid)
+ return ERROR_OK;
+
+ if (cortex_m->core_info->impl_part == CORTEX_M7_PARTNO
+ && cortex_m->dcb_dhcsr & S_RESET_ST) {
+ cache->defer_identification = true;
+ return ERROR_OK;
+ }
+
+ return armv7m_identify_cache_internal(target);
+}
+
+int armv7m_deferred_identify_cache(struct target *target)
+{
+ struct armv7m_common *armv7m = target_to_armv7m(target);
+ struct armv7m_cache_common *cache = &armv7m->armv7m_cache;
+
+ if (cache->info_valid || !cache->defer_identification)
+ return ERROR_OK;
+
+ int retval = armv7m_identify_cache_internal(target);
+ if (retval != ERROR_OK)
+ return retval;
+
+ cache->defer_identification = false;
+
+ return ERROR_OK;
+}
+
int armv7m_d_cache_flush(struct target *target, uint32_t address,
unsigned int length)
{
@@ -250,6 +298,11 @@ int armv7m_handle_cache_info_command(struct command_invocation *cmd,
return ERROR_FAIL;
}
+ if (cache->defer_identification) {
+ command_print(cmd, "Cache not detected yet");
+ return ERROR_OK;
+ }
+
if (!cache->info_valid) {
command_print(cmd, "No cache detected");
return ERROR_OK;
diff --git a/src/target/armv7m_cache.h b/src/target/armv7m_cache.h
index 576bff8d6..e6d943209 100644
--- a/src/target/armv7m_cache.h
+++ b/src/target/armv7m_cache.h
@@ -38,6 +38,7 @@ struct armv7m_arch_cache {
// common cache information
struct armv7m_cache_common {
bool info_valid;
+ bool defer_identification;
bool has_i_cache;
bool has_d_u_cache;
unsigned int loc; // level of coherency
@@ -47,6 +48,7 @@ struct armv7m_cache_common {
};
int armv7m_identify_cache(struct target *target);
+int armv7m_deferred_identify_cache(struct target *target);
int armv7m_d_cache_flush(struct target *target, uint32_t address,
unsigned int length);
int armv7m_i_cache_inval(struct target *target, uint32_t address,
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index d15575bd7..ea94f1242 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -876,6 +876,10 @@ static int cortex_m_debug_entry(struct target *target)
}
// read caches state
+ retval = armv7m_deferred_identify_cache(target);
+ if (retval != ERROR_OK)
+ return retval;
+
uint32_t ccr = 0;
if (armv7m->armv7m_cache.info_valid) {
retval = mem_ap_read_u32(armv7m->debug_ap, CCR, &ccr);
@@ -1018,6 +1022,10 @@ static int cortex_m_poll_one(struct target *target)
/* S_RESET_ST was expected (in a reset command). Continue processing
* to quickly get out of TARGET_RESET state */
+ } else {
+ retval = armv7m_deferred_identify_cache(target);
+ if (retval != ERROR_OK)
+ return retval;
}
if (target->state == TARGET_RESET) {
@@ -2952,6 +2960,18 @@ int cortex_m_examine(struct target *target)
if (retval != ERROR_OK)
return retval;
+ /*
+ * Use a safe value of sticky S_RESET_ST for cache detection, before
+ * clearing it below.
+ */
+ if (!armv7m->is_hla_target) {
+ retval = armv7m_identify_cache(target);
+ if (retval != ERROR_OK) {
+ LOG_ERROR("Cannot detect cache");
+ return retval;
+ }
+ }
+
/* Don't cumulate sticky S_RESET_ST at the very first read of DHCSR
* as S_RESET_ST may indicate a reset that happened long time ago
* (most probably the power-on reset before OpenOCD was started).
@@ -3021,14 +3041,6 @@ int cortex_m_examine(struct target *target)
LOG_TARGET_INFO(target, "target has %d breakpoints, %d watchpoints",
cortex_m->fp_num_code,
cortex_m->dwt_num_comp);
-
- if (!armv7m->is_hla_target) {
- retval = armv7m_identify_cache(target);
- if (retval != ERROR_OK) {
- LOG_ERROR("Cannot detect cache");
- return retval;
- }
- }
}
return ERROR_OK;
-----------------------------------------------------------------------
Summary of changes:
src/target/armv7m_cache.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++-
src/target/armv7m_cache.h | 2 ++
src/target/cortex_m.c | 28 +++++++++++++++++-------
3 files changed, 76 insertions(+), 9 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-11-30 07:39:45
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 37dcf4359bd22025aaa809a8559b129ed6607195 (commit)
from a1c7cd4fef95ef85dc87c6ebd66e3e3cc5dcda9d (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 37dcf4359bd22025aaa809a8559b129ed6607195
Author: Tomas Vanek <va...@fb...>
Date: Fri Nov 21 09:27:20 2025 +0100
target/cortex_a: emit 'resumed' event for all SMP cores
In a SMP configuration 'resumed' event was emitted only for
the active core, in contradiction to 'halted' event, which
gets emitted for all cores from the SMP group:
> resume
target event 3 (resume-start) for core stm32mp15x.cpu0
target event 2 (resumed) for core stm32mp15x.cpu0
target event 4 (resume-end) for core stm32mp15x.cpu0
target event 7 (gdb-start) for core stm32mp15x.cpu0
> halt
target event 0 (gdb-halt) for core stm32mp15x.cpu1
target event 1 (halted) for core stm32mp15x.cpu1
target event 0 (gdb-halt) for core stm32mp15x.cpu0
target event 1 (halted) for core stm32mp15x.cpu0
target event 8 (gdb-end) for core stm32mp15x.cpu0
Emit 'resumed' event in cortex_a_restore_smp().
While on it replace adding the returned errors together
with the proper error handling.
Change-Id: I9debef0884519cde767707f78f163b136ecc7aa5
Signed-off-by: Tomas Vanek <va...@fb...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9244
Reviewed-by: Antonio Borneo <bor...@gm...>
Tested-by: jenkins
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index a9c034b55..3d8603a4b 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -968,7 +968,7 @@ static int cortex_a_internal_restart(struct target *target)
static int cortex_a_restore_smp(struct target *target, bool handle_breakpoints)
{
- int retval = 0;
+ int retval = ERROR_OK;
struct target_list *head;
target_addr_t address;
@@ -977,9 +977,17 @@ static int cortex_a_restore_smp(struct target *target, bool handle_breakpoints)
if ((curr != target) && (curr->state != TARGET_RUNNING)
&& target_was_examined(curr)) {
/* resume current address , not in step mode */
- retval += cortex_a_internal_restore(curr, true, &address,
+ int retval2 = cortex_a_internal_restore(curr, true, &address,
handle_breakpoints, false);
- retval += cortex_a_internal_restart(curr);
+
+ if (retval2 == ERROR_OK)
+ retval2 = cortex_a_internal_restart(curr);
+
+ if (retval2 == ERROR_OK)
+ target_call_event_callbacks(curr, TARGET_EVENT_RESUMED);
+
+ if (retval == ERROR_OK)
+ retval = retval2; // save the first error
}
}
return retval;
-----------------------------------------------------------------------
Summary of changes:
src/target/cortex_a.c | 14 +++++++++++---
1 file changed, 11 insertions(+), 3 deletions(-)
hooks/post-receive
--
Main OpenOCD repository
|
|
From: openocd-gerrit <ope...@us...> - 2025-11-27 21:08:45
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via a1c7cd4fef95ef85dc87c6ebd66e3e3cc5dcda9d (commit)
from 1ea763d23c2337374909170687e16d1c5b9d9e89 (commit)
Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit a1c7cd4fef95ef85dc87c6ebd66e3e3cc5dcda9d
Author: Marc Schink <de...@za...>
Date: Mon Jul 14 07:01:58 2025 +0000
flash/nor/stm32lx: Add 'option_load' command
Add command to re-load option bytes.
Tested with STM32L072CZ and STM32L152RCT6.
Change-Id: I5653f2222a48af1fe0332d4bdc3552e481e375d0
Signed-off-by: Marc Schink <de...@za...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8998
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 57f8703ad..09bbd3dd9 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -8422,6 +8422,12 @@ data). This is the only way to unlock a protected flash (unless RDP
Level is 2 which can't be unlocked at all).
The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
+
+@deffn {Command} {stm32lx option_load} num
+Forces a re-load of the option byte registers.
+This command will cause a system reset of the device.
+The @var{num} parameter is a value shown by @command{flash banks}.
+@end deffn
@end deffn
@deffn {Flash Driver} {stm32l4x}
diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c
index 2c7563e95..f0e8db5ba 100644
--- a/src/flash/nor/stm32lx.c
+++ b/src/flash/nor/stm32lx.c
@@ -90,6 +90,7 @@ static int stm32lx_lock_program_memory(struct flash_bank *bank);
static int stm32lx_enable_write_half_page(struct flash_bank *bank);
static int stm32lx_erase_sector(struct flash_bank *bank, int sector);
static int stm32lx_wait_until_bsy_clear(struct flash_bank *bank);
+static int stm32lx_obl_launch(struct flash_bank *bank);
static int stm32lx_lock(struct flash_bank *bank);
static int stm32lx_unlock(struct flash_bank *bank);
static int stm32lx_mass_erase(struct flash_bank *bank);
@@ -354,6 +355,26 @@ COMMAND_HANDLER(stm32lx_handle_unlock_command)
return retval;
}
+COMMAND_HANDLER(stm32lx_handle_option_load_command)
+{
+ if (CMD_ARGC != 1)
+ return ERROR_COMMAND_SYNTAX_ERROR;
+
+ struct flash_bank *bank;
+ int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = stm32lx_obl_launch(bank);
+ if (retval != ERROR_OK) {
+ command_print(CMD, "failed to load option bytes");
+ return retval;
+ }
+
+ return ERROR_OK;
+}
+
static int stm32lx_protect_check(struct flash_bank *bank)
{
int retval;
@@ -921,6 +942,13 @@ static const struct command_registration stm32lx_exec_command_handlers[] = {
.usage = "bank_id",
.help = "Lower the readout protection from Level 1 to 0.",
},
+ {
+ .name = "option_load",
+ .handler = stm32lx_handle_option_load_command,
+ .mode = COMMAND_EXEC,
+ .usage = "bank_id",
+ .help = "Force re-load of device options (will cause device reset).",
+ },
COMMAND_REGISTRATION_DONE
};
@@ -1238,7 +1266,10 @@ static int stm32lx_obl_launch(struct flash_bank *bank)
{
struct target *target = bank->target;
struct stm32lx_flash_bank *stm32lx_info = bank->driver_priv;
- int retval;
+
+ int retval = stm32lx_unlock_options_bytes(bank);
+ if (retval != ERROR_OK)
+ return retval;
/* This will fail as the target gets immediately rebooted */
target_write_u32(target, stm32lx_info->flash_base + FLASH_PECR,
-----------------------------------------------------------------------
Summary of changes:
doc/openocd.texi | 6 ++++++
src/flash/nor/stm32lx.c | 33 ++++++++++++++++++++++++++++++++-
2 files changed, 38 insertions(+), 1 deletion(-)
hooks/post-receive
--
Main OpenOCD repository
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|
From: openocd-gerrit <ope...@us...> - 2025-11-24 14:05:07
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 1ea763d23c2337374909170687e16d1c5b9d9e89 (commit)
from 7b6496db7e1c41d62be944021f46543bbbfba4ae (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 1ea763d23c2337374909170687e16d1c5b9d9e89
Author: Greg Savin <gre...@si...>
Date: Mon Feb 7 09:28:31 2022 -0800
rtos: server/gdb_server: fix missing thread ID in stop reply
Cherry-picked from [1].
To replicate the issue that this fixes:
1. Connect to a multi-hart RISC-V target configured as an SMP group.
2. Start a GDB instance against the running OpenOCD.
3. Observe that GDB might display "warning: multi-threaded target
stopped without sending a thread-id, using first non-exited thread."
4. Set a breakpoint in code that any non-hart-0 hart is expected to
reach (but hart 0 is not expected to reach).
5. Allow a non-hart-0 hart to reach the breakpoint.
6. Remove the breakpoint.
7. Do a few sequential `stepi` commands in GDB.
8. Observe that GDB displays "Switching to Thread 1" even though the
thread that was just single stepped was not Thread 1 in GDB. Also
observe that the register values in GDB correspond to the thread that
was single-stepped, not Thread 1. Basically GDB erroneously starts to
consider thread 1 to be current, when in fact the thread that was
single-stepped is still current.
The changes in this pull request are intended to avoid the erroneous
"Switching to Thread 1" described in (8) above.
What was happening was that, in a couple areas of code, non-hart-0 harts
weren't seen as belonging to an RTOS module, and this had the effect of
(1) bypassing `hwthread_update_threads()` being called after a halt; (2)
omitting a thread ID in a stop reply over GDB remote protocol connection
(requiring GDB to take an arbitrary guess of current thread id, a guess
that is wrong unless the current thread happens to be hart 0).
Link: https://github.com/riscv-collab/riscv-openocd/pull/675 [1]
Change-Id: I9872062dfa0e3f1ca531d282d52a1b04c527546a
Signed-off-by: Greg Savin <gre...@si...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9183
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 547314c0a..cc0e92edf 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -11,6 +11,7 @@
#include "rtos.h"
#include "target/target.h"
+#include "target/smp.h"
#include "helper/log.h"
#include "helper/binarybuffer.h"
#include "helper/types.h"
@@ -715,10 +716,24 @@ int rtos_generic_stack_read(struct target *target,
return ERROR_OK;
}
+struct rtos *rtos_from_target(struct target *target)
+{
+ if (target->rtos && target->rtos->type)
+ return target->rtos;
+
+ struct target_list *pos;
+ foreach_smp_target(pos, target->smp_targets)
+ if (pos->target->rtos && pos->target->rtos->type)
+ return pos->target->rtos;
+
+ return NULL;
+}
+
int rtos_update_threads(struct target *target)
{
- if ((target->rtos) && (target->rtos->type))
- target->rtos->type->update_threads(target->rtos);
+ struct rtos *rtos = rtos_from_target(target);
+ if (rtos)
+ rtos->type->update_threads(rtos);
return ERROR_OK;
}
diff --git a/src/rtos/rtos.h b/src/rtos/rtos.h
index 2084739cf..17efccf0e 100644
--- a/src/rtos/rtos.h
+++ b/src/rtos/rtos.h
@@ -154,6 +154,11 @@ int rtos_write_buffer(struct target *target, target_addr_t address,
bool rtos_needs_fake_step(struct target *target, int64_t thread_id);
struct target *rtos_swbp_target(struct target *target, target_addr_t address,
uint32_t length, enum breakpoint_type type);
+/**
+ * Get the RTOS from the target itself, or from one of the targets in
+ * the same SMP node, or NULL when no RTOS is set.
+ */
+struct rtos *rtos_from_target(struct target *target);
// Keep in alphabetic order this list of rtos
extern const struct rtos_type chibios_rtos;
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index f09e4807e..a989bda57 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -813,9 +813,12 @@ static void gdb_signal_reply(struct target *target, struct connection *connectio
sig_reply_len = snprintf(sig_reply, sizeof(sig_reply), "W00");
} else {
struct target *ct;
- if (target->rtos) {
- target->rtos->current_threadid = target->rtos->current_thread;
- target->rtos->gdb_target_for_threadid(connection, target->rtos->current_threadid, &ct);
+ struct rtos *rtos;
+
+ rtos = rtos_from_target(target);
+ if (rtos) {
+ rtos->current_threadid = rtos->current_thread;
+ rtos->gdb_target_for_threadid(connection, rtos->current_threadid, &ct);
} else {
ct = target;
}
@@ -853,9 +856,9 @@ static void gdb_signal_reply(struct target *target, struct connection *connectio
}
current_thread[0] = '\0';
- if (target->rtos)
+ if (rtos)
snprintf(current_thread, sizeof(current_thread), "thread:%" PRIx64 ";",
- target->rtos->current_thread);
+ rtos->current_thread);
sig_reply_len = snprintf(sig_reply, sizeof(sig_reply), "T%2.2x%s%s",
signal_var, stop_reason, current_thread);
-----------------------------------------------------------------------
Summary of changes:
src/rtos/rtos.c | 19 +++++++++++++++++--
src/rtos/rtos.h | 5 +++++
src/server/gdb_server.c | 13 ++++++++-----
3 files changed, 30 insertions(+), 7 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2025-11-24 14:04:51
|
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- Log -----------------------------------------------------------------
commit 7b6496db7e1c41d62be944021f46543bbbfba4ae
Author: Tim Newsome <ti...@si...>
Date: Mon Jan 31 09:23:38 2022 -0800
rtos: server: target: ask the RTOS which target to set swbp on.
This is the result of squashing two commits from RISC-V OpenOCD:
- [1] ("Ask the RTOS which target to set swbp on. (#673)")
- [2] ("Fix breackpoint_add for rtos swbp (#734)")
The resulting change lets the RTOS pick the "current" target for setting
the software breakpoint on, which matters if address translation differs
between threads.
Link: https://github.com/riscv-collab/riscv-openocd/commit/52ca5d198e3b [1]
Link: https://github.com/riscv-collab/riscv-openocd/commit/8ae41e86e15d [2]
Change-Id: I67ce24d6aa0ca9225436b380065d1e265424e70f
Signed-off-by: Tim Newsome <ti...@si...>
Signed-off-by: Evgeniy Naydanov <evg...@sy...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9176
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/rtos/hwthread.c b/src/rtos/hwthread.c
index d4fc880f6..d422fac53 100644
--- a/src/rtos/hwthread.c
+++ b/src/rtos/hwthread.c
@@ -29,6 +29,8 @@ static int hwthread_read_buffer(struct rtos *rtos, target_addr_t address,
static int hwthread_write_buffer(struct rtos *rtos, target_addr_t address,
uint32_t size, const uint8_t *buffer);
static bool hwthread_needs_fake_step(struct target *target, int64_t thread_id);
+struct target *hwthread_swbp_target(struct rtos *rtos, target_addr_t address,
+ uint32_t length, enum breakpoint_type type);
#define HW_THREAD_NAME_STR_SIZE (32)
@@ -60,7 +62,8 @@ const struct rtos_type hwthread_rtos = {
.set_reg = hwthread_set_reg,
.read_buffer = hwthread_read_buffer,
.write_buffer = hwthread_write_buffer,
- .needs_fake_step = hwthread_needs_fake_step
+ .needs_fake_step = hwthread_needs_fake_step,
+ .swbp_target = hwthread_swbp_target,
};
struct hwthread_params {
@@ -456,3 +459,9 @@ bool hwthread_needs_fake_step(struct target *target, int64_t thread_id)
{
return false;
}
+
+struct target *hwthread_swbp_target(struct rtos *rtos, target_addr_t address,
+ uint32_t length, enum breakpoint_type type)
+{
+ return hwthread_find_thread(rtos->target, rtos->current_thread);
+}
diff --git a/src/rtos/rtos.c b/src/rtos/rtos.c
index 7957a5b6b..547314c0a 100644
--- a/src/rtos/rtos.c
+++ b/src/rtos/rtos.c
@@ -762,3 +762,11 @@ bool rtos_needs_fake_step(struct target *target, int64_t thread_id)
return target->rtos->type->needs_fake_step(target, thread_id);
return target->rtos->current_thread != thread_id;
}
+
+struct target *rtos_swbp_target(struct target *target, target_addr_t address,
+ uint32_t length, enum breakpoint_type type)
+{
+ if (target->rtos->type->swbp_target)
+ return target->rtos->type->swbp_target(target->rtos, address, length, type);
+ return target;
+}
diff --git a/src/rtos/rtos.h b/src/rtos/rtos.h
index bbd1d1a1d..2084739cf 100644
--- a/src/rtos/rtos.h
+++ b/src/rtos/rtos.h
@@ -9,6 +9,7 @@
#define OPENOCD_RTOS_RTOS_H
#include "server/server.h"
+#include "target/breakpoints.h"
#include "target/target.h"
typedef int64_t threadid_t;
@@ -86,6 +87,12 @@ struct rtos_type {
* target running a multi-threading OS. If an RTOS can do this, override
* needs_fake_step(). */
bool (*needs_fake_step)(struct target *target, int64_t thread_id);
+ /* When a software breakpoint is set, it is set on only one target,
+ * because we assume memory is shared across them. By default this is the
+ * first target in the SMP group. Override this function to have
+ * breakpoint_add() use a different target. */
+ struct target * (*swbp_target)(struct rtos *rtos, target_addr_t address,
+ uint32_t length, enum breakpoint_type type);
};
struct stack_register_offset {
@@ -145,6 +152,8 @@ int rtos_read_buffer(struct target *target, target_addr_t address,
int rtos_write_buffer(struct target *target, target_addr_t address,
uint32_t size, const uint8_t *buffer);
bool rtos_needs_fake_step(struct target *target, int64_t thread_id);
+struct target *rtos_swbp_target(struct target *target, target_addr_t address,
+ uint32_t length, enum breakpoint_type type);
// Keep in alphabetic order this list of rtos
extern const struct rtos_type chibios_rtos;
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 486080bbd..f09e4807e 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1814,7 +1814,15 @@ static int gdb_breakpoint_watchpoint_packet(struct connection *connection,
case 0:
case 1:
if (packet[0] == 'Z') {
- retval = breakpoint_add(target, address, size, bp_type);
+ struct target *bp_target = target;
+ if (target->rtos && bp_type == BKPT_SOFT) {
+ bp_target = rtos_swbp_target(target, address, size, bp_type);
+ if (!bp_target) {
+ retval = ERROR_FAIL;
+ break;
+ }
+ }
+ retval = breakpoint_add(bp_target, address, size, bp_type);
} else {
assert(packet[0] == 'z');
retval = breakpoint_remove(target, address);
diff --git a/src/target/breakpoints.c b/src/target/breakpoints.c
index fa6b635f0..753c343c5 100644
--- a/src/target/breakpoints.c
+++ b/src/target/breakpoints.c
@@ -210,16 +210,10 @@ int breakpoint_add(struct target *target,
unsigned int length,
enum breakpoint_type type)
{
- if (target->smp) {
- struct target_list *head;
-
- if (type == BKPT_SOFT) {
- head = list_first_entry(target->smp_targets, struct target_list, lh);
- return breakpoint_add_internal(head->target, address, length, type);
- }
-
- foreach_smp_target(head, target->smp_targets) {
- struct target *curr = head->target;
+ if (target->smp && type == BKPT_HARD) {
+ struct target_list *list_node;
+ foreach_smp_target(list_node, target->smp_targets) {
+ struct target *curr = list_node->target;
int retval = breakpoint_add_internal(curr, address, length, type);
if (retval != ERROR_OK)
return retval;
-----------------------------------------------------------------------
Summary of changes:
src/rtos/hwthread.c | 11 ++++++++++-
src/rtos/rtos.c | 8 ++++++++
src/rtos/rtos.h | 9 +++++++++
src/server/gdb_server.c | 10 +++++++++-
src/target/breakpoints.c | 14 ++++----------
5 files changed, 40 insertions(+), 12 deletions(-)
hooks/post-receive
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From: openocd-gerrit <ope...@us...> - 2025-11-24 10:52:41
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 7487fade751a70fe58f5ba106abc4ed5ecda8a8e (commit)
from 461af9b3abd1aeb94f047f990074b7e5d954fbea (commit)
Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 7487fade751a70fe58f5ba106abc4ed5ecda8a8e
Author: NikLeberg <nik...@gm...>
Date: Mon Aug 11 13:19:08 2025 +0200
jtag/drivers/jtag_dpi: fix wraparound bug in runtest
Commit 0847a4d7fb98 ("jtag/commands: Use 'unsigned int' data type")
introduced bug when changing loop variable from `int` to `unsigned int`.
Instead of getting negative and terminating the loop, the value wraps
around to `INT_MAX` and the loop never finishes.
Change-Id: I055025a1f8eb4abe50955607b3e89530dfd92af4
Signed-off-by: NikLeberg <nik...@gm...>
Fixes: 0847a4d7fb98 ("jtag/commands: Use 'unsigned int' data type")
Reviewed-on: https://review.openocd.org/c/openocd/+/9078
Reviewed-by: Evgeniy Naydanov <eu...@gm...>
Reviewed-by: zapb <de...@za...>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/jtag/drivers/jtag_dpi.c b/src/jtag/drivers/jtag_dpi.c
index d6418d39c..35dd24507 100644
--- a/src/jtag/drivers/jtag_dpi.c
+++ b/src/jtag/drivers/jtag_dpi.c
@@ -189,7 +189,7 @@ static int jtag_dpi_runtest(unsigned int num_cycles)
return ERROR_FAIL;
}
snprintf(buf, sizeof(buf), "ib %d\n", num_bits);
- while (num_cycles > 0) {
+ for (unsigned int cycle = 0; cycle < num_cycles; cycle += num_bits + 6) {
ret = write_sock(buf, strlen(buf));
if (ret != ERROR_OK) {
LOG_ERROR("write_sock() fail, file %s, line %d",
@@ -208,8 +208,6 @@ static int jtag_dpi_runtest(unsigned int num_cycles)
__FILE__, __LINE__);
goto out;
}
-
- num_cycles -= num_bits + 6;
}
out:
-----------------------------------------------------------------------
Summary of changes:
src/jtag/drivers/jtag_dpi.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
hooks/post-receive
--
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From: openocd-gerrit <ope...@us...> - 2025-11-22 19:33:24
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
via 461af9b3abd1aeb94f047f990074b7e5d954fbea (commit)
from aa6a07108643acc1762efa34ea39c6421389b66b (commit)
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- Log -----------------------------------------------------------------
commit 461af9b3abd1aeb94f047f990074b7e5d954fbea
Author: Erhan Kurubas <erh...@es...>
Date: Mon Oct 24 18:08:35 2022 +0200
rtt/tcl: fix format specifiers
Format specifier in the LOG_XXX calls replaced as below;
type old new
uint32_t %u %PRIu32
Signed-off-by: Erhan Kurubas <erh...@es...>
Change-Id: Ie351a63088c63f33467ad3c854167870bc1b4843
Reviewed-on: https://review.openocd.org/c/openocd/+/7286
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/src/rtt/tcl.c b/src/rtt/tcl.c
index bae71b6ce..beb12d90d 100644
--- a/src/rtt/tcl.c
+++ b/src/rtt/tcl.c
@@ -117,7 +117,7 @@ COMMAND_HANDLER(handle_rtt_channels_command)
ctrl = rtt_get_control();
- command_print(CMD, "Channels: up=%u, down=%u", ctrl->num_up_channels,
+ command_print(CMD, "Channels: up=%" PRIu32 ", down=%" PRIu32, ctrl->num_up_channels,
ctrl->num_down_channels);
command_print(CMD, "Up-channels:");
@@ -134,7 +134,7 @@ COMMAND_HANDLER(handle_rtt_channels_command)
if (!info.size)
continue;
- command_print(CMD, "%u: %s %u %u", i, info.name, info.size,
+ command_print(CMD, "%u: %s %" PRIu32 " %" PRIu32, i, info.name, info.size,
info.flags);
}
@@ -149,7 +149,7 @@ COMMAND_HANDLER(handle_rtt_channels_command)
if (!info.size)
continue;
- command_print(CMD, "%u: %s %u %u", i, info.name, info.size,
+ command_print(CMD, "%u: %s %" PRIu32 " %" PRIu32, i, info.name, info.size,
info.flags);
}
-----------------------------------------------------------------------
Summary of changes:
src/rtt/tcl.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
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From: openocd-gerrit <ope...@us...> - 2025-11-22 19:32:12
|
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".
The branch, master has been updated
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from cd41947febbeb908e2c0dbf6c3c0e74d799da6c0 (commit)
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- Log -----------------------------------------------------------------
commit aa6a07108643acc1762efa34ea39c6421389b66b
Author: Mark Zhuang <mar...@sp...>
Date: Fri Oct 25 14:45:06 2024 +0800
doc:style: do not use multiple empty lines
Enable LINE_SPACING but only check multiple blank lines now
Change-Id: I332d4d414a04eec8fc54b49d416a954d30592219
Signed-off-by: Mark Zhuang <mar...@sp...>
Reviewed-on: https://review.openocd.org/c/openocd/+/8365
Reviewed-by: zapb <de...@za...>
Reviewed-by: Jan Matyas <jan...@co...>
Tested-by: jenkins
Reviewed-by: Antonio Borneo <bor...@gm...>
diff --git a/.checkpatch.conf b/.checkpatch.conf
index 01be7a909..b95dbe271 100644
--- a/.checkpatch.conf
+++ b/.checkpatch.conf
@@ -14,7 +14,6 @@
--ignore ENOSYS
--ignore FILE_PATH_CHANGES
--ignore GERRIT_CHANGE_ID
---ignore LINE_SPACING
--ignore LOGICAL_CONTINUATIONS
--ignore MACRO_WITH_FLOW_CONTROL
--ignore PARENTHESIS_ALIGNMENT
diff --git a/doc/manual/style.txt b/doc/manual/style.txt
index fa08f4de9..e8a375cdd 100644
--- a/doc/manual/style.txt
+++ b/doc/manual/style.txt
@@ -45,7 +45,7 @@ OpenOCD project.
- use TAB characters for indentation; do NOT use spaces.
- displayed TAB width is 4 characters.
- use Unix line endings ('\\n'); do NOT use DOS endings ('\\r\\n')
-- limit adjacent empty lines to at most two (2).
+- do NOT use multiple empty lines.
- remove any trailing empty lines at the end of source files
- do not "comment out" code from the tree nor put it within a block
@code
diff --git a/tools/scripts/checkpatch.pl b/tools/scripts/checkpatch.pl
index 1011b3305..89f0a2178 100755
--- a/tools/scripts/checkpatch.pl
+++ b/tools/scripts/checkpatch.pl
@@ -4040,6 +4040,7 @@ sub process {
}
}
+if (!$OpenOCD) {
# check for missing blank lines after struct/union declarations
# with exceptions for various attributes and macros
if ($prevline =~ /^[\+ ]};?\s*$/ &&
@@ -4059,6 +4060,7 @@ sub process {
fix_insert_line($fixlinenr, "\+");
}
}
+} # !$OpenOCD
# check for multiple consecutive blank lines
if ($prevline =~ /^[\+ ]\s*$/ &&
@@ -4073,6 +4075,7 @@ sub process {
$last_blank_line = $linenr;
}
+if (!$OpenOCD) {
# check for missing blank lines after declarations
# (declarations must have the same indentation and not be at the start of line)
if (($prevline =~ /\+(\s+)\S/) && $sline =~ /^\+$1\S/) {
@@ -4118,6 +4121,7 @@ sub process {
}
}
}
+} # !$OpenOCD
# check for spaces at the beginning of a line.
# Exceptions:
-----------------------------------------------------------------------
Summary of changes:
.checkpatch.conf | 1 -
doc/manual/style.txt | 2 +-
tools/scripts/checkpatch.pl | 4 ++++
3 files changed, 5 insertions(+), 2 deletions(-)
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