openocd-commit — OpenOCD commit maling list - read only

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1139-g68b6d3ad4

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  68b6d3ad477b45a54282571ebd4ed8a53cf7dd90 (commit)
      from  c132aed2a611a16f4759626123ab78e446a737ce (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 68b6d3ad477b45a54282571ebd4ed8a53cf7dd90
Author: Adrien Charruel <ach...@na...>
Date:   Fri Nov 8 15:18:07 2024 +0100

    jtag/driver/angie: Update Angie probe driver
    
    Update jtag driver code to reflect these changes and properly drive
    Angie probe.
    The rationale behind this is to increase the probe performances,
    especially in use cases when large files shall be loaded on a target.
    The USB transfer performances are now close to those obtained with a
    standard FTDI probe.
    
    Change-Id: I3b31d75a3f66c2d07fed8c7423f765acc30925f8
    Signed-off-by: Adrien Charruel <ach...@na...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8711
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/contrib/60-openocd.rules b/contrib/60-openocd.rules
index 6632841a4..2a2fe88e6 100644
--- a/contrib/60-openocd.rules
+++ b/contrib/60-openocd.rules
@@ -252,8 +252,6 @@ ATTRS{idVendor}=="303a", ATTRS{idProduct}=="1002", MODE="660", GROUP="plugdev",
 # ANGIE USB-JTAG Adapter
 ATTRS{idVendor}=="584e", ATTRS{idProduct}=="414f", MODE="660", GROUP="plugdev", TAG+="uaccess"
 ATTRS{idVendor}=="584e", ATTRS{idProduct}=="424e", MODE="660", GROUP="plugdev", TAG+="uaccess"
-ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4255", MODE="660", GROUP="plugdev", TAG+="uaccess"
-ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4355", MODE="660", GROUP="plugdev", TAG+="uaccess"
 ATTRS{idVendor}=="584e", ATTRS{idProduct}=="4a55", MODE="660", GROUP="plugdev", TAG+="uaccess"
 
 # Marvell Sheevaplug
diff --git a/src/jtag/drivers/Makefile.am b/src/jtag/drivers/Makefile.am
index e55e0478c..481840504 100644
--- a/src/jtag/drivers/Makefile.am
+++ b/src/jtag/drivers/Makefile.am
@@ -127,8 +127,6 @@ endif
 if ANGIE
   angiedir = $(pkgdatadir)/angie
   DRIVERFILES     += %D%/angie.c
-  DRIVERFILES     += %D%/angie/include/msgtypes.h
-  EXTRA_DIST      += %D%/angie/README
   dist_angie_DATA  = %D%/angie/angie_firmware.bin
   dist_angie_DATA += %D%/angie/angie_bitstream.bit
   %C%_libocdjtagdrivers_la_LIBADD += -lm
diff --git a/src/jtag/drivers/angie.c b/src/jtag/drivers/angie.c
index 56a118eae..6d8dc2c3b 100644
--- a/src/jtag/drivers/angie.c
+++ b/src/jtag/drivers/angie.c
@@ -1,274 +1,398 @@
 // SPDX-License-Identifier: GPL-2.0-or-later
-/***************************************************************************
-	File : angie.c															*
-	Contents : OpenOCD driver code for NanoXplore USB-JTAG ANGIE			*
-	adapter hardware.														*
-	Based on openULINK driver code by: Martin Schmoelzer.					*
-	Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.				*
-	<abo...@na...>											*
-	<ahm...@gm...>											*
- ***************************************************************************/
+/****************************************************************************
+ * File : angie.c
+ * Contents : Driver code for NanoXplore USB-JTAG ANGIE
+ * adapter hardware.
+ * Based on FT232R driver code by: Serge Vakulenko
+ *
+ * Copyright 2024, Ahmed BOUDJELIDA, NanoXplore SAS.
+ * <abo...@na...>
+ ****************************************************************************/
 
 #ifdef HAVE_CONFIG_H
 #include "config.h"
 #endif
 
-#include <stdio.h>
-#include <stdlib.h>
-#include <math.h>
-#include "helper/system.h"
-#include <helper/types.h>
+#if IS_CYGWIN == 1
+#include "windows.h"
+#undef LOG_ERROR
+#endif
+
+// project specific includes
+#include <jtag/adapter.h>
 #include <jtag/interface.h>
 #include <jtag/commands.h>
+#include <helper/time_support.h>
+#include "libusb_helper.h"
 #include <target/image.h>
 #include <libusb.h>
-#include "libusb_helper.h"
-#include "angie/include/msgtypes.h"
 
-/** USB Vendor ID of ANGIE device in unconfigured state (no firmware loaded
- *  yet) or with its firmware. */
-#define ANGIE_VID				0x584e
+// system includes
+#include <string.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <sys/time.h>
+#include <time.h>
+
+/*
+ * Sync bit bang mode is implemented as described in FTDI Application
+ * Note AN232R-01: "Bit Bang Modes for the ANGIE and FT245R".
+ */
 
-/** USB Product ID of ANGIE device in unconfigured state (no firmware loaded
- *  yet) or with its firmware. */
-#define ANGIE_PID 0x414F
-#define ANGIE_PID_2 0x424e
-#define ANGIE_PID_3 0x4255
-#define ANGIE_PID_4 0x4355
-#define ANGIE_PID_5 0x4a55
+/**
+ * USB endpoints.
+ */
+#define IN_EP	0x84
+#define OUT_EP	0x02
 
-/** Address of EZ-USB ANGIE CPU Control & Status register. This register can be
- *  written by issuing a Control EP0 vendor request. */
-#define CPUCS_REG				0xE600
+/**
+ * Address of EZ-USB ANGIE CPU Control & Status register.
+ * This register can be written by issuing a Control EP0 vendor request.
+ */
+#define CPUCS_REG		0xE600
 
 /** USB Control EP0 bRequest: "Firmware Load". */
 #define REQUEST_FIRMWARE_LOAD	0xA0
 
 /** Value to write into CPUCS to put EZ-USB ANGIE into reset. */
-#define CPU_RESET				0x01
+#define CPU_RESET		0x01
 
 /** Value to write into CPUCS to put EZ-USB ANGIE out of reset. */
-#define CPU_START				0x00
+#define CPU_START		0x00
 
 /** Base address of firmware in EZ-USB ANGIE code space. */
-#define FIRMWARE_ADDR			0x0000
-
-/** USB interface number */
-#define USB_INTERFACE			0
+#define FIRMWARE_ADDR	0x0000
 
 /** Delay (in microseconds) to wait while EZ-USB performs ReNumeration. */
-#define ANGIE_RENUMERATION_DELAY_US	1500000
+#define ANGIE_RENUMERATION_DELAY_US	800000
 
 /** Default location of ANGIE firmware image. */
-#define ANGIE_FIRMWARE_FILE		PKGDATADIR "/angie/angie_firmware.bin"
+#define ANGIE_FIRMWARE_FILE	PKGDATADIR "/angie/angie_firmware.bin"
 
 /** Default location of ANGIE firmware image. */
-#define ANGIE_BITSTREAM_FILE		PKGDATADIR "/angie/angie_bitstream.bit"
+#define ANGIE_BITSTREAM_FILE	PKGDATADIR "/angie/angie_bitstream.bit"
+
+/**
+ * Maximum size of a single firmware section.
+ * Entire EZ-USB ANGIE code space = 16kB
+ */
+#define ANGIE_FW_SECTION_SIZE	16384
+
+/** Vendor Requests */
+#define VR_CFGOPEN				0xB0
+#define VR_DATAOUTOPEN			0xB2
+
+#define ANGIE_VID			    0x584E /* NX Vendor id */
+#define ANGIE_NPROG_PID			0x424E /* ANGIE non programmed */
+#define ANGIE_PROG_OOCD_PID		0x414F /* ANGIE programmed OpenOCD */
+#define ANGIE_PROG_NXB2_PID		0x4a55 /* ANGIE programmed Nxbase2 */
+
+#define TCK_GPIO		0
+#define TDI_GPIO		1
+#define TDO_GPIO		2
+#define TMS_GPIO		3
+#define NTRST_GPIO		4
+#define NSYSRST_GPIO	6
 
-/** Maximum size of a single firmware section. Entire EZ-USB ANGIE code space = 16kB */
-#define SECTION_BUFFERSIZE		16384
+#define ANGIE_XFER_BUFFER_TOTAL_SIZE (16 * 1024)
+#define ANGIE_USB_BULK_SIZE 512
 
-/** Tuning of OpenOCD SCAN commands split into multiple ANGIE commands. */
-#define SPLIT_SCAN_THRESHOLD	10
+/** USB timeout delay in milliseconds */
+#define ANGIE_USB_TIMEOUT_MS	1000
 
-/** ANGIE hardware type */
-enum angie_type {
-	ANGIE,
+/**
+ * List of elements used in a multiple commands reply.
+ */
+struct read_queue {
+	struct list_head list;
 };
 
-enum angie_payload_direction {
-	PAYLOAD_DIRECTION_OUT,
-	PAYLOAD_DIRECTION_IN
+/**
+ * Entry element used to forge a reply buffer for openocd JTAG core.
+ */
+struct read_queue_entry {
+	const struct scan_command *cmd;
+	int reply_buffer_offset;
+	uint8_t *buffer;
+	struct list_head list;
 };
 
-enum angie_delay_type {
-	DELAY_CLOCK_TCK,
-	DELAY_CLOCK_TMS,
-	DELAY_SCAN_IN,
-	DELAY_SCAN_OUT,
-	DELAY_SCAN_IO
+/**
+ * Angie device main context
+ */
+struct angie {
+	struct libusb_device_handle *usbdev;
+	uint8_t xfer_buffer[ANGIE_XFER_BUFFER_TOTAL_SIZE];
+	size_t xfer_buffer_len;
+	uint8_t reply_buffer[ANGIE_XFER_BUFFER_TOTAL_SIZE];
+	size_t  reply_buffer_len;
+	struct read_queue read_queue;
 };
 
 /**
- * ANGIE command (ANGIE command queue element).
+ * Angie device singleton
+ */
+struct angie *angie_handle;
+
+/**
+ * Init read queue list
  *
- * For the OUT direction payload, things are quite easy: Payload is stored
- * in a rather small array (up to 63 bytes), the payload is always allocated
- * by the function generating the command and freed by angie_clear_queue().
+ * @param queue: pointer on the read queue head
+ */
+static void angie_read_queue_init(struct read_queue *queue)
+{
+	INIT_LIST_HEAD(&queue->list);
+}
+
+
+/**
+ * Add a single entry to the read queue
  *
- * For the IN direction payload, things get a little bit more complicated:
- * The maximum IN payload size for a single command is 64 bytes. Assume that
- * a single OpenOCD command needs to scan 256 bytes. This results in the
- * generation of four ANGIE commands. The function generating these
- * commands shall allocate an uint8_t[256] array. Each command's #payload_in
- * pointer shall point to the corresponding offset where IN data shall be
- * placed, while #payload_in_start shall point to the first element of the 256
- * byte array.
- * - first command:  #payload_in_start + 0
- * - second command: #payload_in_start + 64
- * - third command:  #payload_in_start + 128
- * - fourth command: #payload_in_start + 192
+ * @param queue: read queue list
+ * @param entry to append
+ */
+static void angie_read_queue_add(struct read_queue *queue,
+								 struct read_queue_entry *entry)
+{
+	list_add_tail(&entry->list, &queue->list);
+}
+
+/**
+ * Execute elements enqueued in the read queue list
  *
- * The last command sets #needs_postprocessing to true.
+ * @param queue: read queue list
+ * @param device: pointer on the angie device
  */
-struct angie_cmd {
-	uint8_t id;			/**< ANGIE command ID */
+static void angie_read_queue_execute(struct read_queue *queue,
+									 struct angie *device)
+{
+	struct read_queue_entry *entry;
+	struct read_queue_entry *tmp;
+
+	list_for_each_entry_safe(entry, tmp, &queue->list, list) {
+		int scan_size = jtag_scan_size(entry->cmd);
+
+		// iterate over each bit in scan data
+		for (int bit_cnt = 0; bit_cnt < scan_size; bit_cnt++) {
+			// calculate byte index
+			int bytec = bit_cnt / 8;
+			// calculate bit mask: isolate the specific bit in corresponding byte
+			int bcval = 1 << (bit_cnt % 8);
+			// extract tdo value using index: "bit0_index + bit_cnt*2 + 1"
+			int val = device->reply_buffer[entry->reply_buffer_offset + bit_cnt * 2 + 1];
+			if (val & (1 << TDO_GPIO))
+				entry->buffer[bytec] |= bcval;
+			else
+				entry->buffer[bytec] &= ~bcval;
+		}
+
+		jtag_read_buffer(entry->buffer, entry->cmd);
 
-	uint8_t *payload_out;		/**< Pointer where OUT payload shall be stored */
-	uint8_t payload_out_size;	/**< OUT direction payload size for this command */
+		list_del(&entry->list);
+		free(entry->buffer);
+		free(entry);
+	}
+}
 
-	uint8_t *payload_in_start;	/**< Pointer to first element of IN payload array */
-	uint8_t *payload_in;		/**< Pointer where IN payload shall be stored */
-	uint8_t payload_in_size;	/**< IN direction payload size for this command */
+/**
+ * Clear the read queue list
+ *
+ * @param queue: read queue list
+ */
+static void angie_read_queue_clean(struct read_queue *queue)
+{
+	struct read_queue_entry *entry;
+	struct read_queue_entry *tmp;
 
-	/** Indicates if this command needs post-processing */
-	bool needs_postprocessing;
+	list_for_each_entry_safe(entry, tmp, &queue->list, list) {
+		list_del(&entry->list);
+		free(entry->buffer);
+		free(entry);
+	}
+}
 
-	/** Indicates if angie_clear_queue() should free payload_in_start  */
-	bool free_payload_in_start;
+/**
+ * Flush a chunk of Angie's buffer
+ *
+ * USB write is done by configuring GPIF register on the target and calling
+ * a USB bulk transfer.
+ * Sequentially a USB read transferred is issued of the same size.
+ * All the operation are synchronous.
+ * Then the read queue list is executed once the read buffer has been retrieved.
+ *
+ * @param device: Angie device pointer
+ * @param xfer_size: amount of bytes to transfer
+ * @param offset: total bytes already sent during this transfer, this will
+ *                offset the receive buffer accordingly
+ * @param bytes_sent: will contain the amount of bytes sent
+ * @return ERROR_OK on success, negative error code otherwise
+ */
+static int angie_buffer_flush_chunk(struct angie *device,
+									int xfer_size,
+									int offset,
+									int *bytes_sent)
+{
+	uint8_t gpifcnt[4];
+	int sent_chunk_size = 0, bytes_received = 0;
 
-	/** Pointer to corresponding OpenOCD command for post-processing */
-	struct jtag_command *cmd_origin;
+	if (bytes_sent)
+		*bytes_sent = 0;
 
-	struct angie_cmd *next;		/**< Pointer to next command (linked list) */
-};
+	h_u32_to_be(gpifcnt, xfer_size);
 
-/** Describes one driver instance */
-struct angie {
-	struct libusb_context *libusb_ctx;
-	struct libusb_device_handle *usb_device_handle;
-	enum angie_type type;
-
-	unsigned int ep_in;		/**< IN endpoint number */
-	unsigned int ep_out;		/**< OUT endpoint number */
-
-	/* delay value for "SLOW_CLOCK commands" in [0:255] range in units of 4 us;
-		-1 means no need for delay */
-	int delay_scan_in;	/**< Delay value for SCAN_IN commands */
-	int delay_scan_out;	/**< Delay value for SCAN_OUT commands */
-	int delay_scan_io;	/**< Delay value for SCAN_IO commands */
-	int delay_clock_tck;	/**< Delay value for CLOCK_TMS commands */
-	int delay_clock_tms;	/**< Delay value for CLOCK_TCK commands */
-
-	int commands_in_queue;		/**< Number of commands in queue */
-	struct angie_cmd *queue_start;	/**< Pointer to first command in queue */
-	struct angie_cmd *queue_end;	/**< Pointer to last command in queue */
-};
+	int ret = jtag_libusb_control_transfer(device->usbdev,
+		LIBUSB_ENDPOINT_OUT | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE,
+		VR_DATAOUTOPEN, 0, 0, (char *)gpifcnt, sizeof(gpifcnt),
+		ANGIE_USB_TIMEOUT_MS, NULL);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("Failed to send GPIF count to target");
+		return ret;
+	}
 
-/**************************** Function Prototypes *****************************/
-
-/* USB helper functions */
-static int angie_usb_open(struct angie *device);
-static int angie_usb_close(struct angie *device);
-
-/* ANGIE MCU (Cypress EZ-USB) specific functions */
-static int angie_cpu_reset(struct angie *device, char reset_bit);
-static int angie_load_firmware_and_renumerate(struct angie *device, const char *filename,
-		uint32_t delay_us);
-static int angie_load_firmware(struct angie *device, const char *filename);
-static int angie_load_bitstream(struct angie *device, const char *filename);
-static int angie_i2c_write(struct angie *device, uint8_t *i2c_data, uint8_t i2c_data_size);
-static int angie_io_extender_config(struct angie *device, uint8_t i2c_adr, uint8_t cfg_value);
-static int angie_write_firmware_section(struct angie *device,
-		struct image *firmware_image, int section_index);
-
-/* Generic helper functions */
-static void angie_dump_signal_states(uint8_t input_signals, uint8_t output_signals);
-
-/* ANGIE command generation helper functions */
-static int angie_allocate_payload(struct angie_cmd *angie_cmd, int size,
-		enum angie_payload_direction direction);
-
-/* ANGIE command queue helper functions */
-static int angie_get_queue_size(struct angie *device,
-		enum angie_payload_direction direction);
-static void angie_clear_queue(struct angie *device);
-static int angie_append_queue(struct angie *device, struct angie_cmd *angie_cmd);
-static int angie_execute_queued_commands(struct angie *device, int timeout_ms);
-
-static void angie_dump_queue(struct angie *device);
-
-static int angie_append_scan_cmd(struct angie *device,
-		enum scan_type scan_type,
-		int scan_size_bits,
-		uint8_t *tdi,
-		uint8_t *tdo_start,
-		uint8_t *tdo,
-		uint8_t tms_count_start,
-		uint8_t tms_sequence_start,
-		uint8_t tms_count_end,
-		uint8_t tms_sequence_end,
-		struct jtag_command *origin,
-		bool postprocess);
-static int angie_append_clock_tms_cmd(struct angie *device, uint8_t count,
-		uint8_t sequence);
-static int angie_append_clock_tck_cmd(struct angie *device, uint16_t count);
-static int angie_append_get_signals_cmd(struct angie *device);
-static int angie_append_set_signals_cmd(struct angie *device, uint8_t low,
-		uint8_t high);
-static int angie_append_sleep_cmd(struct angie *device, uint32_t us);
-static int angie_append_configure_tck_cmd(struct angie *device,
-		int delay_scan_in,
-		int delay_scan_out,
-		int delay_scan_io,
-		int delay_tck,
-		int delay_tms);
-static int angie_append_test_cmd(struct angie *device);
-
-/* ANGIE TCK frequency helper functions */
-static int angie_calculate_delay(enum angie_delay_type type, long f, int *delay);
-
-/* Interface between ANGIE and OpenOCD */
-static void angie_set_end_state(enum tap_state endstate);
-static int angie_queue_statemove(struct angie *device);
-
-static int angie_queue_scan(struct angie *device, struct jtag_command *cmd);
-static int angie_queue_tlr_reset(struct angie *device, struct jtag_command *cmd);
-static int angie_queue_runtest(struct angie *device, struct jtag_command *cmd);
-static int angie_queue_pathmove(struct angie *device, struct jtag_command *cmd);
-static int angie_queue_sleep(struct angie *device, struct jtag_command *cmd);
-static int angie_queue_stableclocks(struct angie *device, struct jtag_command *cmd);
-
-static int angie_post_process_scan(struct angie_cmd *angie_cmd);
-static int angie_post_process_queue(struct angie *device);
-
-/* adapter driver functions */
-static int angie_execute_queue(struct jtag_command *cmd_queue);
-static int angie_khz(int khz, int *jtag_speed);
-static int angie_speed(int speed);
-static int angie_speed_div(int speed, int *khz);
-static int angie_init(void);
-static int angie_quit(void);
-static int angie_reset(int trst, int srst);
-
-/****************************** Global Variables ******************************/
-
-static struct angie *angie_handle;
-
-/**************************** USB helper functions ****************************/
+	ret = jtag_libusb_bulk_write(device->usbdev, OUT_EP,
+							(char *)device->xfer_buffer + offset,
+							xfer_size, ANGIE_USB_TIMEOUT_MS, &sent_chunk_size);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("USB bulk transfer failed");
+		return ret;
+	}
+
+	ret = jtag_libusb_bulk_read(device->usbdev, IN_EP,
+						(char *)device->reply_buffer + offset,
+						sent_chunk_size, ANGIE_USB_TIMEOUT_MS, &bytes_received);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("Failed to read USB reply");
+		return ret;
+	}
+
+	if (sent_chunk_size == xfer_size && bytes_received == xfer_size) {
+		device->reply_buffer_len += xfer_size;
+		device->xfer_buffer_len -= xfer_size;
+		if (bytes_sent)
+			*bytes_sent += sent_chunk_size;
+	} else {
+		return ERROR_FAIL;
+	}
+
+	return ERROR_OK;
+}
 
 /**
- * Opens the ANGIE device
+ * Flush Angie transfer buffer
  *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
+ * Flush is done by chunks of 512 bytes to match hardware internal FIFOs.
+ * Then the read queue list is executed once the read buffer has been retrieved.
+ *
+ * @param device: Angie device pointer
+ * @return ERROR_OK on success, negative error code otherwise
  */
-static int angie_usb_open(struct angie *device)
+static int angie_buffer_flush(struct angie *device)
+{
+	if (device->xfer_buffer_len == 0)
+		return ERROR_OK;
+
+	int total_bytes_sent = 0;
+	device->reply_buffer_len = 0;
+
+	do {
+		int sent_chunk_size;
+		size_t xfer_size = MIN(device->xfer_buffer_len, ANGIE_USB_BULK_SIZE);
+		int ret = angie_buffer_flush_chunk(device, xfer_size,
+				total_bytes_sent, &sent_chunk_size);
+		if (ret != ERROR_OK)
+			return ret;
+		total_bytes_sent += sent_chunk_size;
+	} while (device->xfer_buffer_len > 0);
+
+	angie_read_queue_execute(&device->read_queue, device);
+
+	return ERROR_OK;
+}
+
+/**
+ * Check if transfer buffer has enough remaining space for a given size.
+ * If the buffer is not large enough, flush it.
+ *
+ * @param device: Angie device pointer
+ * @param size to check
+ * @return ERROR_OK on success, negative error code otherwise
+ */
+static int angie_buffer_flush_check(struct angie *device, size_t size)
+{
+	if (device->xfer_buffer_len + size >= ANGIE_XFER_BUFFER_TOTAL_SIZE)
+		return angie_buffer_flush(device);
+	return ERROR_OK;
+}
+
+/**
+ * Append a single byte value to the transfer buffer
+ *
+ * @param device: Angie device pointer
+ * @param value to append
+ * @return ERROR_OK on success, negative error code otherwise
+ */
+static int angie_buffer_append_simple(struct angie *device, uint8_t value)
 {
-	struct libusb_device_handle *usb_device_handle;
-	const uint16_t vids[] = {ANGIE_VID, ANGIE_VID, ANGIE_VID, ANGIE_VID, ANGIE_VID, 0};
-	const uint16_t pids[] = {ANGIE_PID, ANGIE_PID_2, ANGIE_PID_3, ANGIE_PID_4, ANGIE_PID_5, 0};
+	if (device->xfer_buffer_len >= ANGIE_XFER_BUFFER_TOTAL_SIZE) {
+		int ret = angie_buffer_flush(device);
+		if (ret != ERROR_OK)
+			return ret;
+	}
+	device->xfer_buffer[device->xfer_buffer_len++] = value;
+	return ERROR_OK;
+}
 
-	int ret = jtag_libusb_open(vids, pids, NULL, &usb_device_handle, NULL);
+/**
+ * Append a bit-bang JTAG value to the transfer buffer.
+ *
+ * @param device: Angie device pointer
+ * @param tck value
+ * @param tms value
+ * @param tdi value
+ * @return ERROR_OK on success, negative error code otherwise
+ */
+static int angie_buffer_append(struct angie *device, int tck, int tms, int tdi)
+{
+	uint8_t val = (1 << NTRST_GPIO) | (1 << NSYSRST_GPIO);
+	if (tck)
+		val |= (1 << TCK_GPIO);
+	if (tms)
+		val |= (1 << TMS_GPIO);
+	if (tdi)
+		val |= (1 << TDI_GPIO);
+
+	return angie_buffer_append_simple(device, val);
+}
 
+/**
+ * Open Angie USB interface
+ *
+ * @param device: Angie device pointer
+ * @return ERROR_OK on success, negative error code otherwise
+ */
+static int angie_usb_open(struct angie *device)
+{
+	uint16_t avids[] = {
+		ANGIE_VID,
+		ANGIE_VID,
+		ANGIE_VID,
+		0,
+	};
+	uint16_t apids[] = {
+		ANGIE_NPROG_PID,
+		ANGIE_PROG_OOCD_PID,
+		ANGIE_PROG_NXB2_PID,
+		0,
+	};
+	struct libusb_device_handle *usb_dev;
+
+	int ret = jtag_libusb_open(avids, apids, NULL, &usb_dev, NULL);
 	if (ret != ERROR_OK) {
-		LOG_ERROR("Could not find and open ANGIE");
+		LOG_ERROR("Failed to open ANGIE USB interface");
 		return ret;
 	}
 
-	device->usb_device_handle = usb_device_handle;
-	device->type = ANGIE;
+	device->usbdev = usb_dev;
 
 	return ERROR_OK;
 }
@@ -276,80 +400,84 @@ static int angie_usb_open(struct angie *device)
 /**
  * Releases the ANGIE interface and closes the USB device handle.
  *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
+ * @param device: Angie device pointer
+ * @return ERROR_OK on success, negative error code otherwise
  */
 static int angie_usb_close(struct angie *device)
 {
-	if (device->usb_device_handle) {
-		if (libusb_release_interface(device->usb_device_handle, 0) != 0) {
+	int ret = ERROR_OK;
+
+	if (device->usbdev) {
+		if (libusb_release_interface(device->usbdev, 0) != LIBUSB_SUCCESS) {
 			LOG_ERROR("Could not release interface 0");
-			return ERROR_FAIL;
+			ret = ERROR_FAIL;
 		}
 
-		jtag_libusb_close(device->usb_device_handle);
-		device->usb_device_handle = NULL;
+		jtag_libusb_close(device->usbdev);
+		device->usbdev = NULL;
 	}
-	return ERROR_OK;
-}
 
-/******************* ANGIE CPU (EZ-USB) specific functions ********************/
+	return ret;
+}
 
 /**
  * Writes '0' or '1' to the CPUCS register, putting the EZ-USB CPU into reset
  * or out of reset.
  *
- * @param device pointer to struct angie identifying ANGIE driver instance.
+ * @param device: Angie device pointer
  * @param reset_bit 0 to put CPU into reset, 1 to put CPU out of reset.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
+ * @return ERROR_OK on success, negative error code otherwise
  */
 static int angie_cpu_reset(struct angie *device, char reset_bit)
 {
-	return jtag_libusb_control_transfer(device->usb_device_handle,
-			(LIBUSB_ENDPOINT_OUT | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE),
-			REQUEST_FIRMWARE_LOAD, CPUCS_REG, 0, &reset_bit, 1, LIBUSB_TIMEOUT_MS, NULL);
+	return jtag_libusb_control_transfer(device->usbdev,
+		LIBUSB_ENDPOINT_OUT | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE,
+		REQUEST_FIRMWARE_LOAD, CPUCS_REG, 0, &reset_bit, 1,
+		ANGIE_USB_TIMEOUT_MS, NULL);
 }
 
 /**
- * Puts the ANGIE's EZ-USB microcontroller into reset state, downloads
- * the firmware image, resumes the microcontroller and re-enumerates
- * USB devices.
+ * Send one contiguous firmware section to the ANGIE's EZ-USB microcontroller
+ * over the USB bus.
  *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- *  The usb_handle member will be modified during re-enumeration.
- * @param filename path to the Intel HEX file containing the firmware image.
- * @param delay_us the delay to wait for the device to re-enumerate.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
+ * @param device: Angie device pointer
+ * @param address: address of the firmware section
+ * @param data: pointer to the data to be sent
+ * @param size: size of the data
+ * @return ERROR_OK on success, negative error code otherwise
  */
-static int angie_load_firmware_and_renumerate(struct angie *device,
-	const char *filename, uint32_t delay_us)
+static int angie_write_firmware_section(struct angie *device, uint16_t address,
+										uint8_t *data, size_t size)
 {
-	int ret;
+	int bytes_remaining = size;
 
-	/* Basic process: After downloading the firmware, the ANGIE will disconnect
-	 * itself and re-connect after a short amount of time so we have to close
-	 * the handle and re-enumerate USB devices */
+	// Send section data in chunks of up to 64 bytes to ANGIE
+	while (bytes_remaining > 0) {
+		int chunk_size;
+		int transferred;
 
-	ret = angie_load_firmware(device, filename);
-	if (ret != ERROR_OK)
-		return ret;
+		if (bytes_remaining > 64)
+			chunk_size = 64;
+		else
+			chunk_size = bytes_remaining;
 
-	ret = angie_usb_close(device);
-	if (ret != ERROR_OK)
-		return ret;
+		int ret = jtag_libusb_control_transfer(device->usbdev,
+			LIBUSB_ENDPOINT_OUT | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE,
+			REQUEST_FIRMWARE_LOAD, address, FIRMWARE_ADDR, (char *)data,
+			chunk_size, ANGIE_USB_TIMEOUT_MS, &transferred);
 
-	usleep(delay_us);
+		if (ret != ERROR_OK)
+			return ret;
 
-	ret = angie_usb_open(device);
-	if (ret != ERROR_OK)
-		return ret;
+		if (transferred != chunk_size) {
+			// Abort if libusb sent less data than requested
+			return ERROR_FAIL;
+		}
 
-	ret = libusb_claim_interface(angie_handle->usb_device_handle, 0);
-	if (ret != LIBUSB_SUCCESS)
-		return ERROR_FAIL;
+		bytes_remaining -= chunk_size;
+		address += chunk_size;
+		data += chunk_size;
+	}
 
 	return ERROR_OK;
 }
@@ -358,18 +486,16 @@ static int angie_load_firmware_and_renumerate(struct angie *device,
  * Downloads a firmware image to the ANGIE's EZ-USB microcontroller
  * over the USB bus.
  *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @param filename an absolute or relative path to the Intel HEX file
+ * @param device: Angie device pointer
+ * @param filename: an absolute or relative path to the Intel HEX file
  *  containing the firmware image.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
+ * @return ERROR_OK on success, negative error code otherwise
  */
 static int angie_load_firmware(struct angie *device, const char *filename)
 {
 	struct image angie_firmware_image;
-	int ret;
 
-	ret = angie_cpu_reset(device, CPU_RESET);
+	int ret = angie_cpu_reset(device, CPU_RESET);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Could not halt ANGIE CPU");
 		return ret;
@@ -384,12 +510,34 @@ static int angie_load_firmware(struct angie *device, const char *filename)
 		return ret;
 	}
 
-	/* Download all sections in the image to ANGIE */
+	uint8_t *data = malloc(ANGIE_FW_SECTION_SIZE);
+	if (!data) {
+		LOG_ERROR("Out of memory");
+		return ERROR_FAIL;
+	}
+
+	// Download all sections in the image to ANGIE
 	for (unsigned int i = 0; i < angie_firmware_image.num_sections; i++) {
-		ret = angie_write_firmware_section(device, &angie_firmware_image, i);
+		size_t size_read;
+		uint32_t size = angie_firmware_image.sections[i].size;
+		int addr = angie_firmware_image.sections[i].base_address;
+
+		LOG_DEBUG("section %02i at addr 0x%04x (size 0x%04" PRIx32 ")",
+			i, addr, size);
+
+		ret = image_read_section(&angie_firmware_image, i, 0,
+						size, data, &size_read);
+		if (ret != ERROR_OK)
+			goto exit;
+		if (size_read != size) {
+			ret = ERROR_FAIL;
+			goto exit;
+		}
+
+		ret = angie_write_firmware_section(device, addr, data, size);
 		if (ret != ERROR_OK) {
 			LOG_ERROR("Could not write firmware section");
-			return ret;
+			goto exit;
 		}
 	}
 
@@ -398,9 +546,52 @@ static int angie_load_firmware(struct angie *device, const char *filename)
 	ret = angie_cpu_reset(device, CPU_START);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Could not restart ANGIE CPU");
-		return ret;
+		goto exit;
 	}
 
+exit:
+	free(data);
+	return ret;
+}
+
+/**
+ * Puts the ANGIE's EZ-USB microcontroller into reset state, downloads
+ * the firmware image, resumes the microcontroller and re-enumerates
+ * USB devices.
+ *
+ * @param device: Angie device pointer
+ *  The usb_handle member will be modified during re-enumeration.
+ * @param filename: path to the Intel HEX file containing the firmware image.
+ * @param delay_us: the delay to wait for the device to re-enumerate.
+ * @return ERROR_OK on success, negative error code otherwise
+ */
+static int angie_load_firmware_and_renumerate(struct angie *device,
+											  const char *filename,
+											  uint32_t delay_us)
+{
+	/*
+	 * Basic process: After downloading the firmware, the ANGIE will disconnect
+	 * itself and re-connect after a short amount of time so we have to close
+	 * the handle and re-enumerate USB devices.
+	 */
+
+	int ret = angie_load_firmware(device, filename);
+	if (ret != ERROR_OK)
+		return ret;
+
+	ret = angie_usb_close(device);
+	if (ret != ERROR_OK)
+		return ret;
+
+	usleep(delay_us);
+
+	ret = angie_usb_open(device);
+	if (ret != ERROR_OK)
+		return ret;
+
+	if (libusb_claim_interface(angie_handle->usbdev, 0) != LIBUSB_SUCCESS)
+		return ERROR_FAIL;
+
 	return ERROR_OK;
 }
 
@@ -408,1982 +599,766 @@ static int angie_load_firmware(struct angie *device, const char *filename)
  * Downloads a bitstream file to the ANGIE's FPGA through the EZ-USB microcontroller
  * over the USB bus.
  *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @param filename an absolute or relative path to the Xilinx .bit file
+ * @param device: Angie device pointer
+ * @param filename: an absolute or relative path to the Xilinx .bit file
  *  containing the bitstream data.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
+ * @return ERROR_OK on success, negative error code otherwise
  */
 static int angie_load_bitstream(struct angie *device, const char *filename)
 {
-	int ret, transferred;
+	int ret = ERROR_OK, transferred;
 	const char *bitstream_file_path = filename;
 	FILE *bitstream_file = NULL;
 	char *bitstream_data = NULL;
-	size_t bitstream_size = 0;
 	uint8_t gpifcnt[4];
 
-	/* Open the bitstream file */
+	// Open the bitstream file
 	bitstream_file = fopen(bitstream_file_path, "rb");
 	if (!bitstream_file) {
 		LOG_ERROR("Failed to open bitstream file: %s\n", bitstream_file_path);
-		return ERROR_FAIL;
+		ret = ERROR_FAIL;
+		goto exit;
 	}
 
-	/* Get the size of the bitstream file */
+	// Get the size of the bitstream file
 	fseek(bitstream_file, 0, SEEK_END);
-	bitstream_size = ftell(bitstream_file);
+	size_t bitstream_size = ftell(bitstream_file);
 	fseek(bitstream_file, 0, SEEK_SET);
 
-	/* Allocate memory for the bitstream data */
+	// Allocate memory for the bitstream data
 	bitstream_data = malloc(bitstream_size);
 	if (!bitstream_data) {
 		LOG_ERROR("Failed to allocate memory for bitstream data.");
-		fclose(bitstream_file);
-		return ERROR_FAIL;
+		ret = ERROR_FAIL;
+		goto exit;
 	}
 
-	/* Read the bitstream data from the file */
+	// Read the bitstream data from the file
 	if (fread(bitstream_data, 1, bitstream_size, bitstream_file) != bitstream_size) {
 		LOG_ERROR("Failed to read bitstream data.");
-		free(bitstream_data);
-		fclose(bitstream_file);
-		return ERROR_FAIL;
+		ret = ERROR_FAIL;
+		goto exit;
 	}
 
+	// CFG Open
 	h_u32_to_be(gpifcnt, bitstream_size);
-
-	/* CFGopen */
-	ret = jtag_libusb_control_transfer(device->usb_device_handle,
-		0x00, 0xB0, 0, 0, (char *)gpifcnt, 4, LIBUSB_TIMEOUT_MS, &transferred);
+	ret = jtag_libusb_control_transfer(device->usbdev,
+		LIBUSB_ENDPOINT_OUT | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE,
+		VR_CFGOPEN, 0, 0, (char *)gpifcnt, sizeof(gpifcnt),
+		ANGIE_USB_TIMEOUT_MS, &transferred);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed opencfg");
-		/* Abort if libusb sent less data than requested */
-		return ERROR_FAIL;
+		goto exit;
 	}
 
-	/* Send the bitstream data to the microcontroller */
+	// Send the bitstream data to the microcontroller
 	int actual_length = 0;
-	ret = jtag_libusb_bulk_write(device->usb_device_handle, 0x02, bitstream_data, bitstream_size, 1000, &actual_length);
+	ret = jtag_libusb_bulk_write(device->usbdev, OUT_EP, bitstream_data,
+			bitstream_size, ANGIE_USB_TIMEOUT_MS, &actual_length);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to send bitstream data: %s", libusb_strerror(ret));
-		free(bitstream_data);
-		fclose(bitstream_file);
-		return ERROR_FAIL;
+		goto exit;
 	}
 
 	LOG_INFO("Bitstream sent successfully.");
 
-	/* Clean up */
+exit:
 	free(bitstream_data);
-	fclose(bitstream_file);
+	if (bitstream_file)
+		fclose(bitstream_file);
 
-	/* CFGclose */
-	transferred = 0;
-	ret = jtag_libusb_control_transfer(device->usb_device_handle,
-		0x00, 0xB1, 0, 0, NULL, 0, LIBUSB_TIMEOUT_MS, &transferred);
-	if (ret != ERROR_OK) {
-		LOG_ERROR("Failed cfgclose");
-		/* Abort if libusb sent less data than requested */
-		return ERROR_FAIL;
-	}
-	return ERROR_OK;
+	return ret;
 }
 
 /**
- * Send an i2c write operation to dev-board components.
+ * Check if Angie firmware must be updated
  *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @param i2c_data table of i2c data that we want to write to slave device.
- * @param i2c_data_size the size of i2c data table.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
+ * @param device: Angie device pointer
+ * @return true if update is needed, false otherwise
  */
-static int angie_i2c_write(struct angie *device, uint8_t *i2c_data, uint8_t i2c_data_size)
+static bool angie_is_firmware_needed(struct angie *device)
 {
-	char i2c_data_buffer[i2c_data_size + 2];
-	char buffer_received[1];
-	int ret, transferred;
-	i2c_data_buffer[0] = 0; // write = 0
-	i2c_data_buffer[1] = i2c_data_size - 1; // i2c_data count (without address)
-
-	for (uint8_t i = 0; i < i2c_data_size; i++)
-		i2c_data_buffer[i + 2] = i2c_data[i];
-
-	// Send i2c packet to Dev-board and configure its clock source /
-	ret = jtag_libusb_bulk_write(device->usb_device_handle, 0x06, i2c_data_buffer,
-								 i2c_data_size + 2, 1000, &transferred);
-	if (ret != ERROR_OK) {
-		LOG_ERROR("Error in i2c clock gen configuration : ret ERROR");
-		return ret;
-	}
-	if (transferred != i2c_data_size + 2) {
-		LOG_ERROR("Error in i2c clock gen configuration : bytes transferred");
-		return ERROR_FAIL;
-	}
+	struct libusb_device_descriptor desc;
 
-	usleep(500);
+	// Get String Descriptor to determine if firmware needs to be loaded
+	int ret = libusb_get_device_descriptor(libusb_get_device(angie_handle->usbdev),
+										&desc);
+	if (ret != LIBUSB_SUCCESS)
+		// Could not get descriptor -> Unconfigured or original Keil firmware
+		return true;
+	else if (desc.idProduct != ANGIE_PROG_OOCD_PID)
+		return true;
 
-	// Receive packet from ANGIE /
-	ret = jtag_libusb_bulk_write(device->usb_device_handle, 0x88, buffer_received, 1, 1000, &transferred);
-	if (ret != ERROR_OK) {
-		LOG_ERROR("Error in i2c clock gen configuration : ret ERROR");
-		return ret;
+	return false;
+}
+
+/**
+ * Set TAP end state
+ *
+ * @param state
+ */
+static void angie_set_end_state(enum tap_state state)
+{
+	if (tap_is_state_stable(state)) {
+		tap_set_end_state(state);
+	} else {
+		LOG_ERROR("BUG: %i is not a valid end state", state);
+		exit(-1);
 	}
-	return ERROR_OK;
 }
 
 /**
- * Configure dev-board gpio extender modules by configuring their
- * register 3 and register 1 responsible for IO directions and values.
+ * Move TAP to given state
  *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @param i2c_adr i2c address of the gpio extender.
- * @param cfg_value IOs configuration to be written in register Number 3.
- * @param value the IOs value to be written in register Number 1.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
+ * @param device: Angie device pointer
+ * @param skip: number of state to skip during move
+ * @return ERROR_OK on success, negative error code otherwise
  */
-static int angie_io_extender_config(struct angie *device, uint8_t i2c_adr, uint8_t cfg_value)
+static int angie_state_move(struct angie *device, int skip)
 {
-	uint8_t ioconfig[3] = {i2c_adr, 3, cfg_value};
-	int ret = angie_i2c_write(device, ioconfig, 3);
+	int ret;
+	int tms = 0;
+	uint8_t tms_scan = tap_get_tms_path(tap_get_state(), tap_get_end_state());
+	int tms_count = tap_get_tms_path_len(tap_get_state(), tap_get_end_state());
+
+	// tms_scan has 8 bits that we bitbang one by one
+	for (int i = skip; i < tms_count; i++) {
+		tms = (tms_scan >> i) & 1;
+		ret = angie_buffer_append(device, 0, tms, 0);
+		if (ret != ERROR_OK)
+			return ret;
+		ret = angie_buffer_append(device, 1, tms, 0);
+		if (ret != ERROR_OK)
+			return ret;
+	}
+	ret = angie_buffer_append(device, 0, tms, 0);
 	if (ret != ERROR_OK)
 		return ret;
 
-	usleep(500);
-	return ret;
+	tap_set_state(tap_get_end_state());
+
+	return ERROR_OK;
 }
 
 /**
- * Send one contiguous firmware section to the ANGIE's EZ-USB microcontroller
- * over the USB bus.
+ * Return JTAG SCAN command size in bytes
  *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @param firmware_image pointer to the firmware image that contains the section
- *  which should be sent to the ANGIE's EZ-USB microcontroller.
- * @param section_index index of the section within the firmware image.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
+ * @param device: Angie device pointer
+ * @param cmd: SCAN command
+ * @return size of command in the transfer buffer in bytes
  */
-static int angie_write_firmware_section(struct angie *device,
-	struct image *firmware_image, int section_index)
+static int angie_jtag_scan_size(struct angie *device,
+								const struct scan_command *cmd)
 {
-	int addr, bytes_remaining, chunk_size;
-	uint8_t data[SECTION_BUFFERSIZE];
-	uint8_t *data_ptr = data;
-	uint16_t size;
-	size_t size_read;
-	int ret, transferred;
+	int cmd_size = 0;
+	int count = 0;
 
-	size = (uint16_t)firmware_image->sections[section_index].size;
-	addr = (uint16_t)firmware_image->sections[section_index].base_address;
+	// move to TAP_IRSHIFT or TAP_DRSHIFT state
+	if (cmd->ir_scan)
+		count = tap_get_tms_path_len(tap_get_state(), TAP_IRSHIFT);
+	else
+		count = tap_get_tms_path_len(tap_get_state(), TAP_DRSHIFT);
+	cmd_size += count * 2 + 1;
+
+	// add scan size
+	cmd_size += jtag_scan_size(cmd) * 2;
+
+	/*
+	 * move to cmd specified end state
+	 * Also, see below function
+	 * we *KNOW* the above loop transitioned out of
+	 * the shift state, so we skip the first state
+	 * and move directly to the end state.
+	 */
+	if (cmd->ir_scan)
+		count = tap_get_tms_path_len(TAP_IRSHIFT, cmd->end_state) - 1;
+	else
+		count = tap_get_tms_path_len(TAP_DRSHIFT, cmd->end_state) - 1;
+	cmd_size += count * 2 + 1;
 
-	LOG_DEBUG("section %02i at addr 0x%04x (size 0x%04" PRIx16 ")", section_index, addr,
-		size);
+	return cmd_size;
+}
 
-	/* Copy section contents to local buffer */
-	ret = image_read_section(firmware_image, section_index, 0, size, data,
-			&size_read);
+/**
+ * Execute JTAG SCAN command
+ *
+ * @param device: Angie device pointer
+ * @param cmd: SCAN command
+ * @return ERROR_OK on success, negative error code otherwise
+ */
+static int angie_jtag_execute_scan(struct angie *device,
+								   const struct scan_command *cmd)
+{
+	uint8_t *buffer = NULL;
+	LOG_DEBUG_IO("SCAN: size=%d %s scan end in %s", jtag_scan_size(cmd),
+			(cmd->ir_scan) ? "IR" : "DR", tap_state_name(cmd->end_state));
 
+	if (cmd->ir_scan) {
+		if (tap_get_state() != TAP_IRSHIFT)
+			angie_set_end_state(TAP_IRSHIFT);
+	} else {
+		if (tap_get_state() != TAP_DRSHIFT)
+			angie_set_end_state(TAP_DRSHIFT);
+	}
+	int ret = angie_state_move(device, 0);
 	if (ret != ERROR_OK)
 		return ret;
-	if (size_read != size)
-		return ERROR_FAIL;
+	angie_set_end_state(cmd->end_state);
+
+	// Execute scan
+	int scan_size = jtag_build_buffer(cmd, &buffer);
+	enum scan_type type = jtag_scan_type(cmd);
+
+	// starting byte index
+	int start_offset = device->xfer_buffer_len;
+
+	// iterate over each bit in all scan data
+	int tms = 0;
+	int tdi = 0;
+	for (int i = 0; i < scan_size; i++) {
+		// calculate tms
+		// if we finish shifting tdi bits : '1' , else '0'
+		tms = (i == scan_size - 1) ? 1 : 0;
+		// calculate byte index
+		int bytec = i / 8;
+		// calculate bit mask: isolate the specific bit in corresponding byte
+		int bcval = 1 << (i % 8);
+		// if type is not SCAN_IN (not just reading data)
+		// and the bit masked is '1' then tdi = '1'
+		tdi = 0;
+		if (type != SCAN_IN && (buffer[bytec] & bcval))
+			tdi = 1;
+		// write tdi and tms twice in tck=0 and tck=1
+		ret = angie_buffer_append(device, 0, tms, tdi);
+		if (ret != ERROR_OK)
+			return ret;
+		ret = angie_buffer_append(device, 1, tms, tdi);
+		if (ret != ERROR_OK)
+			return ret;
+	}
 
-	bytes_remaining = size;
+	angie_set_end_state(cmd->end_state);
+	if (tap_get_state() != tap_get_end_state()) {
+		/*
+		 * We *KNOW* the above loop transitioned out of
+		 * the shift state, so we skip the first state
+		 * and move directly to the end state.
+		 */
+		ret = angie_state_move(device, 1);
+		if (ret != ERROR_OK)
+			return ret;
+	}
 
-	/* Send section data in chunks of up to 64 bytes to ANGIE */
-	while (bytes_remaining > 0) {
-		if (bytes_remaining > 64)
-			chunk_size = 64;
-		else
-			chunk_size = bytes_remaining;
-
-		ret = jtag_libusb_control_transfer(device->usb_device_handle,
-				(LIBUSB_ENDPOINT_OUT | LIBUSB_REQUEST_TYPE_VENDOR | LIBUSB_RECIPIENT_DEVICE),
-				REQUEST_FIRMWARE_LOAD, addr, FIRMWARE_ADDR, (char *)data_ptr,
-				chunk_size, LIBUSB_TIMEOUT_MS, &transferred);
-
-		if (ret != ERROR_OK)
-			return ret;
-
-		if (transferred != chunk_size) {
-			/* Abort if libusb sent less data than requested */
+	if (jtag_scan_type(cmd) != SCAN_OUT) {
+		// queue read back buffer for further processing
+		struct read_queue_entry *entry = malloc(sizeof(*entry));
+		if (!entry) {
+			LOG_ERROR("Out of memory");
+			free(buffer);
 			return ERROR_FAIL;
 		}
 
-		bytes_remaining -= chunk_size;
-		addr += chunk_size;
-		data_ptr += chunk_size;
-	}
-
-	return ERROR_OK;
-}
-
-/************************** Generic helper functions **************************/
-
-/**
- * Print state of interesting signals via LOG_INFO().
- *
- * @param input_signals input signal states as returned by CMD_GET_SIGNALS
- * @param output_signals output signal states as returned by CMD_GET_SIGNALS
- */
-static void angie_dump_signal_states(uint8_t input_signals, uint8_t output_signals)
-{
-	LOG_INFO("ANGIE signal states: TDI: %i, TDO: %i, TMS: %i, TCK: %i, TRST: %i "
-		"SRST: %i",
-		(output_signals & SIGNAL_TDI   ? 1 : 0),
-		(input_signals  & SIGNAL_TDO   ? 1 : 0),
-		(output_signals & SIGNAL_TMS   ? 1 : 0),
-		(output_signals & SIGNAL_TCK   ? 1 : 0),
-		(output_signals & SIGNAL_TRST  ? 1 : 0),
-		(output_signals & SIGNAL_SRST  ? 1 : 0));
-}
-
-/**************** ANGIE command generation helper functions ***************/
-
-/**
- * Allocate and initialize space in memory for ANGIE command payload.
- *
- * @param angie_cmd pointer to command whose payload should be allocated.
- * @param size the amount of memory to allocate (bytes).
- * @param direction which payload to allocate.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
- */
-static int angie_allocate_payload(struct angie_cmd *angie_cmd, int size,
-	enum angie_payload_direction direction)
-{
-	uint8_t *payload;
-
-	payload = calloc(size, sizeof(uint8_t));
-
-	if (!payload) {
-		LOG_ERROR("Could not allocate ANGIE command payload: out of memory");
-		return ERROR_FAIL;
-	}
-
-	switch (direction) {
-	    case PAYLOAD_DIRECTION_OUT:
-		    if (angie_cmd->payload_out) {
-			    LOG_ERROR("BUG: Duplicate payload allocation for ANGIE command");
-			    free(payload);
-			    return ERROR_FAIL;
-		    }
-			angie_cmd->payload_out = payload;
-			angie_cmd->payload_out_size = size;
-		    break;
-	    case PAYLOAD_DIRECTION_IN:
-		    if (angie_cmd->payload_in_start) {
-			    LOG_ERROR("BUG: Duplicate payload allocation for ANGIE command");
-			    free(payload);
-			    return ERROR_FAIL;
-		    }
-
-			angie_cmd->payload_in_start = payload;
-		    angie_cmd->payload_in = payload;
-		    angie_cmd->payload_in_size = size;
-
-			/* By default, free payload_in_start in angie_clear_queue(). Commands
-			 * that do not want this behavior (e. g. split scans) must turn it off
-			 * separately! */
-		    angie_cmd->free_payload_in_start = true;
-
-		    break;
-	}
-
-	return ERROR_OK;
-}
-
-/****************** ANGIE command queue helper functions ******************/
-
-/**
- * Get the current number of bytes in the queue, including command IDs.
- *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @param direction the transfer direction for which to get byte count.
- * @return the number of bytes currently stored in the queue for the specified
- *  direction.
- */
-static int angie_get_queue_size(struct angie *device,
-	enum angie_payload_direction direction)
-{
-	struct angie_cmd *current = device->queue_start;
-	int sum = 0;
-
-	while (current) {
-		switch (direction) {
-		    case PAYLOAD_DIRECTION_OUT:
-			    sum += current->payload_out_size + 1;	/* + 1 byte for Command ID */
-			    break;
-		    case PAYLOAD_DIRECTION_IN:
-			    sum += current->payload_in_size;
-			    break;
-		}
-
-		current = current->next;
-	}
-
-	return sum;
-}
-
-/**
- * Clear the ANGIE command queue.
- *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- */
-static void angie_clear_queue(struct angie *device)
-{
-	struct angie_cmd *current = device->queue_start;
-	struct angie_cmd *next = NULL;
-
-	while (current) {
-		/* Save pointer to next element */
-		next = current->next;
-
-		/* Free payloads: OUT payload can be freed immediately */
-		free(current->payload_out);
-		current->payload_out = NULL;
-
-		/* IN payload MUST be freed ONLY if no other commands use the
-		 * payload_in_start buffer */
-		if (current->free_payload_in_start) {
-			free(current->payload_in_start);
-			current->payload_in_start = NULL;
-			current->payload_in = NULL;
-		}
-
-		/* Free queue element */
-		free(current);
-
-		/* Proceed with next element */
-		current = next;
-	}
-
-	device->commands_in_queue = 0;
-	device->queue_start = NULL;
-	device->queue_end = NULL;
-}
-
-/**
- * Add a command to the ANGIE command queue.
- *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @param angie_cmd pointer to command that shall be appended to the ANGIE
- *  command queue.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
- */
-static int angie_append_queue(struct angie *device, struct angie_cmd *angie_cmd)
-{
-	int newsize_out, newsize_in;
-	int ret = ERROR_OK;
-
-	newsize_out = angie_get_queue_size(device, PAYLOAD_DIRECTION_OUT) + 1
-		+ angie_cmd->payload_out_size;
-
-	newsize_in = angie_get_queue_size(device, PAYLOAD_DIRECTION_IN)
-		+ angie_cmd->payload_in_size;
-
-	/* Check if the current command can be appended to the queue */
-	if (newsize_out > 64 || newsize_in > 64) {
-		/* New command does not fit. Execute all commands in queue before starting
-		 * new queue with the current command as first entry. */
-		ret = angie_execute_queued_commands(device, LIBUSB_TIMEOUT_MS);
-
-		if (ret == ERROR_OK)
-			ret = angie_post_process_queue(device);
-
-		if (ret == ERROR_OK)
-			angie_clear_queue(device);
-	}
-
-	if (!device->queue_start) {
-		/* Queue was empty */
-		device->commands_in_queue = 1;
-
-		device->queue_start = angie_cmd;
-		device->queue_end = angie_cmd;
-	} else {
-		/* There are already commands in the queue */
-		device->commands_in_queue++;
-
-		device->queue_end->next = angie_cmd;
-		device->queue_end = angie_cmd;
-	}
-
-	if (ret != ERROR_OK)
-		angie_clear_queue(device);
-
-	return ret;
-}
-
-/**
- * Sends all queued ANGIE commands to the ANGIE for execution.
- *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @param timeout_ms
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
- */
-static int angie_execute_queued_commands(struct angie *device, int timeout_ms)
-{
-	struct angie_cmd *current;
-	int ret, i, index_out, index_in, count_out, count_in, transferred;
-	uint8_t buffer[64];
-
-	if (LOG_LEVEL_IS(LOG_LVL_DEBUG_IO))
-		angie_dump_queue(device);
-
-	index_out = 0;
-	count_out = 0;
-	count_in = 0;
-
-	for (current = device->queue_start; current; current = current->next) {
-		/* Add command to packet */
-		buffer[index_out] = current->id;
-		index_out++;
-		count_out++;
-
-		for (i = 0; i < current->payload_out_size; i++)
-			buffer[index_out + i] = current->payload_out[i];
-		index_out += current->payload_out_size;
-		count_in += current->payload_in_size;
-		count_out += current->payload_out_size;
-	}
-
-	/* Send packet to ANGIE */
-	ret = jtag_libusb_bulk_write(device->usb_device_handle, device->ep_out,
-			(char *)buffer, count_out, timeout_ms, &transferred);
-	if (ret != ERROR_OK) {
-		LOG_ERROR("Libusb bulk write queued commands failed.");
-		return ret;
-	}
-	if (transferred != count_out) {
-		LOG_ERROR("Libusb bulk write queued commands failed: transferred byte count");
-		return ERROR_FAIL;
-	}
-
-	/* Wait for response if commands contain IN payload data */
-	if (count_in > 0) {
-		ret = jtag_libusb_bulk_write(device->usb_device_handle, device->ep_in,
-				(char *)buffer, count_in, timeout_ms, &transferred);
-	if (ret != ERROR_OK) {
-		LOG_ERROR("Libusb bulk write input payload data failed");
-		return ret;
-	}
-	if (transferred != count_in) {
-		LOG_ERROR("Libusb bulk write input payload data failed: transferred byte count");
-		return ERROR_FAIL;
-	}
-
-		/* Write back IN payload data */
-		index_in = 0;
-		for (current = device->queue_start; current; current = current->next) {
-			for (i = 0; i < current->payload_in_size; i++) {
-				current->payload_in[i] = buffer[index_in];
-				index_in++;
-			}
-		}
-	}
-	return ERROR_OK;
-}
-
-/**
- * Convert an ANGIE command ID (\a id) to a human-readable string.
- *
- * @param id the ANGIE command ID.
- * @return the corresponding human-readable string.
- */
-static const char *angie_cmd_id_string(uint8_t id)
-{
-	switch (id) {
-	case CMD_SCAN_IN:
-		return "CMD_SCAN_IN";
-	case CMD_SLOW_SCAN_IN:
-		return "CMD_SLOW_SCAN_IN";
-	case CMD_SCAN_OUT:
-		return "CMD_SCAN_OUT";
-	case CMD_SLOW_SCAN_OUT:
-		return "CMD_SLOW_SCAN_OUT";
-	case CMD_SCAN_IO:
-		return "CMD_SCAN_IO";
-	case CMD_SLOW_SCAN_IO:
-		return "CMD_SLOW_SCAN_IO";
-	case CMD_CLOCK_TMS:
-		return "CMD_CLOCK_TMS";
-	case CMD_SLOW_CLOCK_TMS:
-		return "CMD_SLOW_CLOCK_TMS";
-	case CMD_CLOCK_TCK:
-		return "CMD_CLOCK_TCK";
-	case CMD_SLOW_CLOCK_TCK:
-		return "CMD_SLOW_CLOCK_TCK";
-	case CMD_SLEEP_US:
-		return "CMD_SLEEP_US";
-	case CMD_SLEEP_MS:
-		return "CMD_SLEEP_MS";
-	case CMD_GET_SIGNALS:
-		return "CMD_GET_SIGNALS";
-	case CMD_SET_SIGNALS:
-		return "CMD_SET_SIGNALS";
-	case CMD_CONFIGURE_TCK_FREQ:
-		return "CMD_CONFIGURE_TCK_FREQ";
-	case CMD_SET_LEDS:
-		return "CMD_SET_LEDS";
-	case CMD_TEST:
-		return "CMD_TEST";
-	default:
-		return "CMD_UNKNOWN";
-	}
-}
-
-/**
- * Print one ANGIE command to stdout.
- *
- * @param angie_cmd pointer to ANGIE command.
- */
-static void angie_dump_command(struct angie_cmd *angie_cmd)
-{
-	char hex[64 * 3];
-	for (int i = 0; i < angie_cmd->payload_out_size; i++)
-		sprintf(hex + 3 * i, "%02" PRIX8 " ", angie_cmd->payload_out[i]);
-
-	hex[3 * angie_cmd->payload_out_size - 1] = 0;
-	LOG_DEBUG_IO(" %-22s | OUT size = %" PRIi8 ", bytes = %s",
-					angie_cmd_id_string(angie_cmd->id), angie_cmd->payload_out_size, hex);
-
-	LOG_DEBUG_IO("\n                         | IN size  =  %" PRIi8 "\n", angie_cmd->payload_in_size);
-}
-
-/**
- * Print the ANGIE command queue to stdout.
- *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- */
-static void angie_dump_queue(struct angie *device)
-{
-	struct angie_cmd *current;
-
-	LOG_DEBUG_IO("ANGIE command queue:\n");
-
-	for (current = device->queue_start; current; current = current->next)
-		angie_dump_command(current);
-}
-
-/**
- * Perform JTAG scan
- *
- * Creates and appends a JTAG scan command to the ANGIE command queue.
- * A JTAG scan consists of three steps:
- * - Move to the desired SHIFT state, depending on scan type (IR/DR scan).
- * - Shift TDI data into the JTAG chain, optionally reading the TDO pin.
- * - Move to the desired end state.
- *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @param scan_type the type of the scan (IN, OUT, IO (bidirectional)).
- * @param scan_size_bits number of bits to shift into the JTAG chain.
- * @param tdi pointer to array containing TDI data.
- * @param tdo_start pointer to first element of array where TDO data shall be
- *  stored. See #angie_cmd for details.
- * @param tdo pointer to array where TDO data shall be stored
- * @param tms_count_start number of TMS state transitions to perform BEFORE
- *  shifting data into the JTAG chain.
- * @param tms_sequence_start sequence of TMS state transitions that will be
- *  performed BEFORE shifting data into the JTAG chain.
- * @param tms_count_end number of TMS state transitions to perform AFTER
- *  shifting data into the JTAG chain.
- * @param tms_sequence_end sequence of TMS state transitions that will be
- *  performed AFTER shifting data into the JTAG chain.
- * @param origin pointer to OpenOCD command that generated this scan command.
- * @param postprocess whether this command needs to be post-processed after
- *  execution.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
- */
-static int angie_append_scan_cmd(struct angie *device, enum scan_type scan_type,
-	int scan_size_bits, uint8_t *tdi, uint8_t *tdo_start, uint8_t *tdo,
-	uint8_t tms_count_start, uint8_t tms_sequence_start, uint8_t tms_count_end,
-	uint8_t tms_sequence_end, struct jtag_command *origin, bool postprocess)
-{
-	struct angie_cmd *cmd = calloc(1, sizeof(struct angie_cmd));
-	int ret, i, scan_size_bytes;
-	uint8_t bits_last_byte;
-
-	if (!cmd)
-		return ERROR_FAIL;
-
-	/* Check size of command. USB buffer can hold 64 bytes, 1 byte is command ID,
-	 * 5 bytes are setup data -> 58 remaining payload bytes for TDI data */
-	if (scan_size_bits > (58 * 8)) {
-		LOG_ERROR("BUG: Tried to create CMD_SCAN_IO ANGIE command with too"
-			" large payload");
-		free(cmd);
-		return ERROR_FAIL;
-	}
-
-	scan_size_bytes = DIV_ROUND_UP(scan_size_bits, 8);
-
-	bits_last_byte = scan_size_bits % 8;
-	if (bits_last_byte == 0)
-		bits_last_byte = 8;
-
-	/* Allocate out_payload depending on scan type */
-	switch (scan_type) {
-	    case SCAN_IN:
-		    if (device->delay_scan_in < 0)
-			    cmd->id = CMD_SCAN_IN;
-		    else
-			    cmd->id = CMD_SLOW_SCAN_IN;
-		    ret = angie_allocate_payload(cmd, 5, PAYLOAD_DIRECTION_IN);
-		    break;
-	    case SCAN_OUT:
-		    if (device->delay_scan_out < 0)
-			    cmd->id = CMD_SCAN_OUT;
-		    else
-			    cmd->id = CMD_SLOW_SCAN_OUT;
-		    ret = angie_allocate_payload(cmd, scan_size_bytes + 5, PAYLOAD_DIRECTION_OUT);
-		    break;
-	    case SCAN_IO:
-		    if (device->delay_scan_io < 0)
-			    cmd->id = CMD_SCAN_IO;
-		    else
-			    cmd->id = CMD_SLOW_SCAN_IO;
-		    ret = angie_allocate_payload(cmd, scan_size_bytes + 5, PAYLOAD_DIRECTION_OUT);
-		    break;
-	    default:
-		    LOG_ERROR("BUG: 'append scan cmd' encountered an unknown scan type");
-		    ret = ERROR_FAIL;
-		    break;
-	}
-
-	if (ret != ERROR_OK) {
-		free(cmd);
-		return ret;
-	}
-
-	/* Build payload_out that is common to all scan types */
-	cmd->payload_out[0] = scan_size_bytes & 0xFF;
-	cmd->payload_out[1] = bits_last_byte & 0xFF;
-	cmd->payload_out[2] = ((tms_count_start & 0x0F) << 4) | (tms_count_end & 0x0F);
-	cmd->payload_out[3] = tms_sequence_start;
-	cmd->payload_out[4] = tms_sequence_end;
-
-	/* Setup payload_out for types with OUT transfer */
-	if (scan_type == SCAN_OUT || scan_type == SCAN_IO) {
-		for (i = 0; i < scan_size_bytes; i++)
-			cmd->payload_out[i + 5] = tdi[i];
-	}
-
-	/* Setup payload_in pointers for types with IN transfer */
-	if (scan_type == SCAN_IN || scan_type == SCAN_IO) {
-		cmd->payload_in_start = tdo_start;
-		cmd->payload_in = tdo;
-		cmd->payload_in_size = scan_size_bytes;
-	}
-
-	cmd->needs_postprocessing = postprocess;
-	cmd->cmd_origin = origin;
-
-	/* For scan commands, we free payload_in_start only when the command is
-	 * the last in a series of split commands or a stand-alone command */
-	cmd->free_payload_in_start = postprocess;
-
-	return angie_append_queue(device, cmd);
-}
-
-/**
- * Perform TAP state transitions
- *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @param count defines the number of TCK clock cycles generated (up to 8).
- * @param sequence defines the TMS pin levels for each state transition. The
- *  Least-Significant Bit is read first.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
- */
-static int angie_append_clock_tms_cmd(struct angie *device, uint8_t count,
-	uint8_t sequence)
-{
-	struct angie_cmd *cmd = calloc(1, sizeof(struct angie_cmd));
-	int ret;
-
-	if (!cmd) {
-		LOG_ERROR("Out of memory");
-		return ERROR_FAIL;
-	}
-
-	if (device->delay_clock_tms < 0)
-		cmd->id = CMD_CLOCK_TMS;
-	else
-		cmd->id = CMD_SLOW_CLOCK_TMS;
-
-	/* CMD_CLOCK_TMS has two OUT payload bytes and zero IN payload bytes */
-	ret = angie_allocate_payload(cmd, 2, PAYLOAD_DIRECTION_OUT);
-	if (ret != ERROR_OK) {
-		free(cmd);
-		return ret;
-	}
-
-	cmd->payload_out[0] = count;
-	cmd->payload_out[1] = sequence;
-
-	return angie_append_queue(device, cmd);
-}
-
-/**
- * Generate a defined amount of TCK clock cycles
- *
- * All other JTAG signals are left unchanged.
- *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @param count the number of TCK clock cycles to generate.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
- */
-static int angie_append_clock_tck_cmd(struct angie *device, uint16_t count)
-{
-	struct angie_cmd *cmd = calloc(1, sizeof(struct angie_cmd));
-	int ret;
-
-	if (!cmd) {
-		LOG_ERROR("Out of memory");
-		return ERROR_FAIL;
-	}
-
-	if (device->delay_clock_tck < 0)
-		cmd->id = CMD_CLOCK_TCK;
-	else
-		cmd->id = CMD_SLOW_CLOCK_TCK;
-
-	/* CMD_CLOCK_TCK has two OUT payload bytes and zero IN payload bytes */
-	ret = angie_allocate_payload(cmd, 2, PAYLOAD_DIRECTION_OUT);
-	if (ret != ERROR_OK) {
-		free(cmd);
-		return ret;
-	}
-
-	cmd->payload_out[0] = count & 0xff;
-	cmd->payload_out[1] = (count >> 8) & 0xff;
-
-	return angie_append_queue(device, cmd);
-}
-
-/**
- * Read JTAG signals.
- *
- * @param device pointer to struct angie identifying ANGIE driver instance.
- * @return on success: ERROR_OK
- * @return on failure: ERROR_FAIL
- */
-...
 
[truncated message content]

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1138-gc132aed2a

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  c132aed2a611a16f4759626123ab78e446a737ce (commit)
      from  18d5ea95e59e83ebee8379f0de459d2f8f0482f4 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit c132aed2a611a16f4759626123ab78e446a737ce
Author: Ahmed BOUDJELIDA <abo...@na...>
Date:   Wed Apr 23 17:42:33 2025 +0200

    contrib/firmware/angie: deactivate srst signal in bitstream
    
    angie probe doesn't use srst pin anymore, it was removed in
    latest version.
    
    Change-Id: I6b1439f2328770e5b525c3d129afd08bddf42025
    Signed-off-by: Ahmed BOUDJELIDA <abo...@na...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8859
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/contrib/firmware/angie/hdl/src/angie_bitstream.vhd b/contrib/firmware/angie/hdl/src/angie_bitstream.vhd
index a1b86862d..737a84ce5 100644
--- a/contrib/firmware/angie/hdl/src/angie_bitstream.vhd
+++ b/contrib/firmware/angie/hdl/src/angie_bitstream.vhd
@@ -75,7 +75,6 @@ signal trst_clk, trst_rst, trst_d, trst_q : std_logic;
 signal tms_clk, tms_rst, tms_d, tms_q : std_logic;
 signal tdi_clk, tdi_rst, tdi_d, tdi_q : std_logic;
 signal tdo_clk, tdo_rst, tdo_d, tdo_q : std_logic;
-signal srst_clk, srst_rst, srst_d, srst_q : std_logic;
 
 ----------------------------------------clk_div
 signal clk_div_in, clk_div_out, reset_clk_div : std_logic;
@@ -188,14 +187,6 @@ port map (
    q => tdo_q
 );
 
-DFF_inst_SRST : DFF
-port map (
-   clk => srst_clk,
-   reset => srst_rst,
-   d => srst_d,
-   q => srst_q
-);
-
 -- Instantiate the FIFO OUT
 U0 : fifo_generator_v9_3
 port map (
@@ -233,7 +224,6 @@ trst_clk <= IFCLK_I;
 tms_clk <= IFCLK_I;
 tdi_clk <= IFCLK_I;
 tdo_clk <= IFCLK_I;
-srst_clk <= IFCLK_I;
 
 --------------- FIFOs
 clk_wr_o <= IFCLK_I;
@@ -308,7 +298,6 @@ begin
         tms_rst <= '1';
         tdi_rst <= '1';
         tdo_rst <= '1';
-        srst_rst <= '1';
     else
         reset_mae <= '0';   -- No Reset State Machine
         reset_mae2 <= '0';   -- Reset State Machine
@@ -320,7 +309,6 @@ begin
         tms_rst <= '0';
         tdi_rst <= '0';
         tdo_rst <= '0';
-        srst_rst <= '0';
     end if;
 end process;
 
@@ -419,8 +407,7 @@ ST_0_O <= '0';
 -- TDO : in
 ST_1_O <= '1';
 -- SRST : out
-ST_2_O <= srst_q;
-srst_d <= data_out_o(6);
+ST_2_O <= '1';
 SO_SRST_O <= '0';
 -- MOD : in
 ST_3_O <= '1';
diff --git a/src/jtag/drivers/angie/angie_bitstream.bit b/src/jtag/drivers/angie/angie_bitstream.bit
index fb1c73497..71fbb85e6 100644
Binary files a/src/jtag/drivers/angie/angie_bitstream.bit and b/src/jtag/drivers/angie/angie_bitstream.bit differ

-----------------------------------------------------------------------

Summary of changes:
 contrib/firmware/angie/hdl/src/angie_bitstream.vhd |  15 +--------------
 src/jtag/drivers/angie/angie_bitstream.bit         | Bin 340721 -> 341277 bytes
 2 files changed, 1 insertion(+), 14 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1137-g18d5ea95e

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  18d5ea95e59e83ebee8379f0de459d2f8f0482f4 (commit)
      from  9a150e326a655c9bd2fbead1be43748ca640764c (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 18d5ea95e59e83ebee8379f0de459d2f8f0482f4
Author: Ahmed BOUDJELIDA <abo...@na...>
Date:   Wed Jan 15 16:44:28 2025 +0100

    contrib/firmware/angie: correct usb descriptor issues
    
    Correct the issue of usb descriptor does not appear
    near the PID and VID, Cypress USB controller cannot
    handle direct pointers to memory CODE area, so we
    copy the data in the external RAM area and point
    to it.
    
    Change-Id: I3221627dc8576f6341b444acd9c554fd5cc47918
    Signed-off-by: Ahmed BOUDJELIDA <abo...@na...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8736
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/contrib/firmware/angie/c/include/usb.h b/contrib/firmware/angie/c/include/usb.h
index 37d3b8ae2..dbf41fe8e 100644
--- a/contrib/firmware/angie/c/include/usb.h
+++ b/contrib/firmware/angie/c/include/usb.h
@@ -104,7 +104,7 @@ struct usb_endpoint_descriptor {
 struct usb_language_descriptor {
 	uint8_t blength;		/**< Size of this descriptor in bytes. */
 	uint8_t bdescriptortype;	/**< STRING descriptor type. */
-	uint16_t wlangid[];		/**< LANGID codes. */
+	uint16_t wlangid;		/**< LANGID codes. */
 };
 
 /** USB String Descriptor. See USB 2.0 Spec */
diff --git a/contrib/firmware/angie/c/src/usb.c b/contrib/firmware/angie/c/src/usb.c
index 9b48e8353..6a07cc5d3 100644
--- a/contrib/firmware/angie/c/src/usb.c
+++ b/contrib/firmware/angie/c/src/usb.c
@@ -19,6 +19,7 @@
 #include "i2c.h"
 #include <stdint.h>
 #include <stdio.h>
+#include <string.h>
 
 // #define PRINTF_DEBUG
 
@@ -122,7 +123,7 @@ __code struct usb_endpoint_descriptor bulk_ep8_in_endpoint_descriptor = {
 __code struct usb_language_descriptor language_descriptor = {
 	.blength =				4,
 	.bdescriptortype =		DESCRIPTOR_TYPE_STRING,
-	.wlangid =				{0x0409} /* US English */
+	.wlangid =				0x0409 /* US English */
 };
 
 __code struct usb_string_descriptor strmanufacturer =
@@ -134,15 +135,11 @@ __code struct usb_string_descriptor strproduct =
 __code struct usb_string_descriptor strserialnumber =
 	STR_DESCR(6, '0', '0', '0', '0', '0', '1');
 
-__code struct usb_string_descriptor strconfigdescr  =
-	STR_DESCR(12, 'J', 'T', 'A', 'G', ' ', 'A', 'd', 'a', 'p', 't', 'e', 'r');
-
 /* Table containing pointers to string descriptors */
-__code struct usb_string_descriptor *__code en_string_descriptors[4] = {
+__code struct usb_string_descriptor *__code en_string_descriptors[3] = {
 	&strmanufacturer,
 	&strproduct,
-	&strserialnumber,
-	&strconfigdescr
+	&strserialnumber
 };
 void sudav_isr(void)__interrupt SUDAV_ISR
 {
@@ -196,7 +193,6 @@ void ep6_isr(void)__interrupt	EP6_ISR
 	i2c_recieve();  /* Execute I2C communication */
 	EXIF &= ~0x10;  /* Clear USBINT: Main global interrupt */
 	EPIRQ = 0x40;	/* Clear individual EP6OUT IRQ */
-	REVCTL = 0x3;   /* REVCTL.0 and REVCTL.1 set to 1 */
 }
 void ep8_isr(void)__interrupt	EP8_ISR
 {
@@ -328,63 +324,6 @@ void usb_reset_data_toggle(uint8_t ep)
 	TOGCTL |= BMRESETTOGGLE;
 }
 
-/**
- * Handle GET_STATUS request.
- *
- * @return on success: true
- * @return on failure: false
- */
-bool usb_handle_get_status(void)
-{
-	uint8_t *ep_cs;
-	switch (setup_data.bmrequesttype) {
-	case GS_DEVICE:
-		/* Two byte response: Byte 0, Bit 0 = self-powered, Bit 1 = remote wakeup.
-		 *                    Byte 1: reserved, reset to zero */
-		EP0BUF[0] = 0;
-		EP0BUF[1] = 0;
-
-		/* Send response */
-		EP0BCH = 0;
-		syncdelay(3);
-		EP0BCL = 2;
-		syncdelay(3);
-		break;
-	case GS_INTERFACE:
-		/* Always return two zero bytes according to USB 1.1 spec, p. 191 */
-		EP0BUF[0] = 0;
-		EP0BUF[1] = 0;
-
-		/* Send response */
-		EP0BCH = 0;
-		syncdelay(3);
-		EP0BCL = 2;
-		syncdelay(3);
-		break;
-	case GS_ENDPOINT:
-		/* Get stall bit for endpoint specified in low byte of wIndex */
-		ep_cs = usb_get_endpoint_cs_reg(setup_data.windex & 0xff);
-
-		if (*ep_cs & EPSTALL)
-			EP0BUF[0] = 0x01;
-		else
-			EP0BUF[0] = 0x00;
-
-		/* Second byte sent has to be always zero */
-		EP0BUF[1] = 0;
-
-		/* Send response */
-		EP0BCH = 0;
-		syncdelay(3);
-		EP0BCL = 2;
-		syncdelay(3);
-		break;
-	default:
-		return false;
-	}
-	return true;
-}
-
 /**
  * Handle CLEAR_FEATURE request.
  *
@@ -480,12 +419,17 @@ bool usb_handle_get_descriptor(void)
 	case DESCRIPTOR_TYPE_STRING:
 		if (setup_data.windex == 0) {
 			/* Supply language descriptor */
-			SUDPTRH = HI8(&language_descriptor);
-			SUDPTRL = LO8(&language_descriptor);
+			__xdata struct usb_language_descriptor temp_descriptor;
+			memcpy(&temp_descriptor, &language_descriptor, sizeof(language_descriptor));
+			SUDPTRH = HI8(&temp_descriptor);
+			SUDPTRL = LO8(&temp_descriptor);
 		} else if (setup_data.windex == 0x0409 /* US English */) {
 			/* Supply string descriptor */
-			SUDPTRH = HI8(en_string_descriptors[descriptor_index - 1]);
-			SUDPTRL = LO8(en_string_descriptors[descriptor_index - 1]);
+			__xdata uint8_t temp_descriptors[3];
+			memcpy(temp_descriptors, en_string_descriptors[descriptor_index - 1],
+				   ((struct usb_string_descriptor *)en_string_descriptors[descriptor_index - 1])->blength);
+			SUDPTRH = HI8(temp_descriptors);
+			SUDPTRL = LO8(temp_descriptors);
 		} else {
 			return false;
 		}
@@ -610,6 +554,8 @@ bool usb_handle_vcommands(void)
 			; /* wait to finish transferring in EP0BUF, until not busy */
 		gcnt  = ((uint32_t)(eptr[0]) << 24) | ((uint32_t)(eptr[1]) << 16)
 		| ((uint32_t)(eptr[2]) << 8) | (uint32_t)(eptr[3]);
+		/* REVCTL.0 and REVCTL.1 set to 1 */
+		REVCTL = 0x3;
 		/* Angie board FPGA bitstream download */
 		PIN_RDWR_B = 0;
 		/* Initialize GPIF interface transfer count */
@@ -632,6 +578,10 @@ bool usb_handle_vcommands(void)
 		EP4AUTOINLENL = (uint8_t)((uint32_t)(gcnt) & 0x000000ff);
 		/* Trigger GPIF IN transfer on EP4 */
 		GPIFTRIG = BMGPIFREAD | GPIF_EP4;
+		while (!(GPIFTRIG & BMGPIFDONE)) // poll GPIFTRIG.7 GPIF Done bit
+			;
+		/* REVCTL.0 and REVCTL.1 set to 0 */
+		REVCTL = 0;
 		break;
 	default:
 		return true;	/* Error: unknown VR command */
@@ -646,8 +596,12 @@ void usb_handle_setup_data(void)
 {
 	switch (setup_data.brequest) {
 	case GET_STATUS:
-		if (!usb_handle_get_status())
-			STALL_EP0();
+		EP0BUF[0] = 0;
+		EP0BUF[1] = 0;
+		/* Send response */
+		EP0BCH = 0;
+		EP0BCL = 2;
+		syncdelay(3);
 		break;
 	case CLEAR_FEATURE:
 		if (!usb_handle_clear_feature())
@@ -880,7 +834,9 @@ void interrupt_init(void)
 	/* Clear SUDAV interrupt */
 	USBIRQ = SUDAVI;
 
-	/* Enable Interrupts */
+	/* Enable Interrupts (Do not confuse this with
+	 * EA External Access pin, see ANGIE Schematic)
+	 */
 	EA = 1;
 }
 
diff --git a/src/jtag/drivers/angie/angie_firmware.bin b/src/jtag/drivers/angie/angie_firmware.bin
index 6ba2babb1..ecf2cfd51 100644
Binary files a/src/jtag/drivers/angie/angie_firmware.bin and b/src/jtag/drivers/angie/angie_firmware.bin differ

-----------------------------------------------------------------------

Summary of changes:
 contrib/firmware/angie/c/include/usb.h    |   2 +-
 contrib/firmware/angie/c/src/usb.c        | 100 +++++++++---------------------
 src/jtag/drivers/angie/angie_firmware.bin | Bin 4487 -> 4478 bytes
 3 files changed, 29 insertions(+), 73 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1136-g9a150e326

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  9a150e326a655c9bd2fbead1be43748ca640764c (commit)
      from  ceaa47a2aa86ac476400683f3d78519f1ea79d5a (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 9a150e326a655c9bd2fbead1be43748ca640764c
Author: Ahmed BOUDJELIDA <abo...@na...>
Date:   Thu Dec 12 10:27:14 2024 +0100

    contrib/firmware/angie: add dev-board power detection
    
    Add a check if i2c SDA pin state is HIGH.
    if its HIGH, the dev-board is ON, we receive
    number of Ack.
    in its LOW, the board is OFF, we send this
    information back to driver.
    
    Change-Id: Ia40d3910675cc10e0208d8bc0060a19c12b1409d
    Signed-off-by: Ahmed BOUDJELIDA <abo...@na...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8716
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/contrib/firmware/angie/c/include/i2c.h b/contrib/firmware/angie/c/include/i2c.h
index d0404923b..7a199c15a 100644
--- a/contrib/firmware/angie/c/include/i2c.h
+++ b/contrib/firmware/angie/c/include/i2c.h
@@ -14,6 +14,7 @@
 #include <stdint.h>
 #include <stdio.h>
 
+bool get_status(void);
 void start_cd(void);
 void repeated_start(void);
 void stop_cd(void);
diff --git a/contrib/firmware/angie/c/src/i2c.c b/contrib/firmware/angie/c/src/i2c.c
index 9aadc2c25..4cf82955f 100644
--- a/contrib/firmware/angie/c/src/i2c.c
+++ b/contrib/firmware/angie/c/src/i2c.c
@@ -12,6 +12,19 @@
 #include "delay.h"
 #include "reg_ezusb.h"
 
+bool get_status(void)
+{
+	PIN_SDA_DIR = 1;
+	OEA = 0xF7;
+	delay_us(1);
+	bool sda_state = PIN_SDA;
+	PIN_T0 = sda_state;
+	delay_us(1);
+	OEA = 0xFF;
+	delay_us(1);
+	return sda_state;
+}
+
 void start_cd(void)
 {
 	PIN_SDA_DIR = 0;    // SP6 SDA: OUT
diff --git a/contrib/firmware/angie/c/src/main.c b/contrib/firmware/angie/c/src/main.c
index 042a1eca7..657694b6c 100644
--- a/contrib/firmware/angie/c/src/main.c
+++ b/contrib/firmware/angie/c/src/main.c
@@ -11,9 +11,9 @@
 *****************************************************************************/
 
 #include "usb.h"
+#include "serial.h"
 #include "delay.h"
 #include "reg_ezusb.h"
-#include <serial.h>
 #include <stdio.h>
 
 extern void sudav_isr(void)__interrupt	SUDAV_ISR;
diff --git a/contrib/firmware/angie/c/src/usb.c b/contrib/firmware/angie/c/src/usb.c
index f3bc99ba1..9b48e8353 100644
--- a/contrib/firmware/angie/c/src/usb.c
+++ b/contrib/firmware/angie/c/src/usb.c
@@ -55,7 +55,7 @@ __code struct usb_config_descriptor config_descriptor = {
 							((NUM_ENDPOINTS * 2) * sizeof(struct usb_endpoint_descriptor)),
 	.bnuminterfaces =		2,
 	.bconfigurationvalue =	1,
-	.iconfiguration =		4,	/* String describing this configuration */
+	.iconfiguration =		2,	/* String describing this configuration */
 	.bmattributes =			0x80,	/* Only MSB set according to USB spec */
 	.maxpower =				50	/* 100 mA */
 };
@@ -69,7 +69,7 @@ __code struct usb_interface_descriptor interface_descriptor00 = {
 	.binterfaceclass =		0XFF,
 	.binterfacesubclass =	0x00,
 	.binterfaceprotocol =	0x00,
-	.iinterface =			5
+	.iinterface =			0
 };
 
 __code struct usb_endpoint_descriptor bulk_ep2_endpoint_descriptor = {
@@ -99,7 +99,7 @@ __code struct usb_interface_descriptor interface_descriptor01 = {
 	.binterfaceclass =		0x0A,
 	.binterfacesubclass =	0x00,
 	.binterfaceprotocol =	0x00,
-	.iinterface =			6
+	.iinterface =			0
 };
 
 __code struct usb_endpoint_descriptor bulk_ep6_out_endpoint_descriptor = {
@@ -200,8 +200,8 @@ void ep6_isr(void)__interrupt	EP6_ISR
 }
 void ep8_isr(void)__interrupt	EP8_ISR
 {
-	EXIF &= ~0x10;  /* Clear USBINT: Main global interrupt */
-	EPIRQ = 0x80;	/* Clear individual EP8IN IRQ */
+	EXIF &= ~0x10;		/* Clear USBINT: Main global interrupt */
+	EPIRQ = 0x80;		/* Clear individual EP8IN IRQ */
 }
 void ibn_isr(void)__interrupt	IBN_ISR
 {
@@ -761,16 +761,16 @@ void ep_init(void)
 
 void i2c_recieve(void)
 {
-	PIN_SDA_DIR = 0;
 	if (EP6FIFOBUF[0] == 1) {
-		uint8_t rdwr = EP6FIFOBUF[0];   //read
-		uint8_t data_count = EP6FIFOBUF[1]; //data sent count
+		uint8_t rdwr = EP6FIFOBUF[0];   //read: 1
+		uint8_t reg_byte_check = EP6FIFOBUF[1]; //register given: 1 else: 0
 		uint8_t count = EP6FIFOBUF[2];  //requested data count
 		uint8_t adr = EP6FIFOBUF[3];    //address
 		uint8_t address = get_address(adr, rdwr);   //address byte (read command)
 		uint8_t address_2 = get_address(adr, 0);   //address byte 2 (write command)
 
-		printf("%d\n", address - 1);
+		/* i2c bus state byte */
+		EP8FIFOBUF[0] = get_status();
 
 		/*  start:   */
 		start_cd();
@@ -780,12 +780,10 @@ void i2c_recieve(void)
 		uint8_t ack = get_ack();
 
 		/*   send data   */
-		if (data_count) { //if there is a byte reg
-			for (uint8_t i = 0; i < data_count; i++) {
-				send_byte(EP6FIFOBUF[i + 4]);
-				/*  ack():  */
-				ack = get_ack();
-			}
+		for (int i = 0; i < reg_byte_check; i++) {
+			send_byte(EP6FIFOBUF[i + 4]);
+			/*  ack():  */
+			ack = get_ack();
 		}
 
 		/*  repeated start:  */
@@ -796,14 +794,14 @@ void i2c_recieve(void)
 		ack = get_ack();
 
 		/*   receive data   */
-		for (uint8_t i = 0; i < count - 1; i++) {
+		for (int i = 1; i < count; i++) {
 			EP8FIFOBUF[i] = receive_byte();
 
 			/*  send ack: */
 			send_ack();
 		}
 
-		EP8FIFOBUF[count - 1] = receive_byte();
+		EP8FIFOBUF[count] = receive_byte();
 
 		/*  send Nack:  */
 		send_nack();
@@ -811,44 +809,46 @@ void i2c_recieve(void)
 		/*   stop   */
 		stop_cd();
 
-		EP8BCH = 0; //EP8
+		EP8BCH = (count + 1) >> 8; //EP8
 		syncdelay(3);
-		EP8BCL = count; //EP8
+		EP8BCL = count + 1; //EP8
 
 		EP6BCL = 0x80; //EP6
 		syncdelay(3);
 		EP6BCL = 0x80; //EP6
 	} else {
-		uint8_t rdwr = EP6FIFOBUF[0];   //write
+		uint8_t rdwr = EP6FIFOBUF[0];   //write: 0
 		uint8_t count = EP6FIFOBUF[1];  //data count
 		uint8_t adr = EP6FIFOBUF[2];    //address
 		uint8_t address = get_address(adr, rdwr);   //address byte (read command)
 		uint8_t ack_cnt = 0;
 
-/*  start():   */
+		// i2c bus state byte
+		EP8FIFOBUF[0] = get_status();
+
+		/*  start():   */
 		start_cd();
-/*  address:   */
+		/*  address:   */
 		send_byte(address);   //write
-/*  ack():  */
+		/*  ack():  */
 		if (!get_ack())
 			ack_cnt++;
-/*   send data  */
-		for (uint8_t i = 0; i < count; i++) {
+		/*   send data  */
+		for (int i = 0; i < count; i++) {
 			send_byte(EP6FIFOBUF[i + 3]);
-
 			/*  get ack:  */
 			if (!get_ack())
 				ack_cnt++;
 		}
 
-/*   stop   */
+		/*   stop   */
 		stop_cd();
 
-		EP8FIFOBUF[0] = ack_cnt;
+		EP8FIFOBUF[1] = ack_cnt;
 
 		EP8BCH = 0; //EP8
 		syncdelay(3);
-		EP8BCL = 1; //EP8
+		EP8BCL = 2; //EP8
 
 		EP6BCL = 0x80; //EP6
 		syncdelay(3);
diff --git a/src/jtag/drivers/angie/angie_firmware.bin b/src/jtag/drivers/angie/angie_firmware.bin
index 68486ef8f..6ba2babb1 100644
Binary files a/src/jtag/drivers/angie/angie_firmware.bin and b/src/jtag/drivers/angie/angie_firmware.bin differ

-----------------------------------------------------------------------

Summary of changes:
 contrib/firmware/angie/c/include/i2c.h    |   1 +
 contrib/firmware/angie/c/src/i2c.c        |  13 +++++++
 contrib/firmware/angie/c/src/main.c       |   2 +-
 contrib/firmware/angie/c/src/usb.c        |  58 +++++++++++++++---------------
 src/jtag/drivers/angie/angie_firmware.bin | Bin 10216 -> 4487 bytes
 5 files changed, 44 insertions(+), 30 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1135-gceaa47a2a

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  ceaa47a2aa86ac476400683f3d78519f1ea79d5a (commit)
       via  2f1a0ab35f28655119c743a2913b773a350c6137 (commit)
      from  663d97b38550bf0aba42005912822bff713caeda (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit ceaa47a2aa86ac476400683f3d78519f1ea79d5a
Author: Ahmed BOUDJELIDA <abo...@na...>
Date:   Thu Dec 12 10:17:25 2024 +0100

    contrib/firmware/angie: add new spartan6 VHDL code
    
    This new code implement two FIFOs for handling TX and RX
    JTAG data transfers, its simply receives data and send it
    OUT to target chip in respect of JTAG protocol timing
    constraints.
    The IN FIFO receives data from target chip and send it
    back to openocd.
    
    Change-Id: I17c1231e7f4b0a6b510359fe147b609922e0809e
    Signed-off-by: Ahmed BOUDJELIDA <abo...@na...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8715
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/contrib/firmware/angie/hdl/src/angie_bitstream.ucf b/contrib/firmware/angie/hdl/src/angie_bitstream.ucf
index 9eb0c85c3..48c5b9407 100644
--- a/contrib/firmware/angie/hdl/src/angie_bitstream.ucf
+++ b/contrib/firmware/angie/hdl/src/angie_bitstream.ucf
@@ -1,8 +1,8 @@
 ## SPDX-License-Identifier: BSD-3-Clause
 ##--------------------------------------------------------------------------
-## Project Context: nanoXplore USB-JTAG Adapter Board, Spartan6
-## Design Name:     NJTAG USB-JTAG Adapter FPGA source code
-## Module Name:     _angie_openocd.ucf
+## Project Context: nanoXplore USB to JTAG/I2C Adapter Board, Spartan6
+## Design Name:     ANGIE USB to JTAG/I2C Adapter FPGA source code
+## Module Name:     angie_bitstream.ucf
 ## Target Device:   XC6SLX9-2 TQ144
 ## Tool versions:   ISE Webpack 13.2 -> 14.2
 ## Author:          Ahmed BOUDJELIDA    nanoXplore SAS
@@ -10,41 +10,65 @@
 # WARNING: PullUps on JTAG inputs should be enabled after configuration
 # (bitgen option) since the pins are not connected.
 
-net TRST	LOC = 'P48' ;
-net TMS		LOC = 'P43' ;
-net TCK		LOC = 'P44' ;
-net TDI		LOC = 'P45' ;
-net TDO     LOC = 'P46' ;
-net SRST    LOC = 'P61' ;
-
-net SDA		LOC = 'P50' ;
-net SCL     LOC = 'P51' ;
-net SDA_DIR	LOC = 'P56' ;
-net SCL_DIR	LOC = 'P57' ;
-
-net SI_TDO	LOC = 'P16' ;
-net SO_TRST	LOC = 'P32' ;
-net SO_TMS	LOC = 'P27' ;
-net SO_TCK	LOC = 'P30' ;
-net SO_TDI	LOC = 'P26' ;
-net SO_SRST	LOC = 'P12' ;
-
-net SO_SDA_OUT	LOC = 'P140' ;
-net SO_SDA_IN	LOC = 'P1' ;
-net SO_SCL	LOC = 'P137';
-
-net ST_0	LOC = 'P29' ;
-net ST_1	LOC = 'P21' ;
-net ST_2	LOC = 'P11' ;
-
-net ST_4	LOC = 'P134' ;
-net ST_5	LOC = 'P139' ;
-
-net FTP<0>	LOC = 'P121' ;
-net FTP<1>	LOC = 'P120' ;
-net FTP<2>	LOC = 'P119' ;
-net FTP<3>	LOC = 'P116' ;
-net FTP<4>	LOC = 'P111' ;
-net FTP<5>	LOC = 'P112' ;
-net FTP<6>	LOC = 'P115' ;
-net FTP<7>	LOC = 'P114' ;
+CONFIG VCCAUX = "3.3";
+
+# Timing
+# net IH24        period = 40; # Constrain at 25MHz
+# net IH40        period = 25; # Constrain at 40MHz
+# DCMs placement on Spartan6
+# INST S6MOD_CKMUL.H48_DCM    LOC = DCM0;
+
+# Clock 48MHz
+net IFCLK_I            LOC = 'P123' ;
+
+net GD_IO<0> 	     LOC = 'P48' ;
+net GD_IO<1>		 LOC = 'P43' ;
+net GD_IO<2>         LOC = 'P44' ;
+net GD_IO<3>		 LOC = 'P45' ;
+net GD_IO<4>         LOC = 'P46' ;
+net GD_IO<5>         LOC = 'P61' ;
+net GD_IO<6>         LOC = 'P62' ;
+net GD_IO<7>         LOC = 'P65' ;
+
+net PA2_I            LOC = 'P47' ;
+#net PA3_I            LOC = 'P64' ;
+net JPW_I            LOC = 'P14' ;
+
+net GCTL0_I          LOC = 'P70' ;
+#net GCTL1_I          LOC = 'P55' ;
+#net GCTL2_I          LOC = 'P67' ;
+net GRDY1_I          LOC = 'P118' ;
+
+#net SDA_IO		     LOC = 'P50' ;
+net SDA_IO		    LOC = 'P64' ; #PA3
+#net SCL_I           LOC = 'P51' ;
+net SCL_I           LOC = 'P39' ; #PA4 switch
+net SDA_DIR_I	    LOC = 'P66' ; #PA0 switch
+#net SCL_DIR_I	     LOC = 'P57' ;
+
+net SO_SDA_OUT_O	LOC = 'P140' ;
+net SO_SDA_IN_I	    LOC = 'P1' ;
+net SO_SCL_O	    LOC = 'P137' ;
+
+net SO_TRST_O	    LOC = 'P32' ;
+net SO_TMS_O	    LOC = 'P27' ;
+net SO_TCK_O        LOC = 'P30' ;
+net SO_TDI_O        LOC = 'P26' ;
+net SO_SRST_O       LOC = 'P12' ;
+net SI_TDO_I        LOC = 'P16' ;
+
+net ST_0_O	        LOC = 'P29' ;
+net ST_1_O	        LOC = 'P21' ;
+net ST_2_O	        LOC = 'P11' ;
+net ST_3_O	        LOC = 'P7' ;
+net ST_4_O	        LOC = 'P134' ;
+net ST_5_O	        LOC = 'P139' ;
+
+net FTP_O<0>	    LOC = 'P121' ;
+net FTP_O<1>	    LOC = 'P120' ;
+net FTP_O<2>	    LOC = 'P119' ;
+net FTP_O<3>	    LOC = 'P116' ;
+net FTP_O<4>	    LOC = 'P111' ;
+net FTP_O<5>	    LOC = 'P112' ;
+net FTP_O<6>	    LOC = 'P115' ;
+net FTP_O<7>	    LOC = 'P114' ;
diff --git a/contrib/firmware/angie/hdl/src/angie_bitstream.vhd b/contrib/firmware/angie/hdl/src/angie_bitstream.vhd
index 6004bf2ff..a1b86862d 100644
--- a/contrib/firmware/angie/hdl/src/angie_bitstream.vhd
+++ b/contrib/firmware/angie/hdl/src/angie_bitstream.vhd
@@ -1,103 +1,428 @@
 -- SPDX-License-Identifier: BSD-3-Clause
 ----------------------------------------------------------------------------
--- Project Context: nanoXplore USB-JTAG Adapter Board, Spartan6
--- Design Name:     NJTAG USB-JTAG Adapter FPGA source code
--- Module Name:     _angie_openocd.vhd
+-- Project Context: nanoXplore USB to JTAG/I2C Adapter Board, Spartan6
+-- Design Name:     ANGIE USB to JTAG/I2C Adapter FPGA source code
+-- Module Name:     angie_bitstream.vhd
 -- Target Device:   XC6SLX9-2 TQ144
 -- Tool versions:   ISE Webpack 13.2 -> 14.2
 -- Author:          Ahmed BOUDJELIDA    nanoXplore SAS
 ----------------------------------------------------------------------------
-
+library work;
+use work.all;
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.std_logic_arith.all;
 use ieee.std_logic_unsigned.all;
-library UNISIM;
-use UNISIM.VComponents.all;
-
-entity S609 is port(
-  TRST : in std_logic;
-  TMS : in std_logic;
-  TCK : in std_logic;
-  TDI : in std_logic;
-  TDO : out std_logic;
-  SRST : in std_logic;
-
-  SDA : inout std_logic;
-  SDA_DIR : in std_logic;
-  SCL : in std_logic;
-  SCL_DIR : in std_logic;
-
-  FTP : out std_logic_vector(7 downto 0); -- Test points
-  SI_TDO : in  std_logic;
-  ST_0 : out std_logic;
-  ST_1 : out std_logic;
-  ST_2 : out std_logic;
-
-  ST_4 : out std_logic;
-  ST_5 : out std_logic;
-
-  SO_SDA_OUT : out std_logic;
-  SO_SDA_IN : in std_logic;
-  SO_SCL : out std_logic;
-
-  SO_TRST : out std_logic;
-  SO_TMS : out std_logic;
-  SO_TCK : out std_logic;
-  SO_TDI : out std_logic;
-  SO_SRST : out std_logic
+
+entity angie_bitstream is port(
+  SDA_IO : inout std_logic;
+  SDA_DIR_I : in std_logic;
+  SCL_I : in std_logic;
+
+  JPW_I : in std_logic;     --Devkit power
+
+  SO_SDA_OUT_O : out std_logic;
+  SO_SDA_IN_I : in std_logic;
+  SO_SCL_O : out std_logic;
+
+  ST_0_O : out std_logic;
+  ST_1_O : out std_logic;
+  ST_2_O : out std_logic;
+  ST_3_O : out std_logic;
+  ST_4_O : out std_logic;
+  ST_5_O : out std_logic;
+
+  SO_TRST_O : out std_logic;
+  SO_TMS_O : out std_logic;
+  SO_TCK_O : out std_logic;
+  SO_TDI_O : out std_logic;
+  SO_SRST_O : out std_logic;
+  SI_TDO_I : in std_logic;
+
+  PA2_I : in std_logic; -- GPIF IN
+
+  -- Clock 48MHz
+  IFCLK_I : in std_logic;
+
+  GCTL0_I : in std_logic;
+  GRDY1_I : out std_logic;
+  GD_IO : inout std_logic_vector(7 downto 0);
+  FTP_O : out std_logic_vector(15 downto 0)
 );
-end S609;
+end angie_bitstream;
+
+architecture A_angie_bitstream of angie_bitstream is
+----------------------------------------Fifo out (PC to devkit)
+signal rst_o, clk_wr_o, clk_rd_o : std_logic;
+signal write_en_o, read_en_o : std_logic;
+signal data_in_o, data_out_o : std_logic_vector(7 downto 0);
+signal empty_o, full_o : std_logic;
+
+----------------------------------------Fifo in (devkit to PC)
+signal rst_i, clk_wr_i, clk_rd_i : std_logic;
+signal write_en_i, read_en_i : std_logic;
+signal data_in_i, data_out_i : std_logic_vector(7 downto 0);
+signal empty_i, full_i : std_logic;
+
+signal wr_o, rd_i : std_logic;
+
+----------------------------------------MAE
+signal transit1, transit2 : std_logic;
+
+----------------------------------------DFF
+signal pa2_dff_clk, pa2_dff_rst, pa2_dff_d, pa2_dff_q : std_logic;
+signal trst_clk, trst_rst, trst_d, trst_q : std_logic;
+signal tms_clk, tms_rst, tms_d, tms_q : std_logic;
+signal tdi_clk, tdi_rst, tdi_d, tdi_q : std_logic;
+signal tdo_clk, tdo_rst, tdo_d, tdo_q : std_logic;
+signal srst_clk, srst_rst, srst_d, srst_q : std_logic;
+
+----------------------------------------clk_div
+signal clk_div_in, clk_div_out, reset_clk_div : std_logic;
+signal clk_div2_in, clk_div2_out, reset_clk_div2 : std_logic;
+
+----------------------------------------MAE
+type State_Type is (IDLE, WRITE_OUT, WRITE_IN, DELAY, READ_IN);
+signal state, state2 : State_Type;
+signal reset_mae, reset_mae2 : std_logic;
+
+-- Add Component DFF
+component DFF
+    Port (
+        clk : in std_logic;
+        reset : in std_logic;
+        d : in std_logic;
+        q : out std_logic
+    );
+end component;
+
+-- Add Component Clk_div
+component clk_div
+Port (
+    clk_in : in std_logic;
+    reset : in std_logic;
+    clk_out : out std_logic
+);
+end component;
+
+-- Add component FIFO 64B
+component fifo_generator_v9_3
+PORT (
+    rst : IN STD_LOGIC;
+    wr_clk : IN STD_LOGIC;
+    rd_clk : IN STD_LOGIC;
+    din : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
+    wr_en : IN STD_LOGIC;
+    rd_en : IN STD_LOGIC;
+    dout : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
+    full : OUT STD_LOGIC;
+    empty : OUT STD_LOGIC
+  );
+end component;
+
+signal state1_debug, state2_debug : std_logic;
 
-architecture A_S609 of S609 is
 begin
+-------------------------------------------------------------I2C :
+SDA_IO <= not(SO_SDA_IN_I) when (SDA_DIR_I = '1') else 'Z';
+SO_SDA_OUT_O <= SDA_IO;
+ST_5_O <= SDA_DIR_I;
 
---Directions:
-ST_0 <= '0';
-ST_1 <= '1';
+SO_SCL_O <= SCL_I when (JPW_I = '1') else '0';
+ST_4_O <= '0';
 
---TDO:
-TDO <= not SI_TDO;
+------------------------------------------------------------JTAG :
+-- Instantiate the Clk div by 10
+clk_div_inst : clk_div
+port map (
+    clk_in => clk_div_in,
+    reset => reset_clk_div,
+    clk_out => clk_div_out
+);
+-- Instantiate the Clk div by 10
+clk_div2_inst : clk_div
+port map (
+    clk_in => clk_div2_in,
+    reset => reset_clk_div2,
+    clk_out => clk_div2_out
+);
 
---TRST - TCK - TMS - TDI:
-SO_TRST <= TRST;
-SO_TMS <= TMS;
-SO_TCK <= TCK;
-SO_TDI <= TDI;
-ST_2 <= SRST;
-SO_SRST <= '0';
+-- Instantiate DFFs
+DFF_inst_PA2 : DFF
+port map (
+   clk => pa2_dff_clk,
+   reset => pa2_dff_rst,
+   d => pa2_dff_d,
+   q => pa2_dff_q
+);
 
-SO_SCL <= SCL;
+DFF_inst_TRST : DFF
+port map (
+   clk => trst_clk,
+   reset => trst_rst,
+   d => trst_d,
+   q => trst_q
+);
+
+DFF_inst_TMS : DFF
+port map (
+   clk => tms_clk,
+   reset => tms_rst,
+   d => tms_d,
+   q => tms_q
+);
 
-SDA <= not(SO_SDA_IN) when (SDA_DIR = '1') else 'Z';
-SO_SDA_OUT <= SDA;
+DFF_inst_TDI : DFF
+port map (
+   clk => tdi_clk,
+   reset => tdi_rst,
+   d => tdi_d,
+   q => tdi_q
+);
 
-process(SDA_DIR)
+DFF_inst_TDO : DFF
+port map (
+   clk => tdo_clk,
+   reset => tdo_rst,
+   d => tdo_d,
+   q => tdo_q
+);
+
+DFF_inst_SRST : DFF
+port map (
+   clk => srst_clk,
+   reset => srst_rst,
+   d => srst_d,
+   q => srst_q
+);
+
+-- Instantiate the FIFO OUT
+U0 : fifo_generator_v9_3
+port map (
+    rst => rst_o,
+    wr_clk => clk_wr_o,
+    rd_clk => clk_rd_o,
+    din => data_in_o,
+    wr_en => write_en_o,
+    rd_en => read_en_o,
+    dout => data_out_o,
+    full => full_o,
+    empty => empty_o
+);
+-- Instantiate the FIFO IN
+U1 : fifo_generator_v9_3
+port map (
+    rst => rst_i,
+    wr_clk => clk_wr_i,
+    rd_clk => clk_rd_i,
+    din => data_in_i,
+    wr_en => write_en_i,
+    rd_en => read_en_i,
+    dout => data_out_i,
+    full => full_i,
+    empty => empty_i
+);
+
+--------------- clock dividers
+clk_div_in <= IFCLK_I;          -- 48Mhz
+clk_div2_in <= clk_div_out;     -- 24Mhz
+
+--------------- DFFs
+pa2_dff_clk <= IFCLK_I;
+trst_clk <= IFCLK_I;
+tms_clk <= IFCLK_I;
+tdi_clk <= IFCLK_I;
+tdo_clk <= IFCLK_I;
+srst_clk <= IFCLK_I;
+
+--------------- FIFOs
+clk_wr_o <= IFCLK_I;
+clk_rd_o <= clk_div2_out;
+clk_wr_i <= clk_div2_out;
+clk_rd_i <= IFCLK_I;
+
+--------------------------- GPIF ready :
+GRDY1_I <= '1';
+
+-------------------------------PA2 DFF :
+pa2_dff_rst <= '0';
+pa2_dff_d <= PA2_I;
+
+-------------------- FX2<->Fifo Enable pins :
+write_en_o <= not(wr_o) and not(GCTL0_I);
+read_en_i <= not(rd_i) and not(GCTL0_I);
+
+---------------- FX2->Fifo Data :
+data_in_o <= GD_IO;
+
+------------ FIFO_OUT->Devkit :
+SO_TRST_O <= trst_q;
+trst_d <= data_out_o(4);
+SO_TMS_O <= tms_q;
+tms_d <= data_out_o(3);
+SO_TDI_O <= tdi_q;
+tdi_d <= data_out_o(1);
+------------
+SO_TCK_O <= data_out_o(0);
+
+-------------------- FIFO_OUT->FIFO_IN :
+--data_in_i <= data_out_o;
+
+-------------------- FIFO_IN<-Devkit :
+data_in_i(0) <= '0';
+data_in_i(1) <= '0';
+data_in_i(2) <= tdo_q;
+tdo_d <= not SI_TDO_I;
+data_in_i(3) <= '0';
+data_in_i(4) <= '0';
+data_in_i(5) <= '0';
+data_in_i(6) <= '0';
+data_in_i(7) <= '0';
+
+-------------------- FX2<-FIFO_IN :
+GD_IO <= data_out_i when (state = READ_IN) else "ZZZZZZZZ";
+
+state1_debug <= '1' when state = READ_IN else '0';
+state2_debug <= '1' when state2 = WRITE_IN else '0';
+
+--Points de test:
+FTP_O(0) <= IFCLK_I;
+FTP_O(1) <= GCTL0_I;
+FTP_O(2) <= GD_IO(0);
+FTP_O(3) <= GD_IO(1);
+FTP_O(4) <= JPW_I;
+FTP_O(5) <= PA2_I;
+FTP_O(6) <= empty_o;
+FTP_O(7) <= not SI_TDO_I;
+
+process(pa2_dff_d, pa2_dff_q)
 begin
-	if(SDA_DIR = '0') then
-		ST_5 <= '0';
-	else
-		ST_5 <= '1';
-	end if;
+    if pa2_dff_d = '0' and pa2_dff_q = '1' then
+        reset_mae <= '1';   -- Reset State Machine
+        reset_mae2 <= '1';   -- Reset State Machine
+        rst_o <= '1';   -- Reset OUT
+        rst_i <= '1';   -- Reset IN
+        reset_clk_div <= '1';
+        reset_clk_div2 <= '1';
+        trst_rst <= '1';
+        tms_rst <= '1';
+        tdi_rst <= '1';
+        tdo_rst <= '1';
+        srst_rst <= '1';
+    else
+        reset_mae <= '0';   -- No Reset State Machine
+        reset_mae2 <= '0';   -- Reset State Machine
+        rst_o <= '0';   -- No Reset OUT
+        rst_i <= '0';   -- No Reset IN
+        reset_clk_div <= '0';
+        reset_clk_div2 <= '0';
+        trst_rst <= '0';
+        tms_rst <= '0';
+        tdi_rst <= '0';
+        tdo_rst <= '0';
+        srst_rst <= '0';
+    end if;
 end process;
 
-process(SCL_DIR)
+process(clk_div2_out, reset_mae2)
 begin
-	if(SCL_DIR = '0') then
-		ST_4 <= '0';
-	else
-		ST_4 <= '1';
-	end if;
+    if reset_mae2 = '1' then
+        state2 <= IDLE;
+    elsif rising_edge(clk_div2_out) then
+        case state2 is
+            when IDLE =>
+                read_en_o <= '0';   -- Disable read OUT
+                write_en_i <= '0';   -- Disable write IN
+                transit2 <= '1';
+                if transit1 = '0' and PA2_I = '0' then
+                    state2 <= WRITE_IN;
+				else
+					state2 <= IDLE;
+                end if;
+
+            when WRITE_IN =>
+                read_en_o <= '1';    -- Enable read OUT
+                write_en_i <= '1';    -- Enable write IN
+                if PA2_I = '1' then
+                    state2 <= DELAY;  -- Change state to DELAY
+                else
+                    state2 <= WRITE_IN;  -- Stay in WRITE_IN state
+                end if;
+
+            when DELAY =>
+                transit2 <= '0'; -- Enable READ IN
+                if empty_o = '1' then
+						  read_en_o <= '0';    -- Disable read OUT
+						  write_en_i <= '0';    -- Disable write IN
+                    state2 <= IDLE; -- Change state to IDLE
+                else
+                    state2 <= DELAY;  -- Stay in READ_IN state
+                end if;
+
+            when others =>
+                state2 <= IDLE;
+        end case;
+    end if;
 end process;
 
---Points de test:
-FTP(0) <= SDA;
-FTP(1) <= SCL;
-FTP(2) <= not(SO_SDA_IN);
-FTP(3) <= SDA_DIR;
-FTP(5) <= SRST;
-FTP(4) <= SI_TDO;
-FTP(6) <= '1';
-FTP(7) <= '1';
-
-end A_S609;
+process(IFCLK_I, reset_mae)
+begin
+    if reset_mae = '1' then
+        state <= IDLE;
+    elsif rising_edge(IFCLK_I) then
+        case state is
+            when IDLE =>
+                wr_o <= '1';   -- Disable write OUT
+                rd_i <= '1';    -- Disable read IN
+                transit1 <= '1';
+                if PA2_I = '0' then
+                    state <= WRITE_OUT;    -- Change state to RESET
+                else
+                    state <= IDLE; -- Stay in IDLE state
+                end if;
+
+            when WRITE_OUT =>
+                wr_o <= '0';   -- Enable write OUT
+                if empty_o = '0' then
+                    transit1 <= '0'; -- Enable Rd OUT & Wr IN
+                    state <= DELAY; -- Change state to DELAY
+                else
+                    state <= WRITE_OUT;    -- Stay in WRITE_OUT state
+                end if;
+
+            when DELAY =>
+                if transit2 = '0' then
+                    wr_o <= '1';   -- Disable write OUT
+                    state <= READ_IN;
+                else
+                    state <= DELAY;
+                end if;
+
+            when READ_IN =>
+                rd_i <= '0';    -- Enable read IN
+                if empty_i = '1' then
+                    rd_i <= '1';    -- Enable read IN
+                    state <= IDLE; -- Change state to IDLE
+                else
+                    state <= READ_IN;  -- Stay in READ_IN state
+                end if;
+
+            when others =>
+                state <= IDLE;
+        end case;
+    end if;
+end process;
+
+-- OUT signals direction
+-- TRST, TMS, TCK and TDI : out
+ST_0_O <= '0';
+-- TDO : in
+ST_1_O <= '1';
+-- SRST : out
+ST_2_O <= srst_q;
+srst_d <= data_out_o(6);
+SO_SRST_O <= '0';
+-- MOD : in
+ST_3_O <= '1';
+
+end A_angie_bitstream;
diff --git a/contrib/firmware/angie/hdl/src/clk_div.vhd b/contrib/firmware/angie/hdl/src/clk_div.vhd
new file mode 100644
index 000000000..e69850d57
--- /dev/null
+++ b/contrib/firmware/angie/hdl/src/clk_div.vhd
@@ -0,0 +1,33 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+entity clk_div is
+    Port (
+        clk_in : in  std_logic;
+        reset : in std_logic;
+        clk_out : out std_logic
+    );
+end clk_div;
+
+architecture behavioral of clk_div is
+    -- Division factor N = 4, so we need a 2-bit counter (2^2 = 4)
+--    signal counter : unsigned(1 downto 0) := (others => '0');
+    signal tmp : std_logic;
+begin
+    process(clk_in, reset)
+    begin
+        if reset = '1' then
+--            counter <= (others => '0');
+            tmp <= '0';
+        elsif rising_edge(clk_in) then
+--            if counter = (2**2 - 1) then
+--                counter <= (others => '0');
+            tmp <= NOT tmp; -- Toggle the output clock
+--            else
+--                counter <= counter + 1;
+--            end if;
+        end if;
+    end process;
+    clk_out <= tmp;
+end behavioral;
\ No newline at end of file
diff --git a/contrib/firmware/angie/hdl/src/dff.vhd b/contrib/firmware/angie/hdl/src/dff.vhd
new file mode 100644
index 000000000..c5ccf06d3
--- /dev/null
+++ b/contrib/firmware/angie/hdl/src/dff.vhd
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_arith.ALL;
+use ieee.std_logic_unsigned.ALL;
+
+entity DFF is
+port (  clk : in std_logic;
+        reset : in std_logic;
+        d : in std_logic;
+        q : out std_logic);
+end DFF;
+
+architecture Behavioral of DFF is
+begin
+    process(clk, reset)
+    begin
+        if reset = '1' then
+            q <= '1'; -- Reset output to 0
+        elsif rising_edge(clk) then
+            q <= d; -- Capture D at the rising edge of the clock
+        end if;
+    end process;
+end Behavioral;
\ No newline at end of file
diff --git a/src/jtag/drivers/angie/angie_bitstream.bit b/src/jtag/drivers/angie/angie_bitstream.bit
index 7b3a88f7c..fb1c73497 100644
Binary files a/src/jtag/drivers/angie/angie_bitstream.bit and b/src/jtag/drivers/angie/angie_bitstream.bit differ

commit 2f1a0ab35f28655119c743a2913b773a350c6137
Author: Ahmed BOUDJELIDA <abo...@na...>
Date:   Thu Dec 12 09:36:10 2024 +0100

    contrib/firmware/angie: add GPIF configuration of ANGIE
    
    We make the proper GPIF configurations for OUT/IN transfers
    which are : the GPIF state machines for each direction OUT/IN
    
    We change the Vendor-commands to handle GPIF config before
    triggering it.
    
    Change-Id: I2f3bd7bed1a378536bf017336b5031683d93e3c1
    Signed-off-by: Ahmed BOUDJELIDA <abo...@na...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8713
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/contrib/firmware/angie/c/src/gpif.c b/contrib/firmware/angie/c/src/gpif.c
index f4028be40..0e0d01300 100644
--- a/contrib/firmware/angie/c/src/gpif.c
+++ b/contrib/firmware/angie/c/src/gpif.c
@@ -19,15 +19,15 @@ const char wavedata[128] = {
 /* Output*/ 0x04,     0x07,     0x07,     0x07,     0x07,     0x07,     0x07,     0x07,
 /* LFun  */ 0x00,     0x09,     0x00,     0x00,     0x00,     0x00,     0x00,     0x3F,
 // Wave 1
-/* LenBr */ 0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x07,
-/* Opcode*/ 0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,
-/* Output*/ 0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,
-/* LFun  */ 0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x3F,
+/* LenBr */ 0x01,     0x3F,     0x01,     0x01,     0x01,     0x01,     0x01,     0x07,
+/* Opcode*/ 0x02,     0x07,     0x02,     0x02,     0x02,     0x02,     0x02,     0x00,
+/* Output*/ 0x00,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,
+/* LFun  */ 0x00,     0x09,     0x00,     0x00,     0x00,     0x00,     0x00,     0x3F,
 // Wave 2
-/* LenBr */ 0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x07,
-/* Opcode*/ 0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,
-/* Output*/ 0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,
-/* LFun  */ 0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x3F,
+/* LenBr */ 0x01,     0xBF,     0x01,     0x01,     0x01,     0x01,     0x01,     0x07,
+/* Opcode*/ 0x06,     0x05,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,
+/* Output*/ 0x00,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,
+/* LFun  */ 0x00,     0x09,     0x00,     0x00,     0x00,     0x00,     0x00,     0x3F,
 // Wave 3
 /* LenBr */ 0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x01,     0x07,
 /* Opcode*/ 0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,     0x00,
@@ -47,7 +47,7 @@ const char flowstates[36] = {
 
 /* DO NOT EDIT ... */
 const char initdata[7] = {
-/* Regs  */ 0xE0, 0x00, 0x00, 0x07, 0xEE, 0xF2, 0x00
+/* Regs  */ 0xE0, 0x00, 0x00, 0x03, 0xEE, 0xF1, 0x00
 };
 /* END DO NOT EDIT */
 
diff --git a/contrib/firmware/angie/c/src/main.c b/contrib/firmware/angie/c/src/main.c
index 9290af2ab..042a1eca7 100644
--- a/contrib/firmware/angie/c/src/main.c
+++ b/contrib/firmware/angie/c/src/main.c
@@ -12,7 +12,6 @@
 
 #include "usb.h"
 #include "delay.h"
-#include "protocol.h"
 #include "reg_ezusb.h"
 #include <serial.h>
 #include <stdio.h>
@@ -65,7 +64,7 @@ void gpif_init(void);
 int main(void)
 {
 	CPUCS = ((CPUCS & ~bmclkspd) | (CLK_48M << 3) | CLKOE);	/* required for sio0_init */
-	sio0_init(57600);	/* needed for printf */
+	sio0_init(115200);	/* needed for printf */
 
 	ep_init();
 	gpif_init();
@@ -74,12 +73,10 @@ int main(void)
 
 	/* Perform ReNumeration */
 	USBCS |= (DISCON | RENUM);
-	delay_ms(250);
+	delay_ms(50);
 	USBCS &= ~DISCON;
 
-	/* Begin executing command(s). This function never returns. */
-	command_loop();
-
-	/* Never reached, but SDCC complains about missing return statement */
-	return 0;
+	/* stay here */
+	while (1)
+		;
 }
diff --git a/contrib/firmware/angie/c/src/usb.c b/contrib/firmware/angie/c/src/usb.c
index 35f011f4e..f3bc99ba1 100644
--- a/contrib/firmware/angie/c/src/usb.c
+++ b/contrib/firmware/angie/c/src/usb.c
@@ -11,14 +11,16 @@
 *****************************************************************************/
 
 #include "usb.h"
-#include "stdint.h"
 #include "delay.h"
 #include "io.h"
 #include "reg_ezusb.h"
-#include <fx2macros.h>
-#include <serial.h>
-#include <stdio.h>
+#include "fx2macros.h"
+#include "serial.h"
 #include "i2c.h"
+#include <stdint.h>
+#include <stdio.h>
+
+// #define PRINTF_DEBUG
 
 volatile __xdata __at 0xE6B8 struct setup_data setup_data;
 
@@ -27,7 +29,6 @@ volatile __xdata __at 0xE6B8 struct setup_data setup_data;
  */
 #define NUM_ENDPOINTS 2
 
-
 __code struct usb_device_descriptor device_descriptor = {
 	.blength =				sizeof(struct usb_device_descriptor),
 	.bdescriptortype =		DESCRIPTOR_TYPE_DEVICE,
@@ -543,14 +544,14 @@ void set_gpif_cnt(uint32_t count)
  * Vendor commands handling:
 */
 #define VR_CFGOPEN		0xB0
-#define VR_CFGCLOSE		0xB1
+#define VR_DATAOUTOPEN	0xB2
 
 uint8_t	ix;
 uint8_t bcnt;
 uint8_t __xdata *eptr;
 uint16_t wcnt;
 uint32_t __xdata gcnt;
-bool usb_handle_send_bitstream(void)
+bool usb_handle_vcommands(void)
 {
 	eptr = EP0BUF;						/* points to EP0BUF 64-byte register */
 	wcnt = setup_data.wlength;			/* total transfer count */
@@ -574,43 +575,63 @@ bool usb_handle_send_bitstream(void)
 		/* Angie board FPGA bitstream download */
 		switch ((setup_data.wvalue) & 0x00C0) {
 		case 0x00:
-			PIN_PROGRAM_B = 0;		/* Apply RPGM- pulse */
-			GPIFWFSELECT = 0xF2;	/* Restore Config mode waveforms select */
-			syncdelay(3);
-			EP2FIFOCFG = BMAUTOOUT;	/* and Automatic 8-bit GPIF OUT mode */
-			syncdelay(3);
-			PIN_PROGRAM_B = 1;		/* Negate RPGM- pulse */
-			delay_ms(10);			/* FPGA init time < 10mS */
-			set_gpif_cnt(gcnt);		/* Initialize GPIF interface transfer count */
+			/* Apply RPGM- pulse */
+			PIN_PROGRAM_B = 0;
+			syncdelay(1);
+			/* Negate RPGM- pulse */
+			PIN_PROGRAM_B = 1;
+			/* FPGA init time < 10mS */
+			delay_ms(10);
+			/* Initialize GPIF interface transfer count */
+			set_gpif_cnt(gcnt);
 			PIN_RDWR_B = 0;
-			PIN_CSI_B = 0;
-			GPIFTRIG = GPIF_EP2;	/* Trigger GPIF OUT transfer on EP2 */
-			syncdelay(3);
+			PIN_SDA = 0;
+			/* Trigger GPIF OUT transfer on EP2 */
+			GPIFTRIG = GPIF_EP2;
+			while (!(GPIFTRIG & BMGPIFDONE)) // poll GPIFTRIG.7 GPIF Done bit
+				;
+			PIN_SDA = 1;
+			PIN_RDWR_B = 1;
+			#ifdef PRINTF_DEBUG
+			printf("Program SP6 Done.\n");
+			#endif
+			/* Choose wich Waveform to use */
+			GPIFWFSELECT = 0xF6;
 			break;
 		default:
 			break;
 		}
 		break;
-	case VR_CFGCLOSE:
-		ix = 10;
-		/* wait until GPIF transaction has been completed */
-		while ((GPIFTRIG & BMGPIFDONE) == 0) {
-			if (ix-- == 0) {
-				break;
-			}
-			delay_ms(1);
-		}
-		switch ((setup_data.wvalue) & 0x00C0) {
-			case 0x00:
-				PIN_CSI_B = 1;
-				PIN_RDWR_B = 1;
-				IFCONFIG &= 0xFC; /* Exit gpif mode */
-				break;
-			default:
-				break;
-		}
+	case VR_DATAOUTOPEN:
+		/* Clear bytecount / to allow new data in / to stops NAKing */
 		EP0BCH = 0;
-		EP0BCL = (uint8_t)(setup_data.wlength);	/* Signal buffer is filled */
+		EP0BCL = 0;
+		while (EP0CS & EPBSY)
+			; /* wait to finish transferring in EP0BUF, until not busy */
+		gcnt  = ((uint32_t)(eptr[0]) << 24) | ((uint32_t)(eptr[1]) << 16)
+		| ((uint32_t)(eptr[2]) << 8) | (uint32_t)(eptr[3]);
+		/* Angie board FPGA bitstream download */
+		PIN_RDWR_B = 0;
+		/* Initialize GPIF interface transfer count */
+		GPIFTCB3 = (uint8_t)(((uint32_t)(gcnt) >> 24) & 0x000000ff);
+		GPIFTCB2 = (uint8_t)(((uint32_t)(gcnt) >> 16) & 0x000000ff);
+		GPIFTCB1 = (uint8_t)(((uint32_t)(gcnt) >> 8) & 0x000000ff);
+		GPIFTCB0 = (uint8_t)((uint32_t)(gcnt) & 0x000000ff);
+		/* Trigger GPIF OUT transfer on EP2 */
+		GPIFTRIG = GPIF_EP2;
+		while (!(GPIFTRIG & BMGPIFDONE)) // poll GPIFTRIG.7 GPIF Done bit
+			;
+		PIN_RDWR_B = 1;
+		/* Initialize GPIF interface transfer count */
+		GPIFTCB3 = (uint8_t)(((uint32_t)(gcnt) >> 24) & 0x000000ff);
+		GPIFTCB2 = (uint8_t)(((uint32_t)(gcnt) >> 16) & 0x000000ff);
+		GPIFTCB1 = (uint8_t)(((uint32_t)(gcnt) >> 8) & 0x000000ff);
+		GPIFTCB0 = (uint8_t)((uint32_t)(gcnt) & 0x000000ff);
+		/* Initialize AUTOIN transfer count */
+		EP4AUTOINLENH = (uint8_t)(((uint32_t)(gcnt) >> 8) & 0x000000ff);
+		EP4AUTOINLENL = (uint8_t)((uint32_t)(gcnt) & 0x000000ff);
+		/* Trigger GPIF IN transfer on EP4 */
+		GPIFTRIG = BMGPIFREAD | GPIF_EP4;
 		break;
 	default:
 		return true;	/* Error: unknown VR command */
@@ -677,7 +698,7 @@ void usb_handle_setup_data(void)
 		break;
 	default:
 		/* if not Vendor command, Stall EndPoint 0 */
-		if (usb_handle_send_bitstream())
+		if (usb_handle_vcommands())
 			STALL_EP0();
 		break;
 	}

-----------------------------------------------------------------------

Summary of changes:
 contrib/firmware/angie/c/src/gpif.c                |  18 +-
 contrib/firmware/angie/c/src/main.c                |  13 +-
 contrib/firmware/angie/c/src/usb.c                 |  97 +++--
 contrib/firmware/angie/hdl/src/angie_bitstream.ucf | 106 +++--
 contrib/firmware/angie/hdl/src/angie_bitstream.vhd | 481 +++++++++++++++++----
 contrib/firmware/angie/hdl/src/clk_div.vhd         |  33 ++
 contrib/firmware/angie/hdl/src/dff.vhd             |  23 +
 src/jtag/drivers/angie/angie_bitstream.bit         | Bin 340704 -> 340721 bytes
 8 files changed, 597 insertions(+), 174 deletions(-)
 create mode 100644 contrib/firmware/angie/hdl/src/clk_div.vhd
 create mode 100644 contrib/firmware/angie/hdl/src/dff.vhd


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1133-g663d97b38

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  663d97b38550bf0aba42005912822bff713caeda (commit)
      from  fb7e394dddb16f1b85d0afcaedba77a50c7ea742 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 663d97b38550bf0aba42005912822bff713caeda
Author: Ahmed BOUDJELIDA <abo...@na...>
Date:   Thu Dec 12 09:44:41 2024 +0100

    contrib/firmware/angie: Change ANGIE IOs configuration
    
    We disconnect port B and D which are going to be used by GPIF
    module.
    
    Change-Id: Iffaccbb43ded4b2e0b37f5ee1cc7509e90b0f3d4
    Signed-off-by: Ahmed BOUDJELIDA <abo...@na...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8714
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/contrib/firmware/angie/c/Makefile b/contrib/firmware/angie/c/Makefile
index 1bcc1f7d1..21873da6b 100644
--- a/contrib/firmware/angie/c/Makefile
+++ b/contrib/firmware/angie/c/Makefile
@@ -38,10 +38,8 @@ LDFLAGS = --code-loc 0x0000 --code-size $(CODE_SIZE) --xram-loc $(XRAM_LOC) \
           --xram-size $(XRAM_SIZE) --iram-size 256 --model-small
 
 # list of base object files
-OBJECTS = main.rel usb.rel protocol.rel jtag.rel delay.rel USBJmpTb.rel serial.rel gpif.rel i2c.rel
+OBJECTS = main.rel usb.rel delay.rel USBJmpTb.rel gpif.rel i2c.rel serial.rel
 HEADERS = $(INCLUDE_DIR)/usb.h          \
-          $(INCLUDE_DIR)/protocol.h     \
-          $(INCLUDE_DIR)/jtag.h         \
           $(INCLUDE_DIR)/delay.h        \
           $(INCLUDE_DIR)/reg_ezusb.h    \
           $(INCLUDE_DIR)/io.h           \
diff --git a/contrib/firmware/angie/c/include/io.h b/contrib/firmware/angie/c/include/io.h
index 19289d11d..447aec3b4 100644
--- a/contrib/firmware/angie/c/include/io.h
+++ b/contrib/firmware/angie/c/include/io.h
@@ -14,44 +14,26 @@
 
 #include "reg_ezusb.h"
 
-/***************************************************************************
- *  JTAG Signals:                                                          *
- ***************************************************************************
- * TMS ....... Test Mode Select                                            *
- * TCK ....... Test Clock                                                  *
- * TDI ....... Test Data Input  (from device point of view, not JTAG       *
- *             adapter point of view!)                                     *
- * TDO ....... Test Data Output (from device point of view, not JTAG       *
- *             adapter point of view!)                                     *
- * TRST ...... Test Reset: Used to reset the TAP Finite State Machine      *
- *             into the Test Logic Reset state                             *
- * SRST .....  Chip Reset                                                  *
- ***************************************************************************/
-
 /* PORT A */
-/* PA0 Not Connected */
+#define PIN_SDA_DIR     IOA0
 /* PA1 Not Connected */
-#define PIN_RDWR_B        IOA2
-#define PIN_CSI_B         IOA3
-#define PIN_INIT_B        IOA4
-#define PIN_PROGRAM_B     IOA5
+#define PIN_RDWR_B      IOA2
+#define PIN_SDA         IOA3
+#define PIN_SCL         IOA4
+#define PIN_PROGRAM_B   IOA5
 /* PA6 Not Connected */
 /* PA7 Not Connected */
 
 /* PORT B */
-#define PIN_TRST      IOB0
-#define PIN_TMS       IOB1
-#define PIN_TCK       IOB2
-#define PIN_TDI       IOB3
-#define PIN_TDO       IOB4
-#define PIN_SRST      IOB5
+/* PB0 Not Connected */
+/* PB1 Not Connected */
+/* PB2 Not Connected */
+/* PB3 Not Connected */
+/* PB4 Not Connected */
+/* PB5 Not Connected */
 /* PB6 Not Connected */
 /* PB7 Not Connected */
 
-/* JTAG Signals with direction 'OUT' on port B */
-/* PIN_TDI - PIN_TCK - PIN_TMS - PIN_TRST - PIN_SRST */
-#define MASK_PORTB_DIRECTION_OUT (bmbit0 | bmbit1 | bmbit2 | bmbit3 | bmbit5)
-
 /* PORT C */
 #define PIN_T0      IOC0
 #define PIN_T1      IOC1
@@ -63,10 +45,10 @@
 /* PC7 Not Connected */
 
 /* PORT D */
-#define PIN_SDA         IOD0
-#define PIN_SCL         IOD1
-#define PIN_SDA_DIR     IOD2
-#define PIN_SCL_DIR     IOD3
+/* PD0 Not Connected */
+/* PD1 Not Connected */
+/* PD2 Not Connected */
+/* PD3 Not Connected */
 /* PD4 Not Connected */
 /* PD5 Not Connected */
 /* PD6 Not Connected */
diff --git a/contrib/firmware/angie/c/include/reg_ezusb.h b/contrib/firmware/angie/c/include/reg_ezusb.h
index c22476a1a..735ccaa8a 100644
--- a/contrib/firmware/angie/c/include/reg_ezusb.h
+++ b/contrib/firmware/angie/c/include/reg_ezusb.h
@@ -634,10 +634,10 @@ SFRX(CT4,              0xE6FE);
 SFRX(EP0BUF[64],        0xE740);
 SFRX(EP1INBUF[64],      0xE7C0);
 SFRX(EP1OUTBUF[64],     0xE780);
-SFRX(EP2FIFOBUF[512],   0xF000);
-SFRX(EP4FIFOBUF[512],   0xF400);
-SFRX(EP6FIFOBUF[512],   0xF800);
-SFRX(EP8FIFOBUF[512],   0xFC00);
+SFRX(EP2FIFOBUF[1024],   0xF000);
+SFRX(EP4FIFOBUF[1024],   0xF400);
+SFRX(EP6FIFOBUF[1024],   0xF800);
+SFRX(EP8FIFOBUF[1024],   0xFC00);
 
 /* Error Correction Code (ECC) Registers (FX2LP/FX1 only) */
 SFRX(ECCCFG,            0xE628);
diff --git a/contrib/firmware/angie/c/include/usb.h b/contrib/firmware/angie/c/include/usb.h
index ad8be787e..37d3b8ae2 100644
--- a/contrib/firmware/angie/c/include/usb.h
+++ b/contrib/firmware/angie/c/include/usb.h
@@ -125,12 +125,6 @@ struct setup_data {
 	uint16_t wlength;		/**< Number of bytes to transfer in data stage. */
 };
 
-/* External declarations for variables that need to be accessed outside of
- * the USB module */
-extern volatile bool ep1_out;
-extern volatile bool ep1_in;
-extern volatile bool ep6_out;
-
 extern volatile __xdata __at 0xE6B8 struct setup_data setup_data;
 
 /*
@@ -278,8 +272,8 @@ bool usb_handle_set_feature(void);
 bool usb_handle_get_descriptor(void);
 void usb_handle_set_interface(void);
 void usb_handle_setup_data(void);
-void usb_handle_i2c_in(void);
-void usb_handle_i2c_out(void);
+bool usb_handle_vcommands(void);
+void set_gpif_cnt(uint32_t count);
 
 void i2c_recieve(void);
 void ep_init(void);
diff --git a/contrib/firmware/angie/c/src/i2c.c b/contrib/firmware/angie/c/src/i2c.c
index 10a463bf7..9aadc2c25 100644
--- a/contrib/firmware/angie/c/src/i2c.c
+++ b/contrib/firmware/angie/c/src/i2c.c
@@ -14,12 +14,11 @@
 
 void start_cd(void)
 {
-	PIN_SCL_DIR = 0;
-	PIN_SDA_DIR = 0;
+	PIN_SDA_DIR = 0;    // SP6 SDA: OUT
 	delay_us(10);
-	PIN_SDA = 0; //SDA = 1;
+	PIN_SDA = 0;
 	delay_us(1);
-	PIN_SCL = 0; //SCL = 1;
+	PIN_SCL = 0;
 	delay_us(1);
 }
 
@@ -43,9 +42,7 @@ void stop_cd(void)
 	delay_us(1);
 	PIN_SDA = 1;
 	delay_us(1);
-	PIN_SDA_DIR = 1;
-	delay_us(1);
-	PIN_SCL_DIR = 1;
+	PIN_SDA_DIR = 1;    // SP6 SDA: IN
 	delay_us(1);
 }
 
@@ -79,16 +76,16 @@ void send_nack(void)
 
 bool get_ack(void)
 {
-	PIN_SDA_DIR = 1;
+	PIN_SDA_DIR = 1;    // SP6 SDA: IN
 	delay_us(1);
-	OED = 0xFE;
+	OEA = 0xF7;         // FX2 SDA: IN
 	PIN_SCL = 1;
 	delay_us(1);
 	bool ack = PIN_SDA;
 	PIN_SCL = 0;
 	delay_us(1);
-	OED = 0xFF;
-	PIN_SDA_DIR = 0;
+	OEA = 0xFF;         // FX2 SDA: OUT
+	PIN_SDA_DIR = 0;    // SP6 SDA: OUT
 	delay_us(1);
 	return ack;
 }
@@ -123,8 +120,8 @@ void send_byte(uint8_t input)
 
 uint8_t receive_byte(void)
 {
-	PIN_SDA_DIR = 1;    //FX2 <-- FPGA
-	OED = 0xFE;
+	PIN_SDA_DIR = 1;    // SP6 SDA: IN
+	OEA = 0xF7;         // FX2 SDA: IN
 	uint8_t input = 0x00;
 	for (uint8_t i = 0; i < 8; i++) {
 		PIN_SCL = 1;
@@ -138,7 +135,7 @@ uint8_t receive_byte(void)
 		PIN_SCL = 0;
 		delay_us(1);
 	}
-	OED = 0xFF;
-	PIN_SDA_DIR = 0;
+	OEA = 0xFF;         // FX2 SDA: OUT
+	PIN_SDA_DIR = 0;    // SP6 SDA: OUT
 	return input;
 }

-----------------------------------------------------------------------

Summary of changes:
 contrib/firmware/angie/c/Makefile            |  4 +--
 contrib/firmware/angie/c/include/io.h        | 48 +++++++++-------------------
 contrib/firmware/angie/c/include/reg_ezusb.h |  8 ++---
 contrib/firmware/angie/c/include/usb.h       | 10 ++----
 contrib/firmware/angie/c/src/i2c.c           | 27 +++++++---------
 5 files changed, 34 insertions(+), 63 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1132-gfb7e394dd

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  fb7e394dddb16f1b85d0afcaedba77a50c7ea742 (commit)
      from  9bad45995a5bf46dd37a038c351bd54b35c0f522 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit fb7e394dddb16f1b85d0afcaedba77a50c7ea742
Author: Ahmed BOUDJELIDA <abo...@na...>
Date:   Thu Dec 12 09:08:11 2024 +0100

    contrib/firmware/angie: reorganize the endpoints of the microcontroller
    
    The new firmware of ANGIE will not use Bitbang method to
    transfer jtag data to the target chip. instead, it will use the
    the GPIF module to bypass JTAG data directly to the FPGA and
    then to target chip.
    
    So we delete the protocol and jtag files which handle bitbang.
    
    We are going to use endpoint 2/4 for OUT/IN GPIF transactions,
    and we deactivate the endpoints 1IN and 1OUT.
    
    we will keep the endpoint 6/8 for i2c unchanged.
    
    Change-Id: I0fcb23690526f6a7da044b702217b32522be727a
    Signed-off-by: Ahmed BOUDJELIDA <abo...@na...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8712
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/contrib/firmware/angie/c/include/jtag.h b/contrib/firmware/angie/c/include/jtag.h
deleted file mode 100644
index 6d5df6480..000000000
--- a/contrib/firmware/angie/c/include/jtag.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/****************************************************************************
-	File : jtag.h															*
-	Contents : Jtag handling functions header file for NanoXplore			*
-	USB-JTAG ANGIE adapter hardware.										*
-	Based on openULINK project code by: Martin Schmoelzer.					*
-	Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.				*
-	<abo...@na...>											*
-	<ahm...@gm...>											*
-*****************************************************************************/
-
-#ifndef __JTAG_H
-#define __JTAG_H
-
-#include <stdint.h>
-
-uint16_t jtag_get_signals(void);
-void jtag_configure_tck_delay(uint8_t scan_in, uint8_t scan_out,
-	uint8_t scan_io, uint8_t tck, uint8_t tms);
-void jtag_clock_tms(uint8_t count, uint8_t sequence);
-void jtag_slow_clock_tms(uint8_t count, uint8_t sequence);
-void jtag_set_signals(uint8_t low, uint8_t high);
-void jtag_clock_tck(uint16_t count);
-void jtag_slow_clock_tck(uint16_t count);
-void jtag_scan_in(uint8_t out_offset, uint8_t in_offset);
-void jtag_scan_out(uint8_t out_offset);
-void jtag_scan_io(uint8_t out_offset, uint8_t in_offset);
-void jtag_slow_scan_in(uint8_t out_offset, uint8_t in_offset);
-void jtag_slow_scan_out(uint8_t out_offset);
-void jtag_slow_scan_io(uint8_t out_offset, uint8_t in_offset);
-#endif
diff --git a/contrib/firmware/angie/c/include/protocol.h b/contrib/firmware/angie/c/include/protocol.h
deleted file mode 100644
index a12644b27..000000000
--- a/contrib/firmware/angie/c/include/protocol.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/****************************************************************************
-    File : protocol.h                                                       *
-    Contents : Jtag commands handling protocol header file for NanoXplore   *
-    USB-JTAG ANGIE adapter hardware.                                        *
-    Based on openULINK project code by: Martin Schmoelzer.                  *
-    Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.              *
-    <abo...@na...>                                            *
-	<ahm...@gm...>											*
-*****************************************************************************/
-
-#ifndef __PROTOCOL_H
-#define __PROTOCOL_H
-
-#include <stdbool.h>
-
-bool execute_command(void);
-void command_loop(void);
-
-#endif
diff --git a/contrib/firmware/angie/c/src/jtag.c b/contrib/firmware/angie/c/src/jtag.c
deleted file mode 100644
index 9a44cd0bf..000000000
--- a/contrib/firmware/angie/c/src/jtag.c
+++ /dev/null
@@ -1,674 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/****************************************************************************
-	File : jtag.c															*
-	Contents : Jtag handling functions code for NanoXplore					*
-	USB-JTAG ANGIE adapter hardware.										*
-	Based on openULINK project code by: Martin Schmoelzer.					*
-	Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.				*
-	<abo...@na...>											*
-	<ahm...@gm...>											*
-*****************************************************************************/
-
-#include "jtag.h"
-#include "io.h"
-#include "msgtypes.h"
-#include "reg_ezusb.h"
-#include <stdbool.h>
-#include <serial.h>
-#include <stdio.h>
-
-/** Delay value for SCAN_IN operations with less than maximum TCK frequency */
-uint8_t delay_scan_in;
-
-/** Delay value for SCAN_OUT operations with less than maximum TCK frequency */
-uint8_t delay_scan_out;
-
-/** Delay value for SCAN_IO operations with less than maximum TCK frequency */
-uint8_t delay_scan_io;
-
-/** Delay value for CLOCK_TCK operations with less than maximum frequency */
-uint8_t delay_tck;
-
-/** Delay value for CLOCK_TMS operations with less than maximum frequency */
-uint8_t delay_tms;
-
-/**
- * Perform JTAG SCAN-IN operation at maximum TCK frequency.
- *
- * Dummy data is shifted into the JTAG chain via TDI, TDO data is sampled and
- * stored in the EP2 IN buffer.
- *
- * Maximum achievable TCK frequency is 182 kHz for ANGIE clocked at 24 MHz.
- *
- * @param out_offset offset in EP1OUTBUF where payload data starts
- * @param in_offset
- */
-void jtag_scan_in(uint8_t out_offset, uint8_t in_offset)
-{
-	uint8_t scan_size_bytes, bits_last_byte;
-	uint8_t tms_count_start, tms_count_end;
-	uint8_t tms_sequence_start, tms_sequence_end;
-	uint8_t tdo_data, i, j;
-
-	uint8_t outb_buffer;
-
-	/* Get parameters from EP1OUTBUF */
-	scan_size_bytes = EP1OUTBUF[out_offset];
-	bits_last_byte = EP1OUTBUF[out_offset + 1];
-	tms_count_start = (EP1OUTBUF[out_offset + 2] >> 4) & 0x0F;
-	tms_count_end = EP1OUTBUF[out_offset + 2] & 0x0F;
-	tms_sequence_start = EP1OUTBUF[out_offset + 3];
-	tms_sequence_end = EP1OUTBUF[out_offset + 4];
-
-	if (tms_count_start > 0)
-		jtag_clock_tms(tms_count_start, tms_sequence_start);
-
-	outb_buffer = IOB & ~(bmbit1 | bmbit2 | bmbit3);
-
-	/* Shift all bytes except the last byte */
-	for (i = 0; i < scan_size_bytes - 1; i++) {
-		tdo_data = 0;
-
-		for (j = 0; j < 8; j++) {
-			IOB = outb_buffer;	/* TCK changes here */
-			tdo_data = tdo_data >> 1;
-			IOB = (outb_buffer | bmbit2);
-
-			if (PIN_TDO)
-				tdo_data |= 0x80;
-		}
-
-		/* Copy TDO data to EP1INBUF */
-		EP1INBUF[i + in_offset] = tdo_data;
-	}
-	tdo_data = 0;
-
-	/* Shift the last byte */
-	for (j = 0; j < bits_last_byte; j++) {
-		/* Assert TMS signal if requested and this is the last bit */
-		if (j == (bits_last_byte - 1) && tms_count_end > 0) {
-			outb_buffer |= bmbit1;
-			tms_count_end--;
-			tms_sequence_end = tms_sequence_end >> 1;
-		}
-
-		IOB = outb_buffer;	/* TCK changes here */
-		tdo_data = tdo_data >> 1;
-		IOB = (outb_buffer | bmbit2);
-
-		if (PIN_TDO)
-			tdo_data |= 0x80;
-	}
-	tdo_data = tdo_data >> (8 - bits_last_byte);
-
-	/* Copy TDO data to EP1INBUF */
-	EP1INBUF[i + in_offset] = tdo_data;
-
-	/* Move to correct end state */
-	if (tms_count_end > 0)
-		jtag_clock_tms(tms_count_end, tms_sequence_end);
-}
-
-
-/**
- * Perform JTAG SCAN-IN operation at variable TCK frequency.
- *
- * Dummy data is shifted into the JTAG chain via TDI, TDO data is sampled and
- * stored in the EP2 IN buffer.
- *
- * Maximum achievable TCK frequency is 113 kHz for ANGIE clocked at 24 MHz.
- *
- * @param out_offset offset in EP1OUTBUF where payload data starts
- * @param in_offset
- */
-void jtag_slow_scan_in(uint8_t out_offset, uint8_t in_offset)
-{
-	uint8_t scan_size_bytes, bits_last_byte;
-	uint8_t tms_count_start, tms_count_end;
-	uint8_t tms_sequence_start, tms_sequence_end;
-	uint8_t tdo_data, i, j, k;
-	uint8_t outb_buffer;
-
-	/* Get parameters from EP1OUTBUF */
-	scan_size_bytes = EP1OUTBUF[out_offset];
-	bits_last_byte = EP1OUTBUF[out_offset + 1];
-	tms_count_start = (EP1OUTBUF[out_offset + 2] >> 4) & 0x0F;
-	tms_count_end = EP1OUTBUF[out_offset + 2] & 0x0F;
-	tms_sequence_start = EP1OUTBUF[out_offset + 3];
-	tms_sequence_end = EP1OUTBUF[out_offset + 4];
-
-	if (tms_count_start > 0)
-		jtag_slow_clock_tms(tms_count_start, tms_sequence_start);
-
-	outb_buffer = IOB & ~(bmbit3 | bmbit2 | bmbit1);
-
-	/* Shift all bytes except the last byte */
-	for (i = 0; i < scan_size_bytes - 1; i++) {
-		tdo_data = 0;
-
-		for (j = 0; j < 8; j++) {
-			IOB = outb_buffer;	/* TCK changes here */
-			for (k = 0; k < delay_scan_in; k++)
-				;
-			tdo_data = tdo_data >> 1;
-
-			IOB = (outb_buffer | bmbit2);
-			for (k = 0; k < delay_scan_in; k++)
-				;
-
-			if (PIN_TDO)
-				tdo_data |= 0x80;
-		}
-
-		/* Copy TDO data to EP1INBUF */
-		EP1INBUF[i + in_offset] = tdo_data;
-	}
-
-	tdo_data = 0;
-
-	/* Shift the last byte */
-	for (j = 0; j < bits_last_byte; j++) {
-		/* Assert TMS signal if requested and this is the last bit */
-		if (j == (bits_last_byte - 1) && tms_count_end > 0) {
-			outb_buffer |= bmbit1;
-			tms_count_end--;
-			tms_sequence_end = tms_sequence_end >> 1;
-		}
-
-		IOB = outb_buffer;	/* TCK changes here */
-		for (k = 0; k < delay_scan_in; k++)
-			;
-		tdo_data = tdo_data >> 1;
-
-		IOB = (outb_buffer | bmbit2);
-		for (k = 0; k < delay_scan_in; k++)
-			;
-
-		if (PIN_TDO)
-			tdo_data |= 0x80;
-	}
-	tdo_data = tdo_data >> (8 - bits_last_byte);
-
-	/* Copy TDO data to EP1INBUF */
-	EP1INBUF[i + in_offset] = tdo_data;
-
-	/* Move to correct end state */
-	if (tms_count_end > 0)
-		jtag_slow_clock_tms(tms_count_end, tms_sequence_end);
-}
-
-
-/**
- * Perform JTAG SCAN-OUT operation at maximum TCK frequency.
- *
- * Data stored in EP2 OUT buffer is shifted into the JTAG chain via TDI, TDO
- * data is not sampled.
- * The TAP-FSM state is always left in the PAUSE-DR/PAUSE-IR state.
- *
- * Maximum achievable TCK frequency is 142 kHz for ANGIE clocked at 24 MHz.
- *
- * @param out_offset offset in EP1OUTBUF where payload data starts
- */
-void jtag_scan_out(uint8_t out_offset)
-{
-	uint8_t scan_size_bytes, bits_last_byte;
-	uint8_t tms_count_start, tms_count_end;
-	uint8_t tms_sequence_start, tms_sequence_end;
-	uint8_t tdi_data, i, j;
-	uint8_t outb_buffer;
-
-	/* Get parameters from EP1OUTBUF */
-	scan_size_bytes = EP1OUTBUF[out_offset];
-	bits_last_byte = EP1OUTBUF[out_offset + 1];
-	tms_count_start = (EP1OUTBUF[out_offset + 2] >> 4) & 0x0F;
-	tms_count_end = EP1OUTBUF[out_offset + 2] & 0x0F;
-	tms_sequence_start = EP1OUTBUF[out_offset + 3];
-	tms_sequence_end = EP1OUTBUF[out_offset + 4];
-
-	if (tms_count_start > 0)
-		jtag_clock_tms(tms_count_start, tms_sequence_start);
-	outb_buffer = IOB & ~(bmbit2 | bmbit1);
-
-	/* Shift all bytes except the last byte */
-	for (i = 0; i < scan_size_bytes - 1; i++) {
-		tdi_data = EP1OUTBUF[i + out_offset + 5];
-
-		for (j = 0; j < 8; j++) {
-			if (tdi_data & 0x01)
-				outb_buffer |= bmbit3;
-			else
-				outb_buffer &= ~bmbit3;
-
-			IOB = outb_buffer;	/* TDI and TCK change here */
-			tdi_data = tdi_data >> 1;
-			IOB = (outb_buffer | bmbit2);
-		}
-	}
-	tdi_data = EP1OUTBUF[i + out_offset + 5];
-
-	/* Shift the last byte */
-	for (j = 0; j < bits_last_byte; j++) {
-		if (tdi_data & 0x01)
-			outb_buffer |= bmbit3;
-		else
-			outb_buffer &= ~bmbit3;
-
-		/* Assert TMS signal if requested and this is the last bit */
-		if (j == (bits_last_byte - 1) && tms_count_end > 0) {
-			outb_buffer |= bmbit1;
-			tms_count_end--;
-			tms_sequence_end = tms_sequence_end >> 1;
-		}
-		IOB = outb_buffer;	/* TDI and TCK change here */
-		tdi_data = tdi_data >> 1;
-		IOB = (outb_buffer | bmbit2);
-	}
-
-	/* Move to correct end state */
-	if (tms_count_end > 0)
-		jtag_clock_tms(tms_count_end, tms_sequence_end);
-}
-
-/**
- * Perform JTAG SCAN-OUT operation at maximum TCK frequency.
- *
- * Data stored in EP2 OUT buffer is shifted into the JTAG chain via TDI, TDO
- * data is not sampled.
- * The TAP-FSM state is always left in the PAUSE-DR/PAUSE-IR state.
- *
- * Maximum achievable TCK frequency is 97 kHz for ANGIE clocked at 24 MHz.
- *
- * @param out_offset offset in EP1OUTBUF where payload data starts
- */
-void jtag_slow_scan_out(uint8_t out_offset)
-{
-	uint8_t scan_size_bytes, bits_last_byte;
-	uint8_t tms_count_start, tms_count_end;
-	uint8_t tms_sequence_start, tms_sequence_end;
-	uint8_t tdi_data, i, j, k;
-	uint8_t outb_buffer;
-
-	/* Get parameters from EP1OUTBUF */
-	scan_size_bytes = EP1OUTBUF[out_offset];
-	bits_last_byte = EP1OUTBUF[out_offset + 1];
-	tms_count_start = (EP1OUTBUF[out_offset + 2] >> 4) & 0x0F;
-	tms_count_end = EP1OUTBUF[out_offset + 2] & 0x0F;
-	tms_sequence_start = EP1OUTBUF[out_offset + 3];
-	tms_sequence_end = EP1OUTBUF[out_offset + 4];
-
-	if (tms_count_start > 0)
-		jtag_slow_clock_tms(tms_count_start, tms_sequence_start);
-	outb_buffer = IOB & ~(bmbit2 | bmbit1);
-
-	/* Shift all bytes except the last byte */
-	for (i = 0; i < scan_size_bytes - 1; i++) {
-		tdi_data = EP1OUTBUF[i + out_offset + 5];
-
-		for (j = 0; j < 8; j++) {
-			if (tdi_data & 0x01)
-				outb_buffer |= bmbit3;
-			else
-				outb_buffer &= ~bmbit3;
-			IOB = outb_buffer;	/* TDI and TCK change here */
-			for (k = 0; k < delay_scan_out; k++)
-				;
-			tdi_data = tdi_data >> 1;
-			IOB = (outb_buffer | bmbit2);
-			for (k = 0; k < delay_scan_out; k++)
-				;
-		}
-	}
-	tdi_data = EP1OUTBUF[i + out_offset + 5];
-
-	/* Shift the last byte */
-	for (j = 0; j < bits_last_byte; j++) {
-		if (tdi_data & 0x01)
-			outb_buffer |= bmbit3;
-		else
-			outb_buffer &= ~bmbit3;
-
-		/* Assert TMS signal if requested and this is the last bit */
-		if (j == (bits_last_byte - 1) && tms_count_end > 0) {
-			outb_buffer |= bmbit1;
-			tms_count_end--;
-			tms_sequence_end = tms_sequence_end >> 1;
-		}
-		IOB = outb_buffer;	/* TDI and TCK change here */
-		for (k = 0; k < delay_scan_out; k++)
-			;
-		tdi_data = tdi_data >> 1;
-		IOB = (outb_buffer | bmbit2);
-		for (k = 0; k < delay_scan_out; k++)
-			;
-	}
-
-	/* Move to correct end state */
-	if (tms_count_end > 0)
-		jtag_slow_clock_tms(tms_count_end, tms_sequence_end);
-}
-
-
-/**
- * Perform bidirectional JTAG SCAN operation at maximum TCK frequency.
- *
- * Data stored in EP2 OUT buffer is shifted into the JTAG chain via TDI, TDO
- * data is sampled and stored in the EP2 IN buffer.
- * The TAP-FSM state is always left in the PAUSE-DR/PAUSE-IR state.
- *
- * Maximum achievable TCK frequency is 100 kHz for ANGIE clocked at 24 MHz.
- *
- * @param out_offset offset in EP1OUTBUF where payload data starts
- * @param in_offset
- */
-int it;
-void jtag_scan_io(uint8_t out_offset, uint8_t in_offset)
-{
-	uint8_t scan_size_bytes, bits_last_byte;
-	uint8_t tms_count_start, tms_count_end;
-	uint8_t tms_sequence_start, tms_sequence_end;
-	uint8_t tdi_data, tdo_data, i, j;
-	uint8_t outb_buffer;
-
-	it++;
-	/* Get parameters from EP1OUTBUF */
-	scan_size_bytes = EP1OUTBUF[out_offset];
-	bits_last_byte = EP1OUTBUF[out_offset + 1];
-	tms_count_start = (EP1OUTBUF[out_offset + 2] >> 4) & 0x0F;
-	tms_count_end = EP1OUTBUF[out_offset + 2] & 0x0F;
-	tms_sequence_start = EP1OUTBUF[out_offset + 3];
-	tms_sequence_end = EP1OUTBUF[out_offset + 4];
-
-	if (tms_count_start > 0)
-		jtag_clock_tms(tms_count_start, tms_sequence_start);
-	outb_buffer = IOB & ~(bmbit2 | bmbit1);
-
-	/* Shift all bytes except the last byte */
-	for (i = 0; i < scan_size_bytes - 1; i++) {
-		tdi_data = EP1OUTBUF[i + out_offset + 5];
-		tdo_data = 0;
-		for (j = 0; j < 8; j++) {
-			if (tdi_data & 0x01)
-				outb_buffer |= bmbit3;
-			else
-				outb_buffer &= ~bmbit3;
-			IOB = outb_buffer;	/* TDI and TCK change here */
-			tdi_data = tdi_data >> 1;
-			IOB = (outb_buffer | bmbit2);
-			tdo_data = tdo_data >> 1;
-			if (PIN_TDO)
-				tdo_data |= 0x80;
-		}
-
-		/* Copy TDO data to EP1INBUF */
-		EP1INBUF[i + in_offset] = tdo_data;
-	}
-	tdi_data = EP1OUTBUF[i + out_offset + 5];
-	tdo_data = 0;
-
-	/* Shift the last byte */
-	for (j = 0; j < bits_last_byte; j++) {
-		if (tdi_data & 0x01)
-			outb_buffer |= bmbit3;
-		else
-			outb_buffer &= ~bmbit3;
-
-		/* Assert TMS signal if requested and this is the last bit */
-		if (j == (bits_last_byte - 1) && tms_count_end > 0) {
-			outb_buffer |= bmbit1;
-			tms_count_end--;
-			tms_sequence_end = tms_sequence_end >> 1;
-		}
-		IOB = outb_buffer;	/* TDI and TCK change here */
-		tdi_data = tdi_data >> 1;
-		IOB = (outb_buffer | bmbit2);
-		tdo_data = tdo_data >> 1;
-		if (PIN_TDO)
-			tdo_data |= 0x80;
-	}
-	tdo_data = tdo_data >> (8 - bits_last_byte);
-
-	/* Copy TDO data to EP1INBUF */
-	EP1INBUF[i + in_offset] = tdo_data;
-
-	/* Move to correct end state */
-	if (tms_count_end > 0)
-		jtag_clock_tms(tms_count_end, tms_sequence_end);
-}
-
-/**
- * Perform bidirectional JTAG SCAN operation at maximum TCK frequency.
- *
- * Data stored in EP2 OUT buffer is shifted into the JTAG chain via TDI, TDO
- * data is sampled and stored in the EP2 IN buffer.
- * The TAP-FSM state is always left in the PAUSE-DR/PAUSE-IR state.
- *
- * Maximum achievable TCK frequency is 78 kHz for ANGIE clocked at 24 MHz.
- *
- * @param out_offset offset in EP1OUTBUF where payload data starts
- * @param in_offset
- */
-void jtag_slow_scan_io(uint8_t out_offset, uint8_t in_offset)
-{
-	uint8_t scan_size_bytes, bits_last_byte;
-	uint8_t tms_count_start, tms_count_end;
-	uint8_t tms_sequence_start, tms_sequence_end;
-	uint8_t tdi_data, tdo_data, i, j, k;
-	uint8_t outb_buffer;
-
-	/* Get parameters from EP1OUTBUF */
-	scan_size_bytes = EP1OUTBUF[out_offset];
-	bits_last_byte = EP1OUTBUF[out_offset + 1];
-	tms_count_start = (EP1OUTBUF[out_offset + 2] >> 4) & 0x0F;
-	tms_count_end = EP1OUTBUF[out_offset + 2] & 0x0F;
-	tms_sequence_start = EP1OUTBUF[out_offset + 3];
-	tms_sequence_end = EP1OUTBUF[out_offset + 4];
-
-	if (tms_count_start > 0)
-		jtag_slow_clock_tms(tms_count_start, tms_sequence_start);
-	outb_buffer = IOB & ~(bmbit2 | bmbit1);
-
-	/* Shift all bytes except the last byte */
-	for (i = 0; i < scan_size_bytes - 1; i++) {
-		tdi_data = EP1OUTBUF[i + out_offset + 5];
-		tdo_data = 0;
-		for (j = 0; j < 8; j++) {
-			if (tdi_data & 0x01)
-				outb_buffer |= bmbit3;
-			else
-				outb_buffer &= ~bmbit3;
-			IOB = outb_buffer;	/* TDI and TCK change here */
-			for (k = 0; k < delay_scan_io; k++)
-				;
-			tdi_data = tdi_data >> 1;
-			IOB = (outb_buffer | bmbit2);
-			for (k = 0; k < delay_scan_io; k++)
-				;
-			tdo_data = tdo_data >> 1;
-			if (PIN_TDO)
-				tdo_data |= 0x80;
-		}
-
-		/* Copy TDO data to EP1INBUF */
-		EP1INBUF[i + in_offset] = tdo_data;
-	}
-	tdi_data = EP1OUTBUF[i + out_offset + 5];
-	tdo_data = 0;
-
-	/* Shift the last byte */
-	for (j = 0; j < bits_last_byte; j++) {
-		if (tdi_data & 0x01)
-			outb_buffer |= bmbit3;
-		else
-			outb_buffer &= ~bmbit3;
-
-		/* Assert TMS signal if requested and this is the last bit */
-		if (j == (bits_last_byte - 1) && tms_count_end > 0) {
-			outb_buffer |= bmbit1;
-			tms_count_end--;
-			tms_sequence_end = tms_sequence_end >> 1;
-		}
-		IOB = outb_buffer;	/* TDI and TCK change here */
-		for (k = 0; k < delay_scan_io; k++)
-			;
-		tdi_data = tdi_data >> 1;
-		IOB = (outb_buffer | bmbit2);
-		for (k = 0; k < delay_scan_io; k++)
-			;
-		tdo_data = tdo_data >> 1;
-		if (PIN_TDO)
-			tdo_data |= 0x80;
-	}
-	tdo_data = tdo_data >> (8 - bits_last_byte);
-
-	/* Copy TDO data to EP1INBUF */
-	EP1INBUF[i + in_offset] = tdo_data;
-
-	/* Move to correct end state */
-	if (tms_count_end > 0)
-		jtag_slow_clock_tms(tms_count_end, tms_sequence_end);
-}
-
-/**
- * Generate TCK clock cycles.
- *
- * Maximum achievable TCK frequency is 375 kHz for ANGIE clocked at 24 MHz.
- *
- * @param count number of TCK clock cycles to generate.
- */
-void jtag_clock_tck(uint16_t count)
-{
-	uint16_t i;
-	uint8_t outb_buffer = IOB & ~(bmbit2);
-
-	for (i = 0; i < count; i++) {
-		IOB = outb_buffer;
-		IOB = outb_buffer | bmbit2;
-	}
-}
-
-/**
- * Generate TCK clock cycles at variable frequency.
- *
- * Maximum achievable TCK frequency is 166.6 kHz for ANGIE clocked at 24 MHz.
- *
- * @param count number of TCK clock cycles to generate.
- */
-void jtag_slow_clock_tck(uint16_t count)
-{
-	uint16_t i;
-	uint8_t j;
-	uint8_t outb_buffer = IOB & ~(bmbit2);
-
-	for (i = 0; i < count; i++) {
-		IOB = outb_buffer;
-		for (j = 0; j < delay_tck; j++)
-			;
-		IOB = outb_buffer | bmbit2;
-		for (j = 0; j < delay_tck; j++)
-			;
-	}
-}
-
-/**
- * Perform TAP FSM state transitions at maximum TCK frequency.
- *
- * Maximum achievable TCK frequency is 176 kHz for ANGIE clocked at 24 MHz.
- *
- * @param count the number of state transitions to perform.
- * @param sequence the TMS pin levels for each state transition, starting with
- *  the least-significant bit.
- */
-void jtag_clock_tms(uint8_t count, uint8_t sequence)
-{
-	uint8_t outb_buffer = IOB & ~(bmbit2);
-	uint8_t i;
-
-	for (i = 0; i < count; i++) {
-		/* Set TMS pin according to sequence parameter */
-		if (sequence & 0x1)
-			outb_buffer |= bmbit1;
-		else
-			outb_buffer &= ~bmbit1;
-		IOB = outb_buffer;
-		sequence = sequence >> 1;
-		IOB = outb_buffer | bmbit2;
-	}
-}
-
-/**
- * Perform TAP-FSM state transitions at less than maximum TCK frequency.
- *
- * Maximum achievable TCK frequency is 117 kHz for ANGIE clocked at 24 MHz.
- *
- * @param count the number of state transitions to perform.
- * @param sequence the TMS pin levels for each state transition, starting with
- *  the least-significant bit.
- */
-void jtag_slow_clock_tms(uint8_t count, uint8_t sequence)
-{
-	uint8_t outb_buffer = IOB & ~(bmbit2);
-	uint8_t i, j;
-
-	for (i = 0; i < count; i++) {
-		/* Set TMS pin according to sequence parameter */
-		if (sequence & 0x1)
-			outb_buffer |= bmbit1;
-		else
-			outb_buffer &= ~bmbit1;
-		IOB = outb_buffer;
-		for (j = 0; j < delay_tms; j++)
-			;
-		sequence = sequence >> 1;
-		IOB = outb_buffer | bmbit2;
-		for (j = 0; j < delay_tms; j++)
-			;
-	}
-}
-
-uint16_t jtag_get_signals(void)
-{
-	uint8_t input_signal_state, output_signal_state;
-	input_signal_state = 0;
-	output_signal_state = 0;
-
-	/* Get states of input pins */
-	if (PIN_TDO)
-		input_signal_state |= SIGNAL_TDO;
-
-	/* Get states of output pins */
-	output_signal_state = IOB & MASK_PORTB_DIRECTION_OUT;
-
-	return ((uint16_t)input_signal_state << 8) | ((uint16_t)output_signal_state);
-}
-
-/**
- * Set state of JTAG output signals.
- *
- * @param low signals which should be de-asserted.
- * @param high signals which should be asserted.
- */
-void jtag_set_signals(uint8_t low, uint8_t high)
-{
-	IOB &= ~(low & MASK_PORTB_DIRECTION_OUT);
-	IOB |= (high & MASK_PORTB_DIRECTION_OUT);
-}
-
-/**
- * Configure TCK delay parameters.
- *
- * @param scan_in number of delay cycles in scan_in operations.
- * @param scan_out number of delay cycles in scan_out operations.
- * @param scan_io number of delay cycles in scan_io operations.
- * @param tck number of delay cycles in clock_tck operations.
- * @param tms number of delay cycles in clock_tms operations.
- */
-void jtag_configure_tck_delay(uint8_t scan_in, uint8_t scan_out,
-	uint8_t scan_io, uint8_t tck, uint8_t tms)
-{
-	delay_scan_in = scan_in;
-	delay_scan_out = scan_out;
-	delay_scan_io = scan_io;
-	delay_tck = tck;
-	delay_tms = tms;
-}
diff --git a/contrib/firmware/angie/c/src/protocol.c b/contrib/firmware/angie/c/src/protocol.c
deleted file mode 100644
index e32808db8..000000000
--- a/contrib/firmware/angie/c/src/protocol.c
+++ /dev/null
@@ -1,192 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-
-/****************************************************************************
-	File : protocol.c														*
-	Contents : Jtag commands handling protocol code for NanoXplore			*
-	USB-JTAG ANGIE adapter hardware.										*
-	Based on openULINK project code by: Martin Schmoelzer.					*
-	Copyright 2023, Ahmed Errached BOUDJELIDA, NanoXplore SAS.				*
-	<abo...@na...>											*
-	<ahm...@gm...>											*
-*****************************************************************************/
-
-#include "usb.h"
-#include "protocol.h"
-#include "jtag.h"
-#include "delay.h"
-#include "io.h"
-#include "msgtypes.h"
-#include "reg_ezusb.h"
-#include <serial.h>
-#include <stdio.h>
-
-/** Index in EP1 Bulk-OUT data buffer that contains the current command ID */
-volatile uint8_t cmd_id_index;
-
-/** Number of data bytes already in EP1 Bulk-IN buffer */
-volatile uint8_t payload_index_in;
-
-/**
- * Executes one command and updates global command indexes.
- *
- * @return true if this command was the last command.
- * @return false if there are more commands within the current contents of the
- * Bulk EP1-OUT data buffer.
- */
-bool execute_command(void)
-{
-	uint8_t usb_out_bytecount, usb_in_bytecount;
-	uint16_t signal_state = 0;
-	uint16_t count;
-
-	/* Most commands do not transfer IN data. To save code space, we write 0 to
-	 * usb_in_bytecount here, then modify it in the switch statement below where
-	 * necessary */
-	usb_in_bytecount = 0;
-
-	switch (EP1OUTBUF[cmd_id_index] /* Command ID */) {
-	case CMD_SCAN_IN:
-		usb_out_bytecount = 5;
-		usb_in_bytecount = EP1OUTBUF[cmd_id_index + 1];
-		jtag_scan_in((cmd_id_index + 1), payload_index_in);
-		break;
-	case CMD_SCAN_OUT:
-		usb_out_bytecount = EP1OUTBUF[cmd_id_index + 1] + 5;
-		jtag_scan_out(cmd_id_index + 1);
-		break;
-	case CMD_SCAN_IO:
-		usb_in_bytecount = EP1OUTBUF[cmd_id_index + 1];
-		usb_out_bytecount = usb_in_bytecount + 5;
-		jtag_scan_io((cmd_id_index + 1), payload_index_in);
-		break;
-	case CMD_CLOCK_TMS:
-		usb_out_bytecount = 2;
-		jtag_clock_tms(EP1OUTBUF[cmd_id_index + 1], EP1OUTBUF[cmd_id_index + 2]);
-		break;
-	case CMD_CLOCK_TCK:
-		usb_out_bytecount = 2;
-		count = (uint16_t)EP1OUTBUF[cmd_id_index + 1];
-		count |= ((uint16_t)EP1OUTBUF[cmd_id_index + 2]) << 8;
-		jtag_clock_tck(count);
-		break;
-	case CMD_SLOW_SCAN_IN:
-		usb_out_bytecount = 5;
-		usb_in_bytecount = EP1OUTBUF[cmd_id_index + 1];
-		jtag_slow_scan_in(cmd_id_index + 1, payload_index_in);
-		break;
-	case CMD_SLOW_SCAN_OUT:
-		usb_out_bytecount = EP1OUTBUF[cmd_id_index + 1] + 5;
-		jtag_slow_scan_out(cmd_id_index + 1);
-		break;
-	case CMD_SLOW_SCAN_IO:
-		usb_in_bytecount = EP1OUTBUF[cmd_id_index + 1];
-		usb_out_bytecount = usb_in_bytecount + 5;
-		jtag_slow_scan_io(cmd_id_index + 1, payload_index_in);
-		break;
-	case CMD_SLOW_CLOCK_TMS:
-		usb_out_bytecount = 2;
-		jtag_slow_clock_tms(EP1OUTBUF[cmd_id_index + 1], EP1OUTBUF[cmd_id_index + 2]);
-		break;
-	case CMD_SLOW_CLOCK_TCK:
-		usb_out_bytecount = 2;
-		count = (uint16_t)EP1OUTBUF[cmd_id_index + 1];
-		count |= ((uint16_t)EP1OUTBUF[cmd_id_index + 2]) << 8;
-		jtag_slow_clock_tck(count);
-		break;
-	case CMD_SLEEP_US:
-		usb_out_bytecount = 2;
-		count = (uint16_t)EP1OUTBUF[cmd_id_index + 1];
-		count |= ((uint16_t)EP1OUTBUF[cmd_id_index + 2]) << 8;
-		delay_us(count);
-		break;
-	case CMD_SLEEP_MS:
-		usb_out_bytecount = 2;
-		count = (uint16_t)EP1OUTBUF[cmd_id_index + 1];
-		count |= ((uint16_t)EP1OUTBUF[cmd_id_index + 2]) << 8;
-		delay_ms(count);
-		break;
-	case CMD_GET_SIGNALS:
-		usb_out_bytecount = 0;
-		usb_in_bytecount = 2;
-		signal_state = jtag_get_signals();
-		EP1INBUF[payload_index_in] = (signal_state >> 8);
-		EP1INBUF[payload_index_in + 1] = (signal_state & 0xFF);
-		break;
-	case CMD_SET_SIGNALS:
-		usb_out_bytecount = 2;
-		jtag_set_signals(EP1OUTBUF[cmd_id_index + 1], EP1OUTBUF[cmd_id_index + 2]);
-		break;
-	case CMD_CONFIGURE_TCK_FREQ:
-		usb_out_bytecount = 5;
-		jtag_configure_tck_delay(EP1OUTBUF[cmd_id_index + 1],	/* scan_in */
-		EP1OUTBUF[cmd_id_index + 2],	/* scan_out */
-		EP1OUTBUF[cmd_id_index + 3],	/* scan_io */
-		EP1OUTBUF[cmd_id_index + 4],	/* clock_tck */
-		EP1OUTBUF[cmd_id_index + 5]);	/* clock_tms */
-		break;
-	case CMD_TEST:
-		usb_out_bytecount = 1;
-		/* Do nothing... This command is only used to test if the device is ready
-		 * to accept new commands */
-		break;
-	default:
-		/* Should never be reached */
-		usb_out_bytecount = 0;
-		break;
-	}
-
-	/* Update EP1 Bulk-IN data byte count */
-	payload_index_in += usb_in_bytecount;
-
-	/* Determine if this was the last command */
-	if ((cmd_id_index + usb_out_bytecount + 1) >= EP1OUTBC)
-		return true;
-
-	/* Not the last command, update cmd_id_index */
-	cmd_id_index += (usb_out_bytecount + 1);
-	return false;
-}
-
-/**
- * Forever wait for commands and execute them as they arrive.
- */
-void command_loop(void)
-{
-	bool last_command;
-	while (1) {
-		cmd_id_index = 0;
-		payload_index_in = 0;
-
-		/* Wait until host sends Bulk-OUT packet */
-		while ((!ep1_out) && (!ep6_out))
-			;
-		if (ep6_out) {
-			/* Execute I2C command */
-			i2c_recieve();
-			ep6_out = false;
-		}
-		if (ep1_out) {
-			ep1_out = false;
-			/* Execute the commands */
-			last_command = false;
-			while (!last_command)
-				last_command = execute_command();
-
-			/* Send back EP1 Bulk-IN packet if required */
-			if (payload_index_in > 0) {
-				EP1INBC = payload_index_in;
-				syncdelay(3);
-
-				while (!ep1_in)
-					;
-				ep1_in = false;
-			}
-
-			/* Re-arm EP1-OUT after command execution */
-			EP1OUTBC = 0;
-			syncdelay(3);
-			EP1OUTBC = 0;
-			syncdelay(3);
-		}
-	}
-}
diff --git a/contrib/firmware/angie/c/src/usb.c b/contrib/firmware/angie/c/src/usb.c
index ed23dcfa5..35f011f4e 100644
--- a/contrib/firmware/angie/c/src/usb.c
+++ b/contrib/firmware/angie/c/src/usb.c
@@ -20,124 +20,108 @@
 #include <stdio.h>
 #include "i2c.h"
 
-/* Also update external declarations in "include/usb.h" if making changes to
- * these variables!
- */
-volatile bool ep1_out;
-volatile bool ep1_in;
-volatile bool ep6_out;
-
 volatile __xdata __at 0xE6B8 struct setup_data setup_data;
 
 /* Define number of endpoints (except Control Endpoint 0) in a central place.
  * Be sure to include the necessary endpoint descriptors!
  */
-#define NUM_ENDPOINTS 3
+#define NUM_ENDPOINTS 2
+
 
 __code struct usb_device_descriptor device_descriptor = {
-	.blength =		sizeof(struct usb_device_descriptor),
-	.bdescriptortype =	DESCRIPTOR_TYPE_DEVICE,
-	.bcdusb =			0x0200,	    /* BCD: 02.00 (Version 2.0 USB spec) */
-	.bdeviceclass =		0xEF,
-	.bdevicesubclass =	0x02,
-	.bdeviceprotocol =	0x01,
-	.bmaxpacketsize0 =	64,
-	.idvendor =			0x584e,
-	.idproduct =		0x414f,
-	.bcddevice =		0x0000,
-	.imanufacturer =	1,
-	.iproduct =			2,
-	.iserialnumber =	3,
+	.blength =				sizeof(struct usb_device_descriptor),
+	.bdescriptortype =		DESCRIPTOR_TYPE_DEVICE,
+	.bcdusb =				0x0200,	    /* BCD: 02.00 (Version 2.0 USB spec) */
+	.bdeviceclass =			0xEF,
+	.bdevicesubclass =		0x02,
+	.bdeviceprotocol =		0x01,
+	.bmaxpacketsize0 =		64,
+	.idvendor =				0x584e,
+	.idproduct =			0x414f,
+	.bcddevice =			0x0000,
+	.imanufacturer =		1,
+	.iproduct =				2,
+	.iserialnumber =		3,
 	.bnumconfigurations =	1
 };
 
 /* WARNING: ALL config, interface and endpoint descriptors MUST be adjacent! */
-
 __code struct usb_config_descriptor config_descriptor = {
-	.blength =		sizeof(struct usb_config_descriptor),
-	.bdescriptortype =	DESCRIPTOR_TYPE_CONFIGURATION,
-	.wtotallength =		sizeof(struct usb_config_descriptor) +
-		3 * sizeof(struct usb_interface_descriptor) +
-		((NUM_ENDPOINTS + 2) * sizeof(struct usb_endpoint_descriptor)),
-	.bnuminterfaces =	2,
+	.blength =				sizeof(struct usb_config_descriptor),
+	.bdescriptortype =		DESCRIPTOR_TYPE_CONFIGURATION,
+	.wtotallength =			sizeof(struct usb_config_descriptor) +
+							2 * sizeof(struct usb_interface_descriptor) +
+							((NUM_ENDPOINTS * 2) * sizeof(struct usb_endpoint_descriptor)),
+	.bnuminterfaces =		2,
 	.bconfigurationvalue =	1,
-	.iconfiguration =	1,	/* String describing this configuration */
-	.bmattributes =		0x80,	/* Only MSB set according to USB spec */
-	.maxpower =		50	/* 100 mA */
+	.iconfiguration =		4,	/* String describing this configuration */
+	.bmattributes =			0x80,	/* Only MSB set according to USB spec */
+	.maxpower =				50	/* 100 mA */
 };
 
 __code struct usb_interface_descriptor interface_descriptor00 = {
-	.blength = sizeof(struct usb_interface_descriptor),
-	.bdescriptortype =	DESCRIPTOR_TYPE_INTERFACE,
-	.binterfacenumber =	0,
+	.blength =				sizeof(struct usb_interface_descriptor),
+	.bdescriptortype =		DESCRIPTOR_TYPE_INTERFACE,
+	.binterfacenumber =		0,
 	.balternatesetting =	0,
-	.bnumendpoints =	NUM_ENDPOINTS,
-	.binterfaceclass =	0XFF,
+	.bnumendpoints =		NUM_ENDPOINTS,
+	.binterfaceclass =		0XFF,
 	.binterfacesubclass =	0x00,
 	.binterfaceprotocol =	0x00,
-	.iinterface =		4
-};
-
-__code struct usb_endpoint_descriptor bulk_ep1_out_endpoint_descriptor = {
-	.blength =		sizeof(struct usb_endpoint_descriptor),
-	.bdescriptortype =	0x05,
-	.bendpointaddress =	(1 | USB_DIR_OUT),
-	.bmattributes =		0x02,
-	.wmaxpacketsize =	64,
-	.binterval =		0
+	.iinterface =			5
 };
 
-__code struct usb_endpoint_descriptor bulk_ep1_in_endpoint_descriptor = {
-	.blength =		sizeof(struct usb_endpoint_descriptor),
-	.bdescriptortype =	0x05,
-	.bendpointaddress =	(1 | USB_DIR_IN),
-	.bmattributes =		0x02,
-	.wmaxpacketsize =	64,
-	.binterval =		0
+__code struct usb_endpoint_descriptor bulk_ep2_endpoint_descriptor = {
+	.blength =				sizeof(struct usb_endpoint_descriptor),
+	.bdescriptortype =		0x05,
+	.bendpointaddress =		(2 | USB_DIR_OUT),
+	.bmattributes =			0x02,
+	.wmaxpacketsize =		512,
+	.binterval =			0
 };
 
-__code struct usb_endpoint_descriptor bulk_ep2_endpoint_descriptor = {
-	.blength =		sizeof(struct usb_endpoint_descriptor),
-	.bdescriptortype =	0x05,
-	.bendpointaddress =	(2 | USB_DIR_OUT),
-	.bmattributes =		0x02,
-	.wmaxpacketsize =	512,
-	.binterval =		0
+__code struct usb_endpoint_descriptor bulk_ep4_endpoint_descriptor = {
+	.blength =				sizeof(struct usb_endpoint_descriptor),
+	.bdescriptortype =		0x05,
+	.bendpointaddress =		(4 | USB_DIR_IN),
+	.bmattributes =			0x02,
+	.wmaxpacketsize =		512,
+	.binterval =			0
 };
 
 __code struct usb_interface_descriptor interface_descriptor01 = {
-	.blength = sizeof(struct usb_interface_descriptor),
-	.bdescriptortype =	DESCRIPTOR_TYPE_INTERFACE,
-	.binterfacenumber =	1,
+	.blength =				sizeof(struct usb_interface_descriptor),
+	.bdescriptortype =		DESCRIPTOR_TYPE_INTERFACE,
+	.binterfacenumber =		1,
 	.balternatesetting =	0,
-	.bnumendpoints =	2,
-	.binterfaceclass =	0x0A,
+	.bnumendpoints =		NUM_ENDPOINTS,
+	.binterfaceclass =		0x0A,
 	.binterfacesubclass =	0x00,
 	.binterfaceprotocol =	0x00,
-	.iinterface =		0x00
+	.iinterface =			6
 };
 
 __code struct usb_endpoint_descriptor bulk_ep6_out_endpoint_descriptor = {
-	.blength =		sizeof(struct usb_endpoint_descriptor),
-	.bdescriptortype =	0x05,
-	.bendpointaddress =	(6 | USB_DIR_OUT),
-	.bmattributes =		0x02,
-	.wmaxpacketsize =	512,
-	.binterval =		0
+	.blength =				sizeof(struct usb_endpoint_descriptor),
+	.bdescriptortype =		0x05,
+	.bendpointaddress =		(6 | USB_DIR_OUT),
+	.bmattributes =			0x02,
+	.wmaxpacketsize =		512,
+	.binterval =			0
 };
 
 __code struct usb_endpoint_descriptor bulk_ep8_in_endpoint_descriptor = {
-	.blength =		sizeof(struct usb_endpoint_descriptor),
-	.bdescriptortype =	0x05,
-	.bendpointaddress =	(8 | USB_DIR_IN),
-	.bmattributes =		0x02,
-	.wmaxpacketsize =	512,
-	.binterval =		0
+	.blength =				sizeof(struct usb_endpoint_descriptor),
+	.bdescriptortype =		0x05,
+	.bendpointaddress =		(8 | USB_DIR_IN),
+	.bmattributes =			0x02,
+	.wmaxpacketsize =		512,
+	.binterval =			0
 };
 __code struct usb_language_descriptor language_descriptor = {
-	.blength =		4,
-	.bdescriptortype =	DESCRIPTOR_TYPE_STRING,
-	.wlangid =		{0x0409} /* US English */
+	.blength =				4,
+	.bdescriptortype =		DESCRIPTOR_TYPE_STRING,
+	.wlangid =				{0x0409} /* US English */
 };
 
 __code struct usb_string_descriptor strmanufacturer =
@@ -195,15 +179,9 @@ void ep0out_isr(void)__interrupt	EP0OUT_ISR
 }
 void ep1in_isr(void)__interrupt	EP1IN_ISR
 {
-	ep1_in = true;
-	EXIF &= ~0x10;  /* Clear USBINT: Main global interrupt */
-	EPIRQ = 0x04;	/* Clear individual EP1IN IRQ */
 }
 void ep1out_isr(void)__interrupt	EP1OUT_ISR
 {
-	ep1_out = true;
-	EXIF &= ~0x10;  /* Clear USBINT: Main global interrupt */
-	EPIRQ = 0x08;	/* Clear individual EP1OUT IRQ */
 }
 void ep2_isr(void)__interrupt	EP2_ISR
 {
@@ -213,10 +191,11 @@ void ep4_isr(void)__interrupt	EP4_ISR
 }
 void ep6_isr(void)__interrupt	EP6_ISR
 {
-	ep6_out = true;
+	REVCTL = 0;     /* REVCTL.0 and REVCTL.1 set to 0 */
+	i2c_recieve();  /* Execute I2C communication */
 	EXIF &= ~0x10;  /* Clear USBINT: Main global interrupt */
 	EPIRQ = 0x40;	/* Clear individual EP6OUT IRQ */
-
+	REVCTL = 0x3;   /* REVCTL.0 and REVCTL.1 set to 1 */
 }
 void ep8_isr(void)__interrupt	EP8_ISR
 {
@@ -523,15 +502,28 @@ bool usb_handle_get_descriptor(void)
 void usb_handle_set_interface(void)
 {
 	/* Reset Data Toggle */
-	usb_reset_data_toggle(USB_DIR_IN  | 4);
 	usb_reset_data_toggle(USB_DIR_OUT | 2);
-
-	/* Unstall & clear busy flag of all valid IN endpoints */
-	EP1INCS = 0 | EPBSY;
+	usb_reset_data_toggle(USB_DIR_IN  | 4);
+	usb_reset_data_toggle(USB_DIR_OUT | 6);
+	usb_reset_data_toggle(USB_DIR_IN  | 8);
 
 	/* Unstall all valid OUT endpoints, reset bytecounts */
-	EP1OUTCS = 0;
-	EP1OUTBC = 0;
+	EP2CS = 0;
+	EP4CS = 0;
+	EP6CS = 0;
+	EP8CS = 0;
+	syncdelay(3);
+	EP2BCH = 0;
+	EP2BCL = 0x80;
+	syncdelay(3);
+	EP4BCH = 0;
+	EP4BCL = 0x80;
+	syncdelay(3);
+	EP6BCH = 0;
+	EP6BCL = 0x80;
+	syncdelay(3);
+	EP8BCH = 0;
+	EP8BCL = 0x80;
 	syncdelay(3);
 }
 
@@ -672,8 +664,9 @@ void usb_handle_setup_data(void)
 	case GET_INTERFACE:
 		/* ANGIE only has one interface, return its number */
 		EP0BUF[0] = interface_descriptor00.binterfacenumber;
+		EP0BUF[1] = interface_descriptor01.binterfacenumber;
 		EP0BCH = 0;
-		EP0BCL = 1;
+		EP0BCL = 2;
 		syncdelay(3);
 		break;
 	case SET_INTERFACE:
@@ -695,29 +688,21 @@ void usb_handle_setup_data(void)
  */
 void ep_init(void)
 {
-	EP1INCFG = 0xA0;
-	syncdelay(3);
-	EP1OUTCFG = 0xA0;
-	syncdelay(3);
-	EP2CFG = 0xA0;
-	syncdelay(3);
-	EP4CFG = 0x00;
-	syncdelay(3);
-	EP6CFG = 0xA2;
+	EP1INCFG = 0x00;  /* non VALID */
 	syncdelay(3);
-	EP8CFG = 0xE2;
+	EP1OUTCFG = 0x00;  /* non VALID */
 	syncdelay(3);
 
-	/* arm EP1-OUT */
-	EP1OUTBC = 0;
+	/* JTAG */
+	EP2CFG = 0xA2;  /* VALID | OUT | BULK | 512 Bytes | Double buffer */
 	syncdelay(3);
-	EP1OUTBC = 0;
+	EP4CFG = 0xE2;  /* VALID | IN | BULK | 512 Bytes | Double buffer */
 	syncdelay(3);
 
-	/* arm EP1-IN */
-	EP1INBC = 0;
+	/* I2C */
+	EP6CFG = 0xA2;  /* VALID | OUT | BULK | 512 Bytes | Double buffer */
 	syncdelay(3);
-	EP1INBC = 0;
+	EP8CFG = 0xE2;  /* VALID | IN | BULK | 512 Bytes | Double buffer */
 	syncdelay(3);
 
 	/* arm EP6-OUT */
@@ -726,16 +711,30 @@ void ep_init(void)
 	EP6BCL = 0x80;
 	syncdelay(3);
 
+	/* REVCTL.0 and REVCTL.1 set to 1 */
+	REVCTL = 0x3;
+	/* Arm both EP2 buffers to “prime the pump” */
+	OUTPKTEND = 0x82;
+	syncdelay(3);
+	OUTPKTEND = 0x82;
+	syncdelay(3);
+
 	/* Standard procedure to reset FIFOs */
 	FIFORESET = BMNAKALL;	/* NAK all transfers during the reset */
 	syncdelay(3);
-	FIFORESET = 0x02;		/* reset EP2 FIFO */
+	FIFORESET = BMNAKALL | 0x02;		/* reset EP2 FIFO */
+	syncdelay(3);
+	FIFORESET = BMNAKALL | 0x04;		/* reset EP4 FIFO */
 	syncdelay(3);
 	FIFORESET = 0x00;		/* deactivate the NAK all */
 	syncdelay(3);
+
+	/* configure EP2 in AUTO mode with 8-bit interface */
 	EP2FIFOCFG = 0x00;
 	syncdelay(3);
-	EP2FIFOCFG = BMAUTOOUT;	/* Automatic 8-bit GPIF OUT mode */
+	EP2FIFOCFG = BMAUTOOUT;	/* 8-bit Auto OUT mode */
+	syncdelay(3);
+	EP4FIFOCFG = BMAUTOIN | BMZEROLENIN;	/* 8-bit Auto IN mode */
 	syncdelay(3);
 }
 
@@ -841,9 +840,6 @@ void i2c_recieve(void)
  **/
 void interrupt_init(void)
 {
-	/* Enable Interrupts */
-	EA = 1;
-
 	/* Enable USB interrupt (EIE register) */
 	EUSB = 1;
 	EICON |= 0x20;
@@ -851,17 +847,20 @@ void interrupt_init(void)
 	/* Enable INT 2 & 4 Autovectoring */
 	INTSETUP |= (AV2EN | AV4EN);
 
-	/* Enable individual EP1OUT&IN & EP6&8 interrupts */
-	EPIE |= 0xCC;
+	/* Enable individual EP6&8 interrupts */
+	EPIE |= 0xC0;
 
 	/* Clear individual USB interrupt IRQ */
-	EPIRQ = 0xCC;
+	EPIRQ = 0xC0;
 
 	/* Enable SUDAV interrupt */
 	USBIEN |= SUDAVI;
 
 	/* Clear SUDAV interrupt */
 	USBIRQ = SUDAVI;
+
+	/* Enable Interrupts */
+	EA = 1;
 }
 
 /**
@@ -870,25 +869,12 @@ void interrupt_init(void)
 void io_init(void)
 {
 	/* PORT A */
-	PORTACFG = 0x01;	/* 0: normal ou 1: alternate function (each bit) */
-	OEA = 0xEF;	/* all OUT exept INIT_B IN */
+	PORTACFG = 0x0;	/* 0: normal ou 1: alternate function (each bit) */
+	OEA = 0xEF;
 	IOA = 0xFF;
 
-	/* PORT B */
-	OEB = 0xEF;	/* all OUT exept TDO */
-	IOB = 0xFF;
-	PIN_TRST = 1;
-	PIN_TMS = 0;
-	PIN_TCK = 0;
-	PIN_TDI = 0;
-	PIN_SRST = 1;
-
 	/* PORT C */
-	PORTCCFG = 0x00;	/* 0: normal ou 1: alternate function (each bit) */
+	PORTCCFG = 0x0;	/* 0: normal ou 1: alternate function (each bit) */
 	OEC = 0xFF;
 	IOC = 0xFF;
-
-	/* PORT D */
-	OED = 0xFF;
-	IOD = 0xFF;
 }

-----------------------------------------------------------------------

Summary of changes:
 contrib/firmware/angie/c/include/jtag.h     |  31 --
 contrib/firmware/angie/c/include/protocol.h |  20 -
 contrib/firmware/angie/c/src/jtag.c         | 674 ----------------------------
 contrib/firmware/angie/c/src/protocol.c     | 192 --------
 contrib/firmware/angie/c/src/usb.c          | 258 +++++------
 5 files changed, 122 insertions(+), 1053 deletions(-)
 delete mode 100644 contrib/firmware/angie/c/include/jtag.h
 delete mode 100644 contrib/firmware/angie/c/include/protocol.h
 delete mode 100644 contrib/firmware/angie/c/src/jtag.c
 delete mode 100644 contrib/firmware/angie/c/src/protocol.c


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1131-g9bad45995

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  9bad45995a5bf46dd37a038c351bd54b35c0f522 (commit)
      from  27d14c27a514d118b70b90e42c463a29bb0dd6ba (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 9bad45995a5bf46dd37a038c351bd54b35c0f522
Author: Thomas Huth <th...@re...>
Date:   Mon Jul 21 12:15:35 2025 +0200

    LICENSES: Replace the obsolete address of the FSF in the LGPL-2.1
    
    The FSF does not reside in the Franklin street anymore. Let's update
    the address with the link to their website, as suggested in the latest
    revisions of their LGPL-2.1 license:
    https://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt
    
    Change-Id: If3c272c8e942a59b532c7c2a89ff3a450f34530b
    Signed-off-by: Thomas Huth <th...@re...>
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9075
    Reviewed-by: zapb <de...@za...>
    Tested-by: jenkins

diff --git a/LICENSES/preferred/LGPL-2.1 b/LICENSES/preferred/LGPL-2.1
index 8738a8d57..b19c23d17 100644
--- a/LICENSES/preferred/LGPL-2.1
+++ b/LICENSES/preferred/LGPL-2.1
@@ -16,7 +16,7 @@ GNU LESSER GENERAL PUBLIC LICENSE
 Version 2.1, February 1999
 
 Copyright (C) 1991, 1999 Free Software Foundation, Inc.
-51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+<https://fsf.org/>
 
 Everyone is permitted to copy and distribute verbatim copies of this
 license document, but changing it is not allowed.
@@ -486,9 +486,9 @@ FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
 for more details.
 
 You should have received a copy of the GNU Lesser General Public License
-along with this library; if not, write to the Free Software Foundation,
-Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA Also add
-information on how to contact you by electronic and paper mail.
+along with this library; if not, see <https://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
 
 You should also get your employer (if you work as a programmer) or your
 school, if any, to sign a "copyright disclaimer" for the library, if

-----------------------------------------------------------------------

Summary of changes:
 LICENSES/preferred/LGPL-2.1 | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1130-g27d14c27a

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  27d14c27a514d118b70b90e42c463a29bb0dd6ba (commit)
       via  d9980d08be2b38b5f519a59687687ea543588cda (commit)
      from  f43ad6d10819fff827e53c086be281a20348c574 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 27d14c27a514d118b70b90e42c463a29bb0dd6ba
Author: Thomas Huth <th...@re...>
Date:   Mon Jul 21 12:15:33 2025 +0200

    LICENSES: Replace the obsolete address of the FSF in the GPL-2.0
    
    The FSF does not reside in the Franklin street anymore. Let's update
    the address with the link to their website, as suggested in the latest
    revisions of their GPL-2.0 license:
    https://www.gnu.org/licenses/old-licenses/gpl-2.0.txt
    
    Change-Id: Iaa45bc1e65383ee960055d0013d03bea54a7a91f
    Signed-off-by: Thomas Huth <th...@re...>
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9074
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>

diff --git a/LICENSES/preferred/GPL-2.0 b/LICENSES/preferred/GPL-2.0
index 687bdddb1..25d8343cd 100644
--- a/LICENSES/preferred/GPL-2.0
+++ b/LICENSES/preferred/GPL-2.0
@@ -15,7 +15,7 @@ License-Text:
                        Version 2, June 1991
 
  Copyright (C) 1989, 1991 Free Software Foundation, Inc.,
- 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ <https://fsf.org/>
  Everyone is permitted to copy and distribute verbatim copies
  of this license document, but changing it is not allowed.
 
@@ -317,8 +317,7 @@ the "copyright" line and a pointer to where the full notice is found.
     GNU General Public License for more details.
 
     You should have received a copy of the GNU General Public License along
-    with this program; if not, write to the Free Software Foundation, Inc.,
-    51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+    with this program; if not, see <https://www.gnu.org/licenses/>.
 
 Also add information on how to contact you by electronic and paper mail.
 

commit d9980d08be2b38b5f519a59687687ea543588cda
Author: Thomas Huth <th...@re...>
Date:   Mon Jul 21 12:15:37 2025 +0200

    LICENSES: Replace the obsolete address of the FSF in the GFDL-1.2
    
    The FSF does not reside in the Franklin street anymore. Let's update
    the address with the link to their website, as suggested in the latest
    revisions of their GFDL-1.2 license:
    https://www.gnu.org/licenses/old-licenses/fdl-1.2.txt
    
    Change-Id: I7492b596729deb2837de9529975e4d61b6a582f8
    Signed-off-by: Thomas Huth <th...@re...>
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9073
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>

diff --git a/LICENSES/preferred/GFDL-1.2 b/LICENSES/preferred/GFDL-1.2
index 9217d9c8e..ded6f4d45 100644
--- a/LICENSES/preferred/GFDL-1.2
+++ b/LICENSES/preferred/GFDL-1.2
@@ -18,7 +18,7 @@ License-Text:
 
 
  Copyright (C) 2000,2001,2002  Free Software Foundation, Inc.
-     51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+     <https://fsf.org/>
  Everyone is permitted to copy and distribute verbatim copies
  of this license document, but changing it is not allowed.
 
diff --git a/doc/fdl.texi b/doc/fdl.texi
index 2189f80a6..72916a9fb 100644
--- a/doc/fdl.texi
+++ b/doc/fdl.texi
@@ -7,7 +7,7 @@
 
 @display
 Copyright @copyright{} 2000,2001,2002 Free Software Foundation, Inc.
-51 Franklin St, Fifth Floor, Boston, MA  02110-1301, USA
+<https://fsf.org/>
 
 Everyone is permitted to copy and distribute verbatim copies
 of this license document, but changing it is not allowed.

-----------------------------------------------------------------------

Summary of changes:
 LICENSES/preferred/GFDL-1.2 | 2 +-
 LICENSES/preferred/GPL-2.0  | 5 ++---
 doc/fdl.texi                | 2 +-
 3 files changed, 4 insertions(+), 5 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1128-gf43ad6d10

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  f43ad6d10819fff827e53c086be281a20348c574 (commit)
      from  727c0d46e32d86a61bcfaba5de348176e732d0b2 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit f43ad6d10819fff827e53c086be281a20348c574
Author: Marc Schink <de...@za...>
Date:   Sat Aug 2 11:29:37 2025 +0200

    adapter/cmsis-dap: Fix 'quirk' command
    
    Display only the quirk state without additional text. This makes
    processing via Tcl easier. Also, do not echo the selected quirk state.
    
    Change-Id: I2e8de2742ffc10c7995a30a2a2d8a383b0cfaa69
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9068
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c
index 37f29c1b3..b82647da7 100644
--- a/src/jtag/drivers/cmsis_dap.c
+++ b/src/jtag/drivers/cmsis_dap.c
@@ -2239,11 +2239,13 @@ COMMAND_HANDLER(cmsis_dap_handle_quirk_command)
 	if (CMD_ARGC > 1)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	if (CMD_ARGC == 1)
+	if (CMD_ARGC == 1) {
 		COMMAND_PARSE_ENABLE(CMD_ARGV[0], cmsis_dap_quirk_mode);
+		return ERROR_OK;
+	}
+
+	command_print(CMD, "%s", cmsis_dap_quirk_mode ? "enabled" : "disabled");
 
-	command_print(CMD, "CMSIS-DAP quirk workarounds %s",
-				  cmsis_dap_quirk_mode ? "enabled" : "disabled");
 	return ERROR_OK;
 }
 

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/cmsis_dap.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1127-g727c0d46e

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  727c0d46e32d86a61bcfaba5de348176e732d0b2 (commit)
       via  1950befd76012c0e47ebc20cb79f5911c78b03e6 (commit)
      from  8b4eb936dbd863191e75cb7d1567d75d13b1e231 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 727c0d46e32d86a61bcfaba5de348176e732d0b2
Author: Marc Schink <de...@za...>
Date:   Sat Aug 2 11:13:50 2025 +0200

    adapter/cmsis-dap: Fix 'usb interface' command
    
    Simplify syntax error handling and make the documentation and code
    consistent.
    
    Change-Id: Ib8ee5adff2071964fc6d8e153f3eb82dd20054f3
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9067
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index e34020155..01ca7adfb 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2578,7 +2578,7 @@ This is the default if @command{cmsis-dap backend} is not specified.
 @end itemize
 @end deffn
 
-@deffn {Config Command} {cmsis-dap usb interface} [number]
+@deffn {Config Command} {cmsis-dap usb interface} number
 Specifies the @var{number} of the USB interface to use in v2 mode (USB bulk).
 In most cases need not to be specified and interfaces are searched by
 interface string or for user class interface.
diff --git a/src/jtag/drivers/cmsis_dap_usb_bulk.c b/src/jtag/drivers/cmsis_dap_usb_bulk.c
index 0dd6b2bbc..d34d4e31c 100644
--- a/src/jtag/drivers/cmsis_dap_usb_bulk.c
+++ b/src/jtag/drivers/cmsis_dap_usb_bulk.c
@@ -659,10 +659,10 @@ static void cmsis_dap_usb_cancel_all(struct cmsis_dap *dap)
 
 COMMAND_HANDLER(cmsis_dap_handle_usb_interface_command)
 {
-	if (CMD_ARGC == 1)
-		COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cmsis_dap_usb_interface);
-	else
-		LOG_ERROR("expected exactly one argument to cmsis_dap_usb_interface <interface_number>");
+	if (CMD_ARGC != 1)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], cmsis_dap_usb_interface);
 
 	return ERROR_OK;
 }
@@ -673,7 +673,7 @@ const struct command_registration cmsis_dap_usb_subcommand_handlers[] = {
 		.handler = &cmsis_dap_handle_usb_interface_command,
 		.mode = COMMAND_CONFIG,
 		.help = "set the USB interface number to use (for USB bulk backend only)",
-		.usage = "<interface_number>",
+		.usage = "<number>",
 	},
 	COMMAND_REGISTRATION_DONE
 };

commit 1950befd76012c0e47ebc20cb79f5911c78b03e6
Author: Richard Allen <rs...@gm...>
Date:   Fri May 16 20:26:08 2025 -0500

    target/espressif: add profiling function for ESP32, ESP32-S2
    
    Use the TRAX interface DEBUGPC if available.
    Otherwise use default stop-and-go profiling.
    
    ESP32: FT2232H+Linux: 97ksample/second @ 20mbps JTAG
    
    Change-Id: I1dda43df2727b542b08e338f7f4ba63530844a4f
    Signed-off-by: Richard Allen <rs...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8910
    Reviewed-by: Samuel Obuch <sam...@es...>
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/src/target/espressif/esp32.c b/src/target/espressif/esp32.c
index 5e2490a22..4ea1c8a33 100644
--- a/src/target/espressif/esp32.c
+++ b/src/target/espressif/esp32.c
@@ -501,4 +501,5 @@ struct target_type esp32_target = {
 	.deinit_target = esp_xtensa_target_deinit,
 
 	.commands = esp32_command_handlers,
+	.profiling = esp_xtensa_profiling,
 };
diff --git a/src/target/espressif/esp32s2.c b/src/target/espressif/esp32s2.c
index e32893a6b..eb3ad71f2 100644
--- a/src/target/espressif/esp32s2.c
+++ b/src/target/espressif/esp32s2.c
@@ -538,4 +538,5 @@ struct target_type esp32s2_target = {
 	.deinit_target = esp_xtensa_target_deinit,
 
 	.commands = esp32s2_command_handlers,
+	.profiling = esp_xtensa_profiling,
 };

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi                      |  2 +-
 src/jtag/drivers/cmsis_dap_usb_bulk.c | 10 +++++-----
 src/target/espressif/esp32.c          |  1 +
 src/target/espressif/esp32s2.c        |  1 +
 4 files changed, 8 insertions(+), 6 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1125-g8b4eb936d

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  8b4eb936dbd863191e75cb7d1567d75d13b1e231 (commit)
      from  93c565e7b40cf27ec133da2ceababe7c5f994b28 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 8b4eb936dbd863191e75cb7d1567d75d13b1e231
Author: Antonio Borneo <bor...@gm...>
Date:   Tue Jul 29 16:14:38 2025 +0200

    target: allow events to be modified inside an event handler
    
    The code in an event handler can use the command '$target_name
    configure' to add a new event or to remove or modify an existing
    event.
    Such operation impacts the list of event of the target and also
    modify the event itself, causing OpenOCD to access memory already
    deallocated or not anymore valid.
    
    Use the safe version of list_for_each_entry() to iterate on the
    list of events.
    Make a local copy of the current event, to avoid issues if it gets
    deallocated.
    Use Jim_IncrRefCount() to guarantee that the body of the event
    handler don't gets deallocated when the event is removed.
    
    Change-Id: I936e35adddc030ba7cec6e2fc0c7d3b1b5c4a863
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9063
    Reviewed-by: Evgeniy Naydanov <evg...@sy...>
    Tested-by: jenkins

diff --git a/src/target/target.c b/src/target/target.c
index 002fd7886..ca9b90133 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -4663,11 +4663,18 @@ COMMAND_HANDLER(handle_target_write_memory)
  */
 void target_handle_event(struct target *target, enum target_event e)
 {
-	struct target_event_action *teap;
+	struct target_event_action *teap, *tmp;
 	int retval;
 
-	list_for_each_entry(teap, &target->events_action, list) {
+	list_for_each_entry_safe(teap, tmp, &target->events_action, list) {
 		if (teap->event == e) {
+			/*
+			 * The event can be destroyed by its own handler.
+			 * Make a local copy and use it in place of the original.
+			 */
+			struct target_event_action local_teap = *teap;
+			teap = &local_teap;
+
 			LOG_DEBUG("target: %s (%s) event: %d (%s) action: %s",
 					   target_name(target),
 					   target_type_name(target),
@@ -4683,7 +4690,13 @@ void target_handle_event(struct target *target, enum target_event e)
 			struct target *saved_target_override = cmd_ctx->current_target_override;
 			cmd_ctx->current_target_override = target;
 
+			/*
+			 * The event can be destroyed by its own handler.
+			 * Prevent the body to get deallocated by Jim.
+			 */
+			Jim_IncrRefCount(teap->body);
 			retval = Jim_EvalObj(teap->interp, teap->body);
+			Jim_DecrRefCount(teap->interp, teap->body);
 
 			cmd_ctx->current_target_override = saved_target_override;
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.c | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1124-g93c565e7b

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  93c565e7b40cf27ec133da2ceababe7c5f994b28 (commit)
      from  269fdd233c0a4ae642bf37d991b664cfe8fe3d13 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 93c565e7b40cf27ec133da2ceababe7c5f994b28
Author: Henrik Mau <hen...@an...>
Date:   Mon Jun 30 11:32:44 2025 +0100

    tcl/target/max32690: Add max32690 support
    
    Add configuration file for max32690
    
    Change-Id: I30d90da176f85feba8369c96e1a0bb82a39eca5f
    Signed-off-by: Henrik Mau <hen...@an...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8977
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/max32690.cfg b/tcl/target/max32690.cfg
new file mode 100644
index 000000000..63f987458
--- /dev/null
+++ b/tcl/target/max32690.cfg
@@ -0,0 +1,47 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Maxim Integrated MAX32690 OpenOCD target configuration file
+
+# Set the reset pin configuration
+reset_config srst_only
+adapter srst delay 2
+adapter srst pulse_width 2
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x300000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x4000
+set FLASH_CLK 60
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx.cfg]
+
+# Add additional flash bank
+set FLASH_BASE 0x10300000
+set FLASH_SIZE 0x40000
+set FLC_BASE 0x40029400
+set FLASH_SECTOR 0x2000
+
+flash bank $_CHIPNAME.flash1 max32xxx $FLASH_BASE $FLASH_SIZE 0 0 $_CHIPNAME.cpu \
+$FLC_BASE $FLASH_SECTOR $FLASH_CLK $FLASH_OPTIONS
+
+# Early revisions of the MAX32690 will disable SWD upon reset. There are reserved address locations
+# in the ROM code that can be used to insert breakpoints.
+# This workaround will enable SWD for affected revisions.
+$_CHIPNAME.cpu configure -event reset-assert-pre {
+   if {$halt} {
+      catch {bp 0x0000FFF4 2 hw}
+   }
+}
+
+$_CHIPNAME.cpu configure -event reset-deassert-post {
+   if {$halt} {
+      $::_CHIPNAME.cpu arp_poll
+      $::_CHIPNAME.cpu arp_poll
+      $::_CHIPNAME.cpu arp_halt
+      rbp 0x0000FFF4
+   }
+}

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/max32690.cfg | 47 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
 create mode 100644 tcl/target/max32690.cfg


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1123-g269fdd233

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  269fdd233c0a4ae642bf37d991b664cfe8fe3d13 (commit)
      from  a2d0566a93e7d0123934eec0f96c19f6e3202ac6 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 269fdd233c0a4ae642bf37d991b664cfe8fe3d13
Author: Henrik Mau <hen...@an...>
Date:   Mon Jun 30 11:53:42 2025 +0100

    tcl/target/max32680: Add max32680 support
    
    Add configuration file for max32680
    
    Change-Id: Ibe290fd6d964ae3355f4e064f65b4510a9cbf5dd
    Signed-off-by: Henrik Mau <hen...@an...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8978
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tcl/target/max32680.cfg b/tcl/target/max32680.cfg
new file mode 100644
index 000000000..9c3ad24bd
--- /dev/null
+++ b/tcl/target/max32680.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Maxim Integrated MAX32655 OpenOCD target configuration file
+
+adapter speed 500
+
+# Set the reset pin configuration
+reset_config srst_only
+adapter srst delay 2
+adapter srst pulse_width 2
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x80000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 100
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx_common.cfg]

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/max32680.cfg | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)
 create mode 100644 tcl/target/max32680.cfg


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1122-ga2d0566a9

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  a2d0566a93e7d0123934eec0f96c19f6e3202ac6 (commit)
      from  a0ee2256187ee965b3ab929eaffeaeb67e173dc6 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit a2d0566a93e7d0123934eec0f96c19f6e3202ac6
Author: Henrik Mau <hen...@an...>
Date:   Mon Jun 30 13:23:23 2025 +0100

    tcl/target/max32xxx: Add max3267x support
    
    Add configuration files for max32670, max32672 and max32675
    
    Change-Id: I073db6294740bf46713134d75f718dfc7338156e
    Signed-off-by: Henrik Mau <hen...@an...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8979
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/max32670.cfg b/tcl/target/max32670.cfg
new file mode 100644
index 000000000..b8c76af5e
--- /dev/null
+++ b/tcl/target/max32670.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# maxim Integrated OpenOCD target configuration file
+
+# reset pin configuration
+reset_config none
+adapter_nsrst_delay 200
+adapter_nsrst_assert_width 200
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x60000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx.cfg]
+
+# Early revisions of the MAX32670 will disable SWD upon reset. There are reserved address locations
+# in the ROM code that can be used to insert breakpoints.
+# This workaround will enable SWD for affected revisions.
+$_CHIPNAME.cpu configure -event reset-assert-pre {
+	if {$halt} {catch {bp 0x00002174 2 hw}}
+}
+
+$_CHIPNAME.cpu configure -event reset-deassert-post {
+	if {$halt} {
+		$::_CHIPNAME.cpu arp_poll
+		$::_CHIPNAME.cpu arp_poll
+		$::_CHIPNAME.cpu arp_halt
+		rbp 0x00002174
+	}
+}
diff --git a/tcl/target/max32672.cfg b/tcl/target/max32672.cfg
new file mode 100644
index 000000000..26c7c82db
--- /dev/null
+++ b/tcl/target/max32672.cfg
@@ -0,0 +1,27 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# maxim Integrated OpenOCD target configuration file
+
+# reset pin configuration
+reset_config none
+adapter_nsrst_delay 200
+adapter_nsrst_assert_width 200
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x80000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx.cfg]
+
+# Add additional flash bank
+set FLASH_BASE 0x10080000
+set FLC_BASE 0x40029400
+
+flash bank $_CHIPNAME.flash1 max32xxx $FLASH_BASE $FLASH_SIZE 0 0 $_CHIPNAME.cpu \
+$FLC_BASE $FLASH_SECTOR $FLASH_CLK $FLASH_OPTIONS
diff --git a/tcl/target/max32675.cfg b/tcl/target/max32675.cfg
new file mode 100644
index 000000000..cbc718c9c
--- /dev/null
+++ b/tcl/target/max32675.cfg
@@ -0,0 +1,36 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# maxim Integrated OpenOCD target configuration file
+
+# reset pin configuration
+reset_config none
+adapter_nsrst_delay 200
+adapter_nsrst_assert_width 200
+
+# Set flash parameters
+set FLASH_BASE 0x10000000
+set FLASH_SIZE 0x60000
+set FLC_BASE 0x40029000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x01
+
+# Use Serial Wire Debug
+transport select swd
+
+source [find target/max32xxx.cfg]
+
+# Early revisions of the MAX3275 will disable SWD upon reset. There are reserved address locations
+# in the ROM code that can be used to insert breakpoints.
+# This workaround will enable SWD for affected revisions.
+$_CHIPNAME.cpu configure -event reset-assert-pre {
+	if {$halt} {catch {bp 0x00002174 2 hw}}
+}
+
+$_CHIPNAME.cpu configure -event reset-deassert-post {
+	if {$halt} {
+		$::_CHIPNAME.cpu arp_poll
+		$::_CHIPNAME.cpu arp_poll
+		$::_CHIPNAME.cpu arp_halt
+		rbp 0x00002174
+	}
+}

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/max32670.cfg | 36 ++++++++++++++++++++++++++++++++++++
 tcl/target/max32672.cfg | 27 +++++++++++++++++++++++++++
 tcl/target/max32675.cfg | 36 ++++++++++++++++++++++++++++++++++++
 3 files changed, 99 insertions(+)
 create mode 100644 tcl/target/max32670.cfg
 create mode 100644 tcl/target/max32672.cfg
 create mode 100644 tcl/target/max32675.cfg


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1121-ga0ee22561

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  a0ee2256187ee965b3ab929eaffeaeb67e173dc6 (commit)
      from  ff550ed0b0c6f4e15cbd97a5248cb33ca5d21c88 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit a0ee2256187ee965b3ab929eaffeaeb67e173dc6
Author: Henrik Mau <hen...@an...>
Date:   Mon Jun 30 10:48:04 2025 +0100

    tcl/target/max32xxx: Update max32xxx tcl files to use new flashing algorithm
    
    The max32xxx tcl files have been updated to work with the new flashing
    algorithm. A new max32xxx.cfg file contains common configuration and
    functionality.
    
    Change-Id: Ifaed58836d221ece6192faafa382b30fb72c77a6
    Signed-off-by: Henrik Mau <hen...@an...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8976
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/target/max32620.cfg b/tcl/target/max32620.cfg
index f3a9f84c8..807f8145e 100644
--- a/tcl/target/max32620.cfg
+++ b/tcl/target/max32620.cfg
@@ -1,32 +1,20 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 # Maxim Integrated MAX32620 OpenOCD target configuration file
-# www.maximintegrated.com
 
-# adapter speed
-adapter speed 4000
-
-# reset pin configuration
+# Set the reset pin configuration
 reset_config srst_only
+adapter srst delay 200
 
-if {[using_jtag]} {
-    jtag newtap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
-    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version
-} else {
-    swd newdap max32620 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
-}
-
-dap create max32620.dap -chain-position max32620.cpu
+# Set flash parameters
+set FLASH_BASE 0x0
+set FLASH_SIZE 0x200000
+set FLC_BASE 0x40002000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x00
 
-# target configuration
-target create max32620.cpu cortex_m -dap max32620.dap
-max32620.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
+# Setup the reserved TAP
+set RSV_TAP 1
 
-# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
-#   flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
-#   max32620 flash base address   0x00000000
-#   max32620 flash size           0x200000 (2MB)
-#   max32620 FLC base address     0x40002000
-#   max32620 sector (page) size   0x2000 (8kB)
-#   max32620 clock speed          96 (MHz)
-flash bank max32620.flash max32xxx 0x00000000 0x200000 0 0 max32620.cpu 0x40002000 0x2000 96
+source [find target/max32xxx_common.cfg]
diff --git a/tcl/target/max32625.cfg b/tcl/target/max32625.cfg
index 90eb39266..8d9479c39 100644
--- a/tcl/target/max32625.cfg
+++ b/tcl/target/max32625.cfg
@@ -1,32 +1,20 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 # Maxim Integrated MAX32625 OpenOCD target configuration file
-# www.maximintegrated.com
 
-# adapter speed
-adapter speed 4000
-
-# reset pin configuration
+# Set the reset pin configuration
 reset_config srst_only
+adapter srst delay 200
 
-if {[using_jtag]} {
-    jtag newtap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
-    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f71197 -ignore-version
-} else {
-    swd newdap max32625 cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
-}
-
-dap create max32625.dap -chain-position max32625.cpu
+# Set flash parameters
+set FLASH_BASE 0x0
+set FLASH_SIZE 0x80000
+set FLC_BASE 0x40002000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x00
 
-# target configuration
-target create max32625.cpu cortex_m -dap max32625.dap
-max32625.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
+# Setup the reserved TAP
+set RSV_TAP 1
 
-# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
-#   flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
-#   max32625 flash base address   0x00000000
-#   max32625 flash size           0x80000 (512k)
-#   max32625 FLC base address     0x40002000
-#   max32625 sector (page) size   0x2000 (8kB)
-#   max32625 clock speed          96 (MHz)
-flash bank max32625.flash max32xxx 0x00000000 0x80000 0 0 max32625.cpu 0x40002000 0x2000 96
+source [find target/max32xxx_common.cfg]
diff --git a/tcl/target/max3263x.cfg b/tcl/target/max3263x.cfg
index 852e04af1..413c49188 100644
--- a/tcl/target/max3263x.cfg
+++ b/tcl/target/max3263x.cfg
@@ -1,32 +1,40 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
 # Maxim Integrated MAX3263X OpenOCD target configuration file
-# www.maximintegrated.com
 
-# adapter speed
-adapter speed 4000
+# Set the reset pin configuration
+reset_config none
 
-# reset pin configuration
-reset_config srst_only
+# Set flash parameters
+set FLASH_BASE 0x0
+set FLASH_SIZE 0x200000
+set FLC_BASE 0x40002000
+set FLASH_SECTOR 0x2000
+set FLASH_CLK 96
+set FLASH_OPTIONS 0x00
 
-if {[using_jtag]} {
-    jtag newtap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x4ba00477 -ignore-version
-    jtag newtap maxtest tap -irlen 4 -irmask 0xf -ircapture 0x1 -expected-id 0x07f76197 -ignore-version
-} else {
-    swd newdap max3263x cpu -irlen 4 -irmask 0xf -expected-id 0x2ba01477 -ignore-version
-}
+# Setup the reserved TAP
+set RSV_TAP 1
+
+source [find target/max32xxx_common.cfg]
+
+# Create custom reset sequence
+$_CHIPNAME.cpu configure -event reset-init {
 
-dap create max3263x.dap -chain-position max3263x.cpu
+    # Reset the peripherals
+    mww 0x40000848 0xFFFFFFFF
+    mww 0x4000084C 0xFFFFFFFF
 
-# target configuration
-target create max3263x.cpu cortex_m -dap max3263x.dap
-max3263x.cpu configure -work-area-phys 0x20005000 -work-area-size 0x2000
+    sleep 10
 
-# Config Command: flash bank name driver base size chip_width bus_width target [driver_options]
-#   flash bank <name> max32xxx <base> <size> 0 0 <target> <flc base> <sector> <clk> <burst>
-#   max3263x flash base address   0x00000000
-#   max3263x flash size           0x200000 (2MB)
-#   max3263x FLC base address     0x40002000
-#   max3263x sector (page) size   0x2000 (8kB)
-#   max3263x clock speed          96 (MHz)
-flash bank max3263x.flash max32xxx 0x00000000 0x200000 0 0 max3263x.cpu 0x40002000 0x2000 96
+    mww 0x40000848 0x0
+    mww 0x4000084C 0x0
+
+    # Reset the SP
+    set SP_ADDR [mrw 0x0]
+    reg sp $SP_ADDR
+
+    # Reset the PC to the Reset_Handler
+    set RESET_HANDLER_ADDR  [mrw 0x4]
+    reg pc $RESET_HANDLER_ADDR
+}
diff --git a/tcl/target/max32xxx_common.cfg b/tcl/target/max32xxx_common.cfg
new file mode 100644
index 000000000..50a7d85e9
--- /dev/null
+++ b/tcl/target/max32xxx_common.cfg
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+# Maxim Integrated max32xxx OpenOCD driver configuration file.
+# Contains common settings for max32xxx devices.
+
+source [find mem_helper.tcl]
+source [find target/swj-dp.tcl]
+
+# Set the adapter speed
+if { [info exists ADAPTER_KHZ] } {
+   set _ADAPTER_KHZ $ADAPTER_KHZ
+} else {
+   set _ADAPTER_KHZ 2000
+}
+adapter speed $_ADAPTER_KHZ
+
+# Target configuration
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME max32xxx
+}
+
+# Add reserved TAP
+if { [using_jtag] && [info exists RSV_TAP] } {
+   jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version
+   jtag newtap rsvtap tap -irlen 4 -irmask 0xf -ircapture 0x1 -ignore-version
+} else {
+   swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -ignore-version
+}
+
+
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+target create $_CHIPNAME.cpu cortex_m -dap $_CHIPNAME.dap
+
+# Enable thread-aware debugging
+$_CHIPNAME.cpu configure -rtos hwthread
+
+# Setup working area
+if { [info exists WORK_START] } {
+   set _WORK_START $WORK_START
+} else {
+   set _WORK_START 0x20005000
+}
+
+if { [info exists WORK_SIZE] } {
+   set _WORK_SIZE $WORK_SIZE
+} else {
+   set _WORK_SIZE 0x8000
+}
+
+$_CHIPNAME.cpu configure -work-area-phys $_WORK_START -work-area-size $_WORK_SIZE
+
+# Configure flash driver
+if { [info exists FLASH_BASE] } {
+   set _FLASH_BASE $FLASH_BASE
+} else {
+   set _FLASH_BASE 0x10000000
+}
+
+if { [info exists FLASH_SIZE] } {
+   set _FLASH_SIZE $FLASH_SIZE
+} else {
+   set _FLASH_SIZE 0x10000
+}
+
+if { [info exists FLC_BASE] } {
+   set _FLC_BASE $FLC_BASE
+} else {
+   set _FLC_BASE 0x40029000
+}
+
+if { [info exists FLASH_SECTOR] } {
+   set _FLASH_SECTOR $FLASH_SECTOR
+} else {
+   set _FLASH_SECTOR 0x2000
+}
+
+if { [info exists FLASH_CLK] } {
+   set _FLASH_CLK $FLASH_CLK
+} else {
+   set _FLASH_CLK 96
+}
+
+# OPTIONS_128                     0x01 /* Perform 128 bit flash writes */
+# OPTIONS_ENC                     0x02 /* Encrypt the flash contents */
+# OPTIONS_AUTH                    0x04 /* Authenticate the flash contents */
+# OPTIONS_COUNT                   0x08 /* Add counter values to authentication */
+# OPTIONS_INTER                   0x10 /* Interleave the authentication and count values*/
+# OPTIONS_RELATIVE_XOR            0x20 /* Only XOR the offset of the address when encrypting */
+# OPTIONS_KEYSIZE                 0x40 /* Use a 256 bit KEY */
+
+if { [info exists FLASH_OPTIONS] } {
+   set _FLASH_OPTIONS $FLASH_OPTIONS
+} else {
+   set _FLASH_OPTIONS 0
+}
+
+flash bank $_CHIPNAME.flash max32xxx $_FLASH_BASE $_FLASH_SIZE 0 0 $_CHIPNAME.cpu \
+$_FLC_BASE $_FLASH_SECTOR $_FLASH_CLK $_FLASH_OPTIONS
+
+# call allow_low_pwr_dbg to set this to 1
+set ALLOW_LOW_PWR_DBG 0
+
+proc allow_low_pwr_dbg {} {
+   global ALLOW_LOW_PWR_DBG
+
+   # set our low-power debug flag
+   set ALLOW_LOW_PWR_DBG 1
+}
+
+# enable debug in case of low-power mode
+proc enable_debug {} {
+   set DBGKEY 0xA05F0000
+   set C_DEBUGEN 0x00000001
+   set C_HALT 0x00000002
+
+   echo "Enable debug to connect in low-power mode"
+
+   # enable debug
+   mww 0xE000EDF0 [expr {$DBGKEY | $C_HALT | $C_DEBUGEN}]
+
+   # allow for time waking up
+   sleep 500
+}
+
+$_CHIPNAME.cpu configure -event reset-deassert-post {
+   global ALLOW_LOW_PWR_DBG
+
+   if { $ALLOW_LOW_PWR_DBG == 1 } {
+      enable_debug
+   }
+}

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/max32620.cfg        |  36 ++++-------
 tcl/target/max32625.cfg        |  36 ++++-------
 tcl/target/max3263x.cfg        |  54 ++++++++++-------
 tcl/target/max32xxx_common.cfg | 132 +++++++++++++++++++++++++++++++++++++++++
 4 files changed, 187 insertions(+), 71 deletions(-)
 create mode 100644 tcl/target/max32xxx_common.cfg


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1120-gff550ed0b

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  ff550ed0b0c6f4e15cbd97a5248cb33ca5d21c88 (commit)
      from  3061149545b2be806b9a382995a33f5a60af9555 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit ff550ed0b0c6f4e15cbd97a5248cb33ca5d21c88
Author: Henrik Mau <hen...@an...>
Date:   Tue Feb 25 15:54:44 2025 +0000

    flash/nor/max32xxx: Fix failing flash step for internal flash
    
    When attempting to write to internal flash the flashing step fails with
    'Error: timeout waiting for algorithm, a target reset is recommended'.
    Updated flashing algorithm for MAX32xxx to fix this.
    
    Change-Id: I51350c1320c9699ddcf6cb28d9299538bece4c4f
    Signed-off-by: Henrik Mau <hen...@an...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8794
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: zapb <de...@za...>

diff --git a/contrib/loaders/flash/max32xxx/Makefile b/contrib/loaders/flash/max32xxx/Makefile
index 1565c811c..fe7666f84 100644
--- a/contrib/loaders/flash/max32xxx/Makefile
+++ b/contrib/loaders/flash/max32xxx/Makefile
@@ -1,21 +1,30 @@
 # SPDX-License-Identifier: GPL-2.0-or-later
 
+TARGET=max32xxx_write
+ENTRY=algo_write
+
 BIN2C = ../../../../src/helper/bin2char.sh
 
-CROSS_COMPILE ?= arm-none-eabi-
-AS      = $(CROSS_COMPILE)as
-OBJCOPY = $(CROSS_COMPILE)objcopy
+PREFIX=arm-none-eabi
+CFLAGS=-mthumb -mcpu=cortex-m4 -Wa,-mimplicit-it=thumb
+
+all: $(TARGET).inc
 
-all: max32xxx.inc
+%.o: %.c
+	$(PREFIX)-gcc $(CFLAGS) -Os -Wall -c ${<} -o ${@}
 
-%.elf: %.s
-	$(AS) $< -o $@
+%.elf: %.o
+	$(PREFIX)-ld -nostdlib --entry $(ENTRY) ${<} -o ${@}
+	$(PREFIX)-size ${@}
 
 %.bin: %.elf
-	$(OBJCOPY) -Obinary $< $@
+	$(PREFIX)-objcopy -O binary ${<} ${@}
 
 %.inc: %.bin
 	$(BIN2C) < $< > $@
 
+%.dasm: %.o
+	$(PREFIX)-objdump -S ${<} > ${TARGET}.dasm
+
 clean:
-	-rm -f *.elf *.bin *.inc
+	rm -rf $(TARGET).bin $(TARGET).elf $(TARGET).o $(TARGET).dasm $(TARGET).inc
diff --git a/contrib/loaders/flash/max32xxx/algo_options.h b/contrib/loaders/flash/max32xxx/algo_options.h
new file mode 100644
index 000000000..a4902e08a
--- /dev/null
+++ b/contrib/loaders/flash/max32xxx/algo_options.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ *   Copyright (C) 2016 by Maxim Integrated                                *
+ *   Copyright (C) 2025 Analog Devices, Inc.                               *
+ ***************************************************************************/
+
+#define OPTIONS_128                     0x01 /* Perform 128 bit flash writes */
+#define OPTIONS_ENC                     0x02 /* Encrypt the flash contents */
+#define OPTIONS_AUTH                    0x04 /* Authenticate the flash contents */
+#define OPTIONS_COUNT                   0x08 /* Add counter values to authentication */
+#define OPTIONS_INTER                   0x10 /* Interleave the authentication and count values*/
+#define OPTIONS_RELATIVE_XOR            0x20 /* Only XOR the offset of the address when encrypting */
+#define OPTIONS_KEYSIZE                 0x40 /* Use a 256 bit KEY */
diff --git a/contrib/loaders/flash/max32xxx/flc_regs.h b/contrib/loaders/flash/max32xxx/flc_regs.h
new file mode 100644
index 000000000..9179589dd
--- /dev/null
+++ b/contrib/loaders/flash/max32xxx/flc_regs.h
@@ -0,0 +1,238 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ *   Copyright (C) 2016 by Maxim Integrated                                *
+ *   Copyright (C) 2025 Analog Devices, Inc.                               *
+ ***************************************************************************/
+
+#ifndef _FLC_REGS_H_
+#define _FLC_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__ICCARM__)
+#pragma system_include
+#endif
+
+/*/ @cond */
+/*
+	If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/*/ @endcond */
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     flc
+ * @defgroup    flc_registers Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the FLC Peripheral Module.
+ * @description Flash Memory Control.
+ */
+
+/**
+ * @ingroup flc_registers
+ * Structure type to access the FLC Registers.
+ */
+struct mxc_flc_regs {
+	__IO uint32_t addr;	  /**< <tt>\b 0x00:<\tt> FLC ADDR Register */
+	__IO uint32_t clkdiv; /**< <tt>\b 0x04:<\tt> FLC CLKDIV Register */
+	__IO uint32_t cn;	  /**< <tt>\b 0x08:<\tt> FLC CN Register */
+	__R uint32_t rsv_0xc_0x23[6];
+	__IO uint32_t intr; /**< <tt>\b 0x024:<\tt> FLC INTR Register */
+	__R uint32_t rsv_0x28_0x2f[2];
+	__IO uint32_t data[4]; /**< <tt>\b 0x30:<\tt> FLC DATA Register */
+	__O uint32_t acntl;	   /**< <tt>\b 0x40:<\tt> FLC ACNTL Register */
+};
+
+/* Register offsets for module FLC */
+/**
+ * @ingroup    flc_registers
+ * @defgroup   FLC_Register_Offsets Register Offsets
+ * @brief      FLC Peripheral Register Offsets from the FLC Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_FLC_ADDR ((uint32_t)0x00000000UL)	  /**< Offset from FLC Base Address: <tt> 0x0x000 */
+#define MXC_R_FLC_CLKDIV ((uint32_t)0x00000004UL) /**< Offset from FLC Base Address: <tt> 0x0x004 */
+#define MXC_R_FLC_CN ((uint32_t)0x00000008UL)	  /**< Offset from FLC Base Address: <tt> 0x0x008 */
+#define MXC_R_FLC_INTR ((uint32_t)0x00000024UL)	  /**< Offset from FLC Base Address: <tt> 0x0x024 */
+#define MXC_R_FLC_DATA ((uint32_t)0x00000030UL)	  /**< Offset from FLC Base Address: <tt> 0x0x030 */
+#define MXC_R_FLC_ACNTL ((uint32_t)0x00000040UL)  /**< Offset from FLC Base Address: <tt> 0x0x040 */
+/**@} end of group flc_registers */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup ADDR_Register
+ * @brief    Flash Write Address.
+ * @{
+ */
+#define MXC_F_FLC_ADDR_ADDR_POS 0												  /**< ADDR_ADDR Position */
+#define MXC_F_FLC_ADDR_ADDR ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ADDR_ADDR_POS)) /**< ADDR_ADDR Mask */
+
+/**@} end of group ADDR_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup CLKDIV_Register
+ * @brief    Flash Clock Divide. The clock (PLL0) is divided by this value to generate a 1
+ *           MHz clock for Flash controller.
+ * @{
+ */
+#define MXC_F_FLC_CLKDIV_CLKDIV_POS 0												/**< CLKDIV_CLKDIV Position */
+#define MXC_F_FLC_CLKDIV_CLKDIV ((uint32_t)(0xFFUL << MXC_F_FLC_CLKDIV_CLKDIV_POS)) /**< CLKDIV_CLKDIV Mask */
+
+/**@} end of group CLKDIV_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup CN_Register
+ * @brief    Flash Control Register.
+ * @{
+ */
+#define MXC_F_FLC_CN_WR_POS 0													   /**< CN_WR Position */
+#define MXC_F_FLC_CN_WR ((uint32_t)(0x1UL << MXC_F_FLC_CN_WR_POS))				   /**< CN_WR Mask */
+#define MXC_V_FLC_CN_WR_COMPLETE ((uint32_t)0x0UL)								   /**< CN_WR_COMPLETE Value */
+#define MXC_S_FLC_CN_WR_COMPLETE (MXC_V_FLC_CN_WR_COMPLETE << MXC_F_FLC_CN_WR_POS) /**< CN_WR_COMPLETE Setting */
+#define MXC_V_FLC_CN_WR_START ((uint32_t)0x1UL)									   /**< CN_WR_START Value */
+#define MXC_S_FLC_CN_WR_START (MXC_V_FLC_CN_WR_START << MXC_F_FLC_CN_WR_POS)	   /**< CN_WR_START Setting */
+
+#define MXC_F_FLC_CN_ME_POS 1									   /**< CN_ME Position */
+#define MXC_F_FLC_CN_ME ((uint32_t)(0x1UL << MXC_F_FLC_CN_ME_POS)) /**< CN_ME Mask */
+
+#define MXC_F_FLC_CN_PGE_POS 2										 /**< CN_PGE Position */
+#define MXC_F_FLC_CN_PGE ((uint32_t)(0x1UL << MXC_F_FLC_CN_PGE_POS)) /**< CN_PGE Mask */
+
+#define MXC_F_FLC_CN_WDTH_POS 4														   /**< CN_WDTH Position */
+#define MXC_F_FLC_CN_WDTH ((uint32_t)(0x1UL << MXC_F_FLC_CN_WDTH_POS))				   /**< CN_WDTH Mask */
+#define MXC_V_FLC_CN_WDTH_SIZE128 ((uint32_t)0x0UL)									   /**< CN_WDTH_SIZE128 Value */
+#define MXC_S_FLC_CN_WDTH_SIZE128 (MXC_V_FLC_CN_WDTH_SIZE128 << MXC_F_FLC_CN_WDTH_POS) /**< CN_WDTH_SIZE128 Setting */
+#define MXC_V_FLC_CN_WDTH_SIZE32 ((uint32_t)0x1UL)									   /**< CN_WDTH_SIZE32 Value */
+#define MXC_S_FLC_CN_WDTH_SIZE32 (MXC_V_FLC_CN_WDTH_SIZE32 << MXC_F_FLC_CN_WDTH_POS)   /**< CN_WDTH_SIZE32 Setting */
+
+#define MXC_F_FLC_CN_ERASE_CODE_POS 8												/**< CN_ERASE_CODE Position */
+#define MXC_F_FLC_CN_ERASE_CODE ((uint32_t)(0xFFUL << MXC_F_FLC_CN_ERASE_CODE_POS)) /**< CN_ERASE_CODE Mask */
+#define MXC_V_FLC_CN_ERASE_CODE_NOP ((uint32_t)0x0UL)								/**< CN_ERASE_CODE_NOP Value */
+#define MXC_S_FLC_CN_ERASE_CODE_NOP                                                                                    \
+	(MXC_V_FLC_CN_ERASE_CODE_NOP << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_NOP Setting */
+#define MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE ((uint32_t)0x55UL)	 /**< CN_ERASE_CODE_ERASEPAGE Value */
+#define MXC_S_FLC_CN_ERASE_CODE_ERASEPAGE                                                                              \
+	(MXC_V_FLC_CN_ERASE_CODE_ERASEPAGE << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEPAGE Setting */
+#define MXC_V_FLC_CN_ERASE_CODE_ERASEALL ((uint32_t)0xAAUL)			   /**< CN_ERASE_CODE_ERASEALL Value */
+#define MXC_S_FLC_CN_ERASE_CODE_ERASEALL                                                                               \
+	(MXC_V_FLC_CN_ERASE_CODE_ERASEALL << MXC_F_FLC_CN_ERASE_CODE_POS) /**< CN_ERASE_CODE_ERASEALL Setting */
+
+#define MXC_F_FLC_CN_PEND_POS 24												 /**< CN_PEND Position */
+#define MXC_F_FLC_CN_PEND ((uint32_t)(0x1UL << MXC_F_FLC_CN_PEND_POS))			 /**< CN_PEND Mask */
+#define MXC_V_FLC_CN_PEND_IDLE ((uint32_t)0x0UL)								 /**< CN_PEND_IDLE Value */
+#define MXC_S_FLC_CN_PEND_IDLE (MXC_V_FLC_CN_PEND_IDLE << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_IDLE Setting */
+#define MXC_V_FLC_CN_PEND_BUSY ((uint32_t)0x1UL)								 /**< CN_PEND_BUSY Value */
+#define MXC_S_FLC_CN_PEND_BUSY (MXC_V_FLC_CN_PEND_BUSY << MXC_F_FLC_CN_PEND_POS) /**< CN_PEND_BUSY Setting */
+
+#define MXC_F_FLC_CN_LVE_POS 25												/**< CN_LVE Position */
+#define MXC_F_FLC_CN_LVE ((uint32_t)(0x1UL << MXC_F_FLC_CN_LVE_POS))		/**< CN_LVE Mask */
+#define MXC_V_FLC_CN_LVE_DIS ((uint32_t)0x0UL)								/**< CN_LVE_DIS Value */
+#define MXC_S_FLC_CN_LVE_DIS (MXC_V_FLC_CN_LVE_DIS << MXC_F_FLC_CN_LVE_POS) /**< CN_LVE_DIS Setting */
+#define MXC_V_FLC_CN_LVE_EN ((uint32_t)0x1UL)								/**< CN_LVE_EN Value */
+#define MXC_S_FLC_CN_LVE_EN (MXC_V_FLC_CN_LVE_EN << MXC_F_FLC_CN_LVE_POS)	/**< CN_LVE_EN Setting */
+
+#define MXC_F_FLC_CN_BRST_POS 27													   /**< CN_BRST Position */
+#define MXC_F_FLC_CN_BRST ((uint32_t)(0x1UL << MXC_F_FLC_CN_BRST_POS))				   /**< CN_BRST Mask */
+#define MXC_V_FLC_CN_BRST_DISABLE ((uint32_t)0x0UL)									   /**< CN_BRST_DISABLE Value */
+#define MXC_S_FLC_CN_BRST_DISABLE (MXC_V_FLC_CN_BRST_DISABLE << MXC_F_FLC_CN_BRST_POS) /**< CN_BRST_DISABLE Setting */
+#define MXC_V_FLC_CN_BRST_ENABLE ((uint32_t)0x1UL)									   /**< CN_BRST_ENABLE Value */
+#define MXC_S_FLC_CN_BRST_ENABLE (MXC_V_FLC_CN_BRST_ENABLE << MXC_F_FLC_CN_BRST_POS)   /**< CN_BRST_ENABLE Setting */
+
+#define MXC_F_FLC_CN_UNLOCK_POS 28										   /**< CN_UNLOCK Position */
+#define MXC_F_FLC_CN_UNLOCK ((uint32_t)(0xFUL << MXC_F_FLC_CN_UNLOCK_POS)) /**< CN_UNLOCK Mask */
+#define MXC_V_FLC_CN_UNLOCK_UNLOCKED ((uint32_t)0x2UL)					   /**< CN_UNLOCK_UNLOCKED Value */
+#define MXC_S_FLC_CN_UNLOCK_UNLOCKED                                                                                   \
+	(MXC_V_FLC_CN_UNLOCK_UNLOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_UNLOCKED Setting */
+#define MXC_V_FLC_CN_UNLOCK_LOCKED ((uint32_t)0x3UL)		  /**< CN_UNLOCK_LOCKED Value */
+#define MXC_S_FLC_CN_UNLOCK_LOCKED                                                                                     \
+	(MXC_V_FLC_CN_UNLOCK_LOCKED << MXC_F_FLC_CN_UNLOCK_POS) /**< CN_UNLOCK_LOCKED Setting */
+
+/**@} end of group CN_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup INTR_Register
+ * @brief    Flash Interrupt Register.
+ * @{
+ */
+#define MXC_F_FLC_INTR_DONE_POS 0										   /**< INTR_DONE Position */
+#define MXC_F_FLC_INTR_DONE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONE_POS)) /**< INTR_DONE Mask */
+#define MXC_V_FLC_INTR_DONE_INACTIVE ((uint32_t)0x0UL)					   /**< INTR_DONE_INACTIVE Value */
+#define MXC_S_FLC_INTR_DONE_INACTIVE                                                                                   \
+	(MXC_V_FLC_INTR_DONE_INACTIVE << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_INACTIVE Setting */
+#define MXC_V_FLC_INTR_DONE_PENDING ((uint32_t)0x1UL)		  /**< INTR_DONE_PENDING Value */
+#define MXC_S_FLC_INTR_DONE_PENDING                                                                                    \
+	(MXC_V_FLC_INTR_DONE_PENDING << MXC_F_FLC_INTR_DONE_POS) /**< INTR_DONE_PENDING Setting */
+
+#define MXC_F_FLC_INTR_AF_POS 1														   /**< INTR_AF Position */
+#define MXC_F_FLC_INTR_AF ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AF_POS))				   /**< INTR_AF Mask */
+#define MXC_V_FLC_INTR_AF_NOERROR ((uint32_t)0x0UL)									   /**< INTR_AF_NOERROR Value */
+#define MXC_S_FLC_INTR_AF_NOERROR (MXC_V_FLC_INTR_AF_NOERROR << MXC_F_FLC_INTR_AF_POS) /**< INTR_AF_NOERROR Setting */
+#define MXC_V_FLC_INTR_AF_ERROR ((uint32_t)0x1UL)									   /**< INTR_AF_ERROR Value */
+#define MXC_S_FLC_INTR_AF_ERROR (MXC_V_FLC_INTR_AF_ERROR << MXC_F_FLC_INTR_AF_POS)	   /**< INTR_AF_ERROR Setting */
+
+#define MXC_F_FLC_INTR_DONEIE_POS 8											   /**< INTR_DONEIE Position */
+#define MXC_F_FLC_INTR_DONEIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_DONEIE_POS)) /**< INTR_DONEIE Mask */
+#define MXC_V_FLC_INTR_DONEIE_DISABLE ((uint32_t)0x0UL)						   /**< INTR_DONEIE_DISABLE Value */
+#define MXC_S_FLC_INTR_DONEIE_DISABLE                                                                                  \
+	(MXC_V_FLC_INTR_DONEIE_DISABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_DISABLE Setting */
+#define MXC_V_FLC_INTR_DONEIE_ENABLE ((uint32_t)0x1UL)			 /**< INTR_DONEIE_ENABLE Value */
+#define MXC_S_FLC_INTR_DONEIE_ENABLE                                                                                   \
+	(MXC_V_FLC_INTR_DONEIE_ENABLE << MXC_F_FLC_INTR_DONEIE_POS) /**< INTR_DONEIE_ENABLE Setting */
+
+#define MXC_F_FLC_INTR_AFIE_POS 9										   /**< INTR_AFIE Position */
+#define MXC_F_FLC_INTR_AFIE ((uint32_t)(0x1UL << MXC_F_FLC_INTR_AFIE_POS)) /**< INTR_AFIE Mask */
+
+/**@} end of group INTR_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup DATA_Register
+ * @brief    Flash Write Data.
+ * @{
+ */
+#define MXC_F_FLC_DATA_DATA_POS 0												  /**< DATA_DATA Position */
+#define MXC_F_FLC_DATA_DATA ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_DATA_DATA_POS)) /**< DATA_DATA Mask */
+
+/**@} end of group DATA_Register */
+
+/**
+ * @ingroup  flc_registers
+ * @defgroup ACNTL_Register
+ * @brief    Access Control Register. Writing the ACNTL register with the following values in
+ *           the order shown, allows read and write access to the system and user Information
+ *           block: pflc-acntl = 0x3a7f5ca3; pflc-acntl = 0xa1e34f20; pflc-acntl =
+ *           0x9608b2c1. When unlocked, a write of any word will disable access to system and
+ *           user information block. Readback of this register is always zero.
+ * @{
+ */
+#define MXC_F_FLC_ACNTL_ACNTL_POS 0													  /**< ACNTL_ACNTL Position */
+#define MXC_F_FLC_ACNTL_ACNTL ((uint32_t)(0xFFFFFFFFUL << MXC_F_FLC_ACNTL_ACNTL_POS)) /**< ACNTL_ACNTL Mask */
+
+/**@} end of group ACNTL_Register */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _FLC_REGS_H_ */
diff --git a/contrib/loaders/flash/max32xxx/gcr_regs.h b/contrib/loaders/flash/max32xxx/gcr_regs.h
new file mode 100644
index 000000000..0c5ccdbf3
--- /dev/null
+++ b/contrib/loaders/flash/max32xxx/gcr_regs.h
@@ -0,0 +1,777 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ *   Copyright (C) 2016 by Maxim Integrated                                *
+ *   Copyright (C) 2025 Analog Devices, Inc.                               *
+ ***************************************************************************/
+
+#ifndef _GCR_REGS_H_
+#define _GCR_REGS_H_
+
+/* **** Includes **** */
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(__ICCARM__)
+#pragma system_include
+#endif
+
+#if defined(__CC_ARM)
+#pragma anon_unions
+#endif
+/*/ @cond */
+/*
+	If types are not defined elsewhere (CMSIS) define them here
+*/
+#ifndef __IO
+#define __IO volatile
+#endif
+#ifndef __I
+#define __I volatile const
+#endif
+#ifndef __O
+#define __O volatile
+#endif
+#ifndef __R
+#define __R volatile const
+#endif
+/*/ @endcond */
+
+/* **** Definitions **** */
+
+/**
+ * @ingroup     gcr
+ * @defgroup    gcr_registers GCR_Registers
+ * @brief       Registers, Bit Masks and Bit Positions for the GCR Peripheral Module.
+ * @details Global Control Registers.
+ */
+
+/**
+ * @ingroup gcr_registers
+ * Structure type to access the GCR Registers.
+ */
+struct mxc_gcr_regs {
+	__IO uint32_t scon;	 /**< <tt>\b 0x00:</tt> GCR SCON Register */
+	__IO uint32_t rstr0; /**< <tt>\b 0x04:</tt> GCR RSTR0 Register */
+	__IO uint32_t clkcn; /**< <tt>\b 0x08:</tt> GCR CLKCN Register */
+	__IO uint32_t pm;	 /**< <tt>\b 0x0C:</tt> GCR PM Register */
+	__R uint32_t rsv_0x10_0x17[2];
+	__IO uint32_t pckdiv; /**< <tt>\b 0x18:</tt> GCR PCKDIV Register */
+	__R uint32_t rsv_0x1c_0x23[2];
+	__IO uint32_t perckcn0; /**< <tt>\b 0x24:</tt> GCR PERCKCN0 Register */
+	__IO uint32_t memckcn;	/**< <tt>\b 0x28:</tt> GCR MEMCKCN Register */
+	__IO uint32_t memzcn;	/**< <tt>\b 0x2C:</tt> GCR MEMZCN Register */
+	__R uint32_t rsv_0x30_0x3f[4];
+	__IO uint32_t sysst;	/**< <tt>\b 0x40:</tt> GCR SYSST Register */
+	__IO uint32_t rstr1;	/**< <tt>\b 0x44:</tt> GCR RSTR1 Register */
+	__IO uint32_t perckcn1; /**< <tt>\b 0x48:</tt> GCR PERCKCN1 Register */
+	__IO uint32_t evten;	/**< <tt>\b 0x4C:</tt> GCR EVTEN Register */
+	__I uint32_t revision;	/**< <tt>\b 0x50:</tt> GCR REVISION Register */
+	__IO uint32_t syssie;	/**< <tt>\b 0x54:</tt> GCR SYSSIE Register */
+	__R uint32_t rsv_0x58_0x63[3];
+	__IO uint32_t eccerr;	/**< <tt>\b 0x64:</tt> GCR ECCERR Register */
+	__IO uint32_t eccnded;	/**< <tt>\b 0x68:</tt> GCR ECCNDED Register */
+	__IO uint32_t eccirqen; /**< <tt>\b 0x6C:</tt> GCR ECCIRQEN Register */
+	__IO uint32_t eccerrad; /**< <tt>\b 0x70:</tt> GCR ECCERRAD Register */
+};
+
+/* Register offsets for module GCR */
+/**
+ * @ingroup    gcr_registers
+ * @defgroup   GCR_Register_Offsets Register Offsets
+ * @brief      GCR Peripheral Register Offsets from the GCR Base Peripheral Address.
+ * @{
+ */
+#define MXC_R_GCR_SCON ((uint32_t)0x00000000UL)		/**< Offset from GCR Base Address: 0x0000 */
+#define MXC_R_GCR_RSTR0 ((uint32_t)0x00000004UL)	/**< Offset from GCR Base Address: 0x0004 */
+#define MXC_R_GCR_CLKCN ((uint32_t)0x00000008UL)	/**< Offset from GCR Base Address: 0x0008 */
+#define MXC_R_GCR_PM ((uint32_t)0x0000000CUL)		/**< Offset from GCR Base Address: 0x000C */
+#define MXC_R_GCR_PCKDIV ((uint32_t)0x00000018UL)	/**< Offset from GCR Base Address: 0x0018 */
+#define MXC_R_GCR_PERCKCN0 ((uint32_t)0x00000024UL) /**< Offset from GCR Base Address: 0x0024 */
+#define MXC_R_GCR_MEMCKCN ((uint32_t)0x00000028UL)	/**< Offset from GCR Base Address: 0x0028 */
+#define MXC_R_GCR_MEMZCN ((uint32_t)0x0000002CUL)	/**< Offset from GCR Base Address: 0x002C */
+#define MXC_R_GCR_SYSST ((uint32_t)0x00000040UL)	/**< Offset from GCR Base Address: 0x0040 */
+#define MXC_R_GCR_RSTR1 ((uint32_t)0x00000044UL)	/**< Offset from GCR Base Address: 0x0044 */
+#define MXC_R_GCR_PERCKCN1 ((uint32_t)0x00000048UL) /**< Offset from GCR Base Address: 0x0048 */
+#define MXC_R_GCR_EVTEN ((uint32_t)0x0000004CUL)	/**< Offset from GCR Base Address: 0x004C */
+#define MXC_R_GCR_REVISION ((uint32_t)0x00000050UL) /**< Offset from GCR Base Address: 0x0050 */
+#define MXC_R_GCR_SYSSIE ((uint32_t)0x00000054UL)	/**< Offset from GCR Base Address: 0x0054 */
+#define MXC_R_GCR_ECCERR ((uint32_t)0x00000064UL)	/**< Offset from GCR Base Address: 0x0064 */
+#define MXC_R_GCR_ECCNDED ((uint32_t)0x00000068UL)	/**< Offset from GCR Base Address: 0x0068 */
+#define MXC_R_GCR_ECCIRQEN ((uint32_t)0x0000006CUL) /**< Offset from GCR Base Address: 0x006C */
+#define MXC_R_GCR_ECCERRAD ((uint32_t)0x00000070UL) /**< Offset from GCR Base Address: 0x0070 */
+													/**@} end of group gcr_registers */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_SCON GCR_SCON
+ * @brief    System Control.
+ * @{
+ */
+#define MXC_F_GCR_SCON_BSTAPEN_POS 0											 /**< SCON_BSTAPEN Position */
+#define MXC_F_GCR_SCON_BSTAPEN ((uint32_t)(0x1UL << MXC_F_GCR_SCON_BSTAPEN_POS)) /**< SCON_BSTAPEN Mask */
+#define MXC_V_GCR_SCON_BSTAPEN_DIS ((uint32_t)0x0UL)							 /**< SCON_BSTAPEN_DIS Value */
+#define MXC_S_GCR_SCON_BSTAPEN_DIS                                                                                     \
+	(MXC_V_GCR_SCON_BSTAPEN_DIS << MXC_F_GCR_SCON_BSTAPEN_POS) /**< SCON_BSTAPEN_DIS Setting */
+#define MXC_V_GCR_SCON_BSTAPEN_EN ((uint32_t)0x1UL)			   /**< SCON_BSTAPEN_EN Value */
+#define MXC_S_GCR_SCON_BSTAPEN_EN                                                                                      \
+	(MXC_V_GCR_SCON_BSTAPEN_EN << MXC_F_GCR_SCON_BSTAPEN_POS) /**< SCON_BSTAPEN_EN Setting */
+
+#define MXC_F_GCR_SCON_SBUSARB_POS 1											 /**< SCON_SBUSARB Position */
+#define MXC_F_GCR_SCON_SBUSARB ((uint32_t)(0x3UL << MXC_F_GCR_SCON_SBUSARB_POS)) /**< SCON_SBUSARB Mask */
+#define MXC_V_GCR_SCON_SBUSARB_FIX ((uint32_t)0x0UL)							 /**< SCON_SBUSARB_FIX Value */
+#define MXC_S_GCR_SCON_SBUSARB_FIX                                                                                     \
+	(MXC_V_GCR_SCON_SBUSARB_FIX << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_FIX Setting */
+#define MXC_V_GCR_SCON_SBUSARB_ROUND ((uint32_t)0x1UL)		   /**< SCON_SBUSARB_ROUND Value */
+#define MXC_S_GCR_SCON_SBUSARB_ROUND                                                                                   \
+	(MXC_V_GCR_SCON_SBUSARB_ROUND << MXC_F_GCR_SCON_SBUSARB_POS) /**< SCON_SBUSARB_ROUND Setting */
+
+#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS 4 /**< SCON_FLASH_PAGE_FLIP Position */
+#define MXC_F_GCR_SCON_FLASH_PAGE_FLIP                                                                                 \
+	((uint32_t)(0x1UL << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS))	/**< SCON_FLASH_PAGE_FLIP Mask */
+#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL ((uint32_t)0x0UL) /**< SCON_FLASH_PAGE_FLIP_NORMAL Value */
+#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                                                          \
+	(MXC_V_GCR_SCON_FLASH_PAGE_FLIP_NORMAL                                                                             \
+	 << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS)						 /**< SCON_FLASH_PAGE_FLIP_NORMAL Setting */
+#define MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED ((uint32_t)0x1UL) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Value */
+#define MXC_S_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                                                         \
+	(MXC_V_GCR_SCON_FLASH_PAGE_FLIP_SWAPPED                                                                            \
+	 << MXC_F_GCR_SCON_FLASH_PAGE_FLIP_POS) /**< SCON_FLASH_PAGE_FLIP_SWAPPED Setting */
+
+#define MXC_F_GCR_SCON_CCACHE_FLUSH_POS 6 /**< SCON_CCACHE_FLUSH Position */
+#define MXC_F_GCR_SCON_CCACHE_FLUSH                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS))	 /**< SCON_CCACHE_FLUSH Mask */
+#define MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL ((uint32_t)0x0UL) /**< SCON_CCACHE_FLUSH_NORMAL Value */
+#define MXC_S_GCR_SCON_CCACHE_FLUSH_NORMAL                                                                             \
+	(MXC_V_GCR_SCON_CCACHE_FLUSH_NORMAL << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_NORMAL Setting */
+#define MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH ((uint32_t)0x1UL)					/**< SCON_CCACHE_FLUSH_FLUSH Value */
+#define MXC_S_GCR_SCON_CCACHE_FLUSH_FLUSH                                                                              \
+	(MXC_V_GCR_SCON_CCACHE_FLUSH_FLUSH << MXC_F_GCR_SCON_CCACHE_FLUSH_POS) /**< SCON_CCACHE_FLUSH_FLUSH Setting */
+
+#define MXC_F_GCR_SCON_CCHK_POS 13										   /**< SCON_CCHK Position */
+#define MXC_F_GCR_SCON_CCHK ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CCHK_POS)) /**< SCON_CCHK Mask */
+#define MXC_V_GCR_SCON_CCHK_COMPLETE ((uint32_t)0x0UL)					   /**< SCON_CCHK_COMPLETE Value */
+#define MXC_S_GCR_SCON_CCHK_COMPLETE                                                                                   \
+	(MXC_V_GCR_SCON_CCHK_COMPLETE << MXC_F_GCR_SCON_CCHK_POS) /**< SCON_CCHK_COMPLETE Setting */
+#define MXC_V_GCR_SCON_CCHK_START ((uint32_t)0x1UL)			  /**< SCON_CCHK_START Value */
+#define MXC_S_GCR_SCON_CCHK_START (MXC_V_GCR_SCON_CCHK_START << MXC_F_GCR_SCON_CCHK_POS) /**< SCON_CCHK_START Setting  \
+																						  */
+
+#define MXC_F_GCR_SCON_CHKRES_POS 15										   /**< SCON_CHKRES Position */
+#define MXC_F_GCR_SCON_CHKRES ((uint32_t)(0x1UL << MXC_F_GCR_SCON_CHKRES_POS)) /**< SCON_CHKRES Mask */
+#define MXC_V_GCR_SCON_CHKRES_PASS ((uint32_t)0x0UL)						   /**< SCON_CHKRES_PASS Value */
+#define MXC_S_GCR_SCON_CHKRES_PASS                                                                                     \
+	(MXC_V_GCR_SCON_CHKRES_PASS << MXC_F_GCR_SCON_CHKRES_POS) /**< SCON_CHKRES_PASS Setting */
+#define MXC_V_GCR_SCON_CHKRES_FAIL ((uint32_t)0x1UL)		  /**< SCON_CHKRES_FAIL Value */
+#define MXC_S_GCR_SCON_CHKRES_FAIL                                                                                     \
+	(MXC_V_GCR_SCON_CHKRES_FAIL << MXC_F_GCR_SCON_CHKRES_POS) /**< SCON_CHKRES_FAIL Setting */
+
+#define MXC_F_GCR_SCON_OVR_POS 16													/**< SCON_OVR Position */
+#define MXC_F_GCR_SCON_OVR ((uint32_t)(0x3UL << MXC_F_GCR_SCON_OVR_POS))			/**< SCON_OVR Mask */
+#define MXC_V_GCR_SCON_OVR_0_9V ((uint32_t)0x0UL)									/**< SCON_OVR_0_9V Value */
+#define MXC_S_GCR_SCON_OVR_0_9V (MXC_V_GCR_SCON_OVR_0_9V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_0_9V Setting */
+#define MXC_V_GCR_SCON_OVR_1_0V ((uint32_t)0x1UL)									/**< SCON_OVR_1_0V Value */
+#define MXC_S_GCR_SCON_OVR_1_0V (MXC_V_GCR_SCON_OVR_1_0V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_1_0V Setting */
+#define MXC_V_GCR_SCON_OVR_1_1V ((uint32_t)0x2UL)									/**< SCON_OVR_1_1V Value */
+#define MXC_S_GCR_SCON_OVR_1_1V (MXC_V_GCR_SCON_OVR_1_1V << MXC_F_GCR_SCON_OVR_POS) /**< SCON_OVR_1_1V Setting */
+
+#define MXC_F_GCR_SCON_MEMPROT_EN_POS 20											   /**< SCON_MEMPROT_EN Position */
+#define MXC_F_GCR_SCON_MEMPROT_EN ((uint32_t)(0x1UL << MXC_F_GCR_SCON_MEMPROT_EN_POS)) /**< SCON_MEMPROT_EN Mask */
+#define MXC_V_GCR_SCON_MEMPROT_EN_DIS ((uint32_t)0x0UL)								   /**< SCON_MEMPROT_EN_DIS Value */
+#define MXC_S_GCR_SCON_MEMPROT_EN_DIS                                                                                  \
+	(MXC_V_GCR_SCON_MEMPROT_EN_DIS << MXC_F_GCR_SCON_MEMPROT_EN_POS) /**< SCON_MEMPROT_EN_DIS Setting */
+#define MXC_V_GCR_SCON_MEMPROT_EN_EN ((uint32_t)0x1UL)				 /**< SCON_MEMPROT_EN_EN Value */
+#define MXC_S_GCR_SCON_MEMPROT_EN_EN                                                                                   \
+	(MXC_V_GCR_SCON_MEMPROT_EN_EN << MXC_F_GCR_SCON_MEMPROT_EN_POS) /**< SCON_MEMPROT_EN_EN Setting */
+
+#define MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS 21 /**< SCON_MEMPROT_KEYSZ Position */
+#define MXC_F_GCR_SCON_MEMPROT_KEYSZ                                                                                   \
+	((uint32_t)(0x1UL << MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS)) /**< SCON_MEMPROT_KEYSZ Mask */
+#define MXC_V_GCR_SCON_MEMPROT_KEYSZ_128 ((uint32_t)0x0UL)	/**< SCON_MEMPROT_KEYSZ_128 Value */
+#define MXC_S_GCR_SCON_MEMPROT_KEYSZ_128                                                                               \
+	(MXC_V_GCR_SCON_MEMPROT_KEYSZ_128 << MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS) /**< SCON_MEMPROT_KEYSZ_128 Setting */
+#define MXC_V_GCR_SCON_MEMPROT_KEYSZ_256 ((uint32_t)0x1UL)				   /**< SCON_MEMPROT_KEYSZ_256 Value */
+#define MXC_S_GCR_SCON_MEMPROT_KEYSZ_256                                                                               \
+	(MXC_V_GCR_SCON_MEMPROT_KEYSZ_256 << MXC_F_GCR_SCON_MEMPROT_KEYSZ_POS) /**< SCON_MEMPROT_KEYSZ_256 Setting */
+
+/**@} end of group GCR_SCON_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_RSTR0 GCR_RSTR0
+ * @brief    Reset.
+ * @{
+ */
+#define MXC_F_GCR_RSTR0_DMA_POS 0										   /**< RSTR0_DMA Position */
+#define MXC_F_GCR_RSTR0_DMA ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_DMA_POS)) /**< RSTR0_DMA Mask */
+#define MXC_V_GCR_RSTR0_DMA_RESET_DONE ((uint32_t)0x0UL)				   /**< RSTR0_DMA_RESET_DONE Value */
+#define MXC_S_GCR_RSTR0_DMA_RESET_DONE                                                                                 \
+	(MXC_V_GCR_RSTR0_DMA_RESET_DONE << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_RESET_DONE Setting */
+#define MXC_V_GCR_RSTR0_DMA_BUSY ((uint32_t)0x1UL)				/**< RSTR0_DMA_BUSY Value */
+#define MXC_S_GCR_RSTR0_DMA_BUSY (MXC_V_GCR_RSTR0_DMA_BUSY << MXC_F_GCR_RSTR0_DMA_POS) /**< RSTR0_DMA_BUSY Setting */
+
+#define MXC_F_GCR_RSTR0_WDT_POS 1										   /**< RSTR0_WDT Position */
+#define MXC_F_GCR_RSTR0_WDT ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_WDT_POS)) /**< RSTR0_WDT Mask */
+
+#define MXC_F_GCR_RSTR0_GPIO0_POS 2											   /**< RSTR0_GPIO0 Position */
+#define MXC_F_GCR_RSTR0_GPIO0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO0_POS)) /**< RSTR0_GPIO0 Mask */
+
+#define MXC_F_GCR_RSTR0_GPIO1_POS 3											   /**< RSTR0_GPIO1 Position */
+#define MXC_F_GCR_RSTR0_GPIO1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_GPIO1_POS)) /**< RSTR0_GPIO1 Mask */
+
+#define MXC_F_GCR_RSTR0_TIMER0_POS 5											 /**< RSTR0_TIMER0 Position */
+#define MXC_F_GCR_RSTR0_TIMER0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER0_POS)) /**< RSTR0_TIMER0 Mask */
+
+#define MXC_F_GCR_RSTR0_TIMER1_POS 6											 /**< RSTR0_TIMER1 Position */
+#define MXC_F_GCR_RSTR0_TIMER1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER1_POS)) /**< RSTR0_TIMER1 Mask */
+
+#define MXC_F_GCR_RSTR0_TIMER2_POS 7											 /**< RSTR0_TIMER2 Position */
+#define MXC_F_GCR_RSTR0_TIMER2 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER2_POS)) /**< RSTR0_TIMER2 Mask */
+
+#define MXC_F_GCR_RSTR0_TIMER3_POS 8											 /**< RSTR0_TIMER3 Position */
+#define MXC_F_GCR_RSTR0_TIMER3 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TIMER3_POS)) /**< RSTR0_TIMER3 Mask */
+
+#define MXC_F_GCR_RSTR0_UART0_POS 11										   /**< RSTR0_UART0 Position */
+#define MXC_F_GCR_RSTR0_UART0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_UART0_POS)) /**< RSTR0_UART0 Mask */
+
+#define MXC_F_GCR_RSTR0_SPI0_POS 13											 /**< RSTR0_SPI0 Position */
+#define MXC_F_GCR_RSTR0_SPI0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI0_POS)) /**< RSTR0_SPI0 Mask */
+
+#define MXC_F_GCR_RSTR0_SPI1_POS 14											 /**< RSTR0_SPI1 Position */
+#define MXC_F_GCR_RSTR0_SPI1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SPI1_POS)) /**< RSTR0_SPI1 Mask */
+
+#define MXC_F_GCR_RSTR0_I2C0_POS 16											 /**< RSTR0_I2C0 Position */
+#define MXC_F_GCR_RSTR0_I2C0 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_I2C0_POS)) /**< RSTR0_I2C0 Mask */
+
+#define MXC_F_GCR_RSTR0_CRYPTO_POS 18											 /**< RSTR0_CRYPTO Position */
+#define MXC_F_GCR_RSTR0_CRYPTO ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_CRYPTO_POS)) /**< RSTR0_CRYPTO Mask */
+
+#define MXC_F_GCR_RSTR0_SMPHR_POS 22										   /**< RSTR0_SMPHR Position */
+#define MXC_F_GCR_RSTR0_SMPHR ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SMPHR_POS)) /**< RSTR0_SMPHR Mask */
+
+#define MXC_F_GCR_RSTR0_TRNG_POS 24											 /**< RSTR0_TRNG Position */
+#define MXC_F_GCR_RSTR0_TRNG ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_TRNG_POS)) /**< RSTR0_TRNG Mask */
+
+#define MXC_F_GCR_RSTR0_SRST_POS 29											 /**< RSTR0_SRST Position */
+#define MXC_F_GCR_RSTR0_SRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SRST_POS)) /**< RSTR0_SRST Mask */
+
+#define MXC_F_GCR_RSTR0_PRST_POS 30											 /**< RSTR0_PRST Position */
+#define MXC_F_GCR_RSTR0_PRST ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_PRST_POS)) /**< RSTR0_PRST Mask */
+
+#define MXC_F_GCR_RSTR0_SYSTEM_POS 31											 /**< RSTR0_SYSTEM Position */
+#define MXC_F_GCR_RSTR0_SYSTEM ((uint32_t)(0x1UL << MXC_F_GCR_RSTR0_SYSTEM_POS)) /**< RSTR0_SYSTEM Mask */
+
+/**@} end of group GCR_RSTR0_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_CLKCN GCR_CLKCN
+ * @brief    Clock Control.
+ * @{
+ */
+#define MXC_F_GCR_CLKCN_PSC_POS 6														 /**< CLKCN_PSC Position */
+#define MXC_F_GCR_CLKCN_PSC ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_PSC_POS))				 /**< CLKCN_PSC Mask */
+#define MXC_V_GCR_CLKCN_PSC_DIV1 ((uint32_t)0x0UL)										 /**< CLKCN_PSC_DIV1 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV1 (MXC_V_GCR_CLKCN_PSC_DIV1 << MXC_F_GCR_CLKCN_PSC_POS)	 /**< CLKCN_PSC_DIV1 Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV2 ((uint32_t)0x1UL)										 /**< CLKCN_PSC_DIV2 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV2 (MXC_V_GCR_CLKCN_PSC_DIV2 << MXC_F_GCR_CLKCN_PSC_POS)	 /**< CLKCN_PSC_DIV2 Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV4 ((uint32_t)0x2UL)										 /**< CLKCN_PSC_DIV4 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV4 (MXC_V_GCR_CLKCN_PSC_DIV4 << MXC_F_GCR_CLKCN_PSC_POS)	 /**< CLKCN_PSC_DIV4 Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV8 ((uint32_t)0x3UL)										 /**< CLKCN_PSC_DIV8 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV8 (MXC_V_GCR_CLKCN_PSC_DIV8 << MXC_F_GCR_CLKCN_PSC_POS)	 /**< CLKCN_PSC_DIV8 Setting */
+#define MXC_V_GCR_CLKCN_PSC_DIV16 ((uint32_t)0x4UL)										 /**< CLKCN_PSC_DIV16 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV16 (MXC_V_GCR_CLKCN_PSC_DIV16 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV16 Setting  \
+																						  */
+#define MXC_V_GCR_CLKCN_PSC_DIV32 ((uint32_t)0x5UL)										 /**< CLKCN_PSC_DIV32 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV32 (MXC_V_GCR_CLKCN_PSC_DIV32 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV32 Setting  \
+																						  */
+#define MXC_V_GCR_CLKCN_PSC_DIV64 ((uint32_t)0x6UL)										 /**< CLKCN_PSC_DIV64 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV64 (MXC_V_GCR_CLKCN_PSC_DIV64 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV64 Setting  \
+																						  */
+#define MXC_V_GCR_CLKCN_PSC_DIV128 ((uint32_t)0x7UL)									 /**< CLKCN_PSC_DIV128 Value */
+#define MXC_S_GCR_CLKCN_PSC_DIV128                                                                                     \
+	(MXC_V_GCR_CLKCN_PSC_DIV128 << MXC_F_GCR_CLKCN_PSC_POS) /**< CLKCN_PSC_DIV128 Setting */
+
+#define MXC_F_GCR_CLKCN_CLKSEL_POS 9											 /**< CLKCN_CLKSEL Position */
+#define MXC_F_GCR_CLKCN_CLKSEL ((uint32_t)(0x7UL << MXC_F_GCR_CLKCN_CLKSEL_POS)) /**< CLKCN_CLKSEL Mask */
+#define MXC_V_GCR_CLKCN_CLKSEL_HIRC ((uint32_t)0x0UL)							 /**< CLKCN_CLKSEL_HIRC Value */
+#define MXC_S_GCR_CLKCN_CLKSEL_HIRC                                                                                    \
+	(MXC_V_GCR_CLKCN_CLKSEL_HIRC << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC Setting */
+#define MXC_V_GCR_CLKCN_CLKSEL_LIRC8 ((uint32_t)0x3UL)			/**< CLKCN_CLKSEL_LIRC8 Value */
+#define MXC_S_GCR_CLKCN_CLKSEL_LIRC8                                                                                   \
+	(MXC_V_GCR_CLKCN_CLKSEL_LIRC8 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_LIRC8 Setting */
+#define MXC_V_GCR_CLKCN_CLKSEL_HIRC8 ((uint32_t)0x5UL)			 /**< CLKCN_CLKSEL_HIRC8 Value */
+#define MXC_S_GCR_CLKCN_CLKSEL_HIRC8                                                                                   \
+	(MXC_V_GCR_CLKCN_CLKSEL_HIRC8 << MXC_F_GCR_CLKCN_CLKSEL_POS) /**< CLKCN_CLKSEL_HIRC8 Setting */
+
+#define MXC_F_GCR_CLKCN_CKRDY_POS 13										   /**< CLKCN_CKRDY Position */
+#define MXC_F_GCR_CLKCN_CKRDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_CKRDY_POS)) /**< CLKCN_CKRDY Mask */
+#define MXC_V_GCR_CLKCN_CKRDY_BUSY ((uint32_t)0x0UL)						   /**< CLKCN_CKRDY_BUSY Value */
+#define MXC_S_GCR_CLKCN_CKRDY_BUSY                                                                                     \
+	(MXC_V_GCR_CLKCN_CKRDY_BUSY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_BUSY Setting */
+#define MXC_V_GCR_CLKCN_CKRDY_READY ((uint32_t)0x1UL)		  /**< CLKCN_CKRDY_READY Value */
+#define MXC_S_GCR_CLKCN_CKRDY_READY                                                                                    \
+	(MXC_V_GCR_CLKCN_CKRDY_READY << MXC_F_GCR_CLKCN_CKRDY_POS) /**< CLKCN_CKRDY_READY Setting */
+
+#define MXC_F_GCR_CLKCN_HIRC_EN_POS 18											   /**< CLKCN_HIRC_EN Position */
+#define MXC_F_GCR_CLKCN_HIRC_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_EN_POS)) /**< CLKCN_HIRC_EN Mask */
+#define MXC_V_GCR_CLKCN_HIRC_EN_DIS ((uint32_t)0x0UL)							   /**< CLKCN_HIRC_EN_DIS Value */
+#define MXC_S_GCR_CLKCN_HIRC_EN_DIS                                                                                    \
+	(MXC_V_GCR_CLKCN_HIRC_EN_DIS << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_DIS Setting */
+#define MXC_V_GCR_CLKCN_HIRC_EN_EN ((uint32_t)0x1UL)			 /**< CLKCN_HIRC_EN_EN Value */
+#define MXC_S_GCR_CLKCN_HIRC_EN_EN                                                                                     \
+	(MXC_V_GCR_CLKCN_HIRC_EN_EN << MXC_F_GCR_CLKCN_HIRC_EN_POS) /**< CLKCN_HIRC_EN_EN Setting */
+
+#define MXC_F_GCR_CLKCN_HIRC8M_EN_POS 20											   /**< CLKCN_HIRC8M_EN Position */
+#define MXC_F_GCR_CLKCN_HIRC8M_EN ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_EN_POS)) /**< CLKCN_HIRC8M_EN Mask */
+
+#define MXC_F_GCR_CLKCN_HIRC8M_VS_POS 21											   /**< CLKCN_HIRC8M_VS Position */
+#define MXC_F_GCR_CLKCN_HIRC8M_VS ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_VS_POS)) /**< CLKCN_HIRC8M_VS Mask */
+#define MXC_V_GCR_CLKCN_HIRC8M_VS_VCOR ((uint32_t)0x0UL) /**< CLKCN_HIRC8M_VS_VCOR Value */
+#define MXC_S_GCR_CLKCN_HIRC8M_VS_VCOR                                                                                 \
+	(MXC_V_GCR_CLKCN_HIRC8M_VS_VCOR << MXC_F_GCR_CLKCN_HIRC8M_VS_POS) /**< CLKCN_HIRC8M_VS_VCOR Setting */
+#define MXC_V_GCR_CLKCN_HIRC8M_VS_1V ((uint32_t)0x1UL)				  /**< CLKCN_HIRC8M_VS_1V Value */
+#define MXC_S_GCR_CLKCN_HIRC8M_VS_1V                                                                                   \
+	(MXC_V_GCR_CLKCN_HIRC8M_VS_1V << MXC_F_GCR_CLKCN_HIRC8M_VS_POS) /**< CLKCN_HIRC8M_VS_1V Setting */
+
+#define MXC_F_GCR_CLKCN_HIRC_RDY_POS 26												 /**< CLKCN_HIRC_RDY Position */
+#define MXC_F_GCR_CLKCN_HIRC_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC_RDY_POS)) /**< CLKCN_HIRC_RDY Mask */
+#define MXC_V_GCR_CLKCN_HIRC_RDY_NOT ((uint32_t)0x0UL)								 /**< CLKCN_HIRC_RDY_NOT Value */
+#define MXC_S_GCR_CLKCN_HIRC_RDY_NOT                                                                                   \
+	(MXC_V_GCR_CLKCN_HIRC_RDY_NOT << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_NOT Setting */
+#define MXC_V_GCR_CLKCN_HIRC_RDY_READY ((uint32_t)0x1UL)		   /**< CLKCN_HIRC_RDY_READY Value */
+#define MXC_S_GCR_CLKCN_HIRC_RDY_READY                                                                                 \
+	(MXC_V_GCR_CLKCN_HIRC_RDY_READY << MXC_F_GCR_CLKCN_HIRC_RDY_POS) /**< CLKCN_HIRC_RDY_READY Setting */
+
+#define MXC_F_GCR_CLKCN_HIRC8M_RDY_POS 28 /**< CLKCN_HIRC8M_RDY Position */
+#define MXC_F_GCR_CLKCN_HIRC8M_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_HIRC8M_RDY_POS)) /**< CLKCN_HIRC8M_RDY Mask */
+
+#define MXC_F_GCR_CLKCN_LIRC8K_RDY_POS 29 /**< CLKCN_LIRC8K_RDY Position */
+#define MXC_F_GCR_CLKCN_LIRC8K_RDY ((uint32_t)(0x1UL << MXC_F_GCR_CLKCN_LIRC8K_RDY_POS)) /**< CLKCN_LIRC8K_RDY Mask */
+
+/**@} end of group GCR_CLKCN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PM GCR_PM
+ * @brief    Power Management.
+ * @{
+ */
+#define MXC_F_GCR_PM_MODE_POS 0														 /**< PM_MODE Position */
+#define MXC_F_GCR_PM_MODE ((uint32_t)(0x7UL << MXC_F_GCR_PM_MODE_POS))				 /**< PM_MODE Mask */
+#define MXC_V_GCR_PM_MODE_ACTIVE ((uint32_t)0x0UL)									 /**< PM_MODE_ACTIVE Value */
+#define MXC_S_GCR_PM_MODE_ACTIVE (MXC_V_GCR_PM_MODE_ACTIVE << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_ACTIVE Setting */
+#define MXC_V_GCR_PM_MODE_DEEPSLEEP ((uint32_t)0x2UL)								 /**< PM_MODE_DEEPSLEEP Value */
+#define MXC_S_GCR_PM_MODE_DEEPSLEEP                                                                                    \
+	(MXC_V_GCR_PM_MODE_DEEPSLEEP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_DEEPSLEEP Setting */
+#define MXC_V_GCR_PM_MODE_SHUTDOWN ((uint32_t)0x3UL)	   /**< PM_MODE_SHUTDOWN Value */
+#define MXC_S_GCR_PM_MODE_SHUTDOWN                                                                                     \
+	(MXC_V_GCR_PM_MODE_SHUTDOWN << MXC_F_GCR_PM_MODE_POS)							 /**< PM_MODE_SHUTDOWN Setting */
+#define MXC_V_GCR_PM_MODE_BACKUP ((uint32_t)0x4UL)									 /**< PM_MODE_BACKUP Value */
+#define MXC_S_GCR_PM_MODE_BACKUP (MXC_V_GCR_PM_MODE_BACKUP << MXC_F_GCR_PM_MODE_POS) /**< PM_MODE_BACKUP Setting */
+
+#define MXC_F_GCR_PM_GPIOWKEN_POS 4											   /**< PM_GPIOWKEN Position */
+#define MXC_F_GCR_PM_GPIOWKEN ((uint32_t)(0x1UL << MXC_F_GCR_PM_GPIOWKEN_POS)) /**< PM_GPIOWKEN Mask */
+#define MXC_V_GCR_PM_GPIOWKEN_DIS ((uint32_t)0x0UL)							   /**< PM_GPIOWKEN_DIS Value */
+#define MXC_S_GCR_PM_GPIOWKEN_DIS                                                                                      \
+	(MXC_V_GCR_PM_GPIOWKEN_DIS << MXC_F_GCR_PM_GPIOWKEN_POS)							 /**< PM_GPIOWKEN_DIS Setting */
+#define MXC_V_GCR_PM_GPIOWKEN_EN ((uint32_t)0x1UL)										 /**< PM_GPIOWKEN_EN Value */
+#define MXC_S_GCR_PM_GPIOWKEN_EN (MXC_V_GCR_PM_GPIOWKEN_EN << MXC_F_GCR_PM_GPIOWKEN_POS) /**< PM_GPIOWKEN_EN Setting   \
+																						  */
+
+#define MXC_F_GCR_PM_HIRCPD_POS 15										   /**< PM_HIRCPD Position */
+#define MXC_F_GCR_PM_HIRCPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRCPD_POS)) /**< PM_HIRCPD Mask */
+#define MXC_V_GCR_PM_HIRCPD_ACTIVE ((uint32_t)0x0UL)					   /**< PM_HIRCPD_ACTIVE Value */
+#define MXC_S_GCR_PM_HIRCPD_ACTIVE                                                                                     \
+	(MXC_V_GCR_PM_HIRCPD_ACTIVE << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_ACTIVE Setting */
+#define MXC_V_GCR_PM_HIRCPD_DEEPSLEEP ((uint32_t)0x1UL)		/**< PM_HIRCPD_DEEPSLEEP Value */
+#define MXC_S_GCR_PM_HIRCPD_DEEPSLEEP                                                                                  \
+	(MXC_V_GCR_PM_HIRCPD_DEEPSLEEP << MXC_F_GCR_PM_HIRCPD_POS) /**< PM_HIRCPD_DEEPSLEEP Setting */
+
+#define MXC_F_GCR_PM_HIRC8MPD_POS 17										   /**< PM_HIRC8MPD Position */
+#define MXC_F_GCR_PM_HIRC8MPD ((uint32_t)(0x1UL << MXC_F_GCR_PM_HIRC8MPD_POS)) /**< PM_HIRC8MPD Mask */
+
+/**@} end of group GCR_PM_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PCKDIV GCR_PCKDIV
+ * @brief    Peripheral Clock Divider.
+ * @{
+ */
+#define MXC_F_GCR_PCKDIV_PCF_POS 0											 /**< PCKDIV_PCF Position */
+#define MXC_F_GCR_PCKDIV_PCF ((uint32_t)(0x7UL << MXC_F_GCR_PCKDIV_PCF_POS)) /**< PCKDIV_PCF Mask */
+#define MXC_V_GCR_PCKDIV_PCF_96MHZ ((uint32_t)0x2UL)						 /**< PCKDIV_PCF_96MHZ Value */
+#define MXC_S_GCR_PCKDIV_PCF_96MHZ                                                                                     \
+	(MXC_V_GCR_PCKDIV_PCF_96MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_96MHZ Setting */
+#define MXC_V_GCR_PCKDIV_PCF_48MHZ ((uint32_t)0x3UL)		 /**< PCKDIV_PCF_48MHZ Value */
+#define MXC_S_GCR_PCKDIV_PCF_48MHZ                                                                                     \
+	(MXC_V_GCR_PCKDIV_PCF_48MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_48MHZ Setting */
+#define MXC_V_GCR_PCKDIV_PCF_24MHZ ((uint32_t)0x4UL)		 /**< PCKDIV_PCF_24MHZ Value */
+#define MXC_S_GCR_PCKDIV_PCF_24MHZ                                                                                     \
+	(MXC_V_GCR_PCKDIV_PCF_24MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_24MHZ Setting */
+#define MXC_V_GCR_PCKDIV_PCF_12MHZ ((uint32_t)0x5UL)		 /**< PCKDIV_PCF_12MHZ Value */
+#define MXC_S_GCR_PCKDIV_PCF_12MHZ                                                                                     \
+	(MXC_V_GCR_PCKDIV_PCF_12MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_12MHZ Setting */
+#define MXC_V_GCR_PCKDIV_PCF_6MHZ ((uint32_t)0x6UL)			 /**< PCKDIV_PCF_6MHZ Value */
+#define MXC_S_GCR_PCKDIV_PCF_6MHZ                                                                                      \
+	(MXC_V_GCR_PCKDIV_PCF_6MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_6MHZ Setting */
+#define MXC_V_GCR_PCKDIV_PCF_3MHZ ((uint32_t)0x7UL)			/**< PCKDIV_PCF_3MHZ Value */
+#define MXC_S_GCR_PCKDIV_PCF_3MHZ                                                                                      \
+	(MXC_V_GCR_PCKDIV_PCF_3MHZ << MXC_F_GCR_PCKDIV_PCF_POS) /**< PCKDIV_PCF_3MHZ Setting */
+
+#define MXC_F_GCR_PCKDIV_PCFWEN_POS 3											   /**< PCKDIV_PCFWEN Position */
+#define MXC_F_GCR_PCKDIV_PCFWEN ((uint32_t)(0x1UL << MXC_F_GCR_PCKDIV_PCFWEN_POS)) /**< PCKDIV_PCFWEN Mask */
+#define MXC_V_GCR_PCKDIV_PCFWEN_DISABLED ((uint32_t)0x0UL)						   /**< PCKDIV_PCFWEN_DISABLED Value */
+#define MXC_S_GCR_PCKDIV_PCFWEN_DISABLED                                                                               \
+	(MXC_V_GCR_PCKDIV_PCFWEN_DISABLED << MXC_F_GCR_PCKDIV_PCFWEN_POS) /**< PCKDIV_PCFWEN_DISABLED Setting */
+#define MXC_V_GCR_PCKDIV_PCFWEN_ENABLED ((uint32_t)0x1UL)			  /**< PCKDIV_PCFWEN_ENABLED Value */
+#define MXC_S_GCR_PCKDIV_PCFWEN_ENABLED                                                                                \
+	(MXC_V_GCR_PCKDIV_PCFWEN_ENABLED << MXC_F_GCR_PCKDIV_PCFWEN_POS) /**< PCKDIV_PCFWEN_ENABLED Setting */
+
+#define MXC_F_GCR_PCKDIV_AONCD_POS 14											 /**< PCKDIV_AONCD Position */
+#define MXC_F_GCR_PCKDIV_AONCD ((uint32_t)(0x3UL << MXC_F_GCR_PCKDIV_AONCD_POS)) /**< PCKDIV_AONCD Mask */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_4 ((uint32_t)0x0UL)							 /**< PCKDIV_AONCD_DIV_4 Value */
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_4                                                                                   \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_4 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_4 Setting */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_8 ((uint32_t)0x1UL)			 /**< PCKDIV_AONCD_DIV_8 Value */
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_8                                                                                   \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_8 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_8 Setting */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_16 ((uint32_t)0x2UL)			 /**< PCKDIV_AONCD_DIV_16 Value */
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_16                                                                                  \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_16 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_16 Setting */
+#define MXC_V_GCR_PCKDIV_AONCD_DIV_32 ((uint32_t)0x3UL)			  /**< PCKDIV_AONCD_DIV_32 Value */
+#define MXC_S_GCR_PCKDIV_AONCD_DIV_32                                                                                  \
+	(MXC_V_GCR_PCKDIV_AONCD_DIV_32 << MXC_F_GCR_PCKDIV_AONCD_POS) /**< PCKDIV_AONCD_DIV_32 Setting */
+
+/**@} end of group GCR_PCKDIV_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PERCKCN0 GCR_PERCKCN0
+ * @brief    Peripheral Clock Disable.
+ * @{
+ */
+#define MXC_F_GCR_PERCKCN0_GPIO0D_POS 0												   /**< PERCKCN0_GPIO0D Position */
+#define MXC_F_GCR_PERCKCN0_GPIO0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO0D_POS)) /**< PERCKCN0_GPIO0D Mask */
+#define MXC_V_GCR_PERCKCN0_GPIO0D_EN ((uint32_t)0x0UL)								   /**< PERCKCN0_GPIO0D_EN Value */
+#define MXC_S_GCR_PERCKCN0_GPIO0D_EN                                                                                   \
+	(MXC_V_GCR_PERCKCN0_GPIO0D_EN << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_EN Setting */
+#define MXC_V_GCR_PERCKCN0_GPIO0D_DIS ((uint32_t)0x1UL)				/**< PERCKCN0_GPIO0D_DIS Value */
+#define MXC_S_GCR_PERCKCN0_GPIO0D_DIS                                                                                  \
+	(MXC_V_GCR_PERCKCN0_GPIO0D_DIS << MXC_F_GCR_PERCKCN0_GPIO0D_POS) /**< PERCKCN0_GPIO0D_DIS Setting */
+
+#define MXC_F_GCR_PERCKCN0_GPIO1D_POS 1												   /**< PERCKCN0_GPIO1D Position */
+#define MXC_F_GCR_PERCKCN0_GPIO1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_GPIO1D_POS)) /**< PERCKCN0_GPIO1D Mask */
+
+#define MXC_F_GCR_PERCKCN0_DMAD_POS 5											   /**< PERCKCN0_DMAD Position */
+#define MXC_F_GCR_PERCKCN0_DMAD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_DMAD_POS)) /**< PERCKCN0_DMAD Mask */
+
+#define MXC_F_GCR_PERCKCN0_SPI0D_POS 6												 /**< PERCKCN0_SPI0D Position */
+#define MXC_F_GCR_PERCKCN0_SPI0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI0D_POS)) /**< PERCKCN0_SPI0D Mask */
+
+#define MXC_F_GCR_PERCKCN0_SPI1D_POS 7												 /**< PERCKCN0_SPI1D Position */
+#define MXC_F_GCR_PERCKCN0_SPI1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_SPI1D_POS)) /**< PERCKCN0_SPI1D Mask */
+
+#define MXC_F_GCR_PERCKCN0_UART0D_POS 9												   /**< PERCKCN0_UART0D Position */
+#define MXC_F_GCR_PERCKCN0_UART0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_UART0D_POS)) /**< PERCKCN0_UART0D Mask */
+
+#define MXC_F_GCR_PERCKCN0_I2C0D_POS 13												 /**< PERCKCN0_I2C0D Position */
+#define MXC_F_GCR_PERCKCN0_I2C0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_I2C0D_POS)) /**< PERCKCN0_I2C0D Mask */
+
+#define MXC_F_GCR_PERCKCN0_CRYPTOD_POS 14 /**< PERCKCN0_CRYPTOD Position */
+#define MXC_F_GCR_PERCKCN0_CRYPTOD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_CRYPTOD_POS)) /**< PERCKCN0_CRYPTOD Mask */
+
+#define MXC_F_GCR_PERCKCN0_T0D_POS 15											 /**< PERCKCN0_T0D Position */
+#define MXC_F_GCR_PERCKCN0_T0D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T0D_POS)) /**< PERCKCN0_T0D Mask */
+
+#define MXC_F_GCR_PERCKCN0_T1D_POS 16											 /**< PERCKCN0_T1D Position */
+#define MXC_F_GCR_PERCKCN0_T1D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T1D_POS)) /**< PERCKCN0_T1D Mask */
+
+#define MXC_F_GCR_PERCKCN0_T2D_POS 17											 /**< PERCKCN0_T2D Position */
+#define MXC_F_GCR_PERCKCN0_T2D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T2D_POS)) /**< PERCKCN0_T2D Mask */
+
+#define MXC_F_GCR_PERCKCN0_T3D_POS 18											 /**< PERCKCN0_T3D Position */
+#define MXC_F_GCR_PERCKCN0_T3D ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN0_T3D_POS)) /**< PERCKCN0_T3D Mask */
+
+/**@} end of group GCR_PERCKCN0_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_MEMCKCN GCR_MEMCKCN
+ * @brief    Memory Clock Control Register.
+ * @{
+ */
+#define MXC_F_GCR_MEMCKCN_FWS_POS 0											   /**< MEMCKCN_FWS Position */
+#define MXC_F_GCR_MEMCKCN_FWS ((uint32_t)(0x7UL << MXC_F_GCR_MEMCKCN_FWS_POS)) /**< MEMCKCN_FWS Mask */
+
+#define MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS 16 /**< MEMCKCN_SYSRAM0LS Position */
+#define MXC_F_GCR_MEMCKCN_SYSRAM0LS                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS))	 /**< MEMCKCN_SYSRAM0LS Mask */
+#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE ((uint32_t)0x0UL) /**< MEMCKCN_SYSRAM0LS_ACTIVE Value */
+#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_ACTIVE                                                                             \
+	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_ACTIVE << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_ACTIVE Setting */
+#define MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP ((uint32_t)0x1UL)			/**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Value */
+#define MXC_S_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                                                                        \
+	(MXC_V_GCR_MEMCKCN_SYSRAM0LS_LIGHT_SLEEP                                                                           \
+	 << MXC_F_GCR_MEMCKCN_SYSRAM0LS_POS) /**< MEMCKCN_SYSRAM0LS_LIGHT_SLEEP Setting */
+
+#define MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS 17 /**< MEMCKCN_SYSRAM1LS Position */
+#define MXC_F_GCR_MEMCKCN_SYSRAM1LS                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM1LS_POS)) /**< MEMCKCN_SYSRAM1LS Mask */
+
+#define MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS 18 /**< MEMCKCN_SYSRAM2LS Position */
+#define MXC_F_GCR_MEMCKCN_SYSRAM2LS                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM2LS_POS)) /**< MEMCKCN_SYSRAM2LS Mask */
+
+#define MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS 19 /**< MEMCKCN_SYSRAM3LS Position */
+#define MXC_F_GCR_MEMCKCN_SYSRAM3LS                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM3LS_POS)) /**< MEMCKCN_SYSRAM3LS Mask */
+
+#define MXC_F_GCR_MEMCKCN_SYSRAM4LS_POS 20 /**< MEMCKCN_SYSRAM4LS Position */
+#define MXC_F_GCR_MEMCKCN_SYSRAM4LS                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_SYSRAM4LS_POS)) /**< MEMCKCN_SYSRAM4LS Mask */
+
+#define MXC_F_GCR_MEMCKCN_ICACHELS_POS 24 /**< MEMCKCN_ICACHELS Position */
+#define MXC_F_GCR_MEMCKCN_ICACHELS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ICACHELS_POS)) /**< MEMCKCN_ICACHELS Mask */
+
+#define MXC_F_GCR_MEMCKCN_ROMLS_POS 29											   /**< MEMCKCN_ROMLS Position */
+#define MXC_F_GCR_MEMCKCN_ROMLS ((uint32_t)(0x1UL << MXC_F_GCR_MEMCKCN_ROMLS_POS)) /**< MEMCKCN_ROMLS Mask */
+
+/**@} end of group GCR_MEMCKCN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_MEMZCN GCR_MEMZCN
+ * @brief    Memory Zeroize Control.
+ * @{
+ */
+#define MXC_F_GCR_MEMZCN_SRAM0Z_POS 0											   /**< MEMZCN_SRAM0Z Position */
+#define MXC_F_GCR_MEMZCN_SRAM0Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM0Z_POS)) /**< MEMZCN_SRAM0Z Mask */
+#define MXC_V_GCR_MEMZCN_SRAM0Z_NOP ((uint32_t)0x0UL)							   /**< MEMZCN_SRAM0Z_NOP Value */
+#define MXC_S_GCR_MEMZCN_SRAM0Z_NOP                                                                                    \
+	(MXC_V_GCR_MEMZCN_SRAM0Z_NOP << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_NOP Setting */
+#define MXC_V_GCR_MEMZCN_SRAM0Z_START ((uint32_t)0x1UL)			 /**< MEMZCN_SRAM0Z_START Value */
+#define MXC_S_GCR_MEMZCN_SRAM0Z_START                                                                                  \
+	(MXC_V_GCR_MEMZCN_SRAM0Z_START << MXC_F_GCR_MEMZCN_SRAM0Z_POS) /**< MEMZCN_SRAM0Z_START Setting */
+
+#define MXC_F_GCR_MEMZCN_SRAM1Z_POS 1											   /**< MEMZCN_SRAM1Z Position */
+#define MXC_F_GCR_MEMZCN_SRAM1Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM1Z_POS)) /**< MEMZCN_SRAM1Z Mask */
+
+#define MXC_F_GCR_MEMZCN_SRAM2Z_POS 2											   /**< MEMZCN_SRAM2Z Position */
+#define MXC_F_GCR_MEMZCN_SRAM2Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM2Z_POS)) /**< MEMZCN_SRAM2Z Mask */
+
+#define MXC_F_GCR_MEMZCN_SRAM3Z_POS 3											   /**< MEMZCN_SRAM3Z Position */
+#define MXC_F_GCR_MEMZCN_SRAM3Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM3Z_POS)) /**< MEMZCN_SRAM3Z Mask */
+
+#define MXC_F_GCR_MEMZCN_SRAM4Z_POS 4											   /**< MEMZCN_SRAM4Z Position */
+#define MXC_F_GCR_MEMZCN_SRAM4Z ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_SRAM4Z_POS)) /**< MEMZCN_SRAM4Z Mask */
+
+#define MXC_F_GCR_MEMZCN_ICACHEZ_POS 8												 /**< MEMZCN_ICACHEZ Position */
+#define MXC_F_GCR_MEMZCN_ICACHEZ ((uint32_t)(0x1UL << MXC_F_GCR_MEMZCN_ICACHEZ_POS)) /**< MEMZCN_ICACHEZ Mask */
+
+/**@} end of group GCR_MEMZCN_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_SYSST GCR_SYSST
+ * @brief    System Status Register.
+ * @{
+ */
+#define MXC_F_GCR_SYSST_ICECLOCK_POS 0												 /**< SYSST_ICECLOCK Position */
+#define MXC_F_GCR_SYSST_ICECLOCK ((uint32_t)(0x1UL << MXC_F_GCR_SYSST_ICECLOCK_POS)) /**< SYSST_ICECLOCK Mask */
+#define MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED ((uint32_t)0x0UL) /**< SYSST_ICECLOCK_UNLOCKED Value */
+#define MXC_S_GCR_SYSST_ICECLOCK_UNLOCKED                                                                              \
+	(MXC_V_GCR_SYSST_ICECLOCK_UNLOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_UNLOCKED Setting */
+#define MXC_V_GCR_SYSST_ICECLOCK_LOCKED ((uint32_t)0x1UL)				/**< SYSST_ICECLOCK_LOCKED Value */
+#define MXC_S_GCR_SYSST_ICECLOCK_LOCKED                                                                                \
+	(MXC_V_GCR_SYSST_ICECLOCK_LOCKED << MXC_F_GCR_SYSST_ICECLOCK_POS) /**< SYSST_ICECLOCK_LOCKED Setting */
+
+/**@} end of group GCR_SYSST_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_RSTR1 GCR_RSTR1
+ * @brief    Reset 1.
+ * @{
+ */
+#define MXC_F_GCR_RSTR1_WDT1_POS 8											 /**< RSTR1_WDT1 Position */
+#define MXC_F_GCR_RSTR1_WDT1 ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_WDT1_POS)) /**< RSTR1_WDT1 Mask */
+#define MXC_V_GCR_RSTR1_WDT1_RESET_DONE ((uint32_t)0x0UL)					 /**< RSTR1_WDT1_RESET_DONE Value */
+#define MXC_S_GCR_RSTR1_WDT1_RESET_DONE                                                                                \
+	(MXC_V_GCR_RSTR1_WDT1_RESET_DONE << MXC_F_GCR_RSTR1_WDT1_POS) /**< RSTR1_WDT1_RESET_DONE Setting */
+#define MXC_V_GCR_RSTR1_WDT1_BUSY ((uint32_t)0x1UL)				  /**< RSTR1_WDT1_BUSY Value */
+#define MXC_S_GCR_RSTR1_WDT1_BUSY                                                                                      \
+	(MXC_V_GCR_RSTR1_WDT1_BUSY << MXC_F_GCR_RSTR1_WDT1_POS) /**< RSTR1_WDT1_BUSY Setting */
+
+#define MXC_F_GCR_RSTR1_PUFC_POS 27											 /**< RSTR1_PUFC Position */
+#define MXC_F_GCR_RSTR1_PUFC ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_PUFC_POS)) /**< RSTR1_PUFC Mask */
+
+#define MXC_F_GCR_RSTR1_CSPIS_POS 28										   /**< RSTR1_CSPIS Position */
+#define MXC_F_GCR_RSTR1_CSPIS ((uint32_t)(0x1UL << MXC_F_GCR_RSTR1_CSPIS_POS)) /**< RSTR1_CSPIS Mask */
+
+/**@} end of group GCR_RSTR1_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_PERCKCN1 GCR_PERCKCN1
+ * @brief    Peripheral Clock Disable.
+ * @{
+ */
+#define MXC_F_GCR_PERCKCN1_TRNGD_POS 2												 /**< PERCKCN1_TRNGD Position */
+#define MXC_F_GCR_PERCKCN1_TRNGD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_TRNGD_POS)) /**< PERCKCN1_TRNGD Mask */
+#define MXC_V_GCR_PERCKCN1_TRNGD_EN ((uint32_t)0x0UL)								 /**< PERCKCN1_TRNGD_EN Value */
+#define MXC_S_GCR_PERCKCN1_TRNGD_EN                                                                                    \
+	(MXC_V_GCR_PERCKCN1_TRNGD_EN << MXC_F_GCR_PERCKCN1_TRNGD_POS) /**< PERCKCN1_TRNGD_EN Setting */
+#define MXC_V_GCR_PERCKCN1_TRNGD_DIS ((uint32_t)0x1UL)			  /**< PERCKCN1_TRNGD_DIS Value */
+#define MXC_S_GCR_PERCKCN1_TRNGD_DIS                                                                                   \
+	(MXC_V_GCR_PERCKCN1_TRNGD_DIS << MXC_F_GCR_PERCKCN1_TRNGD_POS) /**< PERCKCN1_TRNGD_DIS Setting */
+
+#define MXC_F_GCR_PERCKCN1_PUFCD_POS 3												 /**< PERCKCN1_PUFCD Position */
+#define MXC_F_GCR_PERCKCN1_PUFCD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_PUFCD_POS)) /**< PERCKCN1_PUFCD Mask */
+
+#define MXC_F_GCR_PERCKCN1_ICACHED_POS 11 /**< PERCKCN1_ICACHED Position */
+#define MXC_F_GCR_PERCKCN1_ICACHED ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_ICACHED_POS)) /**< PERCKCN1_ICACHED Mask */
+
+#define MXC_F_GCR_PERCKCN1_CSPISD_POS 30											   /**< PERCKCN1_CSPISD Position */
+#define MXC_F_GCR_PERCKCN1_CSPISD ((uint32_t)(0x1UL << MXC_F_GCR_PERCKCN1_CSPISD_POS)) /**< PERCKCN1_CSPISD Mask */
+
+/**@} end of group GCR_PERCKCN1_Register */
+
+/**
+ * @ingroup  gcr_registers
+ * @defgroup GCR_EVTEN GCR_EVTEN
+ * @brief    Event Enable Register.
+ * @{
+ */
+#define MXC_F_GCR_EVTEN_CPU0DMAEVENT_POS 0 /**< EVTEN_CPU0DMAEVENT Position */
+#define MXC_F_GCR_EVTEN_CPU0DMAEVENT                                                                                   \
+	((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0DMAEVENT_POS)) /**< EVTEN_CPU0DMAEVENT Mask */
+
+#define MXC_F_GCR_EVTEN_CPU0RXEVENT_POS 1 /**< EVTEN_CPU0RXEVENT Position */
+#define MXC_F_GCR_EVTEN_CPU0RXEVENT                                                                                    \
+	((uint32_t)(0x1UL << MXC_F_GCR_EVTEN_CPU0RXEVENT_POS)) /**< EVTEN_CPU0RXEVENT Mask */
+
+#define MXC_F_GCR_EVTEN_CPU0TXEVENT_POS 2 /**< EVTEN_CPU0TXEVENT Position */
+#define MXC_F_GCR_EVTEN_CPU0TXEVENT                                                                                    \
+	((uint32_t)(0x1UL ...
 
[truncated message content]

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1119-g306114954

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  3061149545b2be806b9a382995a33f5a60af9555 (commit)
      from  003cb92cd505fee903794281041336e06cfa8c03 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 3061149545b2be806b9a382995a33f5a60af9555
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Aug 1 17:28:40 2025 +0200

    flash: at91sam7: align format strings to types
    
    Remove the cast and use the correct conversion specifier.
    
    Change-Id: Idd9fae8cb8858e1f2f098544eb2eaa80bf0c5597
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9066
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c
index a124e49df..093f7ea3e 100644
--- a/src/flash/nor/at91sam7.c
+++ b/src/flash/nor/at91sam7.c
@@ -277,7 +277,7 @@ static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode)
 		if (at91sam7_info->mck_freq > 30000000ul)
 			fws = 1;
 
-		LOG_DEBUG("fmcn[%i]: %i", bank->bank_number, (int)(fmcn));
+		LOG_DEBUG("fmcn[%u]: %" PRIu32, bank->bank_number, fmcn);
 		fmr = fmcn << 16 | fws << 8;
 		target_write_u32(target, mc_fmr[bank->bank_number], fmr);
 	}
@@ -291,11 +291,11 @@ static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t wait
 
 	while ((!((status = at91sam7_get_flash_status(bank->target,
 			bank->bank_number)) & waitbits)) && (timeout-- > 0)) {
-		LOG_DEBUG("status[%i]: 0x%" PRIx32, (int)bank->bank_number, status);
+		LOG_DEBUG("status[%u]: 0x%" PRIx32, bank->bank_number, status);
 		alive_sleep(1);
 	}
 
-	LOG_DEBUG("status[%i]: 0x%" PRIx32, bank->bank_number, status);
+	LOG_DEBUG("status[%u]: 0x%" PRIx32, bank->bank_number, status);
 
 	if (status & 0x0C) {
 		LOG_ERROR("status register: 0x%" PRIx32, status);
@@ -319,7 +319,7 @@ static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t
 
 	fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
 	target_write_u32(target, mc_fcr[bank->bank_number], fcr);
-	LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u",
+	LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %u, page number: %" PRIu16,
 		fcr,
 		bank->bank_number + 1,
 		pagen);

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/at91sam7.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1118-g003cb92cd

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  003cb92cd505fee903794281041336e06cfa8c03 (commit)
       via  9fe3780432847b717d308a224adc4bd50716976e (commit)
      from  37f638bb4c4231b5ddaab0c4656df25f5cbdb0f0 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 003cb92cd505fee903794281041336e06cfa8c03
Author: Antonio Borneo <bor...@gm...>
Date:   Fri Aug 1 17:06:05 2025 +0200

    openocd: drop empty string suffix from format strings
    
    Format strings are often split to allow using the conversion
    specifiers macros from <inttypes.h>.
    When the format string ends with one of such macros, there is no
    need to add an empty string "" after the macro.
    
    In current code we have 203 cases of empty string present, against
    1159 cases of string ending with the macro.
    
    Uniform the style across OpenOCD by removing the empty string.
    
    Don't modify the files 'angie.c' and 'max32xxx.c' as they are
    already changed by other independent commits.
    
    Change-Id: I23f1120101ce1da67c6578635fc6507a58c803e9
    Signed-off-by: Antonio Borneo <bor...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9065
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/at91sam7.c b/src/flash/nor/at91sam7.c
index 86c80765f..a124e49df 100644
--- a/src/flash/nor/at91sam7.c
+++ b/src/flash/nor/at91sam7.c
@@ -291,14 +291,14 @@ static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t wait
 
 	while ((!((status = at91sam7_get_flash_status(bank->target,
 			bank->bank_number)) & waitbits)) && (timeout-- > 0)) {
-		LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
+		LOG_DEBUG("status[%i]: 0x%" PRIx32, (int)bank->bank_number, status);
 		alive_sleep(1);
 	}
 
-	LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
+	LOG_DEBUG("status[%i]: 0x%" PRIx32, bank->bank_number, status);
 
 	if (status & 0x0C) {
-		LOG_ERROR("status register: 0x%" PRIx32 "", status);
+		LOG_ERROR("status register: 0x%" PRIx32, status);
 		if (status & 0x4)
 			LOG_ERROR("Lock Error Bit Detected, Operation Abort");
 		if (status & 0x8)
@@ -915,7 +915,7 @@ static int at91sam7_write(struct flash_bank *bank, const uint8_t *buffer, uint32
 	dst_min_alignment = at91sam7_info->pagesize;
 
 	if (offset % dst_min_alignment) {
-		LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
+		LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32,
 			offset,
 			dst_min_alignment);
 		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
diff --git a/src/flash/nor/atsamv.c b/src/flash/nor/atsamv.c
index d6d8938b6..56db23d36 100644
--- a/src/flash/nor/atsamv.c
+++ b/src/flash/nor/atsamv.c
@@ -310,7 +310,7 @@ static int samv_probe(struct flash_bank *bank)
 	int r = samv_get_device_id(bank, &device_id);
 	if (r != ERROR_OK)
 		return r;
-	LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
+	LOG_INFO("device id = 0x%08" PRIx32, device_id);
 
 	uint8_t eproc = (device_id >> 5) & 0x7;
 	if (eproc != 0) {
diff --git a/src/flash/nor/avrf.c b/src/flash/nor/avrf.c
index 1d317a10c..af8382249 100644
--- a/src/flash/nor/avrf.c
+++ b/src/flash/nor/avrf.c
@@ -126,7 +126,7 @@ static int avr_jtagprg_chiperase(struct avr_common *avr)
 			AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
 		if (mcu_execute_queue() != ERROR_OK)
 			return ERROR_FAIL;
-		LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
+		LOG_DEBUG("poll_value = 0x%04" PRIx32, poll_value);
 	} while (!(poll_value & 0x0200));
 
 	return ERROR_OK;
@@ -187,7 +187,7 @@ static int avr_jtagprg_writeflashpage(struct avr_common *avr,
 			AVR_JTAG_REG_PROGRAMMING_COMMAND_LEN);
 		if (mcu_execute_queue() != ERROR_OK)
 			return ERROR_FAIL;
-		LOG_DEBUG("poll_value = 0x%04" PRIx32 "", poll_value);
+		LOG_DEBUG("poll_value = 0x%04" PRIx32, poll_value);
 	} while (!(poll_value & 0x0200));
 
 	return ERROR_OK;
@@ -253,8 +253,8 @@ static int avrf_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t o
 		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 	}
 
-	LOG_DEBUG("offset is 0x%08" PRIx32 "", offset);
-	LOG_DEBUG("count is %" PRIu32 "", count);
+	LOG_DEBUG("offset is 0x%08" PRIx32, offset);
+	LOG_DEBUG("count is %" PRIu32, count);
 
 	if (avr_jtagprg_enterprogmode(avr) != ERROR_OK)
 		return ERROR_FAIL;
@@ -308,7 +308,7 @@ static int avrf_probe(struct flash_bank *bank)
 	if (mcu_execute_queue() != ERROR_OK)
 		return ERROR_FAIL;
 
-	LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
+	LOG_INFO("device id = 0x%08" PRIx32, device_id);
 	if (EXTRACT_MFG(device_id) != 0x1F)
 		LOG_ERROR("0x%" PRIx32 " is invalid Manufacturer for avr, 0x%X is expected",
 			EXTRACT_MFG(device_id),
@@ -373,7 +373,7 @@ static int avrf_info(struct flash_bank *bank, struct command_invocation *cmd)
 	if (mcu_execute_queue() != ERROR_OK)
 		return ERROR_FAIL;
 
-	LOG_INFO("device id = 0x%08" PRIx32 "", device_id);
+	LOG_INFO("device id = 0x%08" PRIx32, device_id);
 	if (EXTRACT_MFG(device_id) != 0x1F)
 		LOG_ERROR("0x%" PRIx32 " is invalid Manufacturer for avr, 0x%X is expected",
 			EXTRACT_MFG(device_id),
@@ -390,7 +390,7 @@ static int avrf_info(struct flash_bank *bank, struct command_invocation *cmd)
 
 	if (avr_info) {
 		/* chip found */
-		command_print_sameline(cmd, "%s - Rev: 0x%" PRIx32 "", avr_info->name,
+		command_print_sameline(cmd, "%s - Rev: 0x%" PRIx32, avr_info->name,
 			EXTRACT_VER(device_id));
 		return ERROR_OK;
 	} else {
diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 2a15e4913..fdc1682c3 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -2722,7 +2722,7 @@ int cfi_probe(struct flash_bank *bank)
 				if (retval != ERROR_OK)
 					return retval;
 				LOG_DEBUG(
-					"erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32 "",
+					"erase region[%i]: %" PRIu32 " blocks of size 0x%" PRIx32,
 					i,
 					(cfi_info->erase_region_info[i] & 0xffff) + 1,
 					(cfi_info->erase_region_info[i] >> 16) * 256);
@@ -2849,7 +2849,7 @@ int cfi_probe(struct flash_bank *bank)
 		}
 		if (offset != (cfi_info->dev_size * bank->bus_width / bank->chip_width)) {
 			LOG_WARNING(
-				"CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32 "",
+				"CFI size is 0x%" PRIx32 ", but total sector size is 0x%" PRIx32,
 				(cfi_info->dev_size * bank->bus_width / bank->chip_width),
 				offset);
 		}
diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index f8e088657..b011a69c7 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -430,7 +430,7 @@ static int efm32x_wait_status(struct flash_bank *bank, int timeout,
 		if (ret != ERROR_OK)
 			break;
 
-		LOG_DEBUG("status: 0x%" PRIx32 "", status);
+		LOG_DEBUG("status: 0x%" PRIx32, status);
 
 		if (((status & wait_mask) == 0) && (wait_for_set == 0))
 			break;
diff --git a/src/flash/nor/em357.c b/src/flash/nor/em357.c
index 207346f10..a41b5f8b7 100644
--- a/src/flash/nor/em357.c
+++ b/src/flash/nor/em357.c
@@ -115,7 +115,7 @@ static int em357_wait_status_busy(struct flash_bank *bank, int timeout)
 		retval = em357_get_flash_status(bank, &status);
 		if (retval != ERROR_OK)
 			return retval;
-		LOG_DEBUG("status: 0x%" PRIx32 "", status);
+		LOG_DEBUG("status: 0x%" PRIx32, status);
 		if ((status & FLASH_BSY) == 0)
 			break;
 		if (timeout-- <= 0) {
diff --git a/src/flash/nor/lpc288x.c b/src/flash/nor/lpc288x.c
index 3006db1cb..d7a4fdf24 100644
--- a/src/flash/nor/lpc288x.c
+++ b/src/flash/nor/lpc288x.c
@@ -279,7 +279,7 @@ static int lpc288x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
 			/* all writes must start on a sector boundary... */
 			if (offset % bank->sectors[i].size) {
 				LOG_INFO(
-					"offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
+					"offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32,
 					offset,
 					bank->sectors[i].size);
 				return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
@@ -293,7 +293,7 @@ static int lpc288x_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
 
 	/* Range check... */
 	if (first_sector == 0xffffffff || last_sector == 0xffffffff) {
-		LOG_INFO("Range check failed %" PRIx32 " %" PRIx32 "", offset, count);
+		LOG_INFO("Range check failed %" PRIx32 " %" PRIx32, offset, count);
 		return ERROR_FLASH_DST_OUT_OF_BANK;
 	}
 
diff --git a/src/flash/nor/mspm0.c b/src/flash/nor/mspm0.c
index 245fcdd0d..62fd5e8c4 100644
--- a/src/flash/nor/mspm0.c
+++ b/src/flash/nor/mspm0.c
@@ -429,7 +429,7 @@ static int mspm0_read_part_info(struct flash_bank *bank)
 		LOG_WARNING("Unknown Device ID[0x%" PRIx32 "], cannot identify target",
 			did);
 		LOG_DEBUG("did 0x%" PRIx32 ", traceid 0x%" PRIx32 ", userid 0x%" PRIx32
-			", flashram 0x%" PRIx32 "", did, mspm0_info->traceid, userid,
+			", flashram 0x%" PRIx32, did, mspm0_info->traceid, userid,
 			flashram);
 		return ERROR_FLASH_OPERATION_FAILED;
 	}
diff --git a/src/flash/nor/numicro.c b/src/flash/nor/numicro.c
index a0c6e0c81..5809494df 100644
--- a/src/flash/nor/numicro.c
+++ b/src/flash/nor/numicro.c
@@ -567,7 +567,7 @@ static int numicro_reg_unlock(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("protected = 0x%08" PRIx32 "", is_protected);
+	LOG_DEBUG("protected = 0x%08" PRIx32, is_protected);
 	if (is_protected == 0) {	/* means protected - so unlock it */
 		/* unlock flash registers */
 		retval = target_write_u32(target, NUMICRO_SYS_WRPROT - m_address_bias_offset, REG_KEY1);
@@ -828,7 +828,7 @@ static int numicro_protect_check(struct flash_bank *bank)
 	numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG0 - m_address_bias_offset, 0, &config[0]);
 	numicro_fmc_cmd(target, ISPCMD_READ, NUMICRO_CONFIG1 - m_address_bias_offset, 0, &config[1]);
 
-	LOG_DEBUG("CONFIG0: 0x%" PRIx32 ",CONFIG1: 0x%" PRIx32 "", config[0], config[1]);
+	LOG_DEBUG("CONFIG0: 0x%" PRIx32 ",CONFIG1: 0x%" PRIx32, config[0], config[1]);
 
 	if ((config[0] & (1<<7)) == 0)
 		LOG_INFO("CBS=0: Boot From LPROM");
@@ -908,7 +908,7 @@ static int numicro_erase(struct flash_bank *bank, unsigned int first,
 		if (retval != ERROR_OK)
 			return retval;
 		if ((status & ISPCON_ISPFF) != 0) {
-			LOG_DEBUG("failure: 0x%" PRIx32 "", status);
+			LOG_DEBUG("failure: 0x%" PRIx32, status);
 			/* if bit is set, then must write to it to clear it. */
 			retval = target_write_u32(target, NUMICRO_FLASH_ISPCON - m_address_bias_offset, (status | ISPCON_ISPFF));
 			if (retval != ERROR_OK)
@@ -1007,7 +1007,7 @@ static int numicro_write(struct flash_bank *bank, const uint8_t *buffer,
 	if (retval != ERROR_OK)
 		return retval;
 	if ((status & ISPCON_ISPFF) != 0) {
-		LOG_DEBUG("failure: 0x%" PRIx32 "", status);
+		LOG_DEBUG("failure: 0x%" PRIx32, status);
 		/* if bit is set, then must write to it to clear it. */
 		retval = target_write_u32(target,
 					  NUMICRO_FLASH_ISPCON - m_address_bias_offset,
@@ -1037,7 +1037,7 @@ static int numicro_get_cpu_type(struct target *target, const struct numicro_cpu_
 		return ERROR_FLASH_OPERATION_FAILED;
 	}
 
-	LOG_INFO("Device ID: 0x%08" PRIx32 "", part_id);
+	LOG_INFO("Device ID: 0x%08" PRIx32, part_id);
 	/* search part numbers */
 	for (size_t i = 0; i < ARRAY_SIZE(numicro_parts); i++) {
 		if (part_id == numicro_parts[i].partid) {
diff --git a/src/flash/nor/ocl.c b/src/flash/nor/ocl.c
index 61af908f5..f9d981ef9 100644
--- a/src/flash/nor/ocl.c
+++ b/src/flash/nor/ocl.c
@@ -82,9 +82,9 @@ static int ocl_erase(struct flash_bank *bank, unsigned int first,
 
 	if (dcc_buffer[1] != OCL_CMD_DONE) {
 		if (dcc_buffer[0] == OCL_ERASE_ALL)
-			LOG_ERROR("loader response to OCL_ERASE_ALL 0x%08" PRIx32 "", dcc_buffer[1]);
+			LOG_ERROR("loader response to OCL_ERASE_ALL 0x%08" PRIx32, dcc_buffer[1]);
 		else
-			LOG_ERROR("loader response to OCL_ERASE_BLOCK 0x%08" PRIx32 "", dcc_buffer[1]);
+			LOG_ERROR("loader response to OCL_ERASE_BLOCK 0x%08" PRIx32, dcc_buffer[1]);
 		return ERROR_FLASH_OPERATION_FAILED;
 	}
 
@@ -178,7 +178,7 @@ static int ocl_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of
 		}
 
 		if (dcc_buffer[0] != OCL_CMD_DONE) {
-			LOG_ERROR("loader response to OCL_FLASH_BLOCK 0x%08" PRIx32 "", dcc_buffer[0]);
+			LOG_ERROR("loader response to OCL_FLASH_BLOCK 0x%08" PRIx32, dcc_buffer[0]);
 			free(dcc_buffer);
 			return ERROR_FLASH_OPERATION_FAILED;
 		}
@@ -217,7 +217,7 @@ static int ocl_probe(struct flash_bank *bank)
 		return retval;
 
 	if (dcc_buffer[0] != OCL_CMD_DONE) {
-		LOG_ERROR("loader response to OCL_PROBE 0x%08" PRIx32 "", dcc_buffer[0]);
+		LOG_ERROR("loader response to OCL_PROBE 0x%08" PRIx32, dcc_buffer[0]);
 		return ERROR_FLASH_OPERATION_FAILED;
 	}
 
diff --git a/src/flash/nor/pic32mx.c b/src/flash/nor/pic32mx.c
index 982c9610a..59e67cfe2 100644
--- a/src/flash/nor/pic32mx.c
+++ b/src/flash/nor/pic32mx.c
@@ -608,7 +608,7 @@ static int pic32mx_write(struct flash_bank *bank, const uint8_t *buffer, uint32_
 	}
 
 	LOG_DEBUG("writing to flash at address " TARGET_ADDR_FMT " at offset 0x%8.8" PRIx32
-			" count: 0x%8.8" PRIx32 "", bank->base, offset, count);
+			" count: 0x%8.8" PRIx32, bank->base, offset, count);
 
 	if (offset & 0x3) {
 		LOG_WARNING("offset 0x%" PRIx32 "breaks required 4-byte alignment", offset);
@@ -900,7 +900,7 @@ COMMAND_HANDLER(pic32mx_handle_unlock_command)
 		mchip_cmd = MCHP_STATUS;
 		mips_ejtag_drscan_8(ejtag_info, &mchip_cmd);
 		if (timeout-- == 0) {
-			LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8 "", mchip_cmd);
+			LOG_DEBUG("timeout waiting for unlock: 0x%" PRIx8, mchip_cmd);
 			break;
 		}
 		alive_sleep(1);
diff --git a/src/flash/nor/psoc4.c b/src/flash/nor/psoc4.c
index 72cf0ee05..88f9b1310 100644
--- a/src/flash/nor/psoc4.c
+++ b/src/flash/nor/psoc4.c
@@ -178,7 +178,7 @@ static const char *psoc4_decode_chip_protection(uint8_t protection)
 	case PSOC4_CHIP_PROT_KILL:
 		return "protection KILL";
 	default:
-		LOG_WARNING("Unknown protection state 0x%02" PRIx8 "", protection);
+		LOG_WARNING("Unknown protection state 0x%02" PRIx8, protection);
 		return "";
 	}
 }
@@ -658,7 +658,7 @@ static int psoc4_write(struct flash_bank *bank, const uint8_t *buffer,
 			memset(row_buffer + chunk_size, bank->default_padded_value, psoc4_info->row_size - chunk_size);
 		}
 		memcpy(row_buffer + row_offset, buffer, chunk_size);
-		LOG_DEBUG("offset / row: 0x%08" PRIx32 " / %" PRIu32 ", size %" PRIu32 "",
+		LOG_DEBUG("offset / row: 0x%08" PRIx32 " / %" PRIu32 ", size %" PRIu32,
 				offset, row_offset, chunk_size);
 
 		uint32_t macro_idx = row_num / PSOC4_ROWS_PER_MACRO;
@@ -858,7 +858,7 @@ static int get_psoc4_info(struct flash_bank *bank, struct command_invocation *cm
 			"/0x%02" PRIx16 ", silicon id 0x%08" PRIx32,
 			psoc4_info->family_id, family_id, silicon_id);
 	else {
-		command_print_sameline(cmd, "%s silicon id 0x%08" PRIx32 "",
+		command_print_sameline(cmd, "%s silicon id 0x%08" PRIx32,
 			family->name, silicon_id);
 	}
 
diff --git a/src/flash/nor/qn908x.c b/src/flash/nor/qn908x.c
index 8cd7a2f04..a881d549b 100644
--- a/src/flash/nor/qn908x.c
+++ b/src/flash/nor/qn908x.c
@@ -257,7 +257,7 @@ static int qn908x_update_reg(struct target *target, target_addr_t reg,
 	}
 	if (mask == 0xffffffff) {
 		LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": ?? -> 0x%.08"
-				PRIx32 "", reg, new_value);
+				PRIx32, reg, new_value);
 	} else {
 		LOG_DEBUG("Updated reg at " TARGET_ADDR_FMT ": 0x%.08" PRIx32
 				" -> 0x%.08" PRIx32, reg, orig_value, new_value);
diff --git a/src/flash/nor/stellaris.c b/src/flash/nor/stellaris.c
index f7dcc6f0e..d0a32f970 100644
--- a/src/flash/nor/stellaris.c
+++ b/src/flash/nor/stellaris.c
@@ -573,13 +573,13 @@ static void stellaris_read_clock_info(struct flash_bank *bank)
 	unsigned long mainfreq;
 
 	target_read_u32(target, SCB_BASE | RCC, &rcc);
-	LOG_DEBUG("Stellaris RCC %" PRIx32 "", rcc);
+	LOG_DEBUG("Stellaris RCC %" PRIx32, rcc);
 
 	target_read_u32(target, SCB_BASE | RCC2, &rcc2);
-	LOG_DEBUG("Stellaris RCC2 %" PRIx32 "", rcc);
+	LOG_DEBUG("Stellaris RCC2 %" PRIx32, rcc);
 
 	target_read_u32(target, SCB_BASE | PLLCFG, &pllcfg);
-	LOG_DEBUG("Stellaris PLLCFG %" PRIx32 "", pllcfg);
+	LOG_DEBUG("Stellaris PLLCFG %" PRIx32, pllcfg);
 
 	stellaris_info->rcc = rcc;
 	stellaris_info->rcc2 = rcc2;
@@ -659,7 +659,7 @@ static int stellaris_read_part_info(struct flash_bank *bank)
 	target_read_u32(target, SCB_BASE | DID1, &did1);
 	target_read_u32(target, SCB_BASE | DC0, &stellaris_info->dc0);
 	target_read_u32(target, SCB_BASE | DC1, &stellaris_info->dc1);
-	LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32 "",
+	LOG_DEBUG("did0 0x%" PRIx32 ", did1 0x%" PRIx32 ", dc0 0x%" PRIx32 ", dc1 0x%" PRIx32,
 		  did0, did1, stellaris_info->dc0, stellaris_info->dc1);
 
 	ver = DID0_VER(did0);
@@ -871,7 +871,7 @@ static int stellaris_erase(struct flash_bank *bank, unsigned int first,
 		/* Check access violations */
 		target_read_u32(target, FLASH_CRIS, &flash_cris);
 		if (flash_cris & (AMASK)) {
-			LOG_WARNING("Error erasing flash page %i,  flash_cris 0x%" PRIx32 "",
+			LOG_WARNING("Error erasing flash page %i,  flash_cris 0x%" PRIx32,
 					banknr, flash_cris);
 			target_write_u32(target, FLASH_CRIS, 0);
 			return ERROR_FLASH_OPERATION_FAILED;
@@ -967,7 +967,7 @@ static int stellaris_protect(struct flash_bank *bank, int set,
 		/* Check access violations */
 		target_read_u32(target, FLASH_CRIS, &flash_cris);
 		if (flash_cris & (AMASK)) {
-			LOG_WARNING("Error setting flash page protection,  flash_cris 0x%" PRIx32 "", flash_cris);
+			LOG_WARNING("Error setting flash page protection,  flash_cris 0x%" PRIx32, flash_cris);
 			target_write_u32(target, FLASH_CRIS, 0);
 			return ERROR_FLASH_OPERATION_FAILED;
 		}
@@ -1035,7 +1035,7 @@ static int stellaris_write_block(struct flash_bank *bank,
 	if (wcount * 4 < buf_min)
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 
-	LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32 "",
+	LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " wcount=%08" PRIx32,
 			bank, buffer, offset, wcount);
 
 	/* flash write code */
@@ -1115,7 +1115,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32 "",
+	LOG_DEBUG("(bank=%p buffer=%p offset=%08" PRIx32 " count=%08" PRIx32,
 			bank, buffer, offset, count);
 
 	if (stellaris_info->did1 == 0)
@@ -1153,7 +1153,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
 				/* if an error occurred, we examine the reason, and quit */
 				target_read_u32(target, FLASH_CRIS, &flash_cris);
 
-				LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32 "", flash_cris);
+				LOG_ERROR("flash writing failed with CRIS: 0x%" PRIx32, flash_cris);
 				return ERROR_FLASH_OPERATION_FAILED;
 			}
 		} else {
@@ -1165,7 +1165,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
 
 	while (words_remaining > 0) {
 		if (!(address & 0xff))
-			LOG_DEBUG("0x%" PRIx32 "", address);
+			LOG_DEBUG("0x%" PRIx32, address);
 
 		/* Program one word */
 		target_write_u32(target, FLASH_FMA, address);
@@ -1189,7 +1189,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
 		memcpy(last_word, buffer+bytes_written, bytes_remaining);
 
 		if (!(address & 0xff))
-			LOG_DEBUG("0x%" PRIx32 "", address);
+			LOG_DEBUG("0x%" PRIx32, address);
 
 		/* Program one word */
 		target_write_u32(target, FLASH_FMA, address);
@@ -1205,7 +1205,7 @@ static int stellaris_write(struct flash_bank *bank, const uint8_t *buffer,
 	/* Check access violations */
 	target_read_u32(target, FLASH_CRIS, &flash_cris);
 	if (flash_cris & (AMASK)) {
-		LOG_DEBUG("flash_cris 0x%" PRIx32 "", flash_cris);
+		LOG_DEBUG("flash_cris 0x%" PRIx32, flash_cris);
 		return ERROR_FLASH_OPERATION_FAILED;
 	}
 	return ERROR_OK;
diff --git a/src/flash/nor/stm32f1x.c b/src/flash/nor/stm32f1x.c
index 5a3c2da66..f512a26e9 100644
--- a/src/flash/nor/stm32f1x.c
+++ b/src/flash/nor/stm32f1x.c
@@ -170,7 +170,7 @@ static int stm32x_wait_status_busy(struct flash_bank *bank, int timeout)
 		retval = stm32x_get_flash_status(bank, &status);
 		if (retval != ERROR_OK)
 			return retval;
-		LOG_DEBUG("status: 0x%" PRIx32 "", status);
+		LOG_DEBUG("status: 0x%" PRIx32, status);
 		if ((status & FLASH_BSY) == 0)
 			break;
 		if (timeout-- <= 0) {
@@ -825,7 +825,7 @@ static int stm32x_probe(struct flash_bank *bank)
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_INFO("device id = 0x%08" PRIx32 "", dbgmcu_idcode);
+	LOG_INFO("device id = 0x%08" PRIx32, dbgmcu_idcode);
 
 	uint16_t device_id = dbgmcu_idcode & 0xfff;
 	uint16_t rev_id = dbgmcu_idcode >> 16;
@@ -1444,8 +1444,8 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
 	if (optionbyte & (1 << OPT_ERROR))
 		command_print(CMD, "option byte complement error");
 
-	command_print(CMD, "option byte register = 0x%" PRIx32 "", optionbyte);
-	command_print(CMD, "write protection register = 0x%" PRIx32 "", protection);
+	command_print(CMD, "option byte register = 0x%" PRIx32, optionbyte);
+	command_print(CMD, "write protection register = 0x%" PRIx32, protection);
 
 	command_print(CMD, "read protection: %s",
 				(optionbyte & (1 << OPT_READOUT)) ? "on" : "off");
@@ -1465,7 +1465,7 @@ COMMAND_HANDLER(stm32x_handle_options_read_command)
 	if (stm32x_info->has_dual_banks)
 		command_print(CMD, "boot: bank %d", (optionbyte & (1 << OPT_BFB2)) ? 0 : 1);
 
-	command_print(CMD, "user data = 0x%02" PRIx16 "", user_data);
+	command_print(CMD, "user data = 0x%02" PRIx16, user_data);
 
 	return ERROR_OK;
 }
diff --git a/src/flash/nor/stm32l4x.c b/src/flash/nor/stm32l4x.c
index 8001aaf00..2da2c69fe 100644
--- a/src/flash/nor/stm32l4x.c
+++ b/src/flash/nor/stm32l4x.c
@@ -981,7 +981,7 @@ static int stm32l4_wait_status_busy(struct flash_bank *bank, int timeout)
 		retval = stm32l4_read_flash_reg_by_index(bank, STM32_FLASH_SR_INDEX, &status);
 		if (retval != ERROR_OK)
 			return retval;
-		LOG_DEBUG("status: 0x%" PRIx32 "", status);
+		LOG_DEBUG("status: 0x%" PRIx32, status);
 		if ((status & stm32l4_info->sr_bsy_mask) == 0)
 			break;
 		if (timeout-- <= 0) {
@@ -2419,7 +2419,7 @@ COMMAND_HANDLER(stm32l4_handle_option_read_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32 "", reg_addr, value);
+	command_print(CMD, "Option Register: <0x%" PRIx32 "> = 0x%" PRIx32, reg_addr, value);
 
 	return retval;
 }
diff --git a/src/flash/nor/stm32lx.c b/src/flash/nor/stm32lx.c
index 1459e942d..2c7563e95 100644
--- a/src/flash/nor/stm32lx.c
+++ b/src/flash/nor/stm32lx.c
@@ -745,7 +745,7 @@ static int stm32lx_probe(struct flash_bank *bank)
 
 	stm32lx_info->idcode = device_id;
 
-	LOG_DEBUG("device id = 0x%08" PRIx32 "", device_id);
+	LOG_DEBUG("device id = 0x%08" PRIx32, device_id);
 
 	for (n = 0; n < ARRAY_SIZE(stm32lx_parts); n++) {
 		if ((device_id & 0xfff) == stm32lx_parts[n].id) {
@@ -1204,7 +1204,7 @@ static int stm32lx_wait_until_bsy_clear_timeout(struct flash_bank *bank, int tim
 		if (retval != ERROR_OK)
 			return retval;
 
-		LOG_DEBUG("status: 0x%" PRIx32 "", status);
+		LOG_DEBUG("status: 0x%" PRIx32, status);
 		if ((status & FLASH_SR__BSY) == 0)
 			break;
 
diff --git a/src/flash/nor/str7x.c b/src/flash/nor/str7x.c
index b91e22e04..5ba5bfa6d 100644
--- a/src/flash/nor/str7x.c
+++ b/src/flash/nor/str7x.c
@@ -335,7 +335,7 @@ static int str7x_erase(struct flash_bank *bank, unsigned int first,
 	for (unsigned int i = first; i <= last; i++)
 		sectors |= str7x_info->sector_bits[i];
 
-	LOG_DEBUG("sectors: 0x%" PRIx32 "", sectors);
+	LOG_DEBUG("sectors: 0x%" PRIx32, sectors);
 
 	/* clear FLASH_ER register */
 	err = target_write_u32(target, str7x_get_flash_adr(bank, FLASH_ER), 0x0);
diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c
index eff7df5a1..a5058b405 100644
--- a/src/flash/nor/str9xpec.c
+++ b/src/flash/nor/str9xpec.c
@@ -735,7 +735,7 @@ COMMAND_HANDLER(str9xpec_handle_part_id_command)
 
 	idcode = buf_get_u32(buffer, 0, 32);
 
-	command_print(CMD, "str9xpec part id: 0x%8.8" PRIx32 "", idcode);
+	command_print(CMD, "str9xpec part id: 0x%8.8" PRIx32, idcode);
 
 	free(buffer);
 
diff --git a/src/flash/nor/tms470.c b/src/flash/nor/tms470.c
index 00ee77bb8..ba730daaf 100644
--- a/src/flash/nor/tms470.c
+++ b/src/flash/nor/tms470.c
@@ -125,7 +125,7 @@ static int tms470_read_part_info(struct flash_bank *bank)
 	/* read and parse the device identification register */
 	target_read_u32(target, 0xFFFFFFF0, &device_ident_reg);
 
-	LOG_INFO("device_ident_reg = 0x%08" PRIx32 "", device_ident_reg);
+	LOG_INFO("device_ident_reg = 0x%08" PRIx32, device_ident_reg);
 
 	if ((device_ident_reg & 7) == 0) {
 		LOG_WARNING("Cannot identify target as a TMS470 family.");
@@ -300,7 +300,7 @@ COMMAND_HANDLER(tms470_handle_flash_keyset_command)
 
 	if (keys_set) {
 		command_print(CMD,
-			"using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 "",
+			"using flash keys 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32 ", 0x%08" PRIx32,
 			flash_keys[0],
 			flash_keys[1],
 			flash_keys[2],
@@ -419,7 +419,7 @@ static int tms470_try_flash_keys(struct target *target, const uint32_t *key_set)
 			 */
 			target_read_u32(target, 0x00001FF0 + 4 * i, &tmp);
 
-			LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32 "", key_set[i]);
+			LOG_INFO("tms470 writing fmpkey = 0x%08" PRIx32, key_set[i]);
 			target_write_u32(target, 0xFFE89C0C, key_set[i]);
 		}
 
@@ -500,7 +500,7 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban
 	fmmac2 &= ~0x0007;
 	fmmac2 |= (tms470_info->ordinal & 7);
 	target_write_u32(target, 0xFFE8BC04, fmmac2);
-	LOG_DEBUG("set fmmac2 = 0x%04" PRIx32 "", fmmac2);
+	LOG_DEBUG("set fmmac2 = 0x%04" PRIx32, fmmac2);
 
 	/*
 	 * Disable level 1 sector protection by setting bit 15 of FMMAC1.
@@ -508,7 +508,7 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban
 	target_read_u32(target, 0xFFE8BC00, &fmmac1);
 	fmmac1 |= 0x8000;
 	target_write_u32(target, 0xFFE8BC00, fmmac1);
-	LOG_DEBUG("set fmmac1 = 0x%04" PRIx32 "", fmmac1);
+	LOG_DEBUG("set fmmac1 = 0x%04" PRIx32, fmmac1);
 
 	/*
 	 * FMTCREG = 0x2fc0;
@@ -542,7 +542,7 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban
 		LOG_DEBUG("set fmptr3 = 0x9b64");
 	}
 	target_write_u32(target, 0xFFE8A080, fmmaxep);
-	LOG_DEBUG("set fmmaxep = 0x%04" PRIx32 "", fmmaxep);
+	LOG_DEBUG("set fmmaxep = 0x%04" PRIx32, fmmaxep);
 
 	/*
 	 * FMPTR4 = 0xa000
@@ -562,56 +562,56 @@ static int tms470_flash_initialize_internal_state_machine(struct flash_bank *ban
 	sysclk = (plldis ? 1 : (glbctrl & 0x08) ? 4 : 8) * osc_mhz / (1 + (glbctrl & 7));
 	delay = (sysclk > 10) ? (sysclk + 1) / 2 : 5;
 	target_write_u32(target, 0xFFE8A018, (delay << 4) | (delay << 8));
-	LOG_DEBUG("set fmpsetup = 0x%04" PRIx32 "", (delay << 4) | (delay << 8));
+	LOG_DEBUG("set fmpsetup = 0x%04" PRIx32, (delay << 4) | (delay << 8));
 
 	/*
 	 * FMPVEVACCESS, based on delay.
 	 */
 	k = delay | (delay << 8);
 	target_write_u32(target, 0xFFE8A05C, k);
-	LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32 "", k);
+	LOG_DEBUG("set fmpvevaccess = 0x%04" PRIx32, k);
 
 	/*
 	 * FMPCHOLD, FMPVEVHOLD, FMPVEVSETUP, based on delay.
 	 */
 	k <<= 1;
 	target_write_u32(target, 0xFFE8A034, k);
-	LOG_DEBUG("set fmpchold = 0x%04" PRIx32 "", k);
+	LOG_DEBUG("set fmpchold = 0x%04" PRIx32, k);
 	target_write_u32(target, 0xFFE8A040, k);
-	LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32 "", k);
+	LOG_DEBUG("set fmpvevhold = 0x%04" PRIx32, k);
 	target_write_u32(target, 0xFFE8A024, k);
-	LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32 "", k);
+	LOG_DEBUG("set fmpvevsetup = 0x%04" PRIx32, k);
 
 	/*
 	 * FMCVACCESS, based on delay.
 	 */
 	k = delay * 16;
 	target_write_u32(target, 0xFFE8A060, k);
-	LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32 "", k);
+	LOG_DEBUG("set fmcvaccess = 0x%04" PRIx32, k);
 
 	/*
 	 * FMCSETUP, based on delay.
 	 */
 	k = 0x3000 | delay * 20;
 	target_write_u32(target, 0xFFE8A020, k);
-	LOG_DEBUG("set fmcsetup = 0x%04" PRIx32 "", k);
+	LOG_DEBUG("set fmcsetup = 0x%04" PRIx32, k);
 
 	/*
 	 * FMEHOLD, based on delay.
 	 */
 	k = (delay * 20) << 2;
 	target_write_u32(target, 0xFFE8A038, k);
-	LOG_DEBUG("set fmehold = 0x%04" PRIx32 "", k);
+	LOG_DEBUG("set fmehold = 0x%04" PRIx32, k);
 
 	/*
 	 * PWIDTH, CWIDTH, EWIDTH, based on delay.
 	 */
 	target_write_u32(target, 0xFFE8A050, delay * 8);
-	LOG_DEBUG("set fmpwidth = 0x%04" PRIx32 "", delay * 8);
+	LOG_DEBUG("set fmpwidth = 0x%04" PRIx32, delay * 8);
 	target_write_u32(target, 0xFFE8A058, delay * 1000);
-	LOG_DEBUG("set fmcwidth = 0x%04" PRIx32 "", delay * 1000);
+	LOG_DEBUG("set fmcwidth = 0x%04" PRIx32, delay * 1000);
 	target_write_u32(target, 0xFFE8A054, delay * 5400);
-	LOG_DEBUG("set fmewidth = 0x%04" PRIx32 "", delay * 5400);
+	LOG_DEBUG("set fmewidth = 0x%04" PRIx32, delay * 5400);
 
 	return result;
 }
@@ -625,7 +625,7 @@ static int tms470_flash_status(struct flash_bank *bank)
 	uint32_t fmmstat;
 
 	target_read_u32(target, 0xFFE8BC0C, &fmmstat);
-	LOG_DEBUG("set fmmstat = 0x%04" PRIx32 "", fmmstat);
+	LOG_DEBUG("set fmmstat = 0x%04" PRIx32, fmmstat);
 
 	if (fmmstat & 0x0080) {
 		LOG_WARNING("tms470 flash command: erase still active after busy clear.");
@@ -680,7 +680,7 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
 	 */
 	target_read_u32(target, 0xFFFFFFDC, &glbctrl);
 	target_write_u32(target, 0xFFFFFFDC, glbctrl | 0x10);
-	LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl | 0x10);
+	LOG_DEBUG("set glbctrl = 0x%08" PRIx32, glbctrl | 0x10);
 
 	/* Force normal read mode. */
 	target_read_u32(target, 0xFFE89C00, &orig_fmregopt);
@@ -697,11 +697,11 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
 	if (sector < 16) {
 		target_read_u32(target, 0xFFE88008, &fmbsea);
 		target_write_u32(target, 0xFFE88008, fmbsea | (1 << sector));
-		LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea | (1 << sector));
+		LOG_DEBUG("set fmbsea = 0x%04" PRIx32, fmbsea | (1 << sector));
 	} else {
 		target_read_u32(target, 0xFFE8800C, &fmbseb);
 		target_write_u32(target, 0xFFE8800C, fmbseb | (1 << (sector - 16)));
-		LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb | (1 << (sector - 16)));
+		LOG_DEBUG("set fmbseb = 0x%04" PRIx32, fmbseb | (1 << (sector - 16)));
 	}
 	bank->sectors[sector].is_protected = 0;
 
@@ -729,17 +729,17 @@ static int tms470_erase_sector(struct flash_bank *bank, int sector)
 
 	if (sector < 16) {
 		target_write_u32(target, 0xFFE88008, fmbsea);
-		LOG_DEBUG("set fmbsea = 0x%04" PRIx32 "", fmbsea);
+		LOG_DEBUG("set fmbsea = 0x%04" PRIx32, fmbsea);
 		bank->sectors[sector].is_protected = fmbsea & (1 << sector) ? 0 : 1;
 	} else {
 		target_write_u32(target, 0xFFE8800C, fmbseb);
-		LOG_DEBUG("set fmbseb = 0x%04" PRIx32 "", fmbseb);
+		LOG_DEBUG("set fmbseb = 0x%04" PRIx32, fmbseb);
 		bank->sectors[sector].is_protected = fmbseb & (1 << (sector - 16)) ? 0 : 1;
 	}
 	target_write_u32(target, 0xFFE89C00, orig_fmregopt);
-	LOG_DEBUG("set fmregopt = 0x%08" PRIx32 "", orig_fmregopt);
+	LOG_DEBUG("set fmregopt = 0x%08" PRIx32, orig_fmregopt);
 	target_write_u32(target, 0xFFFFFFDC, glbctrl);
-	LOG_DEBUG("set glbctrl = 0x%08" PRIx32 "", glbctrl);
+	LOG_DEBUG("set glbctrl = 0x%08" PRIx32, glbctrl);
 
 	return result;
 }
@@ -920,7 +920,7 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
 		uint16_t word = (((uint16_t) buffer[i]) << 8) | (uint16_t) buffer[i + 1];
 
 		if (word != 0xffff) {
-			LOG_INFO("writing 0x%04x at 0x%08" PRIx32 "", word, addr);
+			LOG_INFO("writing 0x%04x at 0x%08" PRIx32, word, addr);
 
 			/* clear status register */
 			target_write_u16(target, addr, 0x0040);
@@ -940,7 +940,7 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
 			} while (fmmstat & 0x0100);
 
 			if (fmmstat & 0x3ff) {
-				LOG_ERROR("fmstat = 0x%04" PRIx32 "", fmmstat);
+				LOG_ERROR("fmstat = 0x%04" PRIx32, fmmstat);
 				LOG_ERROR(
 					"Could not program word 0x%04x at address 0x%08" PRIx32 ".",
 					word,
@@ -949,7 +949,7 @@ static int tms470_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t
 				break;
 			}
 		} else
-			LOG_INFO("skipping 0xffff at 0x%08" PRIx32 "", addr);
+			LOG_INFO("skipping 0xffff at 0x%08" PRIx32, addr);
 	}
 
 	/* restore */
diff --git a/src/flash/nor/w600.c b/src/flash/nor/w600.c
index 20968dcaa..ba4a42969 100644
--- a/src/flash/nor/w600.c
+++ b/src/flash/nor/w600.c
@@ -128,13 +128,13 @@ static int w600_start_do(struct flash_bank *bank, uint32_t cmd, uint32_t addr,
 	if (len > 0)
 		cmd |= QFLASH_CMD_DATALEN(len - 1) | QFLASH_CMD_DATA;
 
-	LOG_DEBUG("WRITE CMD: 0x%08" PRIx32 "", cmd);
+	LOG_DEBUG("WRITE CMD: 0x%08" PRIx32, cmd);
 	int retval = target_write_u32(target, QFLASH_CMD_INFO, cmd);
 	if (retval != ERROR_OK)
 		return retval;
 
 	addr |= QFLASH_START;
-	LOG_DEBUG("WRITE START: 0x%08" PRIx32 "", addr);
+	LOG_DEBUG("WRITE START: 0x%08" PRIx32, addr);
 	retval = target_write_u32(target, QFLASH_CMD_START, addr);
 	if (retval != ERROR_OK)
 		return retval;
@@ -148,7 +148,7 @@ static int w600_start_do(struct flash_bank *bank, uint32_t cmd, uint32_t addr,
 		LOG_DEBUG("READ START...");
 		retval = target_read_u32(target, QFLASH_CMD_START, &status);
 		if (retval == ERROR_OK)
-			LOG_DEBUG("READ START: 0x%08" PRIx32 "", status);
+			LOG_DEBUG("READ START: 0x%08" PRIx32, status);
 		else
 			LOG_DEBUG("READ START FAILED");
 
@@ -283,7 +283,7 @@ static int w600_probe(struct flash_bank *bank)
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_INFO("flash_id id = 0x%08" PRIx32 "", flash_id);
+	LOG_INFO("flash_id id = 0x%08" PRIx32, flash_id);
 	w600_info->id = flash_id;
 	w600_info->param = NULL;
 	for (i = 0; i < ARRAY_SIZE(w600_param); i++) {
@@ -360,7 +360,7 @@ static int get_w600_info(struct flash_bank *bank, struct command_invocation *cmd
 	if (retval != ERROR_OK)
 		return retval;
 
-	command_print_sameline(cmd, "w600 : 0x%08" PRIx32 "", flash_id);
+	command_print_sameline(cmd, "w600 : 0x%08" PRIx32, flash_id);
 	return ERROR_OK;
 }
 
diff --git a/src/jtag/drivers/jlink.c b/src/jtag/drivers/jlink.c
index f6bb3099d..b8716fa9a 100644
--- a/src/jtag/drivers/jlink.c
+++ b/src/jtag/drivers/jlink.c
@@ -241,7 +241,7 @@ static void jlink_execute_scan(struct jtag_command *cmd)
 
 static void jlink_execute_sleep(struct jtag_command *cmd)
 {
-	LOG_DEBUG_IO("sleep %" PRIu32 "", cmd->cmd.sleep->us);
+	LOG_DEBUG_IO("sleep %" PRIu32, cmd->cmd.sleep->us);
 	jlink_flush();
 	jtag_sleep(cmd->cmd.sleep->us);
 }
diff --git a/src/jtag/drivers/parport.c b/src/jtag/drivers/parport.c
index 143f3bde1..433c20c89 100644
--- a/src/jtag/drivers/parport.c
+++ b/src/jtag/drivers/parport.c
@@ -408,7 +408,7 @@ COMMAND_HANDLER(parport_handle_port_command)
 		}
 	}
 
-	command_print(CMD, "parport port = 0x%" PRIx16 "", parport_port);
+	command_print(CMD, "parport port = 0x%" PRIx16, parport_port);
 
 	return ERROR_OK;
 }
diff --git a/src/jtag/drivers/xlnx-xvc.c b/src/jtag/drivers/xlnx-xvc.c
index 6b3359538..f00650671 100644
--- a/src/jtag/drivers/xlnx-xvc.c
+++ b/src/jtag/drivers/xlnx-xvc.c
@@ -424,7 +424,7 @@ out_err:
 
 static void xlnx_xvc_execute_sleep(struct jtag_command *cmd)
 {
-	LOG_DEBUG("sleep %" PRIu32 "", cmd->cmd.sleep->us);
+	LOG_DEBUG("sleep %" PRIu32, cmd->cmd.sleep->us);
 	usleep(cmd->cmd.sleep->us);
 }
 
diff --git a/src/pld/xilinx_bit.c b/src/pld/xilinx_bit.c
index e4cc52ef9..1c04c7490 100644
--- a/src/pld/xilinx_bit.c
+++ b/src/pld/xilinx_bit.c
@@ -113,7 +113,7 @@ int xilinx_read_bit_file(struct xilinx_bit_file *bit_file, const char *filename)
 		return ERROR_PLD_FILE_LOAD_FAILED;
 	}
 
-	LOG_DEBUG("bit_file: %s %s %s,%s %" PRIu32 "", bit_file->source_file, bit_file->part_name,
+	LOG_DEBUG("bit_file: %s %s %s,%s %" PRIu32, bit_file->source_file, bit_file->part_name,
 		bit_file->date, bit_file->time, bit_file->length);
 
 	fclose(input_file);
diff --git a/src/rtos/ecos.c b/src/rtos/ecos.c
index a70084b4f..7b993c6f2 100644
--- a/src/rtos/ecos.c
+++ b/src/rtos/ecos.c
@@ -1004,7 +1004,7 @@ static int ecos_update_threads(struct rtos *rtos)
 		if (tr_extra && reason_desc)
 			soff += snprintf(&eistr[soff], (eilen - soff), " (%s)", reason_desc);
 		if (pri_extra)
-			(void)snprintf(&eistr[soff], (eilen - soff), ", Priority: %" PRId64 "", priority);
+			(void)snprintf(&eistr[soff], (eilen - soff), ", Priority: %" PRId64, priority);
 		rtos->thread_details[tasks_found].extra_info_str = eistr;
 
 		rtos->thread_details[tasks_found].exists = true;
@@ -1073,7 +1073,7 @@ static int ecos_get_thread_reg_list(struct rtos *rtos, int64_t thread_id,
 				param->uid_width,
 				(uint8_t *)&id);
 		if (retval != ERROR_OK) {
-			LOG_ERROR("Error reading unique id from eCos thread 0x%08" PRIX32 "", thread_index);
+			LOG_ERROR("Error reading unique id from eCos thread 0x%08" PRIX32, thread_index);
 			return retval;
 		}
 
diff --git a/src/server/gdb_server.c b/src/server/gdb_server.c
index 3eba15070..e06412db5 100644
--- a/src/server/gdb_server.c
+++ b/src/server/gdb_server.c
@@ -1557,7 +1557,7 @@ static int gdb_read_memory_packet(struct connection *connection,
 
 	buffer = malloc(len);
 
-	LOG_DEBUG("addr: 0x%16.16" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len);
+	LOG_DEBUG("addr: 0x%16.16" PRIx64 ", len: 0x%8.8" PRIx32, addr, len);
 
 	retval = ERROR_NOT_IMPLEMENTED;
 	if (target->rtos)
@@ -1629,7 +1629,7 @@ static int gdb_write_memory_packet(struct connection *connection,
 
 	buffer = malloc(len);
 
-	LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len);
+	LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32, addr, len);
 
 	if (unhexify(buffer, separator, len) != len)
 		LOG_ERROR("unable to decode memory packet");
@@ -1705,7 +1705,7 @@ static int gdb_write_memory_binary_packet(struct connection *connection,
 	}
 
 	if (len) {
-		LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32 "", addr, len);
+		LOG_DEBUG("addr: 0x%" PRIx64 ", len: 0x%8.8" PRIx32, addr, len);
 
 		retval = ERROR_NOT_IMPLEMENTED;
 		if (target->rtos)
@@ -2874,7 +2874,7 @@ static int gdb_query_packet(struct connection *connection,
 			gdb_connection->output_flag = GDB_OUTPUT_NO;
 
 			if (retval == ERROR_OK) {
-				snprintf(gdb_reply, 10, "C%8.8" PRIx32 "", checksum);
+				snprintf(gdb_reply, 10, "C%8.8" PRIx32, checksum);
 				gdb_put_packet(connection, gdb_reply, 9);
 			} else {
 				retval = gdb_error(connection, retval);
diff --git a/src/target/arm11.c b/src/target/arm11.c
index 583830f94..f5331408b 100644
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -469,7 +469,7 @@ static int arm11_resume(struct target *target, bool current,
 
 		for (bp = target->breakpoints; bp; bp = bp->next) {
 			if (bp->address == address) {
-				LOG_DEBUG("must step over %08" TARGET_PRIxADDR "", bp->address);
+				LOG_DEBUG("must step over %08" TARGET_PRIxADDR, bp->address);
 				arm11_step(target, true, 0, false);
 				break;
 			}
@@ -802,7 +802,7 @@ static int arm11_read_memory_inner(struct target *target,
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "",
+	LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32,
 		address,
 		size,
 		count);
@@ -900,7 +900,7 @@ static int arm11_write_memory_inner(struct target *target,
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32 "",
+	LOG_DEBUG("ADDR %08" PRIx32 "  SIZE %08" PRIx32 "  COUNT %08" PRIx32,
 		address,
 		size,
 		count);
@@ -1264,7 +1264,7 @@ COMMAND_HANDLER(arm11_handle_vcr)
 			return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	LOG_INFO("VCR 0x%08" PRIx32 "", arm11->vcr);
+	LOG_INFO("VCR 0x%08" PRIx32, arm11->vcr);
 	return ERROR_OK;
 }
 
diff --git a/src/target/arm720t.c b/src/target/arm720t.c
index 702d6cfb1..7098aa472 100644
--- a/src/target/arm720t.c
+++ b/src/target/arm720t.c
@@ -197,7 +197,7 @@ static int arm720t_post_debug_entry(struct target *target)
 	retval = jtag_execute_queue();
 	if (retval != ERROR_OK)
 		return retval;
-	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm720t->cp15_control_reg);
+	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm720t->cp15_control_reg);
 
 	arm720t->armv4_5_mmu.mmu_enabled = arm720t->cp15_control_reg & 0x1U;
 	arm720t->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled =
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index 319892da8..5392b6450 100644
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -643,7 +643,7 @@ int arm7_9_execute_sys_speed(struct target *target)
 			keep_alive();
 	}
 	if (timeout) {
-		LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32 "",
+		LOG_ERROR("timeout waiting for SYSCOMP & DBGACK, last DBG_STATUS: %" PRIx32,
 			buf_get_u32(dbg_stat->value, 0, dbg_stat->size));
 		return ERROR_TARGET_TIMEOUT;
 	}
@@ -1332,7 +1332,7 @@ static int arm7_9_debug_entry(struct target *target)
 	for (i = 0; i <= 15; i++) {
 		struct reg *r = arm_reg_current(arm, i);
 
-		LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
+		LOG_DEBUG("r%i: 0x%8.8" PRIx32, i, context[i]);
 
 		buf_set_u32(r->value, 0, 32, context[i]);
 		/* r0 and r15 (pc) have to be restored later */
@@ -1340,7 +1340,7 @@ static int arm7_9_debug_entry(struct target *target)
 		r->valid = true;
 	}
 
-	LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
+	LOG_DEBUG("entered debug state at PC 0x%" PRIx32, context[15]);
 
 	/* exceptions other than USR & SYS have a saved program status register */
 	if (arm->spsr) {
@@ -1594,7 +1594,7 @@ static int arm7_9_restore_context(struct target *target)
 			struct arm_reg *reg_arch_info;
 			reg_arch_info = reg->arch_info;
 			if ((reg->dirty) && (reg_arch_info->mode != ARM_MODE_ANY)) {
-				LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32 "",
+				LOG_DEBUG("writing SPSR of mode %i with value 0x%8.8" PRIx32,
 					i,
 					buf_get_u32(reg->value, 0, 32));
 				arm7_9->write_xpsr(target, buf_get_u32(reg->value, 0, 32), 1);
@@ -1744,7 +1744,7 @@ int arm7_9_resume(struct target *target,
 				uint32_t current_opcode;
 				target_read_u32(target, current_pc, &current_opcode);
 				LOG_ERROR(
-					"Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
+					"Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32,
 					current_opcode);
 				return retval;
 			}
@@ -1789,7 +1789,7 @@ int arm7_9_resume(struct target *target,
 			LOG_DEBUG("new PC after step: 0x%8.8" PRIx32,
 				buf_get_u32(arm->pc->value, 0, 32));
 
-			LOG_DEBUG("set breakpoint at 0x%8.8" TARGET_PRIxADDR "", breakpoint->address);
+			LOG_DEBUG("set breakpoint at 0x%8.8" TARGET_PRIxADDR, breakpoint->address);
 			retval = arm7_9_set_breakpoint(target, breakpoint);
 			if (retval != ERROR_OK)
 				return retval;
@@ -1937,7 +1937,7 @@ int arm7_9_step(struct target *target, bool current, target_addr_t address,
 		uint32_t current_opcode;
 		target_read_u32(target, current_pc, &current_opcode);
 		LOG_ERROR(
-			"Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32 "",
+			"Couldn't calculate PC of next instruction, current opcode was 0x%8.8" PRIx32,
 			current_opcode);
 		return retval;
 	}
@@ -2116,7 +2116,7 @@ int arm7_9_read_memory(struct target *target,
 	int retval;
 	int last_reg = 0;
 
-	LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
+	LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
 		address, size, count);
 
 	if (target->state != TARGET_HALTED) {
@@ -2636,7 +2636,7 @@ int arm7_9_bulk_write_memory(struct target *target,
 		uint32_t endaddress = buf_get_u32(reg_params[0].value, 0, 32);
 		if (endaddress != (address + count*4)) {
 			LOG_ERROR(
-				"DCC write failed, expected end address 0x%08" TARGET_PRIxADDR " got 0x%0" PRIx32 "",
+				"DCC write failed, expected end address 0x%08" TARGET_PRIxADDR " got 0x%0" PRIx32,
 				(address + count*4),
 				endaddress);
 			retval = ERROR_FAIL;
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index a3fff2ae5..55ddb6313 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -427,7 +427,7 @@ static int arm926ejs_post_debug_entry(struct target *target)
 	retval = jtag_execute_queue();
 	if (retval != ERROR_OK)
 		return retval;
-	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32 "", arm926ejs->cp15_control_reg);
+	LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, arm926ejs->cp15_control_reg);
 
 	if (arm926ejs->armv4_5_mmu.armv4_5_cache.ctype == -1) {
 		uint32_t cache_type_reg;
@@ -458,7 +458,7 @@ static int arm926ejs_post_debug_entry(struct target *target)
 	if (retval != ERROR_OK)
 		return retval;
 
-	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32 "",
+	LOG_DEBUG("D FSR: 0x%8.8" PRIx32 ", D FAR: 0x%8.8" PRIx32 ", I FSR: 0x%8.8" PRIx32,
 		arm926ejs->d_fsr, arm926ejs->d_far, arm926ejs->i_fsr);
 
 	uint32_t cache_dbg_ctrl;
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c
index 8619f8f82..820b2c02b 100644
--- a/src/target/arm_disassembler.c
+++ b/src/target/arm_disassembler.c
@@ -324,7 +324,7 @@ static int evaluate_blx_imm(uint32_t opcode,
 
 	snprintf(instruction->text,
 			128,
-			"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX 0x%8.8" PRIx32 "",
+			"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\tBLX 0x%8.8" PRIx32,
 			address,
 			opcode,
 			target_address);
@@ -596,7 +596,7 @@ static int evaluate_load_store(uint32_t opcode,
 	if (!i) {	/* #+-<offset_12> */
 		uint32_t offset_12 = (opcode & 0xfff);
 		if (offset_12)
-			snprintf(offset, 32, ", #%s0x%" PRIx32 "", (u) ? "" : "-", offset_12);
+			snprintf(offset, 32, ", #%s0x%" PRIx32, (u) ? "" : "-", offset_12);
 		else
 			snprintf(offset, 32, "%s", "");
 
@@ -1079,7 +1079,7 @@ static int evaluate_misc_load_store(uint32_t opcode,
 
 	if (i) {/* Immediate offset/index (#+-<offset_8>)*/
 		uint32_t offset_8 = ((opcode & 0xf00) >> 4) | (opcode & 0xf);
-		snprintf(offset, 32, "#%s0x%" PRIx32 "", (u) ? "" : "-", offset_8);
+		snprintf(offset, 32, "#%s0x%" PRIx32, (u) ? "" : "-", offset_8);
 
 		instruction->info.load_store.offset_mode = 0;
 		instruction->info.load_store.offset.offset = offset_8;
@@ -1546,7 +1546,7 @@ static int evaluate_misc_instr(uint32_t opcode,
 
 		snprintf(instruction->text,
 				128,
-				"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s 0x%4.4" PRIx32 "",
+				"0x%8.8" PRIx32 "\t0x%8.8" PRIx32 "\t%s 0x%4.4" PRIx32,
 				address,
 				opcode,
 				mnemonic,
@@ -1790,7 +1790,7 @@ static int evaluate_data_proc(uint32_t opcode,
 
 		immediate = ror(immed_8, rotate_imm * 2);
 
-		snprintf(shifter_operand, 32, "#0x%" PRIx32 "", immediate);
+		snprintf(shifter_operand, 32, "#0x%" PRIx32, immediate);
 
 		instruction->info.data_proc.variant = 0;
 		instruction->info.data_proc.shifter_operand.immediate.immediate = immediate;
@@ -2628,7 +2628,7 @@ static int evaluate_breakpoint_thumb(uint16_t opcode,
 	instruction->type = ARM_BKPT;
 
 	snprintf(instruction->text, 128,
-			"0x%8.8" PRIx32 "  0x%4.4x  \tBKPT\t%#2.2" PRIx32 "",
+			"0x%8.8" PRIx32 "  0x%4.4x  \tBKPT\t%#2.2" PRIx32,
 			address, opcode, imm);
 
 	return ERROR_OK;
diff --git a/src/target/armv4_5.c b/src/target/armv4_5.c
index d90761569..c4d36f40e 100644
--- a/src/target/armv4_5.c
+++ b/src/target/armv4_5.c
@@ -1564,7 +1564,7 @@ int armv4_5_run_algorithm_inner(struct target *target,
 		regvalue = buf_get_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
 				arm_algorithm_info->core_mode, i).value, 0, 32);
 		if (regvalue != context[i]) {
-			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32 "",
+			LOG_DEBUG("restoring register %s with value 0x%8.8" PRIx32,
 				ARMV4_5_CORE_REG_MODE(arm->core_cache,
 				arm_algorithm_info->core_mode, i).name, context[i]);
 			buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
diff --git a/src/target/armv4_5_mmu.c b/src/target/armv4_5_mmu.c
index 0c09cb4ca..4337bfb8f 100644
--- a/src/target/armv4_5_mmu.c
+++ b/src/target/armv4_5_mmu.c
@@ -31,7 +31,7 @@ int armv4_5_mmu_translate_va(struct target *target,
 		return retval;
 	first_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&first_lvl_descriptor);
 
-	LOG_DEBUG("1st lvl desc: %8.8" PRIx32 "", first_lvl_descriptor);
+	LOG_DEBUG("1st lvl desc: %8.8" PRIx32, first_lvl_descriptor);
 
 	if ((first_lvl_descriptor & 0x3) == 0) {
 		LOG_ERROR("Address translation failure");
@@ -68,7 +68,7 @@ int armv4_5_mmu_translate_va(struct target *target,
 
 	second_lvl_descriptor = target_buffer_get_u32(target, (uint8_t *)&second_lvl_descriptor);
 
-	LOG_DEBUG("2nd lvl desc: %8.8" PRIx32 "", second_lvl_descriptor);
+	LOG_DEBUG("2nd lvl desc: %8.8" PRIx32, second_lvl_descriptor);
 
 	if ((second_lvl_descriptor & 0x3) == 0) {
 		LOG_ERROR("Address translation failure");
diff --git a/src/target/avr32_ap7k.c b/src/target/avr32_ap7k.c
index 94962c205..c623df23d 100644
--- a/src/target/avr32_ap7k.c
+++ b/src/target/avr32_ap7k.c
@@ -117,7 +117,7 @@ static int avr32_write_core_reg(struct target *target, int num)
 
 	reg_value = buf_get_u32(ap7k->core_cache->reg_list[num].value, 0, 32);
 	ap7k->core_regs[num] = reg_value;
-	LOG_DEBUG("write core reg %i value 0x%" PRIx32 "", num, reg_value);
+	LOG_DEBUG("write core reg %i value 0x%" PRIx32, num, reg_value);
 	ap7k->core_cache->reg_list[num].valid = true;
 	ap7k->core_cache->reg_list[num].dirty = false;
 
@@ -337,7 +337,7 @@ static int avr32_ap7k_resume(struct target *target, bool current,
 		/* Single step past breakpoint at current address */
 		breakpoint = breakpoint_find(target, resume_pc);
 		if (breakpoint) {
-			LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR "", breakpoint->address);
+			LOG_DEBUG("unset breakpoint at 0x%8.8" TARGET_PRIxADDR, breakpoint->address);
 #if 0
 			avr32_ap7k_unset_breakpoint(target, breakpoint);
 			avr32_ap7k_single_step_core(target);
@@ -372,11 +372,11 @@ static int avr32_ap7k_resume(struct target *target, bool current,
 	if (!debug_execution) {
 		target->state = TARGET_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
-		LOG_DEBUG("target resumed at 0x%" PRIx32 "", resume_pc);
+		LOG_DEBUG("target resumed at 0x%" PRIx32, resume_pc);
 	} else {
 		target->state = TARGET_DEBUG_RUNNING;
 		target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
-		LOG_DEBUG("target debug resumed at 0x%" PRIx32 "", resume_pc);
+		LOG_DEBUG("target debug resumed at 0x%" PRIx32, resume_pc);
 	}
 
 	return ERROR_OK;
@@ -425,7 +425,7 @@ static int avr32_ap7k_read_memory(struct target *target, target_addr_t address,
 {
 	struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
 
-	LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
+	LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
 		address,
 		size,
 		count);
@@ -465,7 +465,7 @@ static int avr32_ap7k_write_memory(struct target *target, target_addr_t address,
 {
 	struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
 
-	LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
+	LOG_DEBUG("address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
 		address,
 		size,
 		count);
@@ -548,7 +548,7 @@ static int avr32_ap7k_arch_state(struct target *target)
 {
 	struct avr32_ap7k_common *ap7k = target_to_ap7k(target);
 
-	LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32 "",
+	LOG_USER("target halted due to %s, pc: 0x%8.8" PRIx32,
 		debug_reason_name(target), ap7k->jtag.dpc);
 
 	return ERROR_OK;
diff --git a/src/target/cortex_m.c b/src/target/cortex_m.c
index 0501a5b2f..a90610b08 100644
--- a/src/target/cortex_m.c
+++ b/src/target/cortex_m.c
@@ -554,7 +554,7 @@ static int cortex_m_clear_halt(struct target *target)
 	retval = mem_ap_write_atomic_u32(armv7m->debug_ap, NVIC_DFSR, cortex_m->nvic_dfsr);
 	if (retval != ERROR_OK)
 		return retval;
-	LOG_TARGET_DEBUG(target, "NVIC_DFSR 0x%" PRIx32 "", cortex_m->nvic_dfsr);
+	LOG_TARGET_DEBUG(target, "NVIC_DFSR 0x%" PRIx32, cortex_m->nvic_dfsr);
 
 	return ERROR_OK;
 }
@@ -616,7 +616,7 @@ static int cortex_m_endreset_event(struct target *target)
 	retval = mem_ap_read_atomic_u32(armv7m->debug_ap, DCB_DEMCR, &dcb_demcr);
 	if (retval != ERROR_OK)
 		return retval;
-	LOG_TARGET_DEBUG(target, "DCB_DEMCR = 0x%8.8" PRIx32 "", dcb_demcr);
+	LOG_TARGET_DEBUG(target, "DCB_DEMCR = 0x%8.8" PRIx32, dcb_demcr);
 
 	/* this register is used for emulated dcc channel */
 	retval = mem_ap_write_u32(armv7m->debug_ap, DCB_DCRDR, 0);
@@ -1911,7 +1911,7 @@ int cortex_m_set_breakpoint(struct target *target, struct breakpoint *breakpoint
 		comparator_list[fp_num].fpcr_value = fpcr_value;
 		target_write_u32(target, comparator_list[fp_num].fpcr_address,
 			comparator_list[fp_num].fpcr_value);
-		LOG_TARGET_DEBUG(target, "fpc_num %i fpcr_value 0x%" PRIx32 "",
+		LOG_TARGET_DEBUG(target, "fpc_num %i fpcr_value 0x%" PRIx32,
 			fp_num,
 			comparator_list[fp_num].fpcr_value);
 		if (!cortex_m->fpb_enabled) {
@@ -2773,7 +2773,7 @@ int cortex_m_examine(struct target *target)
 			else
 				LOG_TARGET_INFO(target, "The erratum 3092511 workaround will resume after an incorrect halt");
 		}
-		LOG_TARGET_DEBUG(target, "cpuid: 0x%8.8" PRIx32 "", cpuid);
+		LOG_TARGET_DEBUG(target, "cpuid: 0x%8.8" PRIx32, cpuid);
 
 		if (cortex_m->core_info->flags & CORTEX_M_F_HAS_FPV4) {
 			uint32_t mvfr0;
diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index dc85a2180..9f9953a56 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -1517,7 +1517,7 @@ static int dsp563xx_read_memory_core(struct target *target,
 	uint8_t *b;
 
 	LOG_DEBUG(
-		"memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
+		"memtype: %d address: 0x%8.8" PRIx32 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
 		mem_type,
 		address,
 		size,
@@ -1698,7 +1698,7 @@ static int dsp563xx_write_memory_core(struct target *target,
 	const uint8_t *b;
 
 	LOG_DEBUG(
-		"memtype: %d address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "",
+		"memtype: %d address: 0x%8.8" TARGET_PRIxADDR ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32,
 		mem_type,
 		address,
 		size,
diff --git a/src/target/embeddedice.c b/src/target/embeddedice.c
index 7aef153b5..7bf5c7c49 100644
--- a/src/target/embeddedice.c
+++ b/src/target/embeddedice.c
@@ -502,7 +502,7 @@ void embeddedice_write_reg(struct reg *reg, uint32_t value)
 {
 	struct embeddedice_reg *ice_reg = reg->arch_info;
 
-	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", ice_reg->addr, value);
+	LOG_DEBUG("%i: 0x%8.8" PRIx32, ice_reg->addr, value);
 
 	arm_jtag_scann(ice_reg->jtag_info, 0x2, TAP_IDLE);
 
diff --git a/src/target/etb.c b/src/target/etb.c
index fb3112d70..f88b58937 100644
--- a/src/target/etb.c
+++ b/src/target/etb.c
@@ -287,7 +287,7 @@ static int etb_write_reg(struct reg *reg, uint32_t value)
 	uint8_t reg_addr = etb_reg->addr & 0x7f;
 	struct scan_field fields[3];
 
-	LOG_DEBUG("%i: 0x%8.8" PRIx32 "", (int)(etb_reg->addr), value);
+	LOG_DEBUG("%i: 0x%8.8" PRIx32, (int)(etb_reg->addr), value);
 
 	etb_scann(etb_reg->etb, 0x0);
 	etb_set_instr(etb_reg->etb, 0xc);
diff --git a/src/target/etm.c b/src/target/etm.c
index d9a3cdc5e..9e5814e34 100644
--- a/src/target/etm.c
+++ b/src/target/etm.c
@@ -584,7 +584,7 @@ static int etm_write_reg(struct reg *reg, uint32_t value)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 	}
 
-	LOG_DEBUG("%s (%u): 0x%8.8" PRIx32 "", r->name, reg_addr, value);
+	LOG_DEBUG("%s (%u): 0x%8.8" PRIx32, r->name, reg_addr, value);
 
 	retval = arm_jtag_scann(etm_reg->jtag_info, 0x6, TAP_IDLE);
 	if (retval != ERROR_OK)
@@ -986,7 +986,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
 					command_print(cmd, "data abort");
 				else {
 					command_print(cmd,
-						"exception vector 0x%2.2" PRIx32 "",
+						"exception vector 0x%2.2" PRIx32,
 						ctx->last_branch);
 					ctx->current_pc = ctx->last_branch;
 					ctx->pipe_index++;
@@ -1044,7 +1044,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
 
 				if (ctx->ptr_ok)
 					command_print(cmd,
-						"address: 0x%8.8" PRIx32 "",
+						"address: 0x%8.8" PRIx32,
 						ctx->last_ptr);
 			}
 
@@ -1059,7 +1059,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
 							if (etmv1_data(ctx, 4, &data) != 0)
 								return ERROR_ETM_ANALYSIS_FAILED;
 							command_print(cmd,
-								"data: 0x%8.8" PRIx32 "",
+								"data: 0x%8.8" PRIx32,
 								data);
 						}
 					}
@@ -1069,7 +1069,7 @@ static int etmv1_analyze_trace(struct etm_context *ctx, struct command_invocatio
 					if (etmv1_data(ctx, arm_access_size(&instruction),
 						&data) != 0)
 						return ERROR_ETM_ANALYSIS_FAILED;
-					command_print(cmd, "data: 0x%8.8" PRIx32 "", data);
+					command_print(cmd, "data: 0x%8.8" PRIx32, data);
 				}
 			}
 
diff --git a/src/target/feroceon.c b/src/target/feroceon.c
index cf2c838b7..fe1c39fe3 100644
--- a/src/target/feroceon.c
+++ b/src/target/feroceon.c
@@ -555,7 +555,7 @@ static int feroceon_bulk_write_memory(struct target *target,
 		if (endaddress != address + count*4) {
 			LOG_ERROR("DCC write failed,"
 				" expected end address 0x%08" TARGET_PRIxADDR
-				" got 0x%0" PRIx32 "",
+				" got 0x%0" PRIx32,
 				address + count*4, endaddress);
 			retval = ERROR_FAIL;
 		}
diff --git a/src/target/image.c b/src/target/image.c
index e8ac066fd..105501fd4 100644
--- a/src/target/image.c
+++ b/src/target/image.c
@@ -670,7 +670,7 @@ static int image_elf32_read_section(struct image *image,
 	if (offset < field32(elf, segment->p_filesz)) {
 		/* maximal size present in file for the current segment */
 		read_size = MIN(size, field32(elf, segment->p_filesz) - offset);
-		LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR "", read_size,
+		LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR, read_size,
 			field32(elf, segment->p_offset) + offset);
 		/* read initialized area of the segment */
 		retval = fileio_seek(elf->fileio, field32(elf, segment->p_offset) + offset);
@@ -713,7 +713,7 @@ static int image_elf64_read_section(struct image *image,
 	if (offset < field64(elf, segment->p_filesz)) {
 		/* maximal size present in file for the current segment */
 		read_size = MIN(size, field64(elf, segment->p_filesz) - offset);
-		LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR "", read_size,
+		LOG_DEBUG("read elf: size = 0x%zx at 0x%" TARGET_PRIxADDR, read_size,
 			field64(elf, segment->p_offset) + offset);
 		/* read initialized area of the segment */
 		retval = fileio_seek(elf->fileio, field64(elf, segment->p_offset) + offset);
@@ -1088,7 +1088,7 @@ int image_read_section(struct image *image,
 	/* don't read past the end of a section */
 	if (offset + size > image->sections[section].size) {
 		LOG_DEBUG(
-			"read past end of section: 0x%8.8" TARGET_PRIxADDR " + 0x%8.8" PRIx32 " > 0x%8.8" PRIx32 "",
+			"read past end of section: 0x%8.8" TARGET_PRIxADDR " + 0x%8.8" PRIx32 " > 0x%8.8" PRIx32,
 			offset,
 			size,
 			image->sections[section].size);
diff --git a/src/target/mips32.c b/src/target/mips32.c
index 4527c5fa8..5683a28b9 100644
--- a/src/target/mips32.c
+++ b/src/target/mips32.c
@@ -374,7 +374,7 @@ static int mips32_read_core_reg(struct target *target, unsigned int num)
 	mips32->core_cache->reg_list[num].valid = true;
 	mips32->core_cache->reg_list[num].dirty = false;
 
-	LOG_DEBUG("read core reg %i value 0x%" PRIx64 "", num, reg_value);
+	LOG_DEBUG("read core reg %i value 0x%" PRIx64, num, reg_value);
 
 	return ERROR_OK;
 }
@@ -419,7 +419,7 @@ static int mips32_write_core_reg(struct target *target, unsigned int num)
 		mips32->core_regs.gpr[cnum] = (uint32_t)reg_value;
 	}
 
-	LOG_DEBUG("write core reg %i value 0x%" PRIx64 "", num, reg_value);
+	LOG_DEBUG("write core reg %i value 0x%" PRIx64, num, reg_value);
 	mips32->core_cache->reg_list[num].valid = true;
 	mips32->core_cache->reg_list[num].dirty = false;
 
@@ -485,7 +485,7 @@ int mips32_arch_state(struct target *target)
 {
 	struct mips32_common *mips32 = target_to_mips32(target);
 
-	LOG_USER("target halted in %s mode due to %s, pc: 0x%8.8" PRIx32 "",
+	LOG_USER("target halted in %s mode due to %s...
 
[truncated message content]

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1116-g37f638bb4

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  37f638bb4c4231b5ddaab0c4656df25f5cbdb0f0 (commit)
       via  ef188a30ac4339c597b3d4dce9c7877bd63bdec2 (commit)
      from  d3c25a45f6536b09917e0fc3e6e51a6adbd4f992 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 37f638bb4c4231b5ddaab0c4656df25f5cbdb0f0
Author: Marc Schink <de...@za...>
Date:   Tue Jan 23 15:52:51 2024 +0100

    tcl/target: Add Artery AT32F4x config
    
    Tested with AT32F415CBT7 and AT32F421C8T7.
    
    Change-Id: I453d34b130b6792100db5e7cc33d68a7e0edfb5c
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8668
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/tcl/target/artery/at32f4x.cfg b/tcl/target/artery/at32f4x.cfg
new file mode 100644
index 000000000..c299aa904
--- /dev/null
+++ b/tcl/target/artery/at32f4x.cfg
@@ -0,0 +1,50 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# Configuration file for Artery AT32F4x family.
+#
+# https://www.arterychip.com/en/product/
+#
+
+# AT32F4x devices support JTAG and SWD transport.
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+   set _CHIPNAME $CHIPNAME
+} else {
+   set _CHIPNAME at32f4x
+}
+
+# Work-area is a space in RAM used for flash programming, by default use 4 KiB.
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x1000
+}
+
+if { [info exists CPUTAPID] } {
+   set _CPUTAPID $CPUTAPID
+} else {
+   if { [using_jtag] } {
+      set _CPUTAPID 0x4ba00477
+   } {
+      set _CPUTAPID 0x1ba01477
+   }
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -endian little -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME artery 0x08000000 0 0 0 $_TARGETNAME
+
+adapter speed 1000
+
+if {![using_hla]} {
+    cortex_m reset_config sysresetreq
+}

commit ef188a30ac4339c597b3d4dce9c7877bd63bdec2
Author: Marc Schink <de...@za...>
Date:   Sat Nov 30 10:23:01 2024 +0000

    flash/nor: Add support for Artery devices
    
    Initial driver for Artery devices without flash loader and dual-bank
    support. Tested with AT32F415CBT7 and AT32F421C8T7.
    
    Change-Id: I3213f8403d0f3db5d205e200f626e73043f55834
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8667
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index b188f2175..e34020155 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6608,6 +6608,50 @@ the flash.
 @end deffn
 @end deffn
 
+@deffn {Flash Driver} {artery}
+@cindex artery
+This driver supports Artery Technology devices from the following series:
+
+@itemize
+@item AT32F403A / AT32F407
+@item AT32F413
+@item AT32F415
+@item AT32F421
+@item AT32F423
+@item AT32F425
+@item AT32F435 / AT32F437
+@item AT32WB415
+@end itemize
+
+Devices with dual-bank flash memory are currently not supported.
+Also, access to user data in the user system data (USD) area is not supported.
+
+The driver supports flash write protection and flash access protection (FAP).
+For the FAP, only the low-level protection is implemented.
+
+@b{Note:} a change of the flash write protection or FAP requires a device reset for the changes to take effect.
+
+The @var{artery} driver provides the following additional commands:
+
+@deffn {Command} {artery fap enable} <bank>
+Enable low-level flash access protection (FAP).
+@end deffn
+
+@deffn {Command} {artery fap disable} <bank>
+Disable flash access protection (FAP).
+@end deffn
+
+@deffn {Command} {artery fap state} <bank>
+Get the flash access protection (FAP) state.
+The state is a boolean value that indicates whether the FAP is configured in level 'low' or higher.
+@end deffn
+
+@deffn {Command} {artery mass_erase} <bank>
+Erase entire bank.
+@end deffn
+
+@end deffn
+
 @deffn {Flash Driver} {at91samd}
 @cindex at91samd
 All members of the ATSAM D2x, D1x, D0x, ATSAMR, ATSAML and ATSAMC microcontroller
diff --git a/src/flash/nor/Makefile.am b/src/flash/nor/Makefile.am
index 7a81b282b..f40855900 100644
--- a/src/flash/nor/Makefile.am
+++ b/src/flash/nor/Makefile.am
@@ -12,6 +12,7 @@ NOR_DRIVERS = \
 	%D%/aduc702x.c \
 	%D%/aducm360.c \
 	%D%/ambiqmicro.c \
+	%D%/artery.c \
 	%D%/at91sam4.c \
 	%D%/at91sam4l.c \
 	%D%/at91samd.c \
@@ -85,6 +86,7 @@ NOR_DRIVERS = \
 	%D%/xmc4xxx.c
 
 NORHEADERS = \
+	%D%/artery.h \
 	%D%/core.h \
 	%D%/cc3220sf.h \
 	%D%/bluenrg-x.h \
diff --git a/src/flash/nor/artery.c b/src/flash/nor/artery.c
new file mode 100644
index 000000000..797d60de5
--- /dev/null
+++ b/src/flash/nor/artery.c
@@ -0,0 +1,2608 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+
+/*
+ * Copyright (C) 2023 by Marc Schink <de...@za...>
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "config.h"
+#endif
+
+#include "imp.h"
+#include <helper/align.h>
+#include <helper/binarybuffer.h>
+#include <helper/time_support.h>
+#include <helper/bits.h>
+#include <target/cortex_m.h>
+
+#include "artery.h"
+
+// Flash timeout values in milliseconds.
+#define FLASH_MASS_ERASE_TIMEOUT	2400
+#define FLASH_ERASE_TIMEOUT			500
+#define FLASH_WRITE_TIMEOUT			5
+#define HICK_STABLE_TIMEOUT			1000
+
+/*
+ * Flash memory register assignment for the following device series:
+ * - AT32F403A / AT32F407
+ * - AT32F413
+ * - AT32F415
+ * - AT32F421
+ * - AT32F423
+ * - AT32F425
+ * - AT32WB415
+ */
+static const uint32_t flash_regs_f4xx_wb415[ARTERY_FLASH_REG_INDEX_NUM] = {
+	[ARTERY_FLASH_REG_PSR] = 0x00,
+	[ARTERY_FLASH_REG_UNLOCK] = 0x04,
+	[ARTERY_FLASH_REG_USD_UNLOCK] = 0x08,
+	[ARTERY_FLASH_REG_STS] = 0x0c,
+	[ARTERY_FLASH_REG_CTRL] = 0x10,
+	[ARTERY_FLASH_REG_ADDR] = 0x14,
+	[ARTERY_FLASH_REG_USD] = 0x1c,
+	[ARTERY_FLASH_REG_EPPS0] = 0x20,
+	// [ARTERY_FLASH_REG_EPPS1] not available.
+};
+
+// Flash memory register assignment for the AT32F435 / AT32F437 series.
+static const uint32_t flash_regs_f435_f437[ARTERY_FLASH_REG_INDEX_NUM] = {
+	[ARTERY_FLASH_REG_PSR] = 0x00,
+	[ARTERY_FLASH_REG_UNLOCK] = 0x04,
+	[ARTERY_FLASH_REG_USD_UNLOCK] = 0x08,
+	[ARTERY_FLASH_REG_STS] = 0x0c,
+	[ARTERY_FLASH_REG_CTRL] = 0x10,
+	[ARTERY_FLASH_REG_ADDR] = 0x14,
+	[ARTERY_FLASH_REG_USD] = 0x1c,
+	[ARTERY_FLASH_REG_EPPS0] = 0x20,
+	[ARTERY_FLASH_REG_EPPS1] = 0x2c,
+};
+
+/*
+ * User system data (USD) offsets for the following device series:
+ * - AT32F415
+ * - AT32F421
+ * - AT32F423
+ * - AT32F425
+ * - AT32WB415
+ */
+static const uint32_t usd_offsets_f4xx_wb415[ARTERY_USD_INDEX_NUM] = {
+	[ARTERY_USD_FAP_INDEX] = 0x00,
+	[ARTERY_USD_SSB_INDEX] = 0x02,
+	[ARTERY_USD_DATA_INDEX] = 0x04,
+	[ARTERY_USD_EPP_INDEX] = 0x08,
+	// [ARTERY_USD_EPP_EXT_INDEX] not available.
+	[ARTERY_USD_DATA_EXT_INDEX] = 0x10,
+};
+
+// User system data (USD) offsets for the AT32F403A / AT32F407 / AT32F413 series.
+static const uint32_t usd_offsets_f403a_f407_f413[ARTERY_USD_INDEX_NUM] = {
+	[ARTERY_USD_FAP_INDEX] = 0x00,
+	[ARTERY_USD_SSB_INDEX] = 0x02,
+	[ARTERY_USD_DATA_INDEX] = 0x04,
+	[ARTERY_USD_EPP_INDEX] = 0x08,
+	// [ARTERY_USD_EPP_EXT_INDEX] not available.
+	[ARTERY_USD_DATA_EXT_INDEX] = 0x14,
+};
+
+// User system data (USD) offsets for the AT32F435 / AT32F437 series.
+static const uint32_t usd_offsets_f435_f437[ARTERY_USD_INDEX_NUM] = {
+	[ARTERY_USD_FAP_INDEX] = 0x00,
+	[ARTERY_USD_SSB_INDEX] = 0x02,
+	[ARTERY_USD_DATA_INDEX] = 0x04,
+	[ARTERY_USD_EPP_INDEX] = 0x08,
+	[ARTERY_USD_EPP_EXT_INDEX] = 0x14,
+	[ARTERY_USD_DATA_EXT_INDEX] = 0x4c,
+};
+
+static const struct artery_series_info artery_series[] = {
+	[ARTERY_SERIES_F403A_F407] = {
+		.has_fap_high_level = false,
+		.has_epp_ext = false,
+		.flash_regs_base = 0x40022000,
+		.flash_regs = flash_regs_f4xx_wb415,
+		.crm_base = 0x40021000,
+		.usd_base = 0x1FFFF800,
+		.usd_offsets = usd_offsets_f403a_f407_f413,
+	},
+	[ARTERY_SERIES_F413] = {
+		.has_fap_high_level = false,
+		.has_epp_ext = false,
+		.flash_regs_base = 0x40022000,
+		.flash_regs = flash_regs_f4xx_wb415,
+		.crm_base = 0x40021000,
+		.usd_base = 0x1FFFF800,
+		.usd_offsets = usd_offsets_f403a_f407_f413,
+	},
+	[ARTERY_SERIES_F415] = {
+		.has_fap_high_level = true,
+		.has_epp_ext = false,
+		.flash_regs_base = 0x40022000,
+		.flash_regs = flash_regs_f4xx_wb415,
+		.crm_base = 0x40021000,
+		.usd_base = 0x1FFFF800,
+		.usd_offsets = usd_offsets_f4xx_wb415,
+	},
+	[ARTERY_SERIES_F421] = {
+		.has_fap_high_level = true,
+		.has_epp_ext = false,
+		.flash_regs_base = 0x40022000,
+		.flash_regs = flash_regs_f4xx_wb415,
+		.crm_base = 0x40021000,
+		.usd_base = 0x1FFFF800,
+		.usd_offsets = usd_offsets_f4xx_wb415,
+	},
+	[ARTERY_SERIES_F423] = {
+		.has_fap_high_level = true,
+		.has_epp_ext = false,
+		.flash_regs_base = 0x40023C00,
+		.flash_regs = flash_regs_f4xx_wb415,
+		.crm_base = 0x40023800,
+		.usd_base = 0x1FFFF800,
+		.usd_offsets = usd_offsets_f4xx_wb415,
+	},
+	[ARTERY_SERIES_F425] = {
+		.has_fap_high_level = true,
+		.has_epp_ext = false,
+		.flash_regs_base = 0x40022000,
+		.flash_regs = flash_regs_f4xx_wb415,
+		.crm_base = 0x40021000,
+		.usd_base = 0x1FFFF800,
+		.usd_offsets = usd_offsets_f4xx_wb415,
+	},
+	[ARTERY_SERIES_F435_F437] = {
+		.has_fap_high_level = false,
+		.has_epp_ext = true,
+		.flash_regs_base = 0x40023C00,
+		.flash_regs = flash_regs_f435_f437,
+		.crm_base = 0x40023800,
+		.usd_base = 0x1FFFC000,
+		.usd_offsets = usd_offsets_f435_f437,
+	},
+	[ARTERY_SERIES_WB415] = {
+		.has_fap_high_level = true,
+		.has_epp_ext = false,
+		.flash_regs_base = 0x40022000,
+		.flash_regs = flash_regs_f4xx_wb415,
+		.crm_base = 0x40021000,
+		.usd_base = 0x1FFFF800,
+		.usd_offsets = usd_offsets_f4xx_wb415,
+	},
+};
+
+static const struct artery_part_info artery_parts[] = {
+	{
+	    .pid = 0x70050240,
+	    .name = "AT32F403AVCT7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x70050241,
+	    .name = "AT32F403ARCT7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x70050242,
+	    .name = "AT32F403ACCT7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x70050243,
+	    .name = "AT32F403ACCU7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x70050249,
+	    .name = "AT32F407VCT7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x7005024a,
+	    .name = "AT32F407RCT7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x700502cd,
+	    .name = "AT32F403AVET7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 512,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x700502ce,
+	    .name = "AT32F403ARET7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 512,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x700502cf,
+	    .name = "AT32F403ACET7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 512,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x700502d0,
+	    .name = "AT32F403ACEU7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 512,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x700502d1,
+	    .name = "AT32F407VET7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 512,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x700502d2,
+	    .name = "AT32F407RET7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 512,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x70050254,
+	    .name = "AT32F407AVCT7",
+	    .series = ARTERY_SERIES_F403A_F407,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x70030240,
+	    .name = "AT32F413RCT7",
+	    .series = ARTERY_SERIES_F413,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x700301c1,
+	    .name = "AT32F413RBT7",
+	    .series = ARTERY_SERIES_F413,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x70030242,
+	    .name = "AT32F413CCT7",
+	    .series = ARTERY_SERIES_F413,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x700301c3,
+	    .name = "AT32F413CBT7",
+	    .series = ARTERY_SERIES_F413,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x70030244,
+	    .name = "AT32F413KCU7-4",
+	    .series = ARTERY_SERIES_F413,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x700301c5,
+	    .name = "AT32F413KBU7-4",
+	    .series = ARTERY_SERIES_F413,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x70030106,
+	    .name = "AT32F413C8T7",
+	    .series = ARTERY_SERIES_F413,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x70030247,
+	    .name = "AT32F413CCU7",
+	    .series = ARTERY_SERIES_F413,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x700301ca,
+	    .name = "AT32F413CBU7",
+	    .series = ARTERY_SERIES_F413,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 48,
+	    .usd_data_size = 8,
+	},
+	{
+	    .pid = 0x70030240,
+	    .name = "AT32F415RCT7",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x70030241,
+	    .name = "AT32F415CCT7",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x70030242,
+	    .name = "AT32F415KCU7-4",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x70030243,
+	    .name = "AT32F415RCT7-7",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x700301c4,
+	    .name = "AT32F415RBT7",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x700301c5,
+	    .name = "AT32F415CBT7",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x700301c6,
+	    .name = "AT32F415KBU7-4",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x700301c7,
+	    .name = "AT32F415RBT7-7",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x70030108,
+	    .name = "AT32F415R8T7",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x70030109,
+	    .name = "AT32F415C8T7",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x7003010a,
+	    .name = "AT32F415K8U7-4",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x7003024c,
+	    .name = "AT32F415CCU7",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x700301cd,
+	    .name = "AT32F415CBU7",
+	    .series = ARTERY_SERIES_F415,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+	{
+	    .pid = 0x50020100,
+	    .name = "AT32F421C8T7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50020101,
+	    .name = "AT32F421K8T7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50020102,
+	    .name = "AT32F421K8U7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50020103,
+	    .name = "AT32F421K8U7-4",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50020104,
+	    .name = "AT32F421F8U7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50020105,
+	    .name = "AT32F421F8P7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50020086,
+	    .name = "AT32F421C6T7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50020087,
+	    .name = "AT32F421K6T7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50020088,
+	    .name = "AT32F421K6U7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50020089,
+	    .name = "AT32F421K6U7-4",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x5002008a,
+	    .name = "AT32F421F6U7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x5002008b,
+	    .name = "AT32F421F6P7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x5001000c,
+	    .name = "AT32F421C4T7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 16,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x5001000d,
+	    .name = "AT32F421K4T7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 16,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x5001000e,
+	    .name = "AT32F421K4U7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 16,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x5001000f,
+	    .name = "AT32F421K4U7-4",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 16,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50010010,
+	    .name = "AT32F421F4U7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 16,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50010011,
+	    .name = "AT32F421F4P7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 16,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50020112,
+	    .name = "AT32F421G8U7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50020093,
+	    .name = "AT32F421G6U7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50010014,
+	    .name = "AT32F421G4U7",
+	    .series = ARTERY_SERIES_F421,
+	    .flash_size = 16,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a3240,
+	    .name = "AT32F423VCT7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a21c1,
+	    .name = "AT32F423VBT7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x70032102,
+	    .name = "AT32F423V8T7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a3243,
+	    .name = "AT32F423RCT7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a21c4,
+	    .name = "AT32F423RBT7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x70032105,
+	    .name = "AT32F423R8T7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a3246,
+	    .name = "AT32F423RCT7-7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a21c7,
+	    .name = "AT32F423RBT7-7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x70032108,
+	    .name = "AT32F423R8T7-7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a3249,
+	    .name = "AT32F423CCT7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a21ca,
+	    .name = "AT32F423CBT7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x7003210b,
+	    .name = "AT32F423C8T7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a324c,
+	    .name = "AT32F423CCU7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a21cd,
+	    .name = "AT32F423CBU7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x7003210e,
+	    .name = "AT32F423C8U7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a3250,
+	    .name = "AT32F423TCU7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a21d1,
+	    .name = "AT32F423TBU7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x70032112,
+	    .name = "AT32F423T8U7",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a3253,
+	    .name = "AT32F423KCU7-4",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x700a21d4,
+	    .name = "AT32F423KBU7-4",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 128,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x70032115,
+	    .name = "AT32F423K8U7-4",
+	    .series = ARTERY_SERIES_F423,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50092100,
+	    .name = "AT32F425R8T7",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50092081,
+	    .name = "AT32F425R6T7",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50092103,
+	    .name = "AT32F425R8T7-7",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50092084,
+	    .name = "AT32F425R6T7-7",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50092106,
+	    .name = "AT32F425C8T7",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50092087,
+	    .name = "AT32F425C6T7",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50092109,
+	    .name = "AT32F425C8U7",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x5009208a,
+	    .name = "AT32F425C6U7",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x5009210c,
+	    .name = "AT32F425K8T7",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x5009208d,
+	    .name = "AT32F425K6T7",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x5009210f,
+	    .name = "AT32F425K8U7-4",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50092090,
+	    .name = "AT32F425K6U7-4",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50092112,
+	    .name = "AT32F425F8P7",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 64,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x50092093,
+	    .name = "AT32F425F6P7",
+	    .series = ARTERY_SERIES_F425,
+	    .flash_size = 32,
+	    .page_size = 1024,
+	    .usd_size = 512,
+	    .usd_data_size = 250,
+	},
+	{
+	    .pid = 0x70084598,
+	    .name = "AT32F435ZDT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 448,
+	    .page_size = 4096,
+	    .usd_size = 4096,
+	    .usd_data_size = 2012,
+	},
+	{
+	    .pid = 0x70083242,
+	    .name = "AT32F435ZCT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 220,
+	},
+	{
+	    .pid = 0x70084599,
+	    .name = "AT32F435VDT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 448,
+	    .page_size = 4096,
+	    .usd_size = 4096,
+	    .usd_data_size = 2012,
+	},
+	{
+	    .pid = 0x70083245,
+	    .name = "AT32F435VCT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 220,
+	},
+	{
+	    .pid = 0x7008459a,
+	    .name = "AT32F435RDT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 448,
+	    .page_size = 4096,
+	    .usd_size = 4096,
+	    .usd_data_size = 2012,
+	},
+	{
+	    .pid = 0x70083248,
+	    .name = "AT32F435RCT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 220,
+	},
+	{
+	    .pid = 0x7008459b,
+	    .name = "AT32F435CDT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 448,
+	    .page_size = 4096,
+	    .usd_size = 4096,
+	    .usd_data_size = 2012,
+	},
+	{
+	    .pid = 0x7008324b,
+	    .name = "AT32F435CCT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 220,
+	},
+	{
+	    .pid = 0x7008459c,
+	    .name = "AT32F435CDU7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 448,
+	    .page_size = 4096,
+	    .usd_size = 4096,
+	    .usd_data_size = 2012,
+	},
+	{
+	    .pid = 0x7008324e,
+	    .name = "AT32F435CCU7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 220,
+	},
+	{
+	    .pid = 0x7008459d,
+	    .name = "AT32F437ZDT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 448,
+	    .page_size = 4096,
+	    .usd_size = 4096,
+	    .usd_data_size = 2012,
+	},
+	{
+	    .pid = 0x70083251,
+	    .name = "AT32F437ZCT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 220,
+	},
+	{
+	    .pid = 0x7008459e,
+	    .name = "AT32F437VDT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 448,
+	    .page_size = 4096,
+	    .usd_size = 4096,
+	    .usd_data_size = 2012,
+	},
+	{
+	    .pid = 0x70083254,
+	    .name = "AT32F437VCT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 220,
+	},
+	{
+	    .pid = 0x7008459f,
+	    .name = "AT32F437RDT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 448,
+	    .page_size = 4096,
+	    .usd_size = 4096,
+	    .usd_data_size = 2012,
+	},
+	{
+	    .pid = 0x70083257,
+	    .name = "AT32F437RCT7",
+	    .series = ARTERY_SERIES_F435_F437,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 512,
+	    .usd_data_size = 220,
+	},
+	{
+	    .pid = 0x70030250,
+	    .name = "AT32WB415CCU7-7",
+	    .series = ARTERY_SERIES_WB415,
+	    .flash_size = 256,
+	    .page_size = 2048,
+	    .usd_size = 1024,
+	    .usd_data_size = 506,
+	},
+};
+
+/* flash bank artery <base> <size> 0 0 <target#> */
+FLASH_BANK_COMMAND_HANDLER(artery_flash_bank_command)
+{
+	if (CMD_ARGC < 6)
+		return ERROR_COMMAND_SYNTAX_ERROR;
+
+	struct artery_flash_bank *artery_info = calloc(1,
+		sizeof(struct artery_flash_bank));
+
+	if (!artery_info)
+		return ERROR_FAIL;
+
+	bank->driver_priv = artery_info;
+	artery_info->probed = false;
+
+	return ERROR_OK;
+}
+
+static int artery_read_flash_register(struct flash_bank *bank,
+		enum artery_flash_reg_index reg, uint32_t *value)
+{
+	const struct artery_flash_bank *artery_info = bank->driver_priv;
+	const struct artery_part_info *part_info = artery_info->part_info;
+	const struct artery_series_info *series_info = &artery_series[part_info->series];
+	uint32_t reg_addr = series_info->flash_regs_base + series_info->flash_regs[reg];
+
+	return target_read_u32(bank->target, reg_addr, value);
+}
+
+static int artery_write_flash_register(struct flash_bank *bank,
+		enum artery_flash_reg_index reg, uint32_t value)
+{
+	const struct artery_flash_bank *artery_info = bank->driver_priv;
+	const struct artery_part_info *part_info = artery_info->part_info;
+	const struct artery_series_info *series_info = &artery_series[part_info->series];
+	uint32_t reg_addr = series_info->flash_regs_base + series_info->flash_regs[reg];
+
+	return target_write_u32(bank->target, reg_addr, value);
+}
+
+static int artery_wait_flash_busy(struct flash_bank *bank, unsigned int timeout)
+{
+	const int64_t start_time = timeval_ms();
+
+	while (true) {
+		uint32_t status;
+		int retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_STS,
+			&status);
+
+		if (retval != ERROR_OK)
+			return retval;
+
+		if (!(status & FLASH_STS_OBF))
+			break;
+
+		if ((timeval_ms() - start_time) > timeout) {
+			LOG_ERROR("Timed out waiting for flash");
+			return ERROR_FAIL;
+		}
+
+		keep_alive();
+	}
+
+	return ERROR_OK;
+}
+
+static int artery_enable_hiclk(struct flash_bank *bank)
+{
+	const struct artery_flash_bank *artery_info = bank->driver_priv;
+	const struct artery_part_info *part_info = artery_info->part_info;
+	const struct artery_series_info *series_info = &artery_series[part_info->series];
+	uint32_t crm_base = series_info->crm_base;
+	struct target *target = bank->target;
+
+	uint32_t crm_ctrl;
+	int ret = target_read_u32(target, crm_base + CRM_REG_CTRL, &crm_ctrl);
+
+	if (ret != ERROR_OK)
+		return ret;
+
+	// High speed internal clock (HICK) is already enabled and ready.
+	if (crm_ctrl & CRM_CTRL_HICKSTBL)
+		return ERROR_OK;
+
+	crm_ctrl |= CRM_CTRL_HICKEN;
+	ret = target_write_u32(target, crm_base + CRM_REG_CTRL, crm_ctrl);
+
+	if (ret != ERROR_OK)
+		return ret;
+
+	const int64_t start_time = timeval_ms();
+
+	while (true) {
+		ret = target_read_u32(target, crm_base + CRM_REG_CTRL, &crm_ctrl);
+
+		if (ret != ERROR_OK)
+			return ret;
+
+		if (crm_ctrl & CRM_CTRL_HICKSTBL)
+			break;
+
+		if ((timeval_ms() - start_time) > HICK_STABLE_TIMEOUT) {
+			LOG_ERROR("Timed out waiting for flash");
+			return ERROR_FAIL;
+		}
+
+		keep_alive();
+	}
+
+	return ERROR_OK;
+}
+
+static int artery_usd_unlock(struct flash_bank *bank)
+{
+	uint32_t ctrl;
+	int retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_CTRL, &ctrl);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (ctrl & FLASH_CTRL_USDULKS)
+		return ERROR_OK;
+
+	retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_USD_UNLOCK, KEY1);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_USD_UNLOCK, KEY2);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_CTRL, &ctrl);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (!(ctrl & FLASH_CTRL_USDULKS)) {
+		LOG_ERROR("Failed to unlock user system data");
+		return ERROR_FAIL;
+	}
+
+	return ERROR_OK;
+}
+
+static int artery_usd_lock(struct flash_bank *bank)
+{
+	uint32_t ctrl;
+
+	int retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_CTRL, &ctrl);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (!(ctrl & FLASH_CTRL_USDULKS))
+		return ERROR_OK;
+
+	ctrl &= ~FLASH_CTRL_USDULKS;
+	retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_CTRL, ctrl);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_CTRL, &ctrl);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (ctrl & FLASH_CTRL_USDULKS) {
+		LOG_ERROR("Failed to lock user system data");
+		return ERROR_FAIL;
+	}
+
+	return ERROR_OK;
+}
+
+// Initialize the device for flash memory operations.
+static int artery_init_flash(struct flash_bank *bank)
+{
+	/*
+	 * The internal high speed clock (HICK) must be enabled before any flash
+	 * operation is performed.
+	 */
+	int retval = artery_enable_hiclk(bank);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to enable HICLK");
+		return retval;
+	}
+
+	uint32_t ctrl;
+	retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_CTRL, &ctrl);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (!(ctrl & FLASH_CTRL_OPLK))
+		return ERROR_OK;
+
+	retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_UNLOCK, KEY1);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_UNLOCK, KEY2);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_CTRL, &ctrl);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (ctrl & FLASH_CTRL_OPLK) {
+		LOG_ERROR("Failed to initialize flash memory");
+		return ERROR_FAIL;
+	}
+
+	return artery_usd_unlock(bank);
+}
+
+// Deinitialize the flash memory controller.
+static int artery_deinit_flash(struct flash_bank *bank)
+{
+	int retval = artery_usd_lock(bank);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	uint32_t ctrl;
+	retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_CTRL, &ctrl);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (ctrl & FLASH_CTRL_OPLK)
+		return ERROR_OK;
+
+	ctrl |= FLASH_CTRL_OPLK;
+	retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_CTRL, ctrl);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_CTRL, &ctrl);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	if (!(ctrl & FLASH_CTRL_OPLK)) {
+		LOG_ERROR("Failed to lock flash");
+		return ERROR_FAIL;
+	}
+
+	return ERROR_OK;
+}
+
+static int artery_read_protection(struct flash_bank *bank, uint64_t *protection)
+{
+	uint32_t epps0;
+	int retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_EPPS0,
+		&epps0);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	const struct artery_flash_bank *artery_info = bank->driver_priv;
+	const struct artery_part_info *part_info = artery_info->part_info;
+
+	uint64_t prot = epps0;
+
+	if (artery_series[part_info->series].has_epp_ext) {
+		uint32_t epps1;
+		retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_EPPS1,
+			&epps1);
+
+		if (retval != ERROR_OK)
+			return retval;
+
+		prot |= (((uint64_t)epps1) << 32);
+	}
+
+	*protection = prot;
+
+	return ERROR_OK;
+}
+
+static int artery_protect_check(struct flash_bank *bank)
+{
+	uint64_t prot;
+	int retval = artery_read_protection(bank, &prot);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to read flash protection settings");
+		return retval;
+	}
+
+	for (unsigned int i = 0; i < bank->num_prot_blocks; i++) {
+		const bool protected = !(prot & (UINT64_C(1) << i));
+		bank->prot_blocks[i].is_protected = protected ? 1 : 0;
+	}
+
+	return ERROR_OK;
+}
+
+static int artery_erase(struct flash_bank *bank, unsigned int first,
+		unsigned int last)
+{
+	struct target *target = bank->target;
+
+	if (target->state != TARGET_HALTED) {
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	int retval = artery_init_flash(bank);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to initialize flash controller");
+		return retval;
+	}
+
+	// Clear the EPPERR bit, otherwise we may read an invalid value later on.
+	retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_STS,
+		FLASH_STS_EPPERR);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to write FLASH_STS register");
+		goto flash_deinit;
+	}
+
+	retval = artery_wait_flash_busy(bank, FLASH_WRITE_TIMEOUT);
+
+	if (retval != ERROR_OK)
+		goto flash_deinit;
+
+	for (unsigned int i = first; i <= last; i++) {
+		retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_ADDR,
+			bank->base + bank->sectors[i].offset);
+
+		if (retval != ERROR_OK) {
+			LOG_ERROR("Failed to write FLASH_ADDR register");
+			goto flash_deinit;
+		}
+
+		retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_CTRL,
+			FLASH_CTRL_SECERS | FLASH_CTRL_ERSTR);
+
+		if (retval != ERROR_OK) {
+			LOG_ERROR("Failed to write FLASH_CTRL register");
+			goto flash_deinit;
+		}
+
+		retval = artery_wait_flash_busy(bank, FLASH_ERASE_TIMEOUT);
+
+		if (retval != ERROR_OK)
+			goto flash_deinit;
+
+		uint32_t sts;
+		retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_STS, &sts);
+
+		if (retval != ERROR_OK) {
+			LOG_ERROR("Failed to read FLASH_STS register");
+			goto flash_deinit;
+		}
+
+		if (sts & FLASH_STS_EPPERR) {
+			LOG_ERROR("Sector %u is write protected", i);
+			retval = ERROR_FLASH_PROTECTED;
+			goto flash_deinit;
+		}
+	}
+
+	int retval_deinit;
+flash_deinit:
+	retval_deinit = artery_deinit_flash(bank);
+
+	if (retval_deinit != ERROR_OK)
+		return retval_deinit;
+
+	return retval;
+}
+
+static int artery_usd_init(struct flash_bank *bank, uint8_t **buffer)
+{
+	const struct artery_flash_bank *artery_info = bank->driver_priv;
+	const struct artery_part_info *part_info = artery_info->part_info;
+	uint32_t usd_size = part_info->usd_size;
+
+	*buffer = malloc(usd_size);
+
+	if (!*buffer) {
+		LOG_ERROR("Failed to allocate USD buffer");
+		return ERROR_FAIL;
+	}
+
+	memset(*buffer, 0xff, usd_size);
+
+	return ERROR_OK;
+}
+
+static int artery_usd_read(struct flash_bank *bank, uint8_t *buffer)
+{
+	const struct artery_flash_bank *artery_info = bank->driver_priv;
+	const struct artery_part_info *part_info = artery_info->part_info;
+	const struct artery_series_info *series_info = &artery_series[part_info->series];
+
+	return target_read_buffer(bank->target, series_info->usd_base,
+		part_info->usd_size, buffer);
+}
+
+static uint8_t artery_usd_read_buffer(const uint8_t *buffer, uint32_t base,
+		uint32_t offset)
+{
+	return buffer[base + (offset * 2)];
+}
+
+static int artery_usd_load(const struct artery_part_info *part_info,
+		const uint8_t *buffer, struct artery_usd *usd)
+{
+	const uint32_t *usd_regs = artery_series[part_info->series].usd_offsets;
+
+	uint8_t fap_level = artery_usd_read_buffer(buffer,
+		usd_regs[ARTERY_USD_FAP_INDEX], 0);
+
+	switch (fap_level) {
+	case ARTERY_FAP_LEVEL_DISABLED:
+	case ARTERY_FAP_LEVEL_HIGH:
+		usd->fap_level = fap_level;
+		break;
+	default:
+		usd->fap_level = ARTERY_FAP_LEVEL_LOW;
+	}
+
+	usd->ssb = artery_usd_read_buffer(buffer, usd_regs[ARTERY_USD_SSB_INDEX], 0);
+	usd->protection = 0;
+
+	for (unsigned int i = 0; i < 4; i++) {
+		const uint8_t prot = artery_usd_read_buffer(buffer,
+			usd_regs[ARTERY_USD_EPP_INDEX], i);
+		usd->protection |= (prot << (i * 8));
+	}
+
+	if (artery_series[part_info->series].has_epp_ext) {
+		usd->protection_ext = 0;
+
+		for (unsigned int i = 0; i < 4; i++) {
+			const uint8_t prot = artery_usd_read_buffer(buffer,
+				usd_regs[ARTERY_USD_EPP_INDEX], i);
+			usd->protection_ext |= (prot << (i * 8));
+		}
+	}
+
+	// All devices have at least two bytes of user data.
+	usd->data[0] = artery_usd_read_buffer(buffer,
+		usd_regs[ARTERY_USD_DATA_INDEX], 0);
+	usd->data[1] = artery_usd_read_buffer(buffer,
+		usd_regs[ARTERY_USD_DATA_INDEX], 1);
+
+	for (unsigned int i = 0; i < part_info->usd_data_size - 2; i++) {
+		usd->data[i + 2] = artery_usd_read_buffer(buffer,
+			usd_regs[ARTERY_USD_DATA_EXT_INDEX], i);
+	}
+
+	return ERROR_OK;
+}
+
+static void artery_usd_write_buffer(uint8_t *buffer, uint32_t base,
+		uint32_t offset, uint8_t data)
+{
+	buffer[base + (offset * 2)] = data;
+	buffer[base + (offset * 2) + 1] = ~data;
+}
+
+static void artery_usd_update(const struct artery_part_info *part_info,
+		uint8_t *buffer, const struct artery_usd *usd)
+{
+	const uint32_t *usd_regs = artery_series[part_info->series].usd_offsets;
+
+	artery_usd_write_buffer(buffer, usd_regs[ARTERY_USD_FAP_INDEX], 0,
+		usd->fap_level);
+	artery_usd_write_buffer(buffer, usd_regs[ARTERY_USD_SSB_INDEX], 0,
+		usd->ssb);
+
+	for (unsigned int i = 0; i < 4; i++) {
+		const uint8_t prot = usd->protection >> (i * 8);
+		artery_usd_write_buffer(buffer, usd_regs[ARTERY_USD_EPP_INDEX], i, prot);
+	}
+
+	if (artery_series[part_info->series].has_epp_ext) {
+		for (unsigned int i = 0; i < 4; i++) {
+			const uint8_t prot = usd->protection_ext >> (i * 8);
+			artery_usd_write_buffer(buffer, usd_regs[ARTERY_USD_EPP_EXT_INDEX],
+				i, prot);
+		}
+	}
+
+	artery_usd_write_buffer(buffer, usd_regs[ARTERY_USD_DATA_INDEX], 0,
+		usd->data[0]);
+	artery_usd_write_buffer(buffer, usd_regs[ARTERY_USD_DATA_INDEX], 1,
+		usd->data[1]);
+
+	for (unsigned int i = 0; i < part_info->usd_data_size - 2; i++) {
+		artery_usd_write_buffer(buffer, usd_regs[ARTERY_USD_DATA_EXT_INDEX], i,
+			usd->data[i + 2]);
+	}
+}
+
+static int artery_usd_write(struct flash_bank *bank, const uint8_t *buffer)
+{
+	struct target *target = bank->target;
+
+	int retval = artery_wait_flash_busy(bank, FLASH_WRITE_TIMEOUT);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	// Clear the PRGMERR bit, otherwise we may read an invalid value later on.
+	retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_STS,
+		FLASH_STS_PRGMERR);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to write FLASH_STS register");
+		return retval;
+	}
+
+	// Set the USDULKS bit to avoid locking the USD area.
+	uint32_t ctrl = FLASH_CTRL_USDULKS | FLASH_CTRL_USDPRGM;
+	retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_CTRL, ctrl);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to write FLASH_CTRL register");
+		return retval;
+	}
+
+	const struct artery_flash_bank *artery_info = bank->driver_priv;
+	const struct artery_part_info *part_info = artery_info->part_info;
+
+	const target_addr_t usd_base = artery_series[part_info->series].usd_base;
+	const uint32_t usd_size = part_info->usd_size;
+
+	unsigned int bytes_written = 0;
+
+	retval = artery_wait_flash_busy(bank, FLASH_WRITE_TIMEOUT);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	while (bytes_written < usd_size) {
+		uint32_t tmp;
+		memcpy(&tmp, buffer + bytes_written, sizeof(tmp));
+
+		if (tmp != 0xffffffff) {
+			retval = target_write_u32(target, usd_base + bytes_written, tmp);
+
+			if (retval != ERROR_OK) {
+				LOG_ERROR("Failed to write user system data");
+				return retval;
+			}
+
+			retval = artery_wait_flash_busy(bank, FLASH_WRITE_TIMEOUT);
+
+			if (retval != ERROR_OK)
+				return retval;
+		}
+
+		bytes_written += 4;
+	}
+
+	uint32_t sts;
+	retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_STS, &sts);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to read FLASH_STS register");
+		return retval;
+	}
+
+	if (sts & FLASH_STS_PRGMERR) {
+		LOG_ERROR("Failed to program user system data");
+		return ERROR_FLASH_OPERATION_FAILED;
+	}
+
+	return ERROR_OK;
+}
+
+static int artery_usd_erase(struct flash_bank *bank)
+{
+	int retval = artery_wait_flash_busy(bank, FLASH_WRITE_TIMEOUT);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	// Set the USDULKS bit to avoid locking the USD area.
+	uint32_t ctrl = FLASH_CTRL_USDULKS | FLASH_CTRL_USDERS | FLASH_CTRL_ERSTR;
+	retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_CTRL, ctrl);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to write FLASH_CTRL register");
+		return retval;
+	}
+
+	retval = artery_wait_flash_busy(bank, FLASH_WRITE_TIMEOUT);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	uint32_t sts;
+	retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_STS, &sts);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to read FLASH_STS register");
+		return retval;
+	}
+
+	retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_CTRL, &ctrl);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to read FLASH_CTRL register");
+		return retval;
+	}
+
+	return ERROR_OK;
+}
+
+static int artery_get_fap(struct flash_bank *bank,
+		enum artery_fap_level *fap_level)
+{
+	uint32_t usd;
+	int retval = artery_read_flash_register(bank, ARTERY_FLASH_REG_USD,
+		&usd);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	const struct artery_flash_bank *artery_info = bank->driver_priv;
+	const struct artery_part_info *part_info = artery_info->part_info;
+	const struct artery_series_info *series_info = &artery_series[part_info->series];
+
+	const bool fap_high = series_info->has_fap_high_level && (usd & FLASH_USD_FAP_HL);
+	const bool fap_low = usd & FLASH_USD_FAP;
+
+	if (fap_high && fap_low)
+		*fap_level = ARTERY_FAP_LEVEL_HIGH;
+	else if (fap_low)
+		*fap_level = ARTERY_FAP_LEVEL_LOW;
+	else
+		*fap_level = ARTERY_FAP_LEVEL_DISABLED;
+
+	return ERROR_OK;
+}
+
+static int artery_protect(struct flash_bank *bank, int set, unsigned int first,
+		unsigned int last)
+{
+	struct target *target = bank->target;
+
+	if (target->state != TARGET_HALTED) {
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	enum artery_fap_level fap_level;
+	int retval = artery_get_fap(bank, &fap_level);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to read FAP level");
+		return retval;
+	}
+
+	if (fap_level != ARTERY_FAP_LEVEL_DISABLED) {
+		LOG_ERROR("Protection cannot be modified when FAP is active");
+		return ERROR_FAIL;
+	}
+
+	uint8_t *usd_buffer;
+	retval = artery_usd_init(bank, &usd_buffer);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = artery_usd_read(bank, usd_buffer);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to read user system data");
+		return retval;
+	}
+
+	const struct artery_flash_bank *artery_info = bank->driver_priv;
+	const struct artery_part_info *part_info = artery_info->part_info;
+
+	struct artery_usd usd;
+	retval = artery_usd_load(part_info, usd_buffer, &usd);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to load user system data");
+		free(usd_buffer);
+		return retval;
+	}
+
+	for (unsigned int i = first; i <= MIN(31, last); i++) {
+		if (bank->prot_blocks[i].is_protected == set)
+			continue;
+
+		if (set)
+			usd.protection &= ~BIT(i);
+		else
+			usd.protection |= BIT(i);
+	}
+
+	for (unsigned int i = 32; i <= last; i++) {
+		if (bank->prot_blocks[i].is_protected == set)
+			continue;
+
+		if (set)
+			usd.protection_ext &= ~BIT(i - 32);
+		else
+			usd.protection_ext |= BIT(i - 32);
+	}
+
+	artery_usd_update(part_info, usd_buffer, &usd);
+	retval = artery_init_flash(bank);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to initialize flash controller");
+		free(usd_buffer);
+		return retval;
+	}
+
+	retval = artery_usd_erase(bank);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to erase user system data");
+		free(usd_buffer);
+		goto flash_deinit;
+	}
+
+	retval = artery_usd_write(bank, usd_buffer);
+
+	free(usd_buffer);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to write user system data");
+		goto flash_deinit;
+	}
+
+	int retval_deinit;
+flash_deinit:
+	retval_deinit = artery_deinit_flash(bank);
+
+	if (retval_deinit != ERROR_OK)
+		return retval_deinit;
+
+	return retval;
+}
+
+static int artery_write_without_loader(struct flash_bank *bank,
+	const uint8_t *buffer, uint32_t offset, uint32_t count)
+{
+	struct target *target = bank->target;
+
+	int retval = artery_wait_flash_busy(bank, FLASH_WRITE_TIMEOUT);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	retval = artery_write_flash_register(bank, ARTERY_FLASH_REG_CTRL,
+		FLASH_CTRL_FPRGM);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("failed to write ctrl register");
+		return retval;
+	}
+
+	const uint32_t block_size = 4;
+
+	uint32_t bytes_written = 0;
+	target_addr_t address = bank->base + offset;
+
+	for (uint32_t i = 0; i < count / block_size; i++) {
+		retval = target_write_memory(target, address, block_size, 1,
+			buffer + bytes_written);
+
+		if (retval != ERROR_OK)
+			return retval;
+
+		retval = artery_wait_flash_busy(bank, FLASH_WRITE_TIMEOUT);
+
+		if (retval != ERROR_OK)
+			return retval;
+
+		address += block_size;
+		bytes_written += block_size;
+	}
+
+	return ERROR_OK;
+}
+
+static int artery_write(struct flash_bank *bank, const uint8_t *buffer,
+	uint32_t offset, uint32_t count)
+{
+	struct target *target = bank->target;
+
+	if (target->state != TARGET_HALTED) {
+		LOG_ERROR("Target not halted");
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
+	int retval = artery_init_flash(bank);
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to initialize flash controller");
+		return retval;
+	}
+
+	retval = artery_write_without_loader(bank, buffer, offset, count);
+
+	if (retval != ERROR_OK) {
+		LOG_ERROR("Failed to write flash memory");
+		goto flash_deinit;
+	}
+
+	int retval_deinit;
+flash_deinit:
+	retval_deinit = artery_deinit_flash(bank);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	return retval_deinit;
+}
+
+static int artery_probe(struct flash_bank *bank)
+{
+	struct target *target = bank->target;
+
+	if (!target_was_examined(target)) {
+		LOG_ERROR("Target not examined yet");
+		return ERROR_TARGET_NOT_EXAMINED;
+	}
+
+	const struct cortex_m_common *cortex_m = target_to_cortex_m_safe(target);
+
+	if (!cortex_m) {
+		LOG_ERROR("Target is not a Cortex-M device");
+		return ERROR_TARGET_INVALID;
+	}
+
+	struct artery_flash_bank *artery_info = bank->driver_priv;
+
+	artery_info->probed = false;
+
+	int retval = target_read_u32(target, DEBUG_IDCODE, &artery_info->idcode);
+
+	if (retval != ERROR_OK)
+		return retval;
+
+	const uint32_t pid = artery_info->idcode;
+	const bool has_fpu = cortex_m->armv7m.fp_feature != FP_NONE;
+	bool check_device_series = false;
+	enum artery_series device_series;
+
+	/*
+	 * The following PIDs are used for AT32F413 and AT32F415 devices. In order
+	 * to distinguish between the series, we use the presence of the FPU. Note
+	 * that we do not rely on the unqiue device ID (UID) which also encodes the
+	 * device series. The reason is that the UID registers are not accessible
+	 * when the flash access protection (FAP) is active.
+	 */
+	switch (pid) {
+	case 0x700301C5:
+	case 0x70030240:
+	case 0x70030242:
+		check_device_series = true;
+		device_series = has_fpu ? ARTERY_SERIES_F413 : ARTERY_SERIES_F415;
+		break;
+	default:
+		break;
+	}
+
+	artery_info->part_info = NULL;
+
+	for (size_t i = 0; i < ARRAY_SIZE(artery_parts); i++) {
+		if (check_device_series && artery_parts[i].series != device_series)
+			continue;
+
+		if (artery_parts[i].pid == pid) {
+			artery_info->part_info = &artery_parts[i];
+			break;
+		}
+	}
+
+	if (!artery_info->part_info) {
+		LOG_ERROR("Cannot identify target as an Artery device");
+		return ERROR_FAIL;
+	}
+
+	const struct artery_part_info *part_info = artery_info->part_info;
+
+	LOG_INFO("Device ID = 0x%08" PRIx32 " (%s)", artery_info->idcode,
+		part_info->name);
+	LOG_INFO("Flash size = %d KiB", part_info->flash_size);
+
+	free(bank->sectors);
+
+	bank->base = FLASH_BASE;
+	bank->size = part_info->flash_size * 1024;
+
+	const unsigned int num_pages = (bank->size) / part_info->page_size;
+
+	// Ensure that the flash infrastructure uses an alignment of 4 bytes.
+	bank->write_start_alignment = 4;
+	bank->write_end_alignment = 4;
+
+	bank->num_sectors = num_pages;
+	bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
+
+	if (!bank->sectors) {
+		LOG_ERROR("Failed to allocate bank sectors");
+		return ERROR_FAIL;
+	}
+
+	for (unsigned int i = 0; i < bank->num_sectors; i++) {
+		bank->sectors[i].offset = i * part_info->page_size;
+		bank->sectors[i].size = part_info->page_size;
+		bank->sectors[i].is_erased = -1;
+		bank->sectors[i].is_protected = 0;
+	}
+
+	free(bank->prot_blocks);
+
+	/*
+	 * Flash erase/program protection (EPPx) registers configuration for each
+	 * device series.
+	 *
+	 * - AT32F403A / AT32F407
+	 * - AT32F413
+	 *
+	 *    Each bit represents a sector of 4 KiB. The last bit represents the
+	 *    entire remaining flash memory and extension area.
+	 *
+	 * - AT32F415
+	 * - AT32WB415
+	 *
+	 *    Each bit represents a sector of 2 KiB. The last bit represents the
+	 *    entire remaining flash memory and extension area.
+	 *
+	 * - AT32F421
+	 * - AT32F423
+	 * - AT32F425
+	 *
+	 *    Each bit represents a sector of 4 KiB. Some bits may not used
+	 *    depending on the flash memory size. The last bit represents only the
+	 *    flash memory extension area.
+	 *
+	 * - AT32F435 / AT32F437
+	 *
+	 *    This device series has an additional erase/program protection (EPP)
+	 *    register.
+	 *
+	 *    The first 32 bits represent a flash sector of 4 KiB per bit.
+	 *
+	 *    The additional 32 bits represent a sector of 128 KiB each. The
+	 *    second last bit covers the remaining flash memory. The last bit is
+	 *    always reserved.
+	 *
+	 */
+	if (part_info->series == ARTERY_SERIES_F435_F437) {
+		// See description above.
+		const unsigned int num_prot_blocks_1 = 32;
+		const unsigned int num_prot_blocks_2 = MIN(31, DIV_ROUND_UP(part_info->flash_size - 128, 128));
+		const unsigned int num_prot_blocks = num_prot_blocks_1 + num_prot_blocks_2;
+		bank->num_prot_blocks = num_prot_blocks;
+		bank->prot_blocks = malloc(sizeof(struct flash_sector) * num_prot_blocks);
+
+		if (!bank->prot_blocks) {
+			LOG_ERROR("Failed to allocate protection blocks");
+			return ERROR_FAIL;
+		}
+
+		const uint32_t prot_block_size = 4096;
+
+		unsigned int i;
+		uint32_t block_offset = 0;
+
+		for (i = 0; i < 32; i++) {
+			bank->prot_blocks[i].offset = block_offset;
+			bank->prot_blocks[i].size = prot_block_size;
+			bank->prot_blocks[i].is_erased = -1;
+			bank->prot_blocks[i].is_protected = -1;
+
+			block_offset += prot_block_size;
+		}
+
+		const uint32_t prot_block_size_2 = 128 * 1024;
+
+		for (; i < (num_prot_blocks - 1); i++) {
+			bank->prot_blocks[i].offset = block_offset;
+			bank->prot_blocks[i].size = prot_block_size_2;
+			bank->prot_blocks[i].is_erased = -1;
+			bank->prot_blocks[i].is_protected = -1;
+
+			block_offset += prot_block_size_2;
+		}
+
+		bank->prot_blocks[i].offset = block_offset;
+		bank->prot_blocks[i].size = bank->size - block_offset;
+		bank->prot_blocks[i].is_erased = -1;
+		bank->prot_blocks[i].is_protected = -1;
+	} else {
+		uint32_t prot_block_size;
+
+		switch (part_info->series) {
+		case ARTERY_SERIES_F403A_F407:
+		case ARTERY_SERIES_F413:
+		case ARTERY_SERIES_F421:
+		case ARTERY_SERIES_F423:
+		case ARTERY_SERIES_F425:
+			prot_block_size = 4096;
+			break;
+		case ARTERY_SERIES_F415:
+		case ARTERY_SERIES_WB415:
+			prot_block_size = 2048;
+			break;
+		default:
+			LOG_ERROR("Unknown Artery device series");
+			return ERROR_FAIL;
+		}
+
+		const unsigned int num_prot_blocks = MIN(bank->size / prot_block_size, 32);
+		bank->num_prot_blocks = num_prot_blocks;
+		bank->prot_blocks = malloc(sizeof(struct flash_sector) * num_prot_blocks);
+
+		if (!bank->prot_blocks) {
+			LOG_ERROR("Failed to allocate protection blocks");
+			return ERROR_FAIL;
+		}
+
+		unsigned int i;
+
+		for (i = 0; i < (num_prot_blocks - 1); i++) {
+			bank->prot_blocks[i].offset = i * prot_block_size;
+			bank->prot_blocks[i].size = prot_block_size;
+			bank->prot_blocks[i].is_erased = -1;
+			bank->prot_blocks[i].is_protected = -1;
+		}
+
+		bank->prot_blocks[i].offset = i * prot_block_size;
+		bank->prot_blocks[i].size = (bank->size - (i * prot_block_size));
+		bank->prot_blocks[i].is_erased = -1;
+		bank->prot_blocks[i].is_protected = -1;
+	}
+
+	artery_info->probed = true;
+
+	return ERROR_OK;
+}
+
+static int artery_auto_probe(struct flash_bank *bank)
+{
+	const struct artery_flash_bank *artery_info = bank->driver_priv;
+
+	if (artery_info->probed)
+		return ERROR_OK;
+
+	return artery_probe(bank);
+}
+
+static int artery_info(struct flash_bank *bank, struct command_invocation *cmd)
+{
+	const struct artery_flash_bank *artery_info = bank->driver_priv;
+	const struct artery_part_info *part_info = artery_info->part_info;
+
+	if (!part_info) {
+		command_print_sameline(cmd, "Cannot identify target device");
+		return ERROR_OK;
+	}
+
+	command_print_sameline(cmd, "%s - %u KiB flash", part_info->name,
+		part_info->flash_size);
+
+	return ERRO...
 
[truncated message content]

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1114-gd3c25a45f

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  d3c25a45f6536b09917e0fc3e6e51a6adbd4f992 (commit)
      from  66ea461846a3a4a96687c9287c3f61ae8ce0b775 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit d3c25a45f6536b09917e0fc3e6e51a6adbd4f992
Author: Samuel Obuch <sam...@es...>
Date:   Tue Jul 8 22:04:08 2025 +0200

    target/xtensa: fix unaligned memory read on retry
    
    When we read unaligned memory there is an offset in the albuff buffer,
    that we account for when copying back to original buffer. But in case
    the first access failed, the retry call already removed the offset,
    so doing it a second time shifts the returned memory.
    
    Change-Id: Ie255c367ca6a001bfe7038a76cf8a6443e398c51
    Signed-off-by: Samuel Obuch <sam...@es...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8987
    Tested-by: jenkins
    Reviewed-by: Ian Thompson <ia...@ca...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index 1a402743f..f8c36b01d 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -2077,17 +2077,16 @@ int xtensa_read_memory(struct target *target, target_addr_t address, uint32_t si
 			/* Disable fast memory access instructions and retry before reporting an error */
 			LOG_TARGET_DEBUG(target, "Disabling LDDR32.P/SDDR32.P");
 			xtensa->probe_lsddr32p = 0;
-			res = xtensa_read_memory(target, address, size, count, albuff);
-			bswap = false;
+			res = xtensa_read_memory(target, address, size, count, buffer);
 		} else {
 			LOG_TARGET_WARNING(target, "Failed reading %d bytes at address "TARGET_ADDR_FMT,
 				count * size, address);
 		}
+	} else {
+		if (bswap)
+			buf_bswap32(albuff, albuff, addrend_al - addrstart_al);
+		memcpy(buffer, albuff + (address & 3), (size * count));
 	}
-
-	if (bswap)
-		buf_bswap32(albuff, albuff, addrend_al - addrstart_al);
-	memcpy(buffer, albuff + (address & 3), (size * count));
 	free(albuff);
 	return res;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/xtensa/xtensa.c | 11 +++++------
 1 file changed, 5 insertions(+), 6 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1113-g66ea46184

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  66ea461846a3a4a96687c9287c3f61ae8ce0b775 (commit)
      from  6bc2c585960d57c40792d072b38da0834d1e72f9 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 66ea461846a3a4a96687c9287c3f61ae8ce0b775
Author: Tomas Vanek <va...@fb...>
Date:   Tue Dec 10 09:47:21 2024 +0100

    drivers/cmsis_dap: fix segfault in quirk mode setting
    
    CMSIS-DAP quirk mode had to be set after init otherwise
    openocd failed due to NULL cmsis_dap_handle
    
    Move quirk_mode from struct cmsis_dap to
    a standalone static variable to allow setting from Tcl config
    before calling cmsis_dap_open()
    
    Signed-off-by: Tomas Vanek <va...@fb...>
    Fixes: 7966: drivers/cmsis_dap: use quirk workarounds optionally | https://review.openocd.org/c/openocd/+/7966
    Fixes: https://sourceforge.net/p/openocd/tickets/420/
    Change-Id: I0b53ec09b35ccf66660e00490f41aaed1bd0f91f
    Reviewed-on: https://review.openocd.org/c/openocd/+/8641
    Reviewed-by: zapb <de...@za...>
    Tested-by: jenkins

diff --git a/src/jtag/drivers/cmsis_dap.c b/src/jtag/drivers/cmsis_dap.c
index 2bfcfcc2b..37f29c1b3 100644
--- a/src/jtag/drivers/cmsis_dap.c
+++ b/src/jtag/drivers/cmsis_dap.c
@@ -76,6 +76,7 @@ static uint16_t cmsis_dap_vid[MAX_USB_IDS + 1] = { 0 };
 static uint16_t cmsis_dap_pid[MAX_USB_IDS + 1] = { 0 };
 static int cmsis_dap_backend = -1;
 static bool swd_mode;
+static bool cmsis_dap_quirk_mode;  /* enable expensive workarounds */
 
 /* CMSIS-DAP General Commands */
 #define CMD_DAP_INFO              0x00
@@ -870,7 +871,7 @@ static void cmsis_dap_swd_write_from_queue(struct cmsis_dap *dap)
 		goto skip;
 	}
 
-	unsigned int packet_count = dap->quirk_mode ? 1 : dap->packet_count;
+	unsigned int packet_count = cmsis_dap_quirk_mode ? 1 : dap->packet_count;
 	dap->pending_fifo_put_idx = (dap->pending_fifo_put_idx + 1) % packet_count;
 	dap->pending_fifo_block_count++;
 	if (dap->pending_fifo_block_count > packet_count)
@@ -990,7 +991,7 @@ static void cmsis_dap_swd_read_process(struct cmsis_dap *dap, enum cmsis_dap_blo
 
 skip:
 	block->transfer_count = 0;
-	if (!dap->quirk_mode && dap->packet_count > 1)
+	if (!cmsis_dap_quirk_mode && dap->packet_count > 1)
 		dap->pending_fifo_get_idx = (dap->pending_fifo_get_idx + 1) % dap->packet_count;
 	dap->pending_fifo_block_count--;
 }
@@ -1086,7 +1087,7 @@ static void cmsis_dap_swd_queue_cmd(uint8_t cmd, uint32_t *dst, uint32_t data)
 		/* Not enough room in the queue. Run the queue. */
 		cmsis_dap_swd_write_from_queue(cmsis_dap_handle);
 
-		unsigned int packet_count = cmsis_dap_handle->quirk_mode ? 1 : cmsis_dap_handle->packet_count;
+		unsigned int packet_count = cmsis_dap_quirk_mode ? 1 : cmsis_dap_handle->packet_count;
 		if (cmsis_dap_handle->pending_fifo_block_count >= packet_count)
 			cmsis_dap_swd_read_process(cmsis_dap_handle, CMSIS_DAP_BLOCKING);
 	}
@@ -1230,7 +1231,7 @@ static int cmsis_dap_swd_switch_seq(enum swd_special_seq seq)
 	if (swd_mode)
 		queued_retval = cmsis_dap_swd_run_queue();
 
-	if (cmsis_dap_handle->quirk_mode && seq != LINE_RESET &&
+	if (cmsis_dap_quirk_mode && seq != LINE_RESET &&
 			(output_pins & (SWJ_PIN_SRST | SWJ_PIN_TRST))
 				== (SWJ_PIN_SRST | SWJ_PIN_TRST)) {
 		/* Following workaround deasserts reset on most adapters.
@@ -2239,10 +2240,10 @@ COMMAND_HANDLER(cmsis_dap_handle_quirk_command)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	if (CMD_ARGC == 1)
-		COMMAND_PARSE_ENABLE(CMD_ARGV[0], cmsis_dap_handle->quirk_mode);
+		COMMAND_PARSE_ENABLE(CMD_ARGV[0], cmsis_dap_quirk_mode);
 
 	command_print(CMD, "CMSIS-DAP quirk workarounds %s",
-				  cmsis_dap_handle->quirk_mode ? "enabled" : "disabled");
+				  cmsis_dap_quirk_mode ? "enabled" : "disabled");
 	return ERROR_OK;
 }
 
diff --git a/src/jtag/drivers/cmsis_dap.h b/src/jtag/drivers/cmsis_dap.h
index aded0e54a..26dc6f0cf 100644
--- a/src/jtag/drivers/cmsis_dap.h
+++ b/src/jtag/drivers/cmsis_dap.h
@@ -52,7 +52,6 @@ struct cmsis_dap {
 	unsigned int pending_fifo_block_count;
 
 	uint16_t caps;
-	bool quirk_mode;	/* enable expensive workarounds */
 
 	uint32_t swo_buf_sz;
 	bool trace_enabled;

-----------------------------------------------------------------------

Summary of changes:
 src/jtag/drivers/cmsis_dap.c | 13 +++++++------
 src/jtag/drivers/cmsis_dap.h |  1 -
 2 files changed, 7 insertions(+), 7 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1112-g6bc2c5859

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  6bc2c585960d57c40792d072b38da0834d1e72f9 (commit)
      from  374a1f99832cbeb5eb345ed6c497b7abe3850f68 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 6bc2c585960d57c40792d072b38da0834d1e72f9
Author: R. Diez <rdi...@rd...>
Date:   Sun Jul 20 10:39:02 2025 +0200

    configure.ac: Remove useless --enable-verbose-usb-io
    
    _DEBUG_USB_IO_ was not actually used anywhere.
    Its last user was the old ft2232 driver removed in Nov 2016
    with commit cc2d4f015f72d7c30d613b50572eb9f31fac515a
    ("Remove since long deprecated ft2232 driver").
    
    Change-Id: I1a98db7c7b03a89cc9347c0a66ec2106d2168c3f
    Signed-off-by: R. Diez <rdi...@rd...>
    
    Reviewed-on: https://review.openocd.org/c/openocd/+/9002
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/configure.ac b/configure.ac
index e05aa6ac8..e7f797608 100644
--- a/configure.ac
+++ b/configure.ac
@@ -262,34 +262,21 @@ AS_IF([test "x$enable_gcov" = "xyes"], [
   AC_DEFINE([USE_GCOV], [0], [0 to leave coverage collection disabled.])
 ])
 
-# set default verbose options, overridden by following options
-debug_usb_io=no
+# set default for debug_usb_comms, overridden by following options
 debug_usb_comms=no
 
 AC_ARG_ENABLE([verbose],
   AS_HELP_STRING([--enable-verbose],
       [Enable verbose JTAG I/O messages (for debugging).]),
   [
-  debug_usb_io=$enableval
   debug_usb_comms=$enableval
   ], [])
 
-AC_ARG_ENABLE([verbose_usb_io],
-  AS_HELP_STRING([--enable-verbose-usb-io],
-      [Enable verbose USB I/O messages (for debugging)]),
-  [debug_usb_io=$enableval], [])
-
 AC_ARG_ENABLE([verbose_usb_comms],
   AS_HELP_STRING([--enable-verbose-usb-comms],
       [Enable verbose USB communication messages (for debugging)]),
   [debug_usb_comms=$enableval], [])
 
-AC_MSG_CHECKING([whether to enable verbose USB I/O messages]);
-AC_MSG_RESULT([$debug_usb_io])
-AS_IF([test "x$debug_usb_io" = "xyes"], [
-  AC_DEFINE([_DEBUG_USB_IO_],[1], [Print verbose USB I/O messages])
-])
-
 AC_MSG_CHECKING([whether to enable verbose USB communication messages]);
 AC_MSG_RESULT([$debug_usb_comms])
 AS_IF([test "x$debug_usb_comms" = "xyes"], [

-----------------------------------------------------------------------

Summary of changes:
 configure.ac | 15 +--------------
 1 file changed, 1 insertion(+), 14 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1111-g374a1f998

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  374a1f99832cbeb5eb345ed6c497b7abe3850f68 (commit)
      from  eea3c568f9bdede39ee7e1446aeeb07d073d0ba8 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 374a1f99832cbeb5eb345ed6c497b7abe3850f68
Author: Marc Schink <de...@za...>
Date:   Sun Jul 13 09:05:40 2025 +0200

    helper/log: Rework 'debug_level' command
    
    The patch changes the following:
    
     - Use correct return value ERROR_COMMAND_ARGUMENT_INVALID is case an
       invalid debug level is provided.
     - Do not echo the selected debug level.
     - Remove the 'debug_level: ' prefix when the debug level is shown.
       This makes processing via Tcl easier.
     - Use command_print() in order to provide the error message to the
       caller.
    
    Change-Id: Ida84a58c61060497fc36a1926eec7dd30c66cd72
    Signed-off-by: Marc Schink <de...@za...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8996
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 90ed9d3b6..b188f2175 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -810,8 +810,7 @@ itself), use the @option{-d} command line switch. This sets the
 @option{debug_level} to "3", outputting the most information,
 including debug messages. The default setting is "2", outputting only
 informational messages, warnings and errors. You can also change this
-setting from within a telnet or gdb session using @command{debug_level<n>}
-(@pxref{debuglevel,,debug_level}).
+setting from within a telnet or gdb session using @ref{debuglevel,,@command{debug_level}}.
 
 You can redirect all output from the server to a file using the
 @option{-l <logfile>} switch.
@@ -9329,10 +9328,10 @@ will proceed to quit.
 @end deffn
 
 @anchor{debuglevel}
-@deffn {Command} {debug_level} [n]
+@deffn {Command} {debug_level} [number]
 @cindex message level
-Display debug level.
-If @var{n} (from 0..4) is provided, then set it to that level.
+Without arguments it displays the current debug level.
+If @var{number} (from 0..4) is provided, then set it to that level.
 This affects the kind of messages sent to the server log.
 Level 0 is error messages only;
 level 1 adds warnings;
diff --git a/src/helper/log.c b/src/helper/log.c
index 8f7ab0039..d8c4e09ac 100644
--- a/src/helper/log.c
+++ b/src/helper/log.c
@@ -207,18 +207,19 @@ void log_printf_lf(enum log_levels level,
 
 COMMAND_HANDLER(handle_debug_level_command)
 {
-	if (CMD_ARGC == 1) {
+	if (!CMD_ARGC) {
+		command_print(CMD, "%i", debug_level);
+	} else if (CMD_ARGC == 1) {
 		int new_level;
 		COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], new_level);
 		if ((new_level > LOG_LVL_DEBUG_IO) || (new_level < LOG_LVL_SILENT)) {
-			LOG_ERROR("level must be between %d and %d", LOG_LVL_SILENT, LOG_LVL_DEBUG_IO);
-			return ERROR_COMMAND_SYNTAX_ERROR;
+			command_print(CMD, "level must be between %d and %d", LOG_LVL_SILENT, LOG_LVL_DEBUG_IO);
+			return ERROR_COMMAND_ARGUMENT_INVALID;
 		}
 		debug_level = new_level;
-	} else if (CMD_ARGC > 1)
+	} else {
 		return ERROR_COMMAND_SYNTAX_ERROR;
-
-	command_print(CMD, "debug_level: %i", debug_level);
+	}
 
 	return ERROR_OK;
 }
@@ -261,11 +262,11 @@ static const struct command_registration log_command_handlers[] = {
 		.name = "debug_level",
 		.handler = handle_debug_level_command,
 		.mode = COMMAND_ANY,
-		.help = "Sets the verbosity level of debugging output. "
+		.help = "Sets or display the verbosity level of debugging output. "
 			"0 shows errors only; 1 adds warnings; "
 			"2 (default) adds other info; 3 adds debugging; "
 			"4 adds extra verbose debugging.",
-		.usage = "number",
+		.usage = "[number]",
 	},
 	COMMAND_REGISTRATION_DONE
 };

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi |  9 ++++-----
 src/helper/log.c | 17 +++++++++--------
 2 files changed, 13 insertions(+), 13 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1110-geea3c568f

[openocd-gerrit <ope...@us...>]

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  eea3c568f9bdede39ee7e1446aeeb07d073d0ba8 (commit)
      from  2248f1ef1275115862bdd97363c68259661adde6 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit eea3c568f9bdede39ee7e1446aeeb07d073d0ba8
Author: Ondřej Hošek <ond...@gm...>
Date:   Mon Jul 14 00:12:19 2025 +0200

    tcl/board: add mikroe/clicker4-stm32f745vg
    
    Add a board configuration file for the MikroElektronika Clicker 4 for
    STM32F745VG (MIKROE-6331), which contains their CMSIS-DAP-compatible
    on-board CODEGRIP programmer.
    
    Place this into its own subdirectory, since MikroElektronika has quite a
    few boards in their portfolio.
    
    Change-Id: If24ca286d65e024f3c3a8522b67727e268ab0bc9
    Signed-off-by: Ondřej Hošek <ond...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/8997
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/tcl/board/mikroe/clicker4-stm32f745vg.cfg b/tcl/board/mikroe/clicker4-stm32f745vg.cfg
new file mode 100644
index 000000000..9ccd94880
--- /dev/null
+++ b/tcl/board/mikroe/clicker4-stm32f745vg.cfg
@@ -0,0 +1,11 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+# This is a MikroElektronika Click 4 board with a single STM32F745VG chip
+# and an on-board CODEGRIP debugger.
+# https://www.mikroe.com/clicker-4-for-stm32f745vgt6
+
+source [find interface/cmsis-dap.cfg]
+transport select jtag
+adapter speed 4000
+
+source [find target/stm32f7x.cfg]

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/mikroe/clicker4-stm32f745vg.cfg | 11 +++++++++++
 1 file changed, 11 insertions(+)
 create mode 100644 tcl/board/mikroe/clicker4-stm32f745vg.cfg


hooks/post-receive
-- 
Main OpenOCD repository