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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1476-gcc32b36c8

From: openocd-gerrit <ope...@us...> - 2026-04-26 06:28:35

This is an automated email from the git hooks/post-receive script. It was
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The branch, master has been updated
       via  cc32b36c8f4a8a4e50b83260a39fd83c4715b234 (commit)
      from  e22380c70f35e272bbb68068df3380e2cf336d3e (commit)

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- Log -----------------------------------------------------------------
commit cc32b36c8f4a8a4e50b83260a39fd83c4715b234
Author: Tomas Vanek <va...@fb...>
Date:   Thu Aug 8 21:03:28 2024 +0200

    target/riscv: do not set DTM_DTMCS_VERSION_UNKNOWN on examine fail
    
    Proper version is necessary for target deinit or future
    re-examinations. Poisoning the version number causes memory leak
    in riscv_deinit_target().
    
    Prevent multiple calls of RISC-V debug version specific init
    on re-examinations, check 'dtm_version' to distinguish
    if the init was done.
    
    Signed-off-by: Tomas Vanek <va...@fb...>
    Change-Id: Ie63ae83626c3fd7498669cb2898309f1c5d4d112
    Reviewed-on: https://review.openocd.org/c/openocd/+/9276
    Tested-by: jenkins

diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index e92366d44..0688ad327 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -2485,28 +2485,36 @@ static int riscv_examine(struct target *target)
 		LOG_TARGET_ERROR(target, "Could not read dtmcontrol. Check JTAG connectivity/board power.");
 		return ERROR_FAIL;
 	}
-	LOG_TARGET_DEBUG(target, "dtmcontrol=0x%x", dtmcontrol);
-	info->dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
-	LOG_TARGET_DEBUG(target, "version=0x%x", info->dtm_version);
-
-	int examine_status = ERROR_FAIL;
-	struct target_type *tt = get_target_type(target);
-	if (!tt)
-		goto examine_fail;
-
-	examine_status = tt->init_target(info->cmd_ctx, target);
-	if (examine_status != ERROR_OK)
-		goto examine_fail;
-
-	examine_status = tt->examine(target);
-	if (examine_status != ERROR_OK)
-		goto examine_fail;
+	LOG_TARGET_DEBUG(target, "dtmcontrol=0x%" PRIx32, dtmcontrol);
+	uint32_t dtm_version = get_field(dtmcontrol, DTMCONTROL_VERSION);
+	LOG_TARGET_DEBUG(target, "version=0x%" PRIx32, dtm_version);
+
+	struct target_type *tt;
+	if (info->dtm_version == DTM_DTMCS_VERSION_UNKNOWN) {
+		info->dtm_version = dtm_version;
+		tt = get_target_type(target);
+		if (!tt) {
+			info->dtm_version = DTM_DTMCS_VERSION_UNKNOWN;
+			return ERROR_FAIL;
+		}
 
-	return ERROR_OK;
+		int retval = tt->init_target(info->cmd_ctx, target);
+		if (retval != ERROR_OK) {
+			info->dtm_version = DTM_DTMCS_VERSION_UNKNOWN;
+			return retval;
+		}
+	} else {
+		if (info->dtm_version != dtm_version) {
+			// REVISIT: could we deinit_target, change version and init_target again?
+			LOG_TARGET_ERROR(target, "dtmcs.version changed to 0x%" PRIx32, dtm_version);
+			return ERROR_FAIL;
+		}
+		tt = get_target_type(target);
+		if (!tt)
+			return ERROR_FAIL;
+	}
 
-examine_fail:
-	info->dtm_version = DTM_DTMCS_VERSION_UNKNOWN;
-	return examine_status;
+	return tt->examine(target);
 }
 
 static int oldriscv_poll(struct target *target)

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv.c | 48 ++++++++++++++++++++++++++++--------------------
 1 file changed, 28 insertions(+), 20 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1475-ge22380c70

From: openocd-gerrit <ope...@us...> - 2026-04-26 06:25:03

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  e22380c70f35e272bbb68068df3380e2cf336d3e (commit)
      from  e10ea84551eb9635e62385a4e64dcf8fde73795e (commit)

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- Log -----------------------------------------------------------------
commit e22380c70f35e272bbb68068df3380e2cf336d3e
Author: Tomas Vanek <va...@fb...>
Date:   Sat Nov 29 21:13:27 2025 +0100

    target: add couple of target examined checks
    
    Add check to target_step() to be like target_resume() and target_halt().
    Add checks to handle_target_get_reg() and handle_target_set_reg()
    to behave similarly as reg command.
    
    Change-Id: I7bfbba9e8e89461897ecd7f20a6628a015a57625
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9274
    Tested-by: jenkins

diff --git a/src/target/target.c b/src/target/target.c
index ec1ce17f3..7a656383d 100644
--- a/src/target/target.c
+++ b/src/target/target.c
@@ -1433,6 +1433,11 @@ int target_step(struct target *target,
 {
 	int retval;
 
+	if (!target_was_examined(target)) {
+		LOG_TARGET_ERROR(target, "not examined");
+		return ERROR_TARGET_NOT_EXAMINED;
+	}
+
 	target_call_event_callbacks(target, TARGET_EVENT_STEP_START);
 
 	retval = target->type->step(target, current, address, handle_breakpoints);
@@ -4687,6 +4692,10 @@ COMMAND_HANDLER(handle_target_get_reg)
 	const int length = Jim_ListLength(CMD_CTX->interp, next_argv);
 
 	const struct target *target = get_current_target(CMD_CTX);
+	if (target->state != TARGET_HALTED) {
+		command_print(CMD, "Error: [%s] not halted", target_name(target));
+		return ERROR_TARGET_NOT_HALTED;
+	}
 
 	for (int i = 0; i < length; i++) {
 		Jim_Obj *elem = Jim_ListGetIndex(CMD_CTX->interp, next_argv, i);
@@ -4747,6 +4756,11 @@ COMMAND_HANDLER(handle_set_reg_command)
 
 	const struct target *target = get_current_target(CMD_CTX);
 	assert(target);
+	if (target->state != TARGET_HALTED) {
+		command_print(CMD, "Error: [%s] not halted", target_name(target));
+		return ERROR_TARGET_NOT_HALTED;
+	}
+
 
 	for (unsigned int i = 0; i < length; i += 2) {
 		const char *reg_name = Jim_String(dict[i]);

-----------------------------------------------------------------------

Summary of changes:
 src/target/target.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1474-ge10ea8455

From: openocd-gerrit <ope...@us...> - 2026-04-26 06:23:16

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  e10ea84551eb9635e62385a4e64dcf8fde73795e (commit)
      from  14f652f1bd2d1ea6acb723bb105708f62306f7ec (commit)

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- Log -----------------------------------------------------------------
commit e10ea84551eb9635e62385a4e64dcf8fde73795e
Author: Tomas Vanek <va...@fb...>
Date:   Sun Feb 8 17:59:44 2026 +0100

    checkpatch: make CODE_INDENT test TAB size aware
    
    The test for too many spaces after TAB uses fixed regular
    expression with 8 spaces. OpenOCD coding style requires TAB size 4
    
    Generate the regex according to --tab-size value.
    
    Change-Id: Iddafa880b1782847c2903cabed9b6a0402e316d8
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9457
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins

diff --git a/tools/scripts/checkpatch.pl b/tools/scripts/checkpatch.pl
index 6235fc7eb..f77f364d1 100755
--- a/tools/scripts/checkpatch.pl
+++ b/tools/scripts/checkpatch.pl
@@ -3932,6 +3932,12 @@ sub process {
 # more than $tabsize must use tabs.
 		if ($rawline =~ /^\+\s* \t\s*\S/ ||
 		    $rawline =~ /^\+\s*        \s*/) {
+			# OpenOCD specific: Begin: fix check on $tabsize
+			# Do nothing in this default upstream case
+		}
+		if ($rawline =~ /^\+\s* \t\s*\S/ ||
+		    $rawline =~ /^\+\s* {$tabsize}\s*/) {
+			# OpenOCD specific: End
 			my $herevet = "$here\n" . cat_vet($rawline) . "\n";
 			$rpt_cleaners = 1;
 			if (ERROR("CODE_INDENT",

-----------------------------------------------------------------------

Summary of changes:
 tools/scripts/checkpatch.pl | 6 ++++++
 1 file changed, 6 insertions(+)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1473-g14f652f1b

From: openocd-gerrit <ope...@us...> - 2026-04-26 05:15:11

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  14f652f1bd2d1ea6acb723bb105708f62306f7ec (commit)
      from  98a83177f4bd0ff7f6177ba0062b75e5adde6015 (commit)

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- Log -----------------------------------------------------------------
commit 14f652f1bd2d1ea6acb723bb105708f62306f7ec
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Fri Feb 6 23:15:28 2026 +0100

    doc: Update EFM32 documentation
    
    Slightly update the EFM32 documentation.
    
    Change-Id: I5919a8352843763306c54470aa64e89f4c18eee5
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9456
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/doc/openocd.texi b/doc/openocd.texi
index a21a3e4bd..ff4bed6f7 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -154,15 +154,15 @@ USB-based, parallel port-based, and other standalone boxes that run
 OpenOCD internally. @xref{Debug Adapter Hardware}.
 
 @b{GDB Debug:} It allows ARM7 (ARM7TDMI and ARM720t), ARM9 (ARM920T,
-ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M3
-(Stellaris LM3, STMicroelectronics STM32 and Energy Micro EFM32) and
+ARM922T, ARM926EJ--S, ARM966E--S), XScale (PXA25x, IXP42x), Cortex-M
+(Stellaris LM3, STMicroelectronics STM32 and Silicon Labs EFM32/EFR32) and
 Intel Quark (x10xx) based cores to be debugged via the GDB protocol.
 
 @b{Flash Programming:} Flash writing is supported for external
 CFI-compatible NOR flashes (Intel and AMD/Spansion command set) and several
 internal flashes (LPC1700, LPC1800, LPC2000, LPC4300, AT91SAM7, AT91SAM3U,
-STR7x, STR9x, LM3, STM32x and EFM32). Preliminary support for various NAND flash
-controllers (LPC3180, Orion, S3C24xx, more) is included.
+STR7x, STR9x, LM3, STM32x and EFM32/EFR32). Preliminary support for various NAND
+flash controllers (LPC3180, Orion, S3C24xx, more) is included.
 
 @section OpenOCD Web Site
 
@@ -7214,25 +7214,25 @@ flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
 @end deffn
 
 @deffn {Flash Driver} {efm32}
-All members of the EFM32/EFR32 microcontroller family from Energy Micro (now Silicon Labs)
-include internal flash and use Arm Cortex-M3 or Cortex-M4 cores. The driver automatically
-recognizes a number of these chips using the chip identification register, and
-autoconfigures itself.
+All members of the EFM32/EFR32 microcontroller family from Silicon Labs (former
+Energy Micro) include internal flash and use Arm Cortex-M3, Cortex-M4 or
+Cortex-M33 cores. The driver automatically recognizes a number of these chips
+using the chip identification register, and autoconfigures itself.
 @example
-flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME efm32 0x80000000 0 0 0 $_TARGETNAME
 @end example
 It supports writing to the user data page, as well as the portion of the lockbits page
-past 512 bytes on chips with larger page sizes. The latter is used by the SiLabs
-bootloader/AppLoader system for encryption keys. Setting protection on these pages is
-currently not supported.
+past 512 bytes on chips with larger page sizes. The latter is used by the
+Silicon Labs bootloader/AppLoader system for encryption keys. Setting protection
+on these pages is currently not supported.
 @example
 flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
 flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
 @end example
 
-A special feature of efm32 controllers is that it is possible to completely disable the
-debug interface by writing the correct values to the 'Debug Lock Word'. OpenOCD supports
-this via the following command:
+A special feature of Silicon Labs Series 0/1 controllers is that it is possible
+to completely disable the debug interface by writing the correct values to the
+'Debug Lock Word'. OpenOCD supports this via the following command:
 @example
 efm32 debuglock num
 @end example

-----------------------------------------------------------------------

Summary of changes:
 doc/openocd.texi | 30 +++++++++++++++---------------
 1 file changed, 15 insertions(+), 15 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1472-g98a83177f

From: openocd-gerrit <ope...@us...> - 2026-04-26 05:14:56

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  98a83177f4bd0ff7f6177ba0062b75e5adde6015 (commit)
      from  d7a518ad44df29c96d5eedc41f9e669f5b7039c0 (commit)

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- Log -----------------------------------------------------------------
commit 98a83177f4bd0ff7f6177ba0062b75e5adde6015
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Thu Feb 26 14:21:38 2026 +0100

    flash/nor/efm32: Use target_get_working_area_avail()
    
    Use the newer API target_get_working_area_avail() rather than testing
    the possible buffer_size in a loop.
    
    Change-Id: Iccd238284dabdcb45a00b208de42bc48dbc5e060
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9480
    Reviewed-by: zapb <de...@za...>
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 63042b920..9f5f1b111 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -893,41 +893,35 @@ static int efm32_write_block(struct flash_bank *bank, const uint8_t *buf,
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	struct target *target = bank->target;
-	uint32_t buffer_size = 16384;
-	struct working_area *write_algorithm;
-	struct working_area *source;
-	struct reg_param reg_params[5];
-	struct armv7m_algorithm armv7m_info;
-	int ret = ERROR_OK;
+	struct working_area *write_algorithm, *source;
+	int ret;
 
 	/* flash write code */
-	if (target_alloc_working_area(target,
-								  efm32_info->info.msc_offset->flash_write_code_len,
-								  &write_algorithm) != ERROR_OK) {
+	ret = target_alloc_working_area(target,
+									efm32_info->info.msc_offset->flash_write_code_len,
+									&write_algorithm);
+	if (ret) {
 		LOG_WARNING("no working area available, can't do block memory writes");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
-
 	ret = target_write_buffer(target, write_algorithm->address,
 							  efm32_info->info.msc_offset->flash_write_code_len,
 							  efm32_info->info.msc_offset->flash_write_code);
-	if (ret != ERROR_OK)
+	if (ret)
 		return ret;
 
 	/* memory buffer */
-	while (target_alloc_working_area_try(target, buffer_size, &source) != ERROR_OK) {
-		buffer_size /= 2;
-		buffer_size &= ~3UL; /* Make sure it's 4 byte aligned */
-		if (buffer_size <= 256) {
-			/* we already allocated the writing code, but failed to get a
-			 * buffer, free the algorithm */
-			target_free_working_area(target, write_algorithm);
-
-			LOG_WARNING("no large enough working area available, can't do block memory writes");
-			return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
-		}
+	uint32_t buffer_size = target_get_working_area_avail(target);
+	if (buffer_size <= 256) {
+		LOG_WARNING("no large enough working area available, can't do block memory writes");
+		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
+	buffer_size = MIN(buffer_size, 16 * 1024);
+	ret = target_alloc_working_area(target, buffer_size, &source);
+	if (ret)
+		return ret;
 
+	struct reg_param reg_params[5];
 	init_reg_param(&reg_params[0], "r0", 32, PARAM_IN_OUT);	/* flash base (in), status (out) */
 	init_reg_param(&reg_params[1], "r1", 32, PARAM_OUT);	/* count (word-32bit) */
 	init_reg_param(&reg_params[2], "r2", 32, PARAM_OUT);	/* buffer start */
@@ -940,9 +934,10 @@ static int efm32_write_block(struct flash_bank *bank, const uint8_t *buf,
 	buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
 	buf_set_u32(reg_params[4].value, 0, 32, address);
 
-	armv7m_info.common_magic = ARMV7M_COMMON_MAGIC;
-	armv7m_info.core_mode = ARM_MODE_THREAD;
-
+	struct armv7m_algorithm armv7m_info = {
+		.common_magic = ARMV7M_COMMON_MAGIC,
+		.core_mode = ARM_MODE_THREAD,
+	};
 	ret = target_run_flash_async_algorithm(target, buf, count, 4,
 										   0, NULL,
 										   5, reg_params,

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 45 ++++++++++++++++++++-------------------------
 1 file changed, 20 insertions(+), 25 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1471-gd7a518ad4

From: openocd-gerrit <ope...@us...> - 2026-04-26 05:13:54

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  d7a518ad44df29c96d5eedc41f9e669f5b7039c0 (commit)
      from  1203440575d65aa6670a7ea191eafeb3350e7954 (commit)

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- Log -----------------------------------------------------------------
commit d7a518ad44df29c96d5eedc41f9e669f5b7039c0
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Wed Feb 11 16:50:01 2026 +0100

    flash/nor/efm32: Fix page size for user data bank
    
    On Series-0/1 devices, the user data bank is always only one sector and
    the size of the page is the same than the main flash bank.
    
    On Series-2, these parameters are stored in separated registers.
    
    This patch has been tested with:
    
        >  reset init
        JTAG tap: efm32.cpu tap/device found: 0x6ba00477 (mfg: 0x23b ...
        [efm32.cpu] halted due to debug-request, current mode: Thread
        xPSR: 0xf9000000 pc: 0x0800289c msp: 0x20001018
        > flash probe 1
        detected part: EFR32ZG28 B322, rev 2
        flash size = 1024 KiB
        flash page size = 8192 B
        flash 'efm32' found at 0x0fe00000
        > flash erase_sector 1 0 last
        erased sectors 0 through 0 on flash bank 1 in 0.019881s
        > flash write_bank 1 /tmp/test.bin
        wrote 1024 bytes from file /tmp/test.bin to flash bank 1 at ...
        > flash verify_bank 1 /tmp/test.bin
        read 1024 bytes from file /tmp/test.bin and flash bank 1 at ...
        contents match
    
    Reported-by: Marc Schink <de...@za...>
    Change-Id: Ie6bbb61dcd8d94facde47200118ff585efc0d7fb
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9459
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 12d0dc5d1..63042b920 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -63,6 +63,8 @@ struct efm32_dev_info_addr {
 #define EFM32_DI_PARTINFO_FAMILY_MASK     0x00ff0000
 #define EFM32_DI_PARTINFO_TYPE_MASK       0x3f000000
 	target_addr_t part_info;
+#define EFM32_DI_PARTINFO_PAGE_SZ_MASK    0x000000ff
+#define EFM32_DI_PARTINFO_PAGE_SZ_UD_MASK 0x0000ff00
 	target_addr_t page_size;
 	target_addr_t flash_sz;
 	target_addr_t ram_sz;
@@ -108,6 +110,7 @@ struct efm32_msc_offset {
 	target_addr_t off_writecmd;
 	target_addr_t off_addrb;
 	target_addr_t off_wdata;
+	target_addr_t off_userdatasize;
 
 #define EFM32_MSC_STATUS_BUSY_MASK           0x0001
 #define EFM32_MSC_STATUS_LOCKED_MASK         0x0002
@@ -139,6 +142,7 @@ static const struct efm32_msc_offset efm32_msc_offset[] = {
 		.off_wdata     = 0x0018,
 		.off_status    = 0x001c,
 		.off_lock      = 0x003c,
+		.off_userdatasize = 0x0000, // Does not exist in Series 0/1
 		.flash_write_code = efm32_flash_write_code_s0_s1,
 		.flash_write_code_len = sizeof(efm32_flash_write_code_s0_s1),
 	},
@@ -149,6 +153,7 @@ static const struct efm32_msc_offset efm32_msc_offset[] = {
 		.off_wdata     = 0x0018,
 		.off_status    = 0x001c,
 		.off_lock      = 0x0040,
+		.off_userdatasize = 0x0000, // Does not exist in Series 0/1
 		.flash_write_code = efm32_flash_write_code_s0_s1,
 		.flash_write_code_len = sizeof(efm32_flash_write_code_s0_s1),
 	},
@@ -159,6 +164,7 @@ static const struct efm32_msc_offset efm32_msc_offset[] = {
 		.off_wdata     = 0x0018,
 		.off_status    = 0x001c,
 		.off_lock      = 0x003c,
+		.off_userdatasize = 0x0034,
 		.flash_write_code = efm32_flash_write_code_s2,
 		.flash_write_code_len = sizeof(efm32_flash_write_code_s2),
 	},
@@ -197,7 +203,6 @@ struct efm32_family_data {
 
 	// Page size in bytes, or 0 to read from msc_di->page_size
 	int page_size;
-
 };
 
 struct efm32_info {
@@ -210,6 +215,7 @@ struct efm32_info {
 	uint16_t flash_sz_kib;
 	uint16_t ram_sz_kib;
 	uint16_t page_size;
+	uint16_t page_size_ud;
 };
 
 struct efm32_flash_chip {
@@ -311,20 +317,20 @@ static int efm32_read_info(struct flash_bank *bank)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	struct efm32_info *efm32_mcu_info = &efm32_info->info;
-	uint8_t tmp;
 	int ret;
 
 	memset(efm32_mcu_info, 0, sizeof(struct efm32_info));
 
-	ret = target_read_u8(bank->target, EFM32_DI_PART_FAMILY, &tmp);
+	uint8_t val8;
+	ret = target_read_u8(bank->target, EFM32_DI_PART_FAMILY, &val8);
 	if (ret != ERROR_OK)
 		return ret;
 	for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
-		if (efm32_families[i].part_id == tmp)
+		if (efm32_families[i].part_id == val8)
 			efm32_mcu_info->family_data = &efm32_families[i];
 	}
 	if (!efm32_mcu_info->family_data) {
-		LOG_ERROR("Unknown MCU family %d", tmp);
+		LOG_ERROR("Unknown MCU family %d", val8);
 		return ERROR_FAIL;
 	}
 
@@ -363,6 +369,7 @@ static int efm32_read_info(struct flash_bank *bank)
 	if (ret != ERROR_OK)
 		return ret;
 
+	efm32_mcu_info->page_size_ud = 0;
 	if (efm32_mcu_info->family_data->page_size != 0) {
 		efm32_mcu_info->page_size = efm32_mcu_info->family_data->page_size;
 	} else if ((efm32_mcu_info->family_data->part_id == 72 ||
@@ -376,14 +383,20 @@ static int efm32_read_info(struct flash_bank *bank)
 		else
 			efm32_mcu_info->page_size = 4096;
 	} else {
-		ret = target_read_u8(bank->target,
+		uint32_t val32;
+		ret = target_read_u32(bank->target,
 							 efm32_mcu_info->di_addr->page_size,
-							 &tmp);
+							 &val32);
 		if (ret != ERROR_OK)
 			return ret;
 
-		efm32_mcu_info->page_size = BIT(tmp) * 1024;
+		efm32_mcu_info->page_size = BIT(FIELD_GET(EFM32_DI_PARTINFO_PAGE_SZ_MASK, val32)) * 1024;
+		if (efm32_mcu_info->family_data->series == 2)
+			efm32_mcu_info->page_size_ud = FIELD_GET(EFM32_DI_PARTINFO_PAGE_SZ_UD_MASK, val32) * 1024;
 	}
+	if (!efm32_mcu_info->page_size_ud)
+		efm32_mcu_info->page_size_ud = efm32_mcu_info->page_size;
+
 	if (efm32_mcu_info->page_size !=  512 &&
 		efm32_mcu_info->page_size != 1024 &&
 		efm32_mcu_info->page_size != 2048 &&
@@ -1172,8 +1185,8 @@ static int efm32_probe(struct flash_bank *bank)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	struct efm32_info *efm32_mcu_info = &efm32_info->info;
-	uint32_t base_address = EFM32_FLASH_BASE_V2;
 	int bank_index = efm32_get_bank_index(bank->base);
+	uint32_t base_address = EFM32_FLASH_BASE_V2;
 	char strbuf[256];
 	int ret;
 
@@ -1202,16 +1215,32 @@ static int efm32_probe(struct flash_bank *bank)
 	free(bank->sectors);
 	bank->sectors = NULL;
 
-	if (bank->base == base_address) {
-		bank->num_sectors = efm32_mcu_info->flash_sz_kib * 1024 / efm32_mcu_info->page_size;
+	uint32_t page_size;
+	if (bank->base == base_address) { /* main flash */
+		page_size = efm32_mcu_info->page_size;
+		bank->num_sectors = efm32_mcu_info->flash_sz_kib * 1024 / page_size;
 		assert(bank->num_sectors > 0);
-	} else {
+	} else if (efm32_info->info.family_data->series != 2) {
+		page_size = efm32_mcu_info->page_size_ud;
 		bank->num_sectors = 1;
+	} else {
+		ret = efm32_msc_clock_enable(bank);
+		if (ret != ERROR_OK)
+			return ret;
+
+		uint32_t userdatasize;
+		ret = efm32_read_reg_u32(bank,
+								 efm32_info->info.msc_offset->off_userdatasize,
+								 &userdatasize);
+		if (ret != ERROR_OK) {
+			LOG_ERROR("Failed to read page size");
+			return ret;
+		}
+		page_size = efm32_mcu_info->page_size_ud;
+		bank->num_sectors = (userdatasize * 256) / page_size;
 	}
-	bank->size = bank->num_sectors * efm32_mcu_info->page_size;
-	bank->sectors = alloc_block_array(0,
-									  efm32_mcu_info->page_size,
-									  bank->num_sectors);
+	bank->size = bank->num_sectors * page_size;
+	bank->sectors = alloc_block_array(0, page_size, bank->num_sectors);
 	if (!bank->sectors)
 		return ERROR_FAIL;
 

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 61 +++++++++++++++++++++++++++++++++++++--------------
 1 file changed, 45 insertions(+), 16 deletions(-)


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- Log -----------------------------------------------------------------
commit 1203440575d65aa6670a7ea191eafeb3350e7954
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Thu Feb 5 15:56:14 2026 +0100

    flash/nor/efm32: Fix tab size
    
    The previous patches was written with tabsize == 8 while the project
    coding style require tabsize == 4.
    
    This on changes the multi-line statements when the arguments have to be
    aligned with the opening parenthesis.
    
    Change-Id: I893857820bdb62f95f2d2e3e8e7fa67d7e0565c0
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9453
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 031b3d99a..12d0dc5d1 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -283,28 +283,28 @@ static const struct efm32_family_data efm32_families[] = {
 const struct flash_driver efm32_flash;
 
 static int efm32_priv_write(struct flash_bank *bank, const uint8_t *buffer,
-			    uint32_t addr, uint32_t count);
+							uint32_t addr, uint32_t count);
 
 static int efm32_write_only_lockbits(struct flash_bank *bank);
 
 static int efm32_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
-			      uint32_t *value)
+							  uint32_t *value)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
 	return target_read_u32(bank->target,
-			       efm32_info->info.family_data->msc_regbase + offset,
-			       value);
+						   efm32_info->info.family_data->msc_regbase + offset,
+						   value);
 }
 
 static int efm32_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
-			       uint32_t value)
+							   uint32_t value)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
 	return target_write_u32(bank->target,
-				efm32_info->info.family_data->msc_regbase + offset,
-				value);
+							efm32_info->info.family_data->msc_regbase + offset,
+							value);
 }
 
 static int efm32_read_info(struct flash_bank *bank)
@@ -333,41 +333,41 @@ static int efm32_read_info(struct flash_bank *bank)
 
 	if (efm32_mcu_info->family_data->series == 2) {
 		ret = target_read_u32(bank->target,
-				      efm32_mcu_info->di_addr->part_info,
-				      &efm32_mcu_info->part_info);
+							  efm32_mcu_info->di_addr->part_info,
+							  &efm32_mcu_info->part_info);
 		if (ret != ERROR_OK)
 			return ret;
 	} else {
 		ret = target_read_u16(bank->target,
-				      efm32_mcu_info->di_addr->part_num,
-				      &efm32_mcu_info->part_num);
+							  efm32_mcu_info->di_addr->part_num,
+							  &efm32_mcu_info->part_num);
 		if (ret != ERROR_OK)
 			return ret;
 	}
 
 	ret = target_read_u8(bank->target,
-			     efm32_mcu_info->di_addr->part_rev,
-			     &efm32_mcu_info->part_rev);
+						 efm32_mcu_info->di_addr->part_rev,
+						 &efm32_mcu_info->part_rev);
 	if (ret != ERROR_OK)
 		return ret;
 
 	ret = target_read_u16(bank->target,
-			      efm32_mcu_info->di_addr->flash_sz,
-			      &efm32_mcu_info->flash_sz_kib);
+						  efm32_mcu_info->di_addr->flash_sz,
+						  &efm32_mcu_info->flash_sz_kib);
 	if (ret != ERROR_OK)
 		return ret;
 
 	ret = target_read_u16(bank->target,
-			      efm32_mcu_info->di_addr->ram_sz,
-			      &efm32_mcu_info->ram_sz_kib);
+						  efm32_mcu_info->di_addr->ram_sz,
+						  &efm32_mcu_info->ram_sz_kib);
 	if (ret != ERROR_OK)
 		return ret;
 
 	if (efm32_mcu_info->family_data->page_size != 0) {
 		efm32_mcu_info->page_size = efm32_mcu_info->family_data->page_size;
 	} else if ((efm32_mcu_info->family_data->part_id == 72 ||
-		    efm32_mcu_info->family_data->part_id == 74) &&
-		   efm32_mcu_info->part_rev < 18) {
+				efm32_mcu_info->family_data->part_id == 74) &&
+			   efm32_mcu_info->part_rev < 18) {
 		/* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid for MCUs
 		 * with part_rev < 18
 		 */
@@ -377,18 +377,18 @@ static int efm32_read_info(struct flash_bank *bank)
 			efm32_mcu_info->page_size = 4096;
 	} else {
 		ret = target_read_u8(bank->target,
-				     efm32_mcu_info->di_addr->page_size,
-				     &tmp);
+							 efm32_mcu_info->di_addr->page_size,
+							 &tmp);
 		if (ret != ERROR_OK)
 			return ret;
 
 		efm32_mcu_info->page_size = BIT(tmp) * 1024;
 	}
 	if (efm32_mcu_info->page_size !=  512 &&
-	    efm32_mcu_info->page_size != 1024 &&
-	    efm32_mcu_info->page_size != 2048 &&
-	    efm32_mcu_info->page_size != 4096 &&
-	    efm32_mcu_info->page_size != 8192) {
+		efm32_mcu_info->page_size != 1024 &&
+		efm32_mcu_info->page_size != 2048 &&
+		efm32_mcu_info->page_size != 4096 &&
+		efm32_mcu_info->page_size != 8192) {
 		LOG_ERROR("Invalid page size %u", efm32_mcu_info->page_size);
 		return ERROR_FAIL;
 	}
@@ -405,18 +405,18 @@ FLASH_BANK_COMMAND_HANDLER(efm32_flash_bank_command)
 	int bank_index = efm32_get_bank_index(bank->base);
 	if (bank_index < 0) {
 		LOG_ERROR("Flash bank with base address %" PRIx32 " is not supported",
-			(uint32_t)bank->base);
+				  (uint32_t)bank->base);
 		return ERROR_FAIL;
 	}
 
 	/* look for an existing flash structure matching target */
 	struct efm32_flash_chip *efm32_info = NULL;
 	for (struct flash_bank *bank_iter = flash_bank_list();
-	     bank_iter;
-	     bank_iter = bank_iter->next) {
+			 bank_iter;
+			 bank_iter = bank_iter->next) {
 		if (bank_iter->driver == &efm32_flash &&
-		    bank_iter->target == bank->target &&
-		    bank->driver_priv) {
+			bank_iter->target == bank->target &&
+			bank->driver_priv) {
 			efm32_info = bank->driver_priv;
 			break;
 		}
@@ -461,11 +461,11 @@ static int efm32_msc_clock_enable(struct flash_bank *bank)
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
 	if (efm32_info->info.family_data->series == 0 ||
-	    efm32_info->info.family_data->series == 1)
+		efm32_info->info.family_data->series == 1)
 		return ERROR_OK;
 
 	unsigned int s2_family = FIELD_GET(EFM32_DI_PARTINFO_FAMILY_MASK,
-			      efm32_info->info.part_info);
+									   efm32_info->info.part_info);
 	uint32_t msc_clken;
 	switch (s2_family) {
 	case 21:
@@ -488,8 +488,8 @@ static int efm32_msc_clock_enable(struct flash_bank *bank)
 		msc_clken = BIT(16);
 	}
 	int ret = target_write_u32(bank->target,
-			       EFM32_CMU_REG_CLKEN1_SET,
-			       msc_clken);
+							   EFM32_CMU_REG_CLKEN1_SET,
+							   msc_clken);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to enable MSC clock");
 		return ret;
@@ -500,7 +500,7 @@ static int efm32_msc_clock_enable(struct flash_bank *bank)
 
 /* set or reset given bits in a register */
 static int efm32_set_reg_bits(struct flash_bank *bank, uint32_t reg,
-			      uint32_t bitmask, int set)
+							  uint32_t bitmask, int set)
 {
 	int ret = 0;
 	uint32_t reg_val = 0;
@@ -522,8 +522,8 @@ static int efm32_set_wren(struct flash_bank *bank, int write_enable)
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
 	return efm32_set_reg_bits(bank,
-				  efm32_info->info.msc_offset->off_writectrl,
-				  EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
+							  efm32_info->info.msc_offset->off_writectrl,
+							  EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
 }
 
 static int efm32_msc_lock(struct flash_bank *bank, int lock)
@@ -531,12 +531,12 @@ static int efm32_msc_lock(struct flash_bank *bank, int lock)
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
 	return efm32_write_reg_u32(bank,
-				   efm32_info->info.msc_offset->off_lock,
-				   lock ? 0 : EFM32_MSC_LOCK_LOCKKEY);
+							   efm32_info->info.msc_offset->off_lock,
+							   lock ? 0 : EFM32_MSC_LOCK_LOCKKEY);
 }
 
 static int efm32_wait_status(struct flash_bank *bank, int timeout_ms,
-			     uint32_t wait_mask, bool wait_for_set)
+							 uint32_t wait_mask, bool wait_for_set)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	int64_t start_ms = timeval_ms();
@@ -544,8 +544,8 @@ static int efm32_wait_status(struct flash_bank *bank, int timeout_ms,
 
 	while (1) {
 		int ret = efm32_read_reg_u32(bank,
-					     efm32_info->info.msc_offset->off_status,
-					     &status);
+									 efm32_info->info.msc_offset->off_status,
+									 &status);
 		if (ret != ERROR_OK)
 			return ret;
 
@@ -582,21 +582,21 @@ static int efm32_erase_page(struct flash_bank *bank, uint32_t addr)
 	LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
 
 	ret = efm32_write_reg_u32(bank,
-				  efm32_info->info.msc_offset->off_addrb,
-				  addr);
+							  efm32_info->info.msc_offset->off_addrb,
+							  addr);
 	if (ret != ERROR_OK)
 		return ret;
 
 	ret = efm32_set_reg_bits(bank,
-				 efm32_info->info.msc_offset->off_writecmd,
-				 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
+							 efm32_info->info.msc_offset->off_writecmd,
+							 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 	if (ret != ERROR_OK)
 		return ret;
 
 	uint32_t status;
 	ret = efm32_read_reg_u32(bank,
-				 efm32_info->info.msc_offset->off_status,
-				 &status);
+							 efm32_info->info.msc_offset->off_status,
+							 &status);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -611,17 +611,17 @@ static int efm32_erase_page(struct flash_bank *bank, uint32_t addr)
 	}
 
 	ret = efm32_set_reg_bits(bank,
-				 efm32_info->info.msc_offset->off_writecmd,
-				 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
+							 efm32_info->info.msc_offset->off_writecmd,
+							 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
 	if (ret != ERROR_OK)
 		return ret;
 
 	return efm32_wait_status(bank, EFM32_FLASH_OPERATION_TIMEOUT,
-				 EFM32_MSC_STATUS_BUSY_MASK, false);
+							 EFM32_MSC_STATUS_BUSY_MASK, false);
 }
 
 static int efm32_erase(struct flash_bank *bank, unsigned int first,
-		       unsigned int last)
+					   unsigned int last)
 {
 	struct target *target = bank->target;
 	int ret = 0;
@@ -745,7 +745,7 @@ static int efm32_write_only_lockbits(struct flash_bank *bank)
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
 	return efm32_priv_write(bank, (uint8_t *)efm32_info->lb_page,
-				EFM32_MSC_LOCK_BITS, LOCKWORDS_SZ);
+							EFM32_MSC_LOCK_BITS, LOCKWORDS_SZ);
 }
 
 static int efm32_write_lock_data(struct flash_bank *bank)
@@ -761,8 +761,8 @@ static int efm32_write_lock_data(struct flash_bank *bank)
 	if (extra_bytes) {
 		extra_data = malloc(extra_bytes);
 		ret = target_read_buffer(bank->target,
-					 EFM32_MSC_LOCK_BITS_EXTRA,
-					 extra_bytes, extra_data);
+								 EFM32_MSC_LOCK_BITS_EXTRA,
+								 extra_bytes, extra_data);
 		if (ret != ERROR_OK) {
 			LOG_ERROR("Failed to read extra contents of LB page");
 			free(extra_data);
@@ -780,8 +780,8 @@ static int efm32_write_lock_data(struct flash_bank *bank)
 
 	if (extra_data) {
 		ret = efm32_priv_write(bank, extra_data,
-				       EFM32_MSC_LOCK_BITS_EXTRA,
-				       extra_bytes);
+							   EFM32_MSC_LOCK_BITS_EXTRA,
+							   extra_bytes);
 		free(extra_data);
 		if (ret != ERROR_OK) {
 			LOG_ERROR("Failed to restore extra contents of LB page");
@@ -822,7 +822,7 @@ static int efm32_set_page_lock(struct flash_bank *bank, size_t page, int set)
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
 	if (bank->base != EFM32_FLASH_BASE_V1 &&
-	    bank->base != EFM32_FLASH_BASE_V2) {
+		bank->base != EFM32_FLASH_BASE_V2) {
 		LOG_ERROR("Locking user and lockbits pages is not supported yet");
 		return ERROR_FAIL;
 	}
@@ -838,7 +838,7 @@ static int efm32_set_page_lock(struct flash_bank *bank, size_t page, int set)
 }
 
 static int efm32_protect(struct flash_bank *bank, int set, unsigned int first,
-			 unsigned int last)
+						 unsigned int last)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	struct target *target = bank->target;
@@ -876,7 +876,7 @@ static int efm32_protect(struct flash_bank *bank, int set, unsigned int first,
 }
 
 static int efm32_write_block(struct flash_bank *bank, const uint8_t *buf,
-			     uint32_t address, uint32_t count)
+							 uint32_t address, uint32_t count)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	struct target *target = bank->target;
@@ -889,15 +889,15 @@ static int efm32_write_block(struct flash_bank *bank, const uint8_t *buf,
 
 	/* flash write code */
 	if (target_alloc_working_area(target,
-				      efm32_info->info.msc_offset->flash_write_code_len,
-				      &write_algorithm) != ERROR_OK) {
+								  efm32_info->info.msc_offset->flash_write_code_len,
+								  &write_algorithm) != ERROR_OK) {
 		LOG_WARNING("no working area available, can't do block memory writes");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
 	ret = target_write_buffer(target, write_algorithm->address,
-				  efm32_info->info.msc_offset->flash_write_code_len,
-				  efm32_info->info.msc_offset->flash_write_code);
+							  efm32_info->info.msc_offset->flash_write_code_len,
+							  efm32_info->info.msc_offset->flash_write_code);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -931,23 +931,23 @@ static int efm32_write_block(struct flash_bank *bank, const uint8_t *buf,
 	armv7m_info.core_mode = ARM_MODE_THREAD;
 
 	ret = target_run_flash_async_algorithm(target, buf, count, 4,
-					       0, NULL,
-					       5, reg_params,
-					       source->address, source->size,
-					       write_algorithm->address, 0,
-					       &armv7m_info);
+										   0, NULL,
+										   5, reg_params,
+										   source->address, source->size,
+										   write_algorithm->address, 0,
+										   &armv7m_info);
 
 	if (ret == ERROR_FLASH_OPERATION_FAILED) {
 		LOG_ERROR("flash write failed at address 0x%" PRIx32,
-			  buf_get_u32(reg_params[4].value, 0, 32));
+				  buf_get_u32(reg_params[4].value, 0, 32));
 
 		if (buf_get_u32(reg_params[0].value, 0, 32) &
-				EFM32_MSC_STATUS_LOCKED_MASK) {
+			EFM32_MSC_STATUS_LOCKED_MASK) {
 			LOG_ERROR("flash memory write protected");
 		}
 
 		if (buf_get_u32(reg_params[0].value, 0, 32) &
-				EFM32_MSC_STATUS_INVADDR_MASK) {
+			EFM32_MSC_STATUS_INVADDR_MASK) {
 			LOG_ERROR("invalid flash memory write address");
 		}
 	}
@@ -965,7 +965,7 @@ static int efm32_write_block(struct flash_bank *bank, const uint8_t *buf,
 }
 
 static int efm32_write_word(struct flash_bank *bank, uint32_t addr,
-			    uint32_t val)
+							uint32_t val)
 {
 	/* this function DOES NOT set WREN; must be set already */
 	/* 1. write address to ADDRB
@@ -986,21 +986,21 @@ static int efm32_write_word(struct flash_bank *bank, uint32_t addr,
 	keep_alive();
 
 	ret = efm32_write_reg_u32(bank,
-				  efm32_info->info.msc_offset->off_addrb,
-				  addr);
+							  efm32_info->info.msc_offset->off_addrb,
+							  addr);
 	if (ret != ERROR_OK)
 		return ret;
 
 	ret = efm32_set_reg_bits(bank,
-				 efm32_info->info.msc_offset->off_writecmd,
-				 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
+							 efm32_info->info.msc_offset->off_writecmd,
+							 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 	if (ret != ERROR_OK)
 		return ret;
 
 	uint32_t status;
 	ret = efm32_read_reg_u32(bank,
-				 efm32_info->info.msc_offset->off_status,
-				 &status);
+							 efm32_info->info.msc_offset->off_status,
+							 &status);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -1015,30 +1015,30 @@ static int efm32_write_word(struct flash_bank *bank, uint32_t addr,
 	}
 
 	ret = efm32_wait_status(bank, EFM32_FLASH_OPERATION_TIMEOUT,
-				EFM32_MSC_STATUS_WDATAREADY_MASK, true);
+							EFM32_MSC_STATUS_WDATAREADY_MASK, true);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Wait for WDATAREADY failed");
 		return ret;
 	}
 
 	ret = efm32_write_reg_u32(bank,
-				  efm32_info->info.msc_offset->off_wdata,
-				  val);
+							  efm32_info->info.msc_offset->off_wdata,
+							  val);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("WDATA write failed");
 		return ret;
 	}
 
 	ret = efm32_write_reg_u32(bank,
-				  efm32_info->info.msc_offset->off_writecmd,
-				  EFM32_MSC_WRITECMD_WRITEONCE_MASK);
+							  efm32_info->info.msc_offset->off_writecmd,
+							  EFM32_MSC_WRITECMD_WRITEONCE_MASK);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("WRITECMD write failed");
 		return ret;
 	}
 
 	ret = efm32_wait_status(bank, EFM32_FLASH_OPERATION_TIMEOUT,
-				EFM32_MSC_STATUS_BUSY_MASK, false);
+							EFM32_MSC_STATUS_BUSY_MASK, false);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Wait for BUSY failed");
 		return ret;
@@ -1048,7 +1048,7 @@ static int efm32_write_word(struct flash_bank *bank, uint32_t addr,
 }
 
 static int efm32_priv_write(struct flash_bank *bank, const uint8_t *buffer,
-			    uint32_t addr, uint32_t count)
+							uint32_t addr, uint32_t count)
 {
 	struct target *target = bank->target;
 	uint8_t *new_buffer = NULL;
@@ -1072,7 +1072,7 @@ static int efm32_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 			return ERROR_FAIL;
 		}
 		LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %"
-			 PRIu32 " and padding with 0xff", old_count, count);
+				 PRIu32 " and padding with 0xff", old_count, count);
 		memset(new_buffer, 0xff, count);
 		buffer = memcpy(new_buffer, buffer, old_count);
 	}
@@ -1124,7 +1124,7 @@ cleanup:
 }
 
 static int efm32_write(struct flash_bank *bank, const uint8_t *buffer,
-		       uint32_t offset, uint32_t count)
+					   uint32_t offset, uint32_t count)
 {
 	if (bank->base == EFM32_MSC_LOCK_BITS && offset < LOCKWORDS_SZ) {
 		LOG_ERROR("Cannot write to lock words");
@@ -1134,20 +1134,20 @@ static int efm32_write(struct flash_bank *bank, const uint8_t *buffer,
 }
 
 static char *efm32_get_str_identifier(struct efm32_info *efm32_mcu_info,
-				      char *buf, size_t len)
+									  char *buf, size_t len)
 {
 	if (!efm32_mcu_info->part_info) {
 		snprintf(buf, len, "%s Gecko, rev %" PRIu8,
-			efm32_mcu_info->family_data->name,
-			efm32_mcu_info->part_rev);
+				 efm32_mcu_info->family_data->name,
+				 efm32_mcu_info->part_rev);
 		return buf;
 	}
 	unsigned int dev_num    = FIELD_GET(EFM32_DI_PARTINFO_NUM_MASK,
-				   efm32_mcu_info->part_info);
+										efm32_mcu_info->part_info);
 	unsigned int dev_family = FIELD_GET(EFM32_DI_PARTINFO_FAMILY_MASK,
-				   efm32_mcu_info->part_info);
+										efm32_mcu_info->part_info);
 	unsigned int dev_type   = FIELD_GET(EFM32_DI_PARTINFO_TYPE_MASK,
-				   efm32_mcu_info->part_info);
+										efm32_mcu_info->part_info);
 
 	const char *types = "FMBZxP";
 	if (dev_type > strlen(types)) {
@@ -1159,12 +1159,12 @@ static char *efm32_get_str_identifier(struct efm32_info *efm32_mcu_info,
 	unsigned int dev_num_digits = dev_num % 1000;
 
 	snprintf(buf, len, "%s%cG%u %c%03u, rev %" PRIu8,
-		types[dev_type] == 'P' ? "EFM32" : "EFR32",
-		types[dev_type],
-		dev_family,
-		dev_num_letter,
-		dev_num_digits,
-		efm32_mcu_info->part_rev);
+			 types[dev_type] == 'P' ? "EFM32" : "EFR32",
+			 types[dev_type],
+			 dev_family,
+			 dev_num_letter,
+			 dev_num_digits,
+			 efm32_mcu_info->part_rev);
 	return buf;
 }
 
@@ -1187,13 +1187,13 @@ static int efm32_probe(struct flash_bank *bank)
 		return ret;
 
 	if (efm32_mcu_info->family_data->series == 0 ||
-	    efm32_mcu_info->family_data->series == 1 ||
-	    FIELD_GET(EFM32_DI_PARTINFO_FAMILY_MASK, efm32_mcu_info->part_info) == 21 ||
-	    FIELD_GET(EFM32_DI_PARTINFO_FAMILY_MASK, efm32_mcu_info->part_info) == 22)
+		efm32_mcu_info->family_data->series == 1 ||
+		FIELD_GET(EFM32_DI_PARTINFO_FAMILY_MASK, efm32_mcu_info->part_info) == 21 ||
+		FIELD_GET(EFM32_DI_PARTINFO_FAMILY_MASK, efm32_mcu_info->part_info) == 22)
 		base_address = EFM32_FLASH_BASE_V1;
 
 	LOG_INFO("detected part: %s",
-		 efm32_get_str_identifier(efm32_mcu_info, strbuf, sizeof(strbuf)));
+			 efm32_get_str_identifier(efm32_mcu_info, strbuf, sizeof(strbuf)));
 	LOG_INFO("flash size = %d KiB", efm32_mcu_info->flash_sz_kib);
 	LOG_INFO("flash page size = %d B", efm32_mcu_info->page_size);
 
@@ -1210,8 +1210,8 @@ static int efm32_probe(struct flash_bank *bank)
 	}
 	bank->size = bank->num_sectors * efm32_mcu_info->page_size;
 	bank->sectors = alloc_block_array(0,
-					  efm32_mcu_info->page_size,
-					  bank->num_sectors);
+									  efm32_mcu_info->page_size,
+									  bank->num_sectors);
 	if (!bank->sectors)
 		return ERROR_FAIL;
 
@@ -1273,9 +1273,9 @@ static int efm32_get_info(struct flash_bank *bank, struct command_invocation *cm
 	}
 
 	command_print_sameline(cmd, "%s",
-			       efm32_get_str_identifier(&efm32_info->info,
-							strbuf,
-							sizeof(strbuf)));
+						   efm32_get_str_identifier(&efm32_info->info,
+													strbuf,
+													sizeof(strbuf)));
 	return ERROR_OK;
 }
 

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 218 +++++++++++++++++++++++++-------------------------
 1 file changed, 109 insertions(+), 109 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1469-g5f1fef005

From: openocd-gerrit <ope...@us...> - 2026-04-26 05:13:11

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  5f1fef0055e167ba25268ab9c11401cb8f5cc463 (commit)
      from  5e6e0a3556ef9f1b2569c0e97720100648aa4395 (commit)

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- Log -----------------------------------------------------------------
commit 5f1fef0055e167ba25268ab9c11401cb8f5cc463
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Fri Jan 23 13:38:01 2026 +0100

    tcl/target: Add support for Silabs Series 2 products
    
    Let's introduce one file per EFR32/EFM32 family so the final user
    does not have to find the tweaks for every parts.
    
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: I544282be675e3dbf9194da615d7f8865631612a2
    Reviewed-on: https://review.openocd.org/c/openocd/+/9399
    Reviewed-by: zapb <de...@za...>
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/tcl/target/silabs/xg21.cfg b/tcl/target/silabs/xg21.cfg
new file mode 100644
index 000000000..bc6e50cea
--- /dev/null
+++ b/tcl/target/silabs/xg21.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2026 Silicon Laboratories Inc.
+#
+# Silicon Labs EFM32PG21/EFR32xG21 target
+
+set FLASHBASE 0x00000000
+source [find target/silabs/series2.cfg]
diff --git a/tcl/target/silabs/xg23.cfg b/tcl/target/silabs/xg23.cfg
new file mode 100644
index 000000000..c166f2fc4
--- /dev/null
+++ b/tcl/target/silabs/xg23.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2026 Silicon Laboratories Inc.
+#
+# Silicon Labs EFM32PG23/EFR32xG23 target
+
+set FLASHBASE 0x08000000
+source [find target/silabs/series2.cfg]
diff --git a/tcl/target/silabs/xg24.cfg b/tcl/target/silabs/xg24.cfg
new file mode 100644
index 000000000..ad40c597e
--- /dev/null
+++ b/tcl/target/silabs/xg24.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2026 Silicon Laboratories Inc.
+#
+# Silicon Labs EFM32PG24/EFR32xG24 target
+
+set FLASHBASE 0x08000000
+source [find target/silabs/series2.cfg]
diff --git a/tcl/target/silabs/xg25.cfg b/tcl/target/silabs/xg25.cfg
new file mode 100644
index 000000000..e238755be
--- /dev/null
+++ b/tcl/target/silabs/xg25.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2026 Silicon Laboratories Inc.
+#
+# Silicon Labs EFM32PG25/EFR32xG25 target
+
+set FLASHBASE 0x08000000
+source [find target/silabs/series2.cfg]
diff --git a/tcl/target/silabs/xg26.cfg b/tcl/target/silabs/xg26.cfg
new file mode 100644
index 000000000..8aa0c7af1
--- /dev/null
+++ b/tcl/target/silabs/xg26.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2026 Silicon Laboratories Inc.
+#
+# Silicon Labs EFM32PG26/EFR32xG26 target
+
+set FLASHBASE 0x08000000
+source [find target/silabs/series2.cfg]
diff --git a/tcl/target/silabs/xg28.cfg b/tcl/target/silabs/xg28.cfg
new file mode 100644
index 000000000..15705c486
--- /dev/null
+++ b/tcl/target/silabs/xg28.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2026 Silicon Laboratories Inc.
+#
+# Silicon Labs EFM32PG28/EFR32xG28 target
+
+set FLASHBASE 0x08000000
+source [find target/silabs/series2.cfg]
diff --git a/tcl/target/silabs/xg29.cfg b/tcl/target/silabs/xg29.cfg
new file mode 100644
index 000000000..224b516fb
--- /dev/null
+++ b/tcl/target/silabs/xg29.cfg
@@ -0,0 +1,7 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2026 Silicon Laboratories Inc.
+#
+# Silicon Labs EFM32PG29/EFR32xG29 target
+
+set FLASHBASE 0x08000000
+source [find target/silabs/series2.cfg]

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/silabs/xg21.cfg | 7 +++++++
 tcl/target/silabs/xg23.cfg | 7 +++++++
 tcl/target/silabs/xg24.cfg | 7 +++++++
 tcl/target/silabs/xg25.cfg | 7 +++++++
 tcl/target/silabs/xg26.cfg | 7 +++++++
 tcl/target/silabs/xg28.cfg | 7 +++++++
 tcl/target/silabs/xg29.cfg | 7 +++++++
 7 files changed, 49 insertions(+)
 create mode 100644 tcl/target/silabs/xg21.cfg
 create mode 100644 tcl/target/silabs/xg23.cfg
 create mode 100644 tcl/target/silabs/xg24.cfg
 create mode 100644 tcl/target/silabs/xg25.cfg
 create mode 100644 tcl/target/silabs/xg26.cfg
 create mode 100644 tcl/target/silabs/xg28.cfg
 create mode 100644 tcl/target/silabs/xg29.cfg


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1468-g5e6e0a355

From: openocd-gerrit <ope...@us...> - 2026-04-26 05:12:45

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
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The branch, master has been updated
       via  5e6e0a3556ef9f1b2569c0e97720100648aa4395 (commit)
      from  291030b5ab2b26ed775a59db508b71fdeb6a867d (commit)

Those revisions listed above that are new to this repository have
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- Log -----------------------------------------------------------------
commit 5e6e0a3556ef9f1b2569c0e97720100648aa4395
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Tue Feb 3 17:30:09 2026 +0100

    tcl/target: Add support for Silabs Series 2
    
    Add the required TCL file for Silabs Series-2. This file is inspired of
    efm32.cfg.
    
    For the consistency, this patch also introduce silabs/series0.cfg and
    silabs/series1.cfg. We keep efm32.cfg for the backward compatibility.
    
    Co-developed-by: Peter Johanson <pe...@pe...>
    Signed-off-by: Peter Johanson <pe...@pe...>
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: Ic923206617e5e5317bc68d9b5ccdd4604b7e72d7
    Reviewed-on: https://review.openocd.org/c/openocd/+/9452
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/tcl/target/efm32.cfg b/tcl/target/efm32.cfg
index 2187c0aca..fe793d0f5 100644
--- a/tcl/target/efm32.cfg
+++ b/tcl/target/efm32.cfg
@@ -1,55 +1,4 @@
-# SPDX-License-Identifier: GPL-2.0-or-later
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2026 Silicon Laboratories Inc.
 
-#
-# Silicon Labs (formerly Energy Micro) EFM32 target
-#
-# Note: All EFM32 chips have SWD support, but only newer series 1
-# chips have JTAG support.
-#
-
-source [find target/swj-dp.tcl]
-
-if { [info exists CHIPNAME] } {
-   set _CHIPNAME $CHIPNAME
-} else {
-   set _CHIPNAME efm32
-}
-
-# Work-area is a space in RAM used for flash programming
-# By default use 2kB
-if { [info exists WORKAREASIZE] } {
-   set _WORKAREASIZE $WORKAREASIZE
-} else {
-   set _WORKAREASIZE 0x800
-}
-
-if { [info exists CPUTAPID] } {
-   set _CPUTAPID $CPUTAPID
-} else {
-   if { [using_jtag] } {
-      set _CPUTAPID 0x4ba00477
-   } {
-      set _CPUTAPID 0x2ba01477
-   }
-}
-
-swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
-dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
-
-adapter speed 1000
-
-set _TARGETNAME $_CHIPNAME.cpu
-target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
-
-$_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
-
-set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME efm32 0 0 0 0 $_TARGETNAME
-flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
-flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
-
-if {![using_hla]} {
-   # if srst is not fitted use SYSRESETREQ to
-   # perform a soft reset
-   cortex_m reset_config sysresetreq
-}
+source [find target/silabs/series0.cfg]
diff --git a/tcl/target/efm32.cfg b/tcl/target/silabs/series0.cfg
similarity index 74%
copy from tcl/target/efm32.cfg
copy to tcl/target/silabs/series0.cfg
index 2187c0aca..c0cfcb2a1 100644
--- a/tcl/target/efm32.cfg
+++ b/tcl/target/silabs/series0.cfg
@@ -10,27 +10,27 @@
 source [find target/swj-dp.tcl]
 
 if { [info exists CHIPNAME] } {
-   set _CHIPNAME $CHIPNAME
+	set _CHIPNAME $CHIPNAME
 } else {
-   set _CHIPNAME efm32
+	set _CHIPNAME efm32
 }
 
 # Work-area is a space in RAM used for flash programming
 # By default use 2kB
 if { [info exists WORKAREASIZE] } {
-   set _WORKAREASIZE $WORKAREASIZE
+	set _WORKAREASIZE $WORKAREASIZE
 } else {
-   set _WORKAREASIZE 0x800
+	set _WORKAREASIZE 0x800
 }
 
 if { [info exists CPUTAPID] } {
-   set _CPUTAPID $CPUTAPID
+	set _CPUTAPID $CPUTAPID
 } else {
-   if { [using_jtag] } {
-      set _CPUTAPID 0x4ba00477
-   } {
-      set _CPUTAPID 0x2ba01477
-   }
+	if { [using_jtag] } {
+		set _CPUTAPID 0x4ba00477
+	} {
+		set _CPUTAPID 0x2ba01477
+	}
 }
 
 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
@@ -49,7 +49,7 @@ flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
 flash bank lockbits.flash efm32 0x0FE04000 0 0 0 $_TARGETNAME
 
 if {![using_hla]} {
-   # if srst is not fitted use SYSRESETREQ to
-   # perform a soft reset
-   cortex_m reset_config sysresetreq
+	# if srst is not fitted use SYSRESETREQ to
+	# perform a soft reset
+	cortex_m reset_config sysresetreq
 }
diff --git a/tcl/target/silabs/series1.cfg b/tcl/target/silabs/series1.cfg
new file mode 100644
index 000000000..fe793d0f5
--- /dev/null
+++ b/tcl/target/silabs/series1.cfg
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2026 Silicon Laboratories Inc.
+
+source [find target/silabs/series0.cfg]
diff --git a/tcl/target/silabs/series2.cfg b/tcl/target/silabs/series2.cfg
new file mode 100644
index 000000000..f3182a502
--- /dev/null
+++ b/tcl/target/silabs/series2.cfg
@@ -0,0 +1,241 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2026 Silicon Laboratories Inc.
+#
+# Silicon Labs Series 2 targets. These target are usually branded as EFM32PG2x
+# or EFR32xG2x (eg. EFM32PG28, EFR32MG27, ...).
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME efm32
+}
+
+# Work-area is a space in RAM used for flash programming. By default use 2kB
+if { [info exists WORKAREASIZE] } {
+	set _WORKAREASIZE $WORKAREASIZE
+} else {
+	set _WORKAREASIZE 0x800
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	# Cortex-M33 TAP IDs for Series 2
+	if { [using_jtag] } {
+		set _CPUTAPID 0x6ba00477
+	} {
+		set _CPUTAPID 0x6ba02477
+	}
+}
+
+# Family group xg21 and xg22 has flash base address 0x00000000. The others has
+# flash base address 0x08000000
+if { [info exists FLASHBASE] } {
+	set _FLASHBASE $FLASHBASE
+} else {
+	set _FLASHBASE 0x08000000
+}
+
+swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+adapter speed 1000
+
+# DCI (Debug Control Interface) is accessible via MEM-AP 1
+set _DCINAME $_CHIPNAME.dci
+target create $_DCINAME mem_ap -dap $_CHIPNAME.dap -ap-num 1
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+set _FLASHNAME $_CHIPNAME.flash
+flash bank $_FLASHNAME efm32 $_FLASHBASE 0 0 0 $_TARGETNAME
+flash bank userdata.flash efm32 0x0FE00000 0 0 0 $_TARGETNAME
+
+if {![using_hla]} {
+	# if srst is not fitted use SYSRESETREQ to perform a soft reset
+	cortex_m reset_config sysresetreq
+
+	$_TARGETNAME configure -event examine-fail {
+		if [catch silabs_s2_dci_read_se_status errstr] {
+			echo $errstr
+		}
+	}
+}
+
+# Debug Challenge Interface registers. See
+#   https://docs.silabs.com/iot-security/1.2.2/series2-secure-debug/
+#   https://docs.silabs.com/iot-security/1.2.2/efr32-dci-swd-programming/
+set _DCI_REG_WDATA   0x1000
+set _DCI_REG_RDATA   0x1004
+set _DCI_REG_STATUS  0x1008
+set _DCI_REG_ID      0x10FC
+
+proc silabs_s2_dci_connect {} {
+	global _DCINAME _DCI_REG_ID
+
+	if [catch {$_DCINAME read_memory $_DCI_REG_ID 32 1} dciid] {
+		return -code error "Failed to read DCIID"
+	}
+	if {$dciid != 0xdc11d} {
+		return -code error "Failed to read correct DCIID (got $dciid)"
+	}
+	echo "Successfully connected to DCI"
+}
+
+proc silabs_s2_dci_read_status {} {
+	global _DCINAME _DCI_REG_STATUS
+
+	return [$_DCINAME read_memory $_DCI_REG_STATUS 32 1]
+}
+
+proc silabs_s2_dci_write_cmd {dci_write_word} {
+	global _DCINAME _DCI_REG_WDATA
+
+	for {set i 0} {$i < 100} {incr i} {
+		set dcistatus [silabs_s2_dci_read_status]
+
+		if {$dcistatus & 1} {
+			echo "DCI WPENDING bit set, retrying"
+			sleep 10
+			continue
+		}
+
+		if {$dcistatus & 0x100} {
+			echo "DCI RDATAVALID is set, can't write to DCIWRITE"
+			return -1
+		}
+
+		$_DCINAME write_memory $_DCI_REG_WDATA 32 $dci_write_word
+		return 0
+	}
+
+	echo "DCI write timeout"
+	return -1
+}
+
+proc silabs_s2_dci_read_response {} {
+	global _DCINAME _DCI_REG_RDATA
+
+	for {set i 0} {$i < 100} {incr i} {
+		set dcistatus [silabs_s2_dci_read_status]
+
+		if {$dcistatus & 0x100} {
+			return [$_DCINAME read_memory $_DCI_REG_RDATA 32 1]
+		}
+
+		echo "DCI RDATAVALID is not set, retrying"
+		sleep 10
+	}
+
+	echo "DCI read timeout"
+	return -1
+}
+
+proc silabs_s2_dci_device_erase {} {
+	silabs_s2_dci_connect
+	poll off
+
+	silabs_s2_dci_write_cmd 8
+	silabs_s2_dci_write_cmd 0x430F0000
+
+	sleep 2000
+	echo "Device erase command sent. Device should now be erased and debug should be available again after a reset"
+	poll on
+}
+
+proc silabs_s2_dci_device_lock {} {
+	echo "Attempting to activate debug lock..."
+
+	silabs_s2_dci_connect
+	poll off
+
+	silabs_s2_dci_write_cmd 8
+	silabs_s2_dci_write_cmd 0x430C0000
+
+	set recvlen [silabs_s2_dci_read_response]
+
+	if {$recvlen & 0xFFFF0000} {
+		echo "command response was not OK, got $recvlen as command response. Can't continue."
+		poll on
+		return
+	}
+
+	sleep 100
+
+	silabs_s2_dci_read_se_status
+	poll on
+}
+
+proc silabs_s2_dci_read_se_status {} {
+	silabs_s2_dci_connect
+	poll off
+
+	# Write len
+	silabs_s2_dci_write_cmd 8
+
+	# Write cmd
+	silabs_s2_dci_write_cmd 0xFE010000
+
+	set recvlen [silabs_s2_dci_read_response]
+
+	if {$recvlen & 0xFFFF0000} {
+		echo "command response was not OK, got $recvlen as command response. Can't continue."
+		poll on
+		return
+	}
+
+	set debuglock_idx 3
+
+	if {$recvlen == 0x28} {
+		set debuglock_idx 7
+	}
+
+	incr recvlen -4
+
+	for {set i 0} {$recvlen > 0} {incr i} {
+		set recvlen [expr {$recvlen - 4}]
+		set sestatusarray($i) [silabs_s2_dci_read_response]
+	}
+
+	poll on
+
+	echo "DCI SESTATUS response:"
+
+	set debuglock $sestatusarray($debuglock_idx)
+
+	if {$debuglock & 0x01} {
+		echo "Debug lock (config): Enabled"
+	} else {
+		echo "Debug lock (config): Disabled"
+	}
+
+	if {$debuglock & 0x02} {
+		echo "Device erase: Enabled"
+	} else {
+		echo "Device erase: Disabled"
+	}
+
+	if {$debuglock & 0x04} {
+		echo "Secure debug: Enabled"
+	} else {
+		echo "Secure debug: Disabled"
+	}
+
+	if {$debuglock & 0x20} {
+		poll off
+		echo "Debug lock (hw status): Enabled"
+		echo ""
+		echo " * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *"
+		echo "  You will not be able to communicate with this device"
+		echo "  unless you perform a device erase (if available, indicated above)!"
+		echo "  Try silabs_s2_dci_device_erase to attempt erase."
+		echo " * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *"
+	} else {
+		echo "Debug lock (hw status): Disabled"
+	}
+}

-----------------------------------------------------------------------

Summary of changes:
 tcl/target/efm32.cfg                         |  57 +------
 tcl/target/{efm32.cfg => silabs/series0.cfg} |  26 +--
 tcl/target/silabs/series1.cfg                |   4 +
 tcl/target/silabs/series2.cfg                | 241 +++++++++++++++++++++++++++
 4 files changed, 261 insertions(+), 67 deletions(-)
 copy tcl/target/{efm32.cfg => silabs/series0.cfg} (74%)
 create mode 100644 tcl/target/silabs/series1.cfg
 create mode 100644 tcl/target/silabs/series2.cfg


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From: openocd-gerrit <ope...@us...> - 2026-04-26 05:12:07

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- Log -----------------------------------------------------------------
commit 291030b5ab2b26ed775a59db508b71fdeb6a867d
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Mon Feb 2 11:59:07 2026 +0100

    flash/nor/efm32: Update copyright
    
    The changes introduced in the previous patches has been inspired from
    various sources. I report here the various the copyrights I have found.
    Note that everything was published under MIT.
    
    Here are the various references I have found:
    
      Karl Palsson:
        https://review.openocd.org/c/openocd/+/6173
      Michael TeichgrÃ¤ber:
        https://github.com/knieriem/openocd-efm32-series2
      Henrik Persson:
        https://github.com/mikrodust-henrikp/openocd-efm32-series2
      Peter Johanson:
        https://github.com/zephyrproject-rtos/openocd/pull/70
    
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: Id87f04c50b0d45c415697811913a6a158d745e62
    Reviewed-on: https://review.openocd.org/c/openocd/+/9451
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 5a1a6a325..031b3d99a 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -16,8 +16,17 @@
  *   Copyright (C) 2014 Nemui Trinomius                                    *
  *   nem...@li...                                        *
  *                                                                         *
+ *   Copyright (C) 2021 Michael TeichgrÃ¤ber                                *
+ *   mte...@gm...                                                  *
+ *                                                                         *
  *   Copyright (C) 2021 Doug Brunner                                       *
  *   dou...@gm...                                              *
+ *                                                                         *
+ *   Copyright (C) 2022 Mikrodust AB                                       *
+ *   hen...@mi...                                          *
+ *                                                                         *
+ *   Copyright (c) 2026 Silicon Laboratories Inc.                          *
+ *   jer...@si...                                            *
  ***************************************************************************/
 
 #ifdef HAVE_CONFIG_H

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 9 +++++++++
 1 file changed, 9 insertions(+)


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- Log -----------------------------------------------------------------
commit c83c9688e08aaaa3ae38c60c929b31a9f24ed2c3
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Thu Feb 5 08:47:38 2026 +0100

    flash/nor/efm32: Support write flash on Series-2
    
    The MSC (Memory System Controller) on Silabs Series-2 does no t has the
    same register map than Series-0 and Series-1. These offset can't be
    hardcoded anymore.
    
    This patch provides a structure to store the offset per series. These
    offsets are also used in the byte code embedded in the driver. For this
    case, we use to version of the byte code (this seems a better solution than
    trying to generate byte code on runtime).
    
    In addition to the offset, the bits in the status register are also changed
    a bit. To work around the problem, we removed the declarations that differ
    between the  two Series.
    
    EFM32_MSC_STATUS_ERASEABORTED_MASK was used to display a warning is case of
    error. Since this bit is not the same between Series-0/1 and Series-2, I
    have just dropped the warning.
    
    Co-developed-by: Peter Johanson <pe...@pe...>
    Signed-off-by: Peter Johanson <pe...@pe...>
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: If645e3fea570c4a3f0670e74d243b0ac9b579ecb
    Reviewed-on: https://review.openocd.org/c/openocd/+/9450
    Reviewed-by: zapb <de...@za...>
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/contrib/loaders/flash/silabs/Makefile b/contrib/loaders/flash/silabs/Makefile
new file mode 100644
index 000000000..7323494ec
--- /dev/null
+++ b/contrib/loaders/flash/silabs/Makefile
@@ -0,0 +1,32 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+BIN2C = ../../../../src/helper/bin2char.sh
+
+CROSS_COMPILE ?= arm-none-eabi-
+
+CC=$(CROSS_COMPILE)gcc
+OBJCOPY=$(CROSS_COMPILE)objcopy
+OBJDUMP=$(CROSS_COMPILE)objdump
+
+
+AFLAGS = -static -nostartfiles -mlittle-endian -Wa,-EL
+CFLAGS = -c -mthumb -nostdlib -nostartfiles -Os -g -fPIC
+
+all: silabs_s0_s1.inc silabs_s2.inc
+
+.PHONY: clean
+
+%.elf: %.S
+	$(CC) $(AFLAGS) $< -o $@
+
+%.lst: %.elf
+	$(OBJDUMP) -S $< > $@
+
+%.bin: %.elf
+	$(OBJCOPY) -Obinary $< $@
+
+%.inc: %.bin
+	$(BIN2C) < $< > $@
+
+clean:
+	-rm -f *.elf *.lst *.bin *.inc
diff --git a/contrib/loaders/flash/efm32.S b/contrib/loaders/flash/silabs/silabs_s0_s1.S
similarity index 100%
copy from contrib/loaders/flash/efm32.S
copy to contrib/loaders/flash/silabs/silabs_s0_s1.S
diff --git a/contrib/loaders/flash/silabs/silabs_s0_s1.inc b/contrib/loaders/flash/silabs/silabs_s0_s1.inc
new file mode 100644
index 000000000..40e616b32
--- /dev/null
+++ b/contrib/loaders/flash/silabs/silabs_s0_s1.inc
@@ -0,0 +1,7 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x01,0x26,0x86,0x60,0x16,0x68,0x00,0x2e,0x22,0xd0,0x55,0x68,0xb5,0x42,0xf9,0xd0,
+0x04,0x61,0x01,0x26,0xc6,0x60,0xc6,0x69,0x06,0x27,0x3e,0x42,0x16,0xd1,0xc6,0x69,
+0x08,0x27,0x3e,0x42,0xfb,0xd0,0x2e,0x68,0x86,0x61,0x08,0x26,0xc6,0x60,0x04,0x35,
+0x04,0x34,0xc6,0x69,0x01,0x27,0x3e,0x42,0xfb,0xd1,0x9d,0x42,0x01,0xd3,0x15,0x46,
+0x08,0x35,0x55,0x60,0x01,0x39,0x00,0x29,0x02,0xd0,0xdb,0xe7,0x00,0x20,0x50,0x60,
+0x30,0x46,0x00,0xbe,
diff --git a/contrib/loaders/flash/efm32.S b/contrib/loaders/flash/silabs/silabs_s2.S
similarity index 92%
rename from contrib/loaders/flash/efm32.S
rename to contrib/loaders/flash/silabs/silabs_s2.S
index b6938512a..d7f43855c 100644
--- a/contrib/loaders/flash/efm32.S
+++ b/contrib/loaders/flash/silabs/silabs_s2.S
@@ -26,9 +26,9 @@
 	 */
 
 /* offsets of registers from flash reg base */
-#define EFM32_MSC_WRITECTRL_OFFSET      0x008
-#define EFM32_MSC_WRITECMD_OFFSET       0x00c
-#define EFM32_MSC_ADDRB_OFFSET          0x010
+#define EFM32_MSC_WRITECTRL_OFFSET      0x00c
+#define EFM32_MSC_WRITECMD_OFFSET       0x010
+#define EFM32_MSC_ADDRB_OFFSET          0x014
 #define EFM32_MSC_WDATA_OFFSET          0x018
 #define EFM32_MSC_STATUS_OFFSET         0x01c
 
@@ -81,7 +81,7 @@ busy:
 
 	cmp     r5, r3          /* wrap rp at end of buffer */
 	bcc     no_wrap
-	mov     r5, r2
+	adds    r5, r2, #0
 	adds    r5, #8
 no_wrap:
 	str     r5, [r2, #4]    /* store rp */
@@ -93,5 +93,5 @@ error:
 	movs    r0, #0
 	str     r0, [r2, #4]    /* set rp = 0 on error */
 exit:
-	mov     r0, r6          /* return status in r0 */
+	adds    r0, r6, #0
 	bkpt    #0
diff --git a/contrib/loaders/flash/silabs/silabs_s2.inc b/contrib/loaders/flash/silabs/silabs_s2.inc
new file mode 100644
index 000000000..f0ef04edd
--- /dev/null
+++ b/contrib/loaders/flash/silabs/silabs_s2.inc
@@ -0,0 +1,7 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x01,0x26,0xc6,0x60,0x16,0x68,0x00,0x2e,0x22,0xd0,0x55,0x68,0xb5,0x42,0xf9,0xd0,
+0x44,0x61,0x01,0x26,0x06,0x61,0xc6,0x69,0x06,0x27,0x3e,0x42,0x16,0xd1,0xc6,0x69,
+0x08,0x27,0x3e,0x42,0xfb,0xd0,0x2e,0x68,0x86,0x61,0x08,0x26,0x06,0x61,0x04,0x35,
+0x04,0x34,0xc6,0x69,0x01,0x27,0x3e,0x42,0xfb,0xd1,0x9d,0x42,0x01,0xd3,0x15,0x1c,
+0x08,0x35,0x55,0x60,0x01,0x39,0x00,0x29,0x02,0xd0,0xdb,0xe7,0x00,0x20,0x50,0x60,
+0x30,0x1c,0x00,0xbe,
diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 7a99161a6..5a1a6a325 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -88,22 +88,72 @@ static const struct efm32_dev_info_addr efm32_dev_info_addr[] = {
 	},
 };
 
-#define EFM32_MSC_REG_WRITECTRL              0x0008
+// Offsets relative to msc_regbase
+struct efm32_msc_offset {
 #define EFM32_MSC_WRITECTRL_WREN_MASK        0x0001
-#define EFM32_MSC_REG_WRITECMD               0x000c
+	target_addr_t off_writectrl;
+
 #define EFM32_MSC_WRITECMD_LADDRIM_MASK      0x0001
 #define EFM32_MSC_WRITECMD_ERASEPAGE_MASK    0x0002
 #define EFM32_MSC_WRITECMD_WRITEONCE_MASK    0x0008
-#define EFM32_MSC_REG_ADDRB                  0x0010
-#define EFM32_MSC_REG_WDATA                  0x0018
-#define EFM32_MSC_REG_STATUS                 0x001c
+	target_addr_t off_writecmd;
+	target_addr_t off_addrb;
+	target_addr_t off_wdata;
+
 #define EFM32_MSC_STATUS_BUSY_MASK           0x0001
 #define EFM32_MSC_STATUS_LOCKED_MASK         0x0002
 #define EFM32_MSC_STATUS_INVADDR_MASK        0x0004
 #define EFM32_MSC_STATUS_WDATAREADY_MASK     0x0008
-#define EFM32_MSC_STATUS_WORDTIMEOUT_MASK    0x0010
-#define EFM32_MSC_STATUS_ERASEABORTED_MASK   0x0020
+	target_addr_t off_status;
+
 #define EFM32_MSC_LOCK_LOCKKEY               0x1b71
+	target_addr_t off_lock;
+
+	const uint8_t *flash_write_code;
+	size_t flash_write_code_len;
+};
+
+// see contrib/loaders/flash/efm32.S for source
+static const uint8_t efm32_flash_write_code_s0_s1[] = {
+#include "../../../contrib/loaders/flash/silabs/silabs_s0_s1.inc"
+};
+
+static const uint8_t efm32_flash_write_code_s2[] = {
+#include "../../../contrib/loaders/flash/silabs/silabs_s2.inc"
+};
+
+static const struct efm32_msc_offset efm32_msc_offset[] = {
+	[0] = {
+		.off_writectrl = 0x0008,
+		.off_writecmd  = 0x000c,
+		.off_addrb     = 0x0010,
+		.off_wdata     = 0x0018,
+		.off_status    = 0x001c,
+		.off_lock      = 0x003c,
+		.flash_write_code = efm32_flash_write_code_s0_s1,
+		.flash_write_code_len = sizeof(efm32_flash_write_code_s0_s1),
+	},
+	[1] = {
+		.off_writectrl = 0x0008,
+		.off_writecmd  = 0x000c,
+		.off_addrb     = 0x0010,
+		.off_wdata     = 0x0018,
+		.off_status    = 0x001c,
+		.off_lock      = 0x0040,
+		.flash_write_code = efm32_flash_write_code_s0_s1,
+		.flash_write_code_len = sizeof(efm32_flash_write_code_s0_s1),
+	},
+	[2] = {
+		.off_writectrl = 0x000c,
+		.off_writecmd  = 0x0010,
+		.off_addrb     = 0x0014,
+		.off_wdata     = 0x0018,
+		.off_status    = 0x001c,
+		.off_lock      = 0x003c,
+		.flash_write_code = efm32_flash_write_code_s2,
+		.flash_write_code_len = sizeof(efm32_flash_write_code_s2),
+	},
+};
 
 // Series 2 only
 #define EFM32_CMU_REG_CLKEN1_SET         0x50009068
@@ -144,6 +194,7 @@ struct efm32_family_data {
 struct efm32_info {
 	const struct efm32_family_data *family_data;
 	const struct efm32_dev_info_addr *di_addr;
+	const struct efm32_msc_offset *msc_offset;
 	uint16_t part_num;     // Series 0/1 only
 	uint32_t part_info;    // Series 2 only
 	uint8_t  part_rev;
@@ -269,6 +320,7 @@ static int efm32_read_info(struct flash_bank *bank)
 	}
 
 	efm32_mcu_info->di_addr = &efm32_dev_info_addr[efm32_mcu_info->family_data->series];
+	efm32_mcu_info->msc_offset = &efm32_msc_offset[efm32_mcu_info->family_data->series];
 
 	if (efm32_mcu_info->family_data->series == 2) {
 		ret = target_read_u32(bank->target,
@@ -458,33 +510,33 @@ static int efm32_set_reg_bits(struct flash_bank *bank, uint32_t reg,
 
 static int efm32_set_wren(struct flash_bank *bank, int write_enable)
 {
-	return efm32_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
+
+	return efm32_set_reg_bits(bank,
+				  efm32_info->info.msc_offset->off_writectrl,
 				  EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
 }
 
 static int efm32_msc_lock(struct flash_bank *bank, int lock)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
-	struct efm32_info *efm32_mcu_info = &efm32_info->info;
-	uint32_t val = lock ? 0 : EFM32_MSC_LOCK_LOCKKEY;
-	uint32_t reg;
 
-	if (efm32_mcu_info->family_data->series == 1)
-		reg = 0x040;
-	else
-		reg = 0x03c;
-
-	return efm32_write_reg_u32(bank, reg, val);
+	return efm32_write_reg_u32(bank,
+				   efm32_info->info.msc_offset->off_lock,
+				   lock ? 0 : EFM32_MSC_LOCK_LOCKKEY);
 }
 
 static int efm32_wait_status(struct flash_bank *bank, int timeout_ms,
 			     uint32_t wait_mask, bool wait_for_set)
 {
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	int64_t start_ms = timeval_ms();
 	uint32_t status = 0;
 
 	while (1) {
-		int ret = efm32_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
+		int ret = efm32_read_reg_u32(bank,
+					     efm32_info->info.msc_offset->off_status,
+					     &status);
 		if (ret != ERROR_OK)
 			return ret;
 
@@ -503,9 +555,6 @@ static int efm32_wait_status(struct flash_bank *bank, int timeout_ms,
 		alive_sleep(1);
 	}
 
-	if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
-		LOG_WARNING("page erase was aborted");
-
 	return ERROR_OK;
 }
 
@@ -518,21 +567,27 @@ static int efm32_erase_page(struct flash_bank *bank, uint32_t addr)
 	   4. write ERASEPAGE
 	   5. wait until !STATUS_BUSY
 	 */
-	int ret = 0;
-	uint32_t status = 0;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
+	int ret;
 
 	LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
 
-	ret = efm32_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
+	ret = efm32_write_reg_u32(bank,
+				  efm32_info->info.msc_offset->off_addrb,
+				  addr);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
+	ret = efm32_set_reg_bits(bank,
+				 efm32_info->info.msc_offset->off_writecmd,
 				 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
+	uint32_t status;
+	ret = efm32_read_reg_u32(bank,
+				 efm32_info->info.msc_offset->off_status,
+				 &status);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -546,7 +601,8 @@ static int efm32_erase_page(struct flash_bank *bank, uint32_t addr)
 		return ERROR_FAIL;
 	}
 
-	ret = efm32_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
+	ret = efm32_set_reg_bits(bank,
+				 efm32_info->info.msc_offset->off_writecmd,
 				 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
 	if (ret != ERROR_OK)
 		return ret;
@@ -813,93 +869,26 @@ static int efm32_protect(struct flash_bank *bank, int set, unsigned int first,
 static int efm32_write_block(struct flash_bank *bank, const uint8_t *buf,
 			     uint32_t address, uint32_t count)
 {
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	struct target *target = bank->target;
 	uint32_t buffer_size = 16384;
 	struct working_area *write_algorithm;
 	struct working_area *source;
 	struct reg_param reg_params[5];
 	struct armv7m_algorithm armv7m_info;
-	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	int ret = ERROR_OK;
 
-	/* see contrib/loaders/flash/efm32.S for src */
-	static const uint8_t efm32_flash_write_code[] = {
-		/* #define EFM32_MSC_WRITECTRL_OFFSET      0x008 */
-		/* #define EFM32_MSC_WRITECMD_OFFSET       0x00c */
-		/* #define EFM32_MSC_ADDRB_OFFSET          0x010 */
-		/* #define EFM32_MSC_WDATA_OFFSET          0x018 */
-		/* #define EFM32_MSC_STATUS_OFFSET         0x01c */
-
-			0x01, 0x26,    /* movs    r6, #1 */
-			0x86, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECTRL_OFFSET] */
-
-		/* wait_fifo: */
-			0x16, 0x68,    /* ldr     r6, [r2, #0] */
-			0x00, 0x2e,    /* cmp     r6, #0 */
-			0x22, 0xd0,    /* beq     exit */
-			0x55, 0x68,    /* ldr     r5, [r2, #4] */
-			0xb5, 0x42,    /* cmp     r5, r6 */
-			0xf9, 0xd0,    /* beq     wait_fifo */
-
-			0x04, 0x61,    /* str     r4, [r0, #EFM32_MSC_ADDRB_OFFSET] */
-			0x01, 0x26,    /* movs    r6, #1 */
-			0xc6, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
-			0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
-			0x06, 0x27,    /* movs    r7, #6 */
-			0x3e, 0x42,    /* tst     r6, r7 */
-			0x16, 0xd1,    /* bne     error */
-
-		/* wait_wdataready: */
-			0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
-			0x08, 0x27,    /* movs    r7, #8 */
-			0x3e, 0x42,    /* tst     r6, r7 */
-			0xfb, 0xd0,    /* beq     wait_wdataready */
-
-			0x2e, 0x68,    /* ldr     r6, [r5] */
-			0x86, 0x61,    /* str     r6, [r0, #EFM32_MSC_WDATA_OFFSET] */
-			0x08, 0x26,    /* movs    r6, #8 */
-			0xc6, 0x60,    /* str     r6, [r0, #EFM32_MSC_WRITECMD_OFFSET] */
-
-			0x04, 0x35,    /* adds    r5, #4 */
-			0x04, 0x34,    /* adds    r4, #4 */
-
-		/* busy: */
-			0xc6, 0x69,    /* ldr     r6, [r0, #EFM32_MSC_STATUS_OFFSET] */
-			0x01, 0x27,    /* movs    r7, #1 */
-			0x3e, 0x42,    /* tst     r6, r7 */
-			0xfb, 0xd1,    /* bne     busy */
-
-			0x9d, 0x42,    /* cmp     r5, r3 */
-			0x01, 0xd3,    /* bcc     no_wrap */
-			0x15, 0x46,    /* mov     r5, r2 */
-			0x08, 0x35,    /* adds    r5, #8 */
-
-		/* no_wrap: */
-			0x55, 0x60,    /* str     r5, [r2, #4] */
-			0x01, 0x39,    /* subs    r1, r1, #1 */
-			0x00, 0x29,    /* cmp     r1, #0 */
-			0x02, 0xd0,    /* beq     exit */
-			0xdb, 0xe7,    /* b       wait_fifo */
-
-		/* error: */
-			0x00, 0x20,    /* movs    r0, #0 */
-			0x50, 0x60,    /* str     r0, [r2, #4] */
-
-		/* exit: */
-			0x30, 0x46,    /* mov     r0, r6 */
-			0x00, 0xbe,    /* bkpt    #0 */
-	};
-
 	/* flash write code */
-	if (target_alloc_working_area(target, sizeof(efm32_flash_write_code),
+	if (target_alloc_working_area(target,
+				      efm32_info->info.msc_offset->flash_write_code_len,
 				      &write_algorithm) != ERROR_OK) {
 		LOG_WARNING("no working area available, can't do block memory writes");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
 	ret = target_write_buffer(target, write_algorithm->address,
-				  sizeof(efm32_flash_write_code),
-				  efm32_flash_write_code);
+				  efm32_info->info.msc_offset->flash_write_code_len,
+				  efm32_info->info.msc_offset->flash_write_code);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -981,23 +970,28 @@ static int efm32_write_word(struct flash_bank *bank, uint32_t addr,
 
 	/* FIXME: EFM32G ref states (7.3.2) that writes should be
 	 * performed twice per dword */
-
-	int ret = 0;
-	uint32_t status = 0;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
+	int ret;
 
 	/* if not called, GDB errors will be reported during large writes */
 	keep_alive();
 
-	ret = efm32_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
+	ret = efm32_write_reg_u32(bank,
+				  efm32_info->info.msc_offset->off_addrb,
+				  addr);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
+	ret = efm32_set_reg_bits(bank,
+				 efm32_info->info.msc_offset->off_writecmd,
 				 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
+	uint32_t status;
+	ret = efm32_read_reg_u32(bank,
+				 efm32_info->info.msc_offset->off_status,
+				 &status);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -1018,13 +1012,16 @@ static int efm32_write_word(struct flash_bank *bank, uint32_t addr,
 		return ret;
 	}
 
-	ret = efm32_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
+	ret = efm32_write_reg_u32(bank,
+				  efm32_info->info.msc_offset->off_wdata,
+				  val);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("WDATA write failed");
 		return ret;
 	}
 
-	ret = efm32_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
+	ret = efm32_write_reg_u32(bank,
+				  efm32_info->info.msc_offset->off_writecmd,
 				  EFM32_MSC_WRITECMD_WRITEONCE_MASK);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("WRITECMD write failed");

-----------------------------------------------------------------------

Summary of changes:
 contrib/loaders/flash/{numicro => silabs}/Makefile |   3 +-
 .../flash/{efm32.S => silabs/silabs_s0_s1.S}       |   0
 contrib/loaders/flash/silabs/silabs_s0_s1.inc      |   7 +
 .../loaders/flash/{efm32.S => silabs/silabs_s2.S}  |  10 +-
 contrib/loaders/flash/silabs/silabs_s2.inc         |   7 +
 src/flash/nor/efm32.c                              | 211 ++++++++++-----------
 6 files changed, 125 insertions(+), 113 deletions(-)
 copy contrib/loaders/flash/{numicro => silabs}/Makefile (83%)
 copy contrib/loaders/flash/{efm32.S => silabs/silabs_s0_s1.S} (100%)
 create mode 100644 contrib/loaders/flash/silabs/silabs_s0_s1.inc
 rename contrib/loaders/flash/{efm32.S => silabs/silabs_s2.S} (92%)
 create mode 100644 contrib/loaders/flash/silabs/silabs_s2.inc


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From: openocd-gerrit <ope...@us...> - 2026-04-26 05:11:20

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The branch, master has been updated
       via  47dc8e3cde6ba13b75f58cde21c4ddc52ceb43ac (commit)
      from  fcfbe3dd6b77f1305696d2a886974cf15847b172 (commit)

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- Log -----------------------------------------------------------------
commit 47dc8e3cde6ba13b75f58cde21c4ddc52ceb43ac
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Wed Feb 4 13:57:35 2026 +0100

    flash/nor/efm32: Support alternative flashbase address
    
    Silicon Labs Series-2 chips don't start the flash at the same address.
    
    Co-developed-by: Peter Johanson <pe...@pe...>
    Signed-off-by: Peter Johanson <pe...@pe...>
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: I586e6b0e26de141db298dbb9329413642cb8a840
    Reviewed-on: https://review.openocd.org/c/openocd/+/9449
    Tested-by: jenkins
    Reviewed-by: zapb <de...@za...>
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 565d457a7..7a99161a6 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -36,7 +36,8 @@
  */
 #define EFM32_FLASH_OPERATION_TIMEOUT   100
 
-#define EFM32_FLASH_BASE                0
+#define EFM32_FLASH_BASE_V1             0x00000000
+#define EFM32_FLASH_BASE_V2             0x08000000
 
 /* size in bytes, not words; must fit all Gecko devices */
 #define LOCKWORDS_SZ                    512
@@ -117,7 +118,8 @@ enum efm32_bank_index {
 static int efm32_get_bank_index(target_addr_t base)
 {
 	switch (base) {
-	case EFM32_FLASH_BASE:
+	case EFM32_FLASH_BASE_V1:
+	case EFM32_FLASH_BASE_V2:
 		return EFM32_BANK_INDEX_MAIN;
 	case EFM32_MSC_USER_DATA:
 		return EFM32_BANK_INDEX_USER_DATA;
@@ -732,7 +734,8 @@ static int efm32_get_page_lock(struct flash_bank *bank, size_t page)
 	uint32_t mask = 0;
 
 	switch (bank->base) {
-	case EFM32_FLASH_BASE:
+	case EFM32_FLASH_BASE_V1:
+	case EFM32_FLASH_BASE_V2:
 		dw = efm32_info->lb_page[page >> 5];
 		mask = BIT(page & 0x1f);
 		break;
@@ -753,7 +756,8 @@ static int efm32_set_page_lock(struct flash_bank *bank, size_t page, int set)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
-	if (bank->base != EFM32_FLASH_BASE) {
+	if (bank->base != EFM32_FLASH_BASE_V1 &&
+	    bank->base != EFM32_FLASH_BASE_V2) {
 		LOG_ERROR("Locking user and lockbits pages is not supported yet");
 		return ERROR_FAIL;
 	}
@@ -1162,6 +1166,7 @@ static int efm32_probe(struct flash_bank *bank)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	struct efm32_info *efm32_mcu_info = &efm32_info->info;
+	uint32_t base_address = EFM32_FLASH_BASE_V2;
 	int bank_index = efm32_get_bank_index(bank->base);
 	char strbuf[256];
 	int ret;
@@ -1175,6 +1180,12 @@ static int efm32_probe(struct flash_bank *bank)
 	if (ret != ERROR_OK)
 		return ret;
 
+	if (efm32_mcu_info->family_data->series == 0 ||
+	    efm32_mcu_info->family_data->series == 1 ||
+	    FIELD_GET(EFM32_DI_PARTINFO_FAMILY_MASK, efm32_mcu_info->part_info) == 21 ||
+	    FIELD_GET(EFM32_DI_PARTINFO_FAMILY_MASK, efm32_mcu_info->part_info) == 22)
+		base_address = EFM32_FLASH_BASE_V1;
+
 	LOG_INFO("detected part: %s",
 		 efm32_get_str_identifier(efm32_mcu_info, strbuf, sizeof(strbuf)));
 	LOG_INFO("flash size = %d KiB", efm32_mcu_info->flash_sz_kib);
@@ -1185,7 +1196,7 @@ static int efm32_probe(struct flash_bank *bank)
 	free(bank->sectors);
 	bank->sectors = NULL;
 
-	if (bank->base == EFM32_FLASH_BASE) {
+	if (bank->base == base_address) {
 		bank->num_sectors = efm32_mcu_info->flash_sz_kib * 1024 / efm32_mcu_info->page_size;
 		assert(bank->num_sectors > 0);
 	} else {

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 21 ++++++++++++++++-----
 1 file changed, 16 insertions(+), 5 deletions(-)


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The branch, master has been updated
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       via  79a0b8b78c48b72e1af32e218ac08f732c446faf (commit)
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- Log -----------------------------------------------------------------
commit fcfbe3dd6b77f1305696d2a886974cf15847b172
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Tue Feb 3 13:25:43 2026 +0100

    flash/nor/efm32: Learn how to start CMU before to flash
    
    Silabs Series-2 SoC requires to configure the CMU (Clock Management
    Unit) before to access to the flash.
    
    Co-developed-by: Peter Johanson <pe...@pe...>
    Signed-off-by: Peter Johanson <pe...@pe...>
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: I3fcedd2fcf24307e98ce47ba5eca1880fc8e5bc5
    Reviewed-on: https://review.openocd.org/c/openocd/+/9448
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: zapb <de...@za...>

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 279af1d5d..565d457a7 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -104,6 +104,9 @@ static const struct efm32_dev_info_addr efm32_dev_info_addr[] = {
 #define EFM32_MSC_STATUS_ERASEABORTED_MASK   0x0020
 #define EFM32_MSC_LOCK_LOCKKEY               0x1b71
 
+// Series 2 only
+#define EFM32_CMU_REG_CLKEN1_SET         0x50009068
+
 enum efm32_bank_index {
 	EFM32_BANK_INDEX_MAIN,
 	EFM32_BANK_INDEX_USER_DATA,
@@ -390,6 +393,48 @@ static void efm32_free_driver_priv(struct flash_bank *bank)
 	}
 }
 
+static int efm32_msc_clock_enable(struct flash_bank *bank)
+{
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
+
+	if (efm32_info->info.family_data->series == 0 ||
+	    efm32_info->info.family_data->series == 1)
+		return ERROR_OK;
+
+	unsigned int s2_family = FIELD_GET(EFM32_DI_PARTINFO_FAMILY_MASK,
+			      efm32_info->info.part_info);
+	uint32_t msc_clken;
+	switch (s2_family) {
+	case 21:
+		msc_clken = 0;
+		break;
+	case 22:
+	case 27:
+	case 29:
+		msc_clken = BIT(17);
+		break;
+	case 23:
+	case 24:
+	case 25:
+	case 26:
+	case 28:
+		msc_clken = BIT(16);
+		break;
+	default:
+		LOG_WARNING("Don't know EFR/EFM Gx family number, can't set MSC register. Use default values..");
+		msc_clken = BIT(16);
+	}
+	int ret = target_write_u32(bank->target,
+			       EFM32_CMU_REG_CLKEN1_SET,
+			       msc_clken);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("Failed to enable MSC clock");
+		return ret;
+	}
+
+	return ERROR_OK;
+}
+
 /* set or reset given bits in a register */
 static int efm32_set_reg_bits(struct flash_bank *bank, uint32_t reg,
 			      uint32_t bitmask, int set)
@@ -519,6 +564,12 @@ static int efm32_erase(struct flash_bank *bank, unsigned int first,
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
+	ret = efm32_msc_clock_enable(bank);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("Failed to enable MSC clock");
+		return ret;
+	}
+
 	efm32_msc_lock(bank, 0);
 	ret = efm32_set_wren(bank, 1);
 	if (ret != ERROR_OK) {
@@ -1019,6 +1070,10 @@ static int efm32_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 	uint32_t words_remaining = count / 4;
 	int retval, retval2;
 
+	retval = efm32_msc_clock_enable(bank);
+	if (retval != ERROR_OK)
+		goto cleanup;
+
 	/* unlock flash registers */
 	efm32_msc_lock(bank, 0);
 	retval = efm32_set_wren(bank, 1);
@@ -1228,6 +1283,12 @@ COMMAND_HANDLER(efm32_handle_debuglock_command)
 	uint32_t *ptr = efm32_info->lb_page + 127;
 	*ptr = 0;
 
+	ret = efm32_msc_clock_enable(bank);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("Failed to enable MSC clock");
+		return ret;
+	}
+
 	ret = efm32_write_lock_data(bank);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to write LB page");

commit 79a0b8b78c48b72e1af32e218ac08f732c446faf
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Fri Feb 6 21:35:53 2026 +0100

    flash/nor/efm32: Don't read lock bank on Series 2
    
    Series-2 don't support lock bank. So, just return an error.
    
    In addition, drop efm32_read_lock_data() from efm32_probe(). It seems it
    mainly used to provide a sanity check about lock bank access. However,
    it makes more sense to call it from efm32_protect() rather than from
    efm32_probe().
    
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: Ide910a33e54586c00dc083e1e825e17a76507baa
    Reviewed-on: https://review.openocd.org/c/openocd/+/9455
    Reviewed-by: zapb <de...@za...>
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 7392463ca..279af1d5d 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -720,14 +720,24 @@ static int efm32_set_page_lock(struct flash_bank *bank, size_t page, int set)
 static int efm32_protect(struct flash_bank *bank, int set, unsigned int first,
 			 unsigned int last)
 {
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	struct target *target = bank->target;
 	int ret = 0;
 
+	if (efm32_info->info.family_data->series == 2)
+		return ERROR_FLASH_OPER_UNSUPPORTED;
+
 	if (target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
+	ret = efm32_read_lock_data(bank);
+	if (ret != ERROR_OK) {
+		LOG_ERROR("Failed to read LB data");
+		return ret;
+	}
+
 	for (unsigned int i = first; i <= last; i++) {
 		ret = efm32_set_page_lock(bank, i, set);
 		if (ret != ERROR_OK) {
@@ -1123,12 +1133,6 @@ static int efm32_probe(struct flash_bank *bank)
 	if (bank->base == EFM32_FLASH_BASE) {
 		bank->num_sectors = efm32_mcu_info->flash_sz_kib * 1024 / efm32_mcu_info->page_size;
 		assert(bank->num_sectors > 0);
-
-		ret = efm32_read_lock_data(bank);
-		if (ret != ERROR_OK) {
-			LOG_ERROR("Failed to read LB data");
-			return ret;
-		}
 	} else {
 		bank->num_sectors = 1;
 	}
@@ -1158,9 +1162,13 @@ static int efm32_auto_probe(struct flash_bank *bank)
 
 static int efm32_protect_check(struct flash_bank *bank)
 {
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	struct target *target = bank->target;
 	int ret = 0;
 
+	if (efm32_info->info.family_data->series == 2)
+		return ERROR_FLASH_OPER_UNSUPPORTED;
+
 	if (target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
 		return ERROR_TARGET_NOT_HALTED;

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 81 +++++++++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 75 insertions(+), 6 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1462-g4dbb94e7c

From: openocd-gerrit <ope...@us...> - 2026-04-26 05:10:34

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  4dbb94e7cb6104c68a66525368f5a048d476d9b7 (commit)
      from  3a367916287988a9205f3556097ffdbe37e75568 (commit)

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- Log -----------------------------------------------------------------
commit 4dbb94e7cb6104c68a66525368f5a048d476d9b7
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Wed Feb 4 11:36:32 2026 +0100

    flash/nor/efm32: Properly display detected target
    
    We can now properly display the information related to the Series 2 SoCs.
    
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: I72f365bfd6109d8705c5eb48f438887f47f2d25f
    Reviewed-on: https://review.openocd.org/c/openocd/+/9447
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>
    Reviewed-by: zapb <de...@za...>

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 6fca63edd..7392463ca 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -1058,12 +1058,48 @@ static int efm32_write(struct flash_bank *bank, const uint8_t *buffer,
 	return efm32_priv_write(bank, buffer, bank->base + offset, count);
 }
 
+static char *efm32_get_str_identifier(struct efm32_info *efm32_mcu_info,
+				      char *buf, size_t len)
+{
+	if (!efm32_mcu_info->part_info) {
+		snprintf(buf, len, "%s Gecko, rev %" PRIu8,
+			efm32_mcu_info->family_data->name,
+			efm32_mcu_info->part_rev);
+		return buf;
+	}
+	unsigned int dev_num    = FIELD_GET(EFM32_DI_PARTINFO_NUM_MASK,
+				   efm32_mcu_info->part_info);
+	unsigned int dev_family = FIELD_GET(EFM32_DI_PARTINFO_FAMILY_MASK,
+				   efm32_mcu_info->part_info);
+	unsigned int dev_type   = FIELD_GET(EFM32_DI_PARTINFO_TYPE_MASK,
+				   efm32_mcu_info->part_info);
+
+	const char *types = "FMBZxP";
+	if (dev_type > strlen(types)) {
+		snprintf(buf, len, "Unknown MCU family %u", dev_type);
+		return buf;
+	}
+
+	char dev_num_letter = 'A' + (dev_num / 1000);
+	unsigned int dev_num_digits = dev_num % 1000;
+
+	snprintf(buf, len, "%s%cG%u %c%03u, rev %" PRIu8,
+		types[dev_type] == 'P' ? "EFM32" : "EFR32",
+		types[dev_type],
+		dev_family,
+		dev_num_letter,
+		dev_num_digits,
+		efm32_mcu_info->part_rev);
+	return buf;
+}
+
 static int efm32_probe(struct flash_bank *bank)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	struct efm32_info *efm32_mcu_info = &efm32_info->info;
-	int ret;
 	int bank_index = efm32_get_bank_index(bank->base);
+	char strbuf[256];
+	int ret;
 
 	assert(bank_index >= 0);
 
@@ -1074,8 +1110,8 @@ static int efm32_probe(struct flash_bank *bank)
 	if (ret != ERROR_OK)
 		return ret;
 
-	LOG_INFO("detected part: %s Gecko, rev %d",
-		 efm32_mcu_info->family_data->name, efm32_mcu_info->part_rev);
+	LOG_INFO("detected part: %s",
+		 efm32_get_str_identifier(efm32_mcu_info, strbuf, sizeof(strbuf)));
 	LOG_INFO("flash size = %d KiB", efm32_mcu_info->flash_sz_kib);
 	LOG_INFO("flash page size = %d B", efm32_mcu_info->page_size);
 
@@ -1147,6 +1183,7 @@ static int efm32_protect_check(struct flash_bank *bank)
 static int efm32_get_info(struct flash_bank *bank, struct command_invocation *cmd)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
+	char strbuf[256];
 	int ret;
 
 	ret = efm32_read_info(bank);
@@ -1155,9 +1192,10 @@ static int efm32_get_info(struct flash_bank *bank, struct command_invocation *cm
 		return ret;
 	}
 
-	command_print_sameline(cmd, "%s Gecko, rev %d",
-			       efm32_info->info.family_data->name,
-			       efm32_info->info.part_rev);
+	command_print_sameline(cmd, "%s",
+			       efm32_get_str_identifier(&efm32_info->info,
+							strbuf,
+							sizeof(strbuf)));
 	return ERROR_OK;
 }
 
@@ -1208,7 +1246,7 @@ static const struct command_registration efm32_command_handlers[] = {
 	{
 		.name = "efm32",
 		.mode = COMMAND_ANY,
-		.help = "efm32 flash command group",
+		.help = "Silicon Labs (EFM32 and EFR32) flash command group",
 		.usage = "",
 		.chain = efm32_exec_command_handlers,
 	},

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 52 ++++++++++++++++++++++++++++++++++++++++++++-------
 1 file changed, 45 insertions(+), 7 deletions(-)


hooks/post-receive
-- 
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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1461-g3a3679162

From: openocd-gerrit <ope...@us...> - 2026-04-26 05:09:48

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  3a367916287988a9205f3556097ffdbe37e75568 (commit)
      from  ce4eb522d6207deb0e5407a1ca350f437ea12291 (commit)

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- Log -----------------------------------------------------------------
commit 3a367916287988a9205f3556097ffdbe37e75568
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Wed Jan 28 13:51:26 2026 +0100

    flash/nor/efm32: Identify Series-2
    
    Silabs Series 2 SoCs change the structure to store the device
    identification. The legacy series relied on family identifier and a part
    number (part_num) while Series-2 store several fields in a uint32_t
    (part_info).
    
    In addition, various fileds related to the flash geometry are not stored on
    the same addresses. These addresses were hard coded. We now have to a
    structure (efm32_dev_info_addr) store the various configuration.
    
    The new series also have a different address for msc register base. Rather
    than relying on "reg_base" in efm32_flash_chip, we take this opportunity to
    centralize the information in struct efm32_families.
    
    For uniformity, we also remove "reg_lock" of the struct efm32_flash_chip.
    We will have to rework the way its work in future patches anyway.
    
    Co-developed-by: Peter Johanson <pe...@pe...>
    Signed-off-by: Peter Johanson <pe...@pe...>
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: Ia863520a1b5840c707e7678d909b2b590ea27e4e
    Reviewed-on: https://review.openocd.org/c/openocd/+/9446
    Reviewed-by: zapb <de...@za...>
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 683621ea7..6fca63edd 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -31,9 +31,6 @@
 #include <target/armv7m.h>
 #include <target/cortex_m.h>
 
-#define EFM_FAMILY_ID_GIANT_GECKO       72
-#define EFM_FAMILY_ID_LEOPARD_GECKO     74
-
 /* Datasheet specifies ~22ms for page erase on first chip generation. 100ms
  * provides reasonable margin.
  */
@@ -45,40 +42,67 @@
 #define LOCKWORDS_SZ                    512
 
 #define EFM32_MSC_INFO_BASE             0x0fe00000
-
-#define EFM32_MSC_USER_DATA             EFM32_MSC_INFO_BASE
+#define EFM32_MSC_USER_DATA             (EFM32_MSC_INFO_BASE + 0x0000)
 #define EFM32_MSC_LOCK_BITS             (EFM32_MSC_INFO_BASE + 0x4000)
-#define EFM32_MSC_LOCK_BITS_EXTRA       (EFM32_MSC_LOCK_BITS + LOCKWORDS_SZ)
-#define EFM32_MSC_DEV_INFO              (EFM32_MSC_INFO_BASE + 0x8000)
-
-/* PAGE_SIZE is not present in Zero, Happy and the original Gecko MCU */
-#define EFM32_MSC_DI_PAGE_SIZE          (EFM32_MSC_DEV_INFO + 0x1e7)
-#define EFM32_MSC_DI_FLASH_SZ           (EFM32_MSC_DEV_INFO + 0x1f8)
-#define EFM32_MSC_DI_RAM_SZ             (EFM32_MSC_DEV_INFO + 0x1fa)
-#define EFM32_MSC_DI_PART_NUM           (EFM32_MSC_DEV_INFO + 0x1fc)
-#define EFM32_MSC_DI_PART_FAMILY        (EFM32_MSC_DEV_INFO + 0x1fe)
-#define EFM32_MSC_DI_PROD_REV           (EFM32_MSC_DEV_INFO + 0x1ff)
-
-#define EFM32_MSC_REGBASE               0x400c0000
-#define EFM32_MSC_REGBASE_SERIES1       0x400e0000
-#define EFM32_MSC_REG_WRITECTRL         0x008
-#define EFM32_MSC_WRITECTRL_WREN_MASK   0x1
-#define EFM32_MSC_REG_WRITECMD          0x00c
-#define EFM32_MSC_WRITECMD_LADDRIM_MASK 0x1
-#define EFM32_MSC_WRITECMD_ERASEPAGE_MASK 0x2
-#define EFM32_MSC_WRITECMD_WRITEONCE_MASK 0x8
-#define EFM32_MSC_REG_ADDRB             0x010
-#define EFM32_MSC_REG_WDATA             0x018
-#define EFM32_MSC_REG_STATUS            0x01c
-#define EFM32_MSC_STATUS_BUSY_MASK      0x1
-#define EFM32_MSC_STATUS_LOCKED_MASK    0x2
-#define EFM32_MSC_STATUS_INVADDR_MASK   0x4
-#define EFM32_MSC_STATUS_WDATAREADY_MASK 0x8
-#define EFM32_MSC_STATUS_WORDTIMEOUT_MASK 0x10
-#define EFM32_MSC_STATUS_ERASEABORTED_MASK 0x20
-#define EFM32_MSC_REG_LOCK              0x03c
-#define EFM32_MSC_REG_LOCK_SERIES1      0x040
-#define EFM32_MSC_LOCK_LOCKKEY          0x1b71
+#define EFM32_MSC_LOCK_BITS_EXTRA       (EFM32_MSC_INFO_BASE + 0x4200)
+
+struct efm32_dev_info_addr {
+	target_addr_t part_num;
+	target_addr_t part_rev;
+#define EFM32_DI_PARTINFO_NUM_MASK        0x0000ffff
+#define EFM32_DI_PARTINFO_FAMILY_MASK     0x00ff0000
+#define EFM32_DI_PARTINFO_TYPE_MASK       0x3f000000
+	target_addr_t part_info;
+	target_addr_t page_size;
+	target_addr_t flash_sz;
+	target_addr_t ram_sz;
+};
+
+#define EFM32_DI_PART_FAMILY           (EFM32_MSC_INFO_BASE + 0x81fe)
+
+static const struct efm32_dev_info_addr efm32_dev_info_addr[] = {
+	[0] = {
+		.part_num  = EFM32_MSC_INFO_BASE + 0x81fc,
+		.part_rev  = EFM32_MSC_INFO_BASE + 0x81ff,
+		.part_info = 0x00000000, // Not used in Series 0/1
+		.page_size = EFM32_MSC_INFO_BASE + 0x81e7,
+		.flash_sz  = EFM32_MSC_INFO_BASE + 0x81f8,
+		.ram_sz    = EFM32_MSC_INFO_BASE + 0x81fa,
+	},
+	[1] = {
+		.part_num  = EFM32_MSC_INFO_BASE + 0x81fc,
+		.part_rev  = EFM32_MSC_INFO_BASE + 0x81ff,
+		.part_info = 0x0000000, // Not used in Series 0/1
+		.page_size = EFM32_MSC_INFO_BASE + 0x81e7,
+		.flash_sz  = EFM32_MSC_INFO_BASE + 0x81f8,
+		.ram_sz    = EFM32_MSC_INFO_BASE + 0x81fa,
+	},
+	[2] = {
+		.part_num  = 0x00000000, // Not used in Series 2
+		.part_rev  = EFM32_MSC_INFO_BASE + 0x8002,
+		.part_info = EFM32_MSC_INFO_BASE + 0x8004,
+		.page_size = EFM32_MSC_INFO_BASE + 0x8008,
+		.flash_sz  = EFM32_MSC_INFO_BASE + 0x800c,
+		.ram_sz    = EFM32_MSC_INFO_BASE + 0x800e,
+	},
+};
+
+#define EFM32_MSC_REG_WRITECTRL              0x0008
+#define EFM32_MSC_WRITECTRL_WREN_MASK        0x0001
+#define EFM32_MSC_REG_WRITECMD               0x000c
+#define EFM32_MSC_WRITECMD_LADDRIM_MASK      0x0001
+#define EFM32_MSC_WRITECMD_ERASEPAGE_MASK    0x0002
+#define EFM32_MSC_WRITECMD_WRITEONCE_MASK    0x0008
+#define EFM32_MSC_REG_ADDRB                  0x0010
+#define EFM32_MSC_REG_WDATA                  0x0018
+#define EFM32_MSC_REG_STATUS                 0x001c
+#define EFM32_MSC_STATUS_BUSY_MASK           0x0001
+#define EFM32_MSC_STATUS_LOCKED_MASK         0x0002
+#define EFM32_MSC_STATUS_INVADDR_MASK        0x0004
+#define EFM32_MSC_STATUS_WDATAREADY_MASK     0x0008
+#define EFM32_MSC_STATUS_WORDTIMEOUT_MASK    0x0010
+#define EFM32_MSC_STATUS_ERASEABORTED_MASK   0x0020
+#define EFM32_MSC_LOCK_LOCKKEY               0x1b71
 
 enum efm32_bank_index {
 	EFM32_BANK_INDEX_MAIN,
@@ -102,27 +126,24 @@ static int efm32_get_bank_index(target_addr_t base)
 }
 
 struct efm32_family_data {
-	int family_id;
-	const char *name;
-
-	/* EFM32 series (EFM32LG995F is the "old" series 0, while EFR32MG12P132
-	   is the "new" series 1). Determines location of MSC registers. */
+	uint8_t part_id;
 	int series;
+	const char *name;
+	uint32_t msc_regbase;
 
-	/* Page size in bytes, or 0 to read from EFM32_MSC_DI_PAGE_SIZE */
+	// Page size in bytes, or 0 to read from msc_di->page_size
 	int page_size;
 
-	/* MSC register base address, or 0 to use default */
-	uint32_t msc_regbase;
 };
 
 struct efm32_info {
 	const struct efm32_family_data *family_data;
+	const struct efm32_dev_info_addr *di_addr;
+	uint16_t part_num;     // Series 0/1 only
+	uint32_t part_info;    // Series 2 only
+	uint8_t  part_rev;
 	uint16_t flash_sz_kib;
 	uint16_t ram_sz_kib;
-	uint16_t part_num;
-	uint8_t part_family;
-	uint8_t prod_rev;
 	uint16_t page_size;
 };
 
@@ -130,69 +151,68 @@ struct efm32_flash_chip {
 	struct efm32_info info;
 	bool probed[EFM32_N_BANKS];
 	uint32_t lb_page[LOCKWORDS_SZ / 4];
-	uint32_t reg_base;
-	uint32_t reg_lock;
 	uint32_t refcount;
 };
 
 static const struct efm32_family_data efm32_families[] = {
-		{ 16, "EFR32MG1P Mighty", .series = 1 },
-		{ 17, "EFR32MG1B Mighty", .series = 1 },
-		{ 18, "EFR32MG1V Mighty", .series = 1 },
-		{ 19, "EFR32BG1P Blue", .series = 1 },
-		{ 20, "EFR32BG1B Blue", .series = 1 },
-		{ 21, "EFR32BG1V Blue", .series = 1 },
-		{ 25, "EFR32FG1P Flex", .series = 1 },
-		{ 26, "EFR32FG1B Flex", .series = 1 },
-		{ 27, "EFR32FG1V Flex", .series = 1 },
-		{ 28, "EFR32MG2P Mighty", .series = 1 },
-		{ 29, "EFR32MG2B Mighty", .series = 1 },
-		{ 30, "EFR32MG2V Mighty", .series = 1 },
-		{ 31, "EFR32BG12P Blue", .series = 1 },
-		{ 32, "EFR32BG12B Blue", .series = 1 },
-		{ 33, "EFR32BG12V Blue", .series = 1 },
-		{ 37, "EFR32FG12P Flex", .series = 1 },
-		{ 38, "EFR32FG12B Flex", .series = 1 },
-		{ 39, "EFR32FG12V Flex", .series = 1 },
-		{ 40, "EFR32MG13P Mighty", .series = 1 },
-		{ 41, "EFR32MG13B Mighty", .series = 1 },
-		{ 42, "EFR32MG13V Mighty", .series = 1 },
-		{ 43, "EFR32BG13P Blue", .series = 1 },
-		{ 44, "EFR32BG13B Blue", .series = 1 },
-		{ 45, "EFR32BG13V Blue", .series = 1 },
-		{ 46, "EFR32ZG13P Zen", .series = 1 },
-		{ 49, "EFR32FG13P Flex", .series = 1 },
-		{ 50, "EFR32FG13B Flex", .series = 1 },
-		{ 51, "EFR32FG13V Flex", .series = 1 },
-		{ 52, "EFR32MG14P Mighty", .series = 1 },
-		{ 53, "EFR32MG14B Mighty", .series = 1 },
-		{ 54, "EFR32MG14V Mighty", .series = 1 },
-		{ 55, "EFR32BG14P Blue", .series = 1 },
-		{ 56, "EFR32BG14B Blue", .series = 1 },
-		{ 57, "EFR32BG14V Blue", .series = 1 },
-		{ 58, "EFR32ZG14P Zen", .series = 1 },
-		{ 61, "EFR32FG14P Flex", .series = 1 },
-		{ 62, "EFR32FG14B Flex", .series = 1 },
-		{ 63, "EFR32FG14V Flex", .series = 1 },
-		{ 71, "EFM32G", .series = 0, .page_size = 512 },
-		{ 72, "EFM32GG Giant", .series = 0 },
-		{ 73, "EFM32TG Tiny", .series = 0, .page_size = 512 },
-		{ 74, "EFM32LG Leopard", .series = 0 },
-		{ 75, "EFM32WG Wonder", .series = 0 },
-		{ 76, "EFM32ZG Zero", .series = 0, .page_size = 1024 },
-		{ 77, "EFM32HG Happy", .series = 0, .page_size = 1024 },
-		{ 81, "EFM32PG1B Pearl", .series = 1 },
-		{ 83, "EFM32JG1B Jade", .series = 1 },
-		{ 85, "EFM32PG12B Pearl", .series = 1 },
-		{ 87, "EFM32JG12B Jade", .series = 1 },
-		{ 89, "EFM32PG13B Pearl", .series = 1 },
-		{ 91, "EFM32JG13B Jade", .series = 1 },
-		{ 100, "EFM32GG11B Giant", .series = 1, .msc_regbase = 0x40000000 },
-		{ 103, "EFM32TG11B Tiny", .series = 1, .msc_regbase = 0x40000000 },
-		{ 106, "EFM32GG12B Giant", .series = 1, .msc_regbase = 0x40000000 },
-		{ 120, "EZR32WG Wonder", .series = 0 },
-		{ 121, "EZR32LG Leopard", .series = 0 },
-		{ 122, "EZR32HG Happy", .series = 0, .page_size = 1024 },
+	{  16, 1, "EFR32MG1P Mighty",  .msc_regbase = 0x400e0000 },
+	{  17, 1, "EFR32MG1B Mighty",  .msc_regbase = 0x400e0000 },
+	{  18, 1, "EFR32MG1V Mighty",  .msc_regbase = 0x400e0000 },
+	{  19, 1, "EFR32BG1P Blue",    .msc_regbase = 0x400e0000 },
+	{  20, 1, "EFR32BG1B Blue",    .msc_regbase = 0x400e0000 },
+	{  21, 1, "EFR32BG1V Blue",    .msc_regbase = 0x400e0000 },
+	{  25, 1, "EFR32FG1P Flex",    .msc_regbase = 0x400e0000 },
+	{  26, 1, "EFR32FG1B Flex",    .msc_regbase = 0x400e0000 },
+	{  27, 1, "EFR32FG1V Flex",    .msc_regbase = 0x400e0000 },
+	{  28, 1, "EFR32MG12P Mighty", .msc_regbase = 0x400e0000 },
+	{  29, 1, "EFR32MG12B Mighty", .msc_regbase = 0x400e0000 },
+	{  30, 1, "EFR32MG12V Mighty", .msc_regbase = 0x400e0000 },
+	{  31, 1, "EFR32BG12P Blue",   .msc_regbase = 0x400e0000 },
+	{  32, 1, "EFR32BG12B Blue",   .msc_regbase = 0x400e0000 },
+	{  33, 1, "EFR32BG12V Blue",   .msc_regbase = 0x400e0000 },
+	{  37, 1, "EFR32FG12P Flex",   .msc_regbase = 0x400e0000 },
+	{  38, 1, "EFR32FG12B Flex",   .msc_regbase = 0x400e0000 },
+	{  39, 1, "EFR32FG12V Flex",   .msc_regbase = 0x400e0000 },
+	{  40, 1, "EFR32MG13P Mighty", .msc_regbase = 0x400e0000 },
+	{  41, 1, "EFR32MG13B Mighty", .msc_regbase = 0x400e0000 },
+	{  42, 1, "EFR32MG13V Mighty", .msc_regbase = 0x400e0000 },
+	{  43, 1, "EFR32BG13P Blue",   .msc_regbase = 0x400e0000 },
+	{  44, 1, "EFR32BG13B Blue",   .msc_regbase = 0x400e0000 },
+	{  45, 1, "EFR32BG13V Blue",   .msc_regbase = 0x400e0000 },
+	{  46, 1, "EFR32ZG13P Zen",    .msc_regbase = 0x400e0000 },
+	{  49, 1, "EFR32FG13P Flex",   .msc_regbase = 0x400e0000 },
+	{  50, 1, "EFR32FG13B Flex",   .msc_regbase = 0x400e0000 },
+	{  51, 1, "EFR32FG13V Flex",   .msc_regbase = 0x400e0000 },
+	{  52, 1, "EFR32MG14P Mighty", .msc_regbase = 0x400e0000 },
+	{  53, 1, "EFR32MG14B Mighty", .msc_regbase = 0x400e0000 },
+	{  54, 1, "EFR32MG14V Mighty", .msc_regbase = 0x400e0000 },
+	{  55, 1, "EFR32BG14P Blue",   .msc_regbase = 0x400e0000 },
+	{  56, 1, "EFR32BG14B Blue",   .msc_regbase = 0x400e0000 },
+	{  57, 1, "EFR32BG14V Blue",   .msc_regbase = 0x400e0000 },
+	{  58, 1, "EFR32ZG14P Zen",    .msc_regbase = 0x400e0000 },
+	{  61, 1, "EFR32FG14P Flex",   .msc_regbase = 0x400e0000 },
+	{  62, 1, "EFR32FG14B Flex",   .msc_regbase = 0x400e0000 },
+	{  63, 1, "EFR32FG14V Flex",   .msc_regbase = 0x400e0000 },
+	{  71, 0, "EFM32G",            .msc_regbase = 0x400c0000, .page_size = 512 },
+	{  72, 0, "EFM32GG Giant",     .msc_regbase = 0x400c0000 },
+	{  73, 0, "EFM32TG Tiny",      .msc_regbase = 0x400c0000, .page_size = 512 },
+	{  74, 0, "EFM32LG Leopard",   .msc_regbase = 0x400c0000 },
+	{  75, 0, "EFM32WG Wonder",    .msc_regbase = 0x400c0000 },
+	{  76, 0, "EFM32ZG Zero",      .msc_regbase = 0x400c0000, .page_size = 1024 },
+	{  77, 0, "EFM32HG Happy",     .msc_regbase = 0x400c0000, .page_size = 1024 },
+	{  81, 1, "EFM32PG1B Pearl",   .msc_regbase = 0x400e0000 },
+	{  83, 1, "EFM32JG1B Jade",    .msc_regbase = 0x400e0000 },
+	{  85, 1, "EFM32PG12B Pearl",  .msc_regbase = 0x400e0000 },
+	{  87, 1, "EFM32JG12B Jade",   .msc_regbase = 0x400e0000 },
+	{  89, 1, "EFM32PG13B Pearl",  .msc_regbase = 0x400e0000 },
+	{  91, 1, "EFM32JG13B Jade",   .msc_regbase = 0x400e0000 },
+	{ 100, 1, "EFM32GG11B Giant",  .msc_regbase = 0x40000000 },
+	{ 103, 1, "EFM32TG11B Tiny",   .msc_regbase = 0x40000000 },
+	{ 106, 1, "EFM32GG12B Giant",  .msc_regbase = 0x40000000 },
+	{ 120, 0, "EZR32WG Wonder",    .msc_regbase = 0x400c0000 },
+	{ 121, 0, "EZR32LG Leopard",   .msc_regbase = 0x400c0000 },
+	{ 122, 0, "EZR32HG Happy",     .msc_regbase = 0x400c0000, .page_size = 1024 },
+	{ 128, 2, "EFR32/EFM32 Series-2", .msc_regbase = 0x50030000 },
 };
 
 const struct flash_driver efm32_flash;
@@ -202,129 +222,109 @@ static int efm32_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 
 static int efm32_write_only_lockbits(struct flash_bank *bank);
 
-static int efm32_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
-{
-	return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
-}
-
-static int efm32_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
-{
-	return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
-}
-
-static int efm32_get_part_num(struct flash_bank *bank, uint16_t *pnum)
-{
-	return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
-}
-
-static int efm32_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
-{
-	return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
-}
-
-static int efm32_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
-{
-	return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
-}
-
 static int efm32_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
 			      uint32_t *value)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
-	uint32_t base = efm32_info->reg_base;
 
-	return target_read_u32(bank->target, base + offset, value);
+	return target_read_u32(bank->target,
+			       efm32_info->info.family_data->msc_regbase + offset,
+			       value);
 }
 
 static int efm32_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
 			       uint32_t value)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
-	uint32_t base = efm32_info->reg_base;
 
-	return target_write_u32(bank->target, base + offset, value);
+	return target_write_u32(bank->target,
+				efm32_info->info.family_data->msc_regbase + offset,
+				value);
 }
 
 static int efm32_read_info(struct flash_bank *bank)
 {
-	int ret;
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	struct efm32_info *efm32_mcu_info = &efm32_info->info;
+	uint8_t tmp;
+	int ret;
 
 	memset(efm32_mcu_info, 0, sizeof(struct efm32_info));
 
-	ret = efm32_get_flash_size(bank, &efm32_mcu_info->flash_sz_kib);
+	ret = target_read_u8(bank->target, EFM32_DI_PART_FAMILY, &tmp);
 	if (ret != ERROR_OK)
 		return ret;
+	for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
+		if (efm32_families[i].part_id == tmp)
+			efm32_mcu_info->family_data = &efm32_families[i];
+	}
+	if (!efm32_mcu_info->family_data) {
+		LOG_ERROR("Unknown MCU family %d", tmp);
+		return ERROR_FAIL;
+	}
 
-	ret = efm32_get_ram_size(bank, &efm32_mcu_info->ram_sz_kib);
-	if (ret != ERROR_OK)
-		return ret;
+	efm32_mcu_info->di_addr = &efm32_dev_info_addr[efm32_mcu_info->family_data->series];
+
+	if (efm32_mcu_info->family_data->series == 2) {
+		ret = target_read_u32(bank->target,
+				      efm32_mcu_info->di_addr->part_info,
+				      &efm32_mcu_info->part_info);
+		if (ret != ERROR_OK)
+			return ret;
+	} else {
+		ret = target_read_u16(bank->target,
+				      efm32_mcu_info->di_addr->part_num,
+				      &efm32_mcu_info->part_num);
+		if (ret != ERROR_OK)
+			return ret;
+	}
 
-	ret = efm32_get_part_num(bank, &efm32_mcu_info->part_num);
+	ret = target_read_u8(bank->target,
+			     efm32_mcu_info->di_addr->part_rev,
+			     &efm32_mcu_info->part_rev);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32_get_part_family(bank, &efm32_mcu_info->part_family);
+	ret = target_read_u16(bank->target,
+			      efm32_mcu_info->di_addr->flash_sz,
+			      &efm32_mcu_info->flash_sz_kib);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32_get_prod_rev(bank, &efm32_mcu_info->prod_rev);
+	ret = target_read_u16(bank->target,
+			      efm32_mcu_info->di_addr->ram_sz,
+			      &efm32_mcu_info->ram_sz_kib);
 	if (ret != ERROR_OK)
 		return ret;
 
-	for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
-		if (efm32_families[i].family_id == efm32_mcu_info->part_family)
-			efm32_mcu_info->family_data = &efm32_families[i];
-	}
-
-	if (!efm32_mcu_info->family_data) {
-		LOG_ERROR("Unknown MCU family %d", efm32_mcu_info->part_family);
-		return ERROR_FAIL;
-	}
-
-	switch (efm32_mcu_info->family_data->series) {
-	case 0:
-		efm32_info->reg_base = EFM32_MSC_REGBASE;
-		efm32_info->reg_lock = EFM32_MSC_REG_LOCK;
-		break;
-	case 1:
-		efm32_info->reg_base = EFM32_MSC_REGBASE_SERIES1;
-		efm32_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1;
-		break;
-	}
-
-	if (efm32_mcu_info->family_data->msc_regbase != 0)
-		efm32_info->reg_base = efm32_mcu_info->family_data->msc_regbase;
-
 	if (efm32_mcu_info->family_data->page_size != 0) {
 		efm32_mcu_info->page_size = efm32_mcu_info->family_data->page_size;
+	} else if ((efm32_mcu_info->family_data->part_id == 72 ||
+		    efm32_mcu_info->family_data->part_id == 74) &&
+		   efm32_mcu_info->part_rev < 18) {
+		/* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid for MCUs
+		 * with part_rev < 18
+		 */
+		if (efm32_mcu_info->flash_sz_kib < 512)
+			efm32_mcu_info->page_size = 2048;
+		else
+			efm32_mcu_info->page_size = 4096;
 	} else {
-		uint8_t pg_size = 0;
-		ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE, &pg_size);
+		ret = target_read_u8(bank->target,
+				     efm32_mcu_info->di_addr->page_size,
+				     &tmp);
 		if (ret != ERROR_OK)
 			return ret;
 
-		efm32_mcu_info->page_size = BIT((pg_size + 10) & 0xff);
-
-		if (efm32_mcu_info->part_family == EFM_FAMILY_ID_GIANT_GECKO ||
-				efm32_mcu_info->part_family == EFM_FAMILY_ID_LEOPARD_GECKO) {
-			/* Giant or Leopard Gecko */
-			if (efm32_mcu_info->prod_rev < 18) {
-				/* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
-				   for MCUs with PROD_REV < 18 */
-				if (efm32_mcu_info->flash_sz_kib < 512)
-					efm32_mcu_info->page_size = 2048;
-				else
-					efm32_mcu_info->page_size = 4096;
-			}
-		}
-
-		if (efm32_mcu_info->page_size != 2048 &&
-		    efm32_mcu_info->page_size != 4096) {
-			LOG_ERROR("Invalid page size %u", efm32_mcu_info->page_size);
-			return ERROR_FAIL;
-		}
+		efm32_mcu_info->page_size = BIT(tmp) * 1024;
+	}
+	if (efm32_mcu_info->page_size !=  512 &&
+	    efm32_mcu_info->page_size != 1024 &&
+	    efm32_mcu_info->page_size != 2048 &&
+	    efm32_mcu_info->page_size != 4096 &&
+	    efm32_mcu_info->page_size != 8192) {
+		LOG_ERROR("Invalid page size %u", efm32_mcu_info->page_size);
+		return ERROR_FAIL;
 	}
 
 	return ERROR_OK;
@@ -418,9 +418,16 @@ static int efm32_set_wren(struct flash_bank *bank, int write_enable)
 static int efm32_msc_lock(struct flash_bank *bank, int lock)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
+	struct efm32_info *efm32_mcu_info = &efm32_info->info;
+	uint32_t val = lock ? 0 : EFM32_MSC_LOCK_LOCKKEY;
+	uint32_t reg;
+
+	if (efm32_mcu_info->family_data->series == 1)
+		reg = 0x040;
+	else
+		reg = 0x03c;
 
-	return efm32_write_reg_u32(bank, efm32_info->reg_lock,
-		(lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
+	return efm32_write_reg_u32(bank, reg, val);
 }
 
 static int efm32_wait_status(struct flash_bank *bank, int timeout_ms,
@@ -851,7 +858,7 @@ static int efm32_write_block(struct flash_bank *bank, const uint8_t *buf,
 	init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);	/* buffer end */
 	init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT);	/* target address */
 
-	buf_set_u32(reg_params[0].value, 0, 32, efm32_info->reg_base);
+	buf_set_u32(reg_params[0].value, 0, 32, efm32_info->info.family_data->msc_regbase);
 	buf_set_u32(reg_params[1].value, 0, 32, count);
 	buf_set_u32(reg_params[2].value, 0, 32, source->address);
 	buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
@@ -1068,7 +1075,7 @@ static int efm32_probe(struct flash_bank *bank)
 		return ret;
 
 	LOG_INFO("detected part: %s Gecko, rev %d",
-		 efm32_mcu_info->family_data->name, efm32_mcu_info->prod_rev);
+		 efm32_mcu_info->family_data->name, efm32_mcu_info->part_rev);
 	LOG_INFO("flash size = %d KiB", efm32_mcu_info->flash_sz_kib);
 	LOG_INFO("flash page size = %d B", efm32_mcu_info->page_size);
 
@@ -1150,7 +1157,7 @@ static int efm32_get_info(struct flash_bank *bank, struct command_invocation *cm
 
 	command_print_sameline(cmd, "%s Gecko, rev %d",
 			       efm32_info->info.family_data->name,
-			       efm32_info->info.prod_rev);
+			       efm32_info->info.part_rev);
 	return ERROR_OK;
 }
 

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 395 +++++++++++++++++++++++++-------------------------
 1 file changed, 201 insertions(+), 194 deletions(-)


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From: openocd-gerrit <ope...@us...> - 2026-04-26 05:09:12

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The branch, master has been updated
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      from  3ca07a2da797c059a053fe55d10284c790d912e1 (commit)

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- Log -----------------------------------------------------------------
commit ce4eb522d6207deb0e5407a1ca350f437ea12291
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Tue Feb 3 13:37:21 2026 +0100

    flash/nor/efm32: Improve code style compliance
    
    The project coding style specify:
    
    > On if statements where the condition is split among multiple lines,
    > increase the indentation of the condition to prevent it to match to the
    > indentation of the then block due to length of 'if ('
    [...]
    > Variables declarations should occur at the point of first use
    
    In addition, unify name of the variable used to return the error code in
    efm32_handle_debuglock_command().
    
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: I07469887df88c0a9912e730a8bb052c16058de98
    Reviewed-on: https://review.openocd.org/c/openocd/+/9445
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 9a09bd37f..683621ea7 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -333,8 +333,6 @@ static int efm32_read_info(struct flash_bank *bank)
 /* flash bank efm32 <base> <size> 0 0 <target#> */
 FLASH_BANK_COMMAND_HANDLER(efm32_flash_bank_command)
 {
-	struct efm32_flash_chip *efm32_info = NULL;
-
 	if (CMD_ARGC < 6)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
@@ -346,10 +344,13 @@ FLASH_BANK_COMMAND_HANDLER(efm32_flash_bank_command)
 	}
 
 	/* look for an existing flash structure matching target */
-	for (struct flash_bank *bank_iter = flash_bank_list(); bank_iter; bank_iter = bank_iter->next) {
-		if (bank_iter->driver == &efm32_flash
-			&& bank_iter->target == bank->target
-			&& bank->driver_priv) {
+	struct efm32_flash_chip *efm32_info = NULL;
+	for (struct flash_bank *bank_iter = flash_bank_list();
+	     bank_iter;
+	     bank_iter = bank_iter->next) {
+		if (bank_iter->driver == &efm32_flash &&
+		    bank_iter->target == bank->target &&
+		    bank->driver_priv) {
 			efm32_info = bank->driver_priv;
 			break;
 		}
@@ -625,13 +626,13 @@ static int efm32_write_only_lockbits(struct flash_bank *bank)
 static int efm32_write_lock_data(struct flash_bank *bank)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
-	int ret = 0;
 
 	/* Preserve any data written to the high portion of the lockbits page */
 	assert(efm32_info->info.page_size >= LOCKWORDS_SZ);
+
 	uint32_t extra_bytes = efm32_info->info.page_size - LOCKWORDS_SZ;
 	uint8_t *extra_data = NULL;
-
+	int ret;
 	if (extra_bytes) {
 		extra_data = malloc(extra_bytes);
 		ret = target_read_buffer(bank->target,
@@ -700,10 +701,7 @@ static int efm32_set_page_lock(struct flash_bank *bank, size_t page, int set)
 	}
 
 	uint32_t *dw = &efm32_info->lb_page[page >> 5];
-	uint32_t mask = 0;
-
-	mask = BIT(page & 0x1f);
-
+	uint32_t mask = BIT(page & 0x1f);
 	if (!set)
 		*dw |= mask;
 	else
@@ -1158,33 +1156,29 @@ static int efm32_get_info(struct flash_bank *bank, struct command_invocation *cm
 
 COMMAND_HANDLER(efm32_handle_debuglock_command)
 {
-	struct target *target = NULL;
-
 	if (CMD_ARGC < 1)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
 	struct flash_bank *bank;
-	int retval = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
-	if (retval != ERROR_OK)
-		return retval;
+	int ret = CALL_COMMAND_HANDLER(flash_command_get_bank, 0, &bank);
+	if (ret != ERROR_OK)
+		return ret;
 
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
-
-	target = bank->target;
+	struct target *target = bank->target;
 
 	if (target->state != TARGET_HALTED) {
 		LOG_ERROR("Target not halted");
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	uint32_t *ptr;
-	ptr = efm32_info->lb_page + 127;
+	uint32_t *ptr = efm32_info->lb_page + 127;
 	*ptr = 0;
 
-	retval = efm32_write_lock_data(bank);
-	if (retval != ERROR_OK) {
+	ret = efm32_write_lock_data(bank);
+	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to write LB page");
-		return retval;
+		return ret;
 	}
 
 	command_print(CMD, "efm32 debug interface locked, reset the device to apply");

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 42 ++++++++++++++++++------------------------
 1 file changed, 18 insertions(+), 24 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1459-g3ca07a2da

From: openocd-gerrit <ope...@us...> - 2026-04-26 05:08:57

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  3ca07a2da797c059a053fe55d10284c790d912e1 (commit)
      from  0c60f128c231bcb3e32378936200e19eb89f8264 (commit)

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- Log -----------------------------------------------------------------
commit 3ca07a2da797c059a053fe55d10284c790d912e1
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Wed Feb 4 14:05:15 2026 +0100

    flash/nor/efm32: Rework efm32_wait_status()
    
    This patch slightly improve efm32_wait_status():
      - Specify unit for the timeout
      - Avoid use of int for the semantic of a boolean
    
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: Iac7082cf4fbce2e762732274d2a10698a3865690
    Reviewed-on: https://review.openocd.org/c/openocd/+/9444
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index fcccce325..9a09bd37f 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -26,6 +26,7 @@
 
 #include "imp.h"
 #include <helper/binarybuffer.h>
+#include <helper/time_support.h>
 #include <target/algorithm.h>
 #include <target/armv7m.h>
 #include <target/cortex_m.h>
@@ -33,9 +34,10 @@
 #define EFM_FAMILY_ID_GIANT_GECKO       72
 #define EFM_FAMILY_ID_LEOPARD_GECKO     74
 
-#define EFM32_FLASH_ERASE_TMO           100
-#define EFM32_FLASH_WDATAREADY_TMO      100
-#define EFM32_FLASH_WRITE_TMO           100
+/* Datasheet specifies ~22ms for page erase on first chip generation. 100ms
+ * provides reasonable margin.
+ */
+#define EFM32_FLASH_OPERATION_TIMEOUT   100
 
 #define EFM32_FLASH_BASE                0
 
@@ -420,25 +422,25 @@ static int efm32_msc_lock(struct flash_bank *bank, int lock)
 		(lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
 }
 
-static int efm32_wait_status(struct flash_bank *bank, int timeout,
-			     uint32_t wait_mask, int wait_for_set)
+static int efm32_wait_status(struct flash_bank *bank, int timeout_ms,
+			     uint32_t wait_mask, bool wait_for_set)
 {
-	int ret = 0;
+	int64_t start_ms = timeval_ms();
 	uint32_t status = 0;
 
 	while (1) {
-		ret = efm32_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
+		int ret = efm32_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 		if (ret != ERROR_OK)
-			break;
+			return ret;
 
 		LOG_DEBUG("status: 0x%" PRIx32, status);
 
-		if ((status & wait_mask) == 0 && wait_for_set == 0)
+		if (!(status & wait_mask) && !wait_for_set)
 			break;
-		else if ((status & wait_mask) != 0 && wait_for_set)
+		if ((status & wait_mask) && wait_for_set)
 			break;
 
-		if (timeout-- <= 0) {
+		if (timeval_ms() - start_ms > timeout_ms) {
 			LOG_ERROR("timed out waiting for MSC status");
 			return ERROR_FAIL;
 		}
@@ -449,7 +451,7 @@ static int efm32_wait_status(struct flash_bank *bank, int timeout,
 	if (status & EFM32_MSC_STATUS_ERASEABORTED_MASK)
 		LOG_WARNING("page erase was aborted");
 
-	return ret;
+	return ERROR_OK;
 }
 
 static int efm32_erase_page(struct flash_bank *bank, uint32_t addr)
@@ -494,8 +496,8 @@ static int efm32_erase_page(struct flash_bank *bank, uint32_t addr)
 	if (ret != ERROR_OK)
 		return ret;
 
-	return efm32_wait_status(bank, EFM32_FLASH_ERASE_TMO,
-				 EFM32_MSC_STATUS_BUSY_MASK, 0);
+	return efm32_wait_status(bank, EFM32_FLASH_OPERATION_TIMEOUT,
+				 EFM32_MSC_STATUS_BUSY_MASK, false);
 }
 
 static int efm32_erase(struct flash_bank *bank, unsigned int first,
@@ -939,8 +941,8 @@ static int efm32_write_word(struct flash_bank *bank, uint32_t addr,
 		return ERROR_FAIL;
 	}
 
-	ret = efm32_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
-				EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
+	ret = efm32_wait_status(bank, EFM32_FLASH_OPERATION_TIMEOUT,
+				EFM32_MSC_STATUS_WDATAREADY_MASK, true);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Wait for WDATAREADY failed");
 		return ret;
@@ -959,8 +961,8 @@ static int efm32_write_word(struct flash_bank *bank, uint32_t addr,
 		return ret;
 	}
 
-	ret = efm32_wait_status(bank, EFM32_FLASH_WRITE_TMO,
-				EFM32_MSC_STATUS_BUSY_MASK, 0);
+	ret = efm32_wait_status(bank, EFM32_FLASH_OPERATION_TIMEOUT,
+				EFM32_MSC_STATUS_BUSY_MASK, false);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Wait for BUSY failed");
 		return ret;

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 38 ++++++++++++++++++++------------------
 1 file changed, 20 insertions(+), 18 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1458-g0c60f128c

From: openocd-gerrit <ope...@us...> - 2026-04-26 05:08:34

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  0c60f128c231bcb3e32378936200e19eb89f8264 (commit)
      from  c2777e3069eab6bf05a018a8024d4cc103eeb488 (commit)

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- Log -----------------------------------------------------------------
commit 0c60f128c231bcb3e32378936200e19eb89f8264
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Wed Jan 28 10:50:10 2026 +0100

    flash/nor/efm32: Fix efm32_get_info() name
    
    get_efm32_info() was the only function that does not follow the name scheme
    of the file.
    
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: I5eea00ff0f06ba5d7d7cb4f9b1fb4394a5f36e20
    Reviewed-on: https://review.openocd.org/c/openocd/+/9443
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 73a699b6c..fcccce325 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -1137,7 +1137,7 @@ static int efm32_protect_check(struct flash_bank *bank)
 	return ERROR_OK;
 }
 
-static int get_efm32_info(struct flash_bank *bank, struct command_invocation *cmd)
+static int efm32_get_info(struct flash_bank *bank, struct command_invocation *cmd)
 {
 	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	int ret;
@@ -1224,6 +1224,6 @@ const struct flash_driver efm32_flash = {
 	.auto_probe         = efm32_auto_probe,
 	.erase_check        = default_flash_blank_check,
 	.protect_check      = efm32_protect_check,
-	.info               = get_efm32_info,
+	.info               = efm32_get_info,
 	.free_driver_priv   = efm32_free_driver_priv,
 };

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)


hooks/post-receive
-- 
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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1457-gc2777e306

From: openocd-gerrit <ope...@us...> - 2026-04-26 05:07:36

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  c2777e3069eab6bf05a018a8024d4cc103eeb488 (commit)
      from  e434b4b929c3c9f54d2fe80884067416b7fe8810 (commit)

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- Log -----------------------------------------------------------------
commit c2777e3069eab6bf05a018a8024d4cc103eeb488
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Wed Jan 28 10:34:59 2026 +0100

    flash/nor/efm32: Fix function prefix
    
    All the functions of flash/nor/efm32.c are prefixed by "efm32x_". The chip
    is named "efm32" everywhere in OpenOCD. The "x" is confusing. Let's drop
    it.
    
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: Ia62200bfd69a31deebdd0a0c662ab44c62cc30d4
    Reviewed-on: https://review.openocd.org/c/openocd/+/9442
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 529d3541e..73a699b6c 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -85,7 +85,7 @@ enum efm32_bank_index {
 	EFM32_N_BANKS
 };
 
-static int efm32x_get_bank_index(target_addr_t base)
+static int efm32_get_bank_index(target_addr_t base)
 {
 	switch (base) {
 	case EFM32_FLASH_BASE:
@@ -124,7 +124,7 @@ struct efm32_info {
 	uint16_t page_size;
 };
 
-struct efm32x_flash_chip {
+struct efm32_flash_chip {
 	struct efm32_info info;
 	bool probed[EFM32_N_BANKS];
 	uint32_t lb_page[LOCKWORDS_SZ / 4];
@@ -195,132 +195,132 @@ static const struct efm32_family_data efm32_families[] = {
 
 const struct flash_driver efm32_flash;
 
-static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
+static int efm32_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 			    uint32_t addr, uint32_t count);
 
-static int efm32x_write_only_lockbits(struct flash_bank *bank);
+static int efm32_write_only_lockbits(struct flash_bank *bank);
 
-static int efm32x_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
+static int efm32_get_flash_size(struct flash_bank *bank, uint16_t *flash_sz)
 {
 	return target_read_u16(bank->target, EFM32_MSC_DI_FLASH_SZ, flash_sz);
 }
 
-static int efm32x_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
+static int efm32_get_ram_size(struct flash_bank *bank, uint16_t *ram_sz)
 {
 	return target_read_u16(bank->target, EFM32_MSC_DI_RAM_SZ, ram_sz);
 }
 
-static int efm32x_get_part_num(struct flash_bank *bank, uint16_t *pnum)
+static int efm32_get_part_num(struct flash_bank *bank, uint16_t *pnum)
 {
 	return target_read_u16(bank->target, EFM32_MSC_DI_PART_NUM, pnum);
 }
 
-static int efm32x_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
+static int efm32_get_part_family(struct flash_bank *bank, uint8_t *pfamily)
 {
 	return target_read_u8(bank->target, EFM32_MSC_DI_PART_FAMILY, pfamily);
 }
 
-static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
+static int efm32_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
 {
 	return target_read_u8(bank->target, EFM32_MSC_DI_PROD_REV, prev);
 }
 
-static int efm32x_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
+static int efm32_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
 			      uint32_t *value)
 {
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
-	uint32_t base = efm32x_info->reg_base;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
+	uint32_t base = efm32_info->reg_base;
 
 	return target_read_u32(bank->target, base + offset, value);
 }
 
-static int efm32x_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
+static int efm32_write_reg_u32(struct flash_bank *bank, target_addr_t offset,
 			       uint32_t value)
 {
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
-	uint32_t base = efm32x_info->reg_base;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
+	uint32_t base = efm32_info->reg_base;
 
 	return target_write_u32(bank->target, base + offset, value);
 }
 
-static int efm32x_read_info(struct flash_bank *bank)
+static int efm32_read_info(struct flash_bank *bank)
 {
 	int ret;
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
-	struct efm32_info *efm32_info = &efm32x_info->info;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
+	struct efm32_info *efm32_mcu_info = &efm32_info->info;
 
-	memset(efm32_info, 0, sizeof(struct efm32_info));
+	memset(efm32_mcu_info, 0, sizeof(struct efm32_info));
 
-	ret = efm32x_get_flash_size(bank, &efm32_info->flash_sz_kib);
+	ret = efm32_get_flash_size(bank, &efm32_mcu_info->flash_sz_kib);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32x_get_ram_size(bank, &efm32_info->ram_sz_kib);
+	ret = efm32_get_ram_size(bank, &efm32_mcu_info->ram_sz_kib);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32x_get_part_num(bank, &efm32_info->part_num);
+	ret = efm32_get_part_num(bank, &efm32_mcu_info->part_num);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32x_get_part_family(bank, &efm32_info->part_family);
+	ret = efm32_get_part_family(bank, &efm32_mcu_info->part_family);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32x_get_prod_rev(bank, &efm32_info->prod_rev);
+	ret = efm32_get_prod_rev(bank, &efm32_mcu_info->prod_rev);
 	if (ret != ERROR_OK)
 		return ret;
 
 	for (size_t i = 0; i < ARRAY_SIZE(efm32_families); i++) {
-		if (efm32_families[i].family_id == efm32_info->part_family)
-			efm32_info->family_data = &efm32_families[i];
+		if (efm32_families[i].family_id == efm32_mcu_info->part_family)
+			efm32_mcu_info->family_data = &efm32_families[i];
 	}
 
-	if (!efm32_info->family_data) {
-		LOG_ERROR("Unknown MCU family %d", efm32_info->part_family);
+	if (!efm32_mcu_info->family_data) {
+		LOG_ERROR("Unknown MCU family %d", efm32_mcu_info->part_family);
 		return ERROR_FAIL;
 	}
 
-	switch (efm32_info->family_data->series) {
+	switch (efm32_mcu_info->family_data->series) {
 	case 0:
-		efm32x_info->reg_base = EFM32_MSC_REGBASE;
-		efm32x_info->reg_lock = EFM32_MSC_REG_LOCK;
+		efm32_info->reg_base = EFM32_MSC_REGBASE;
+		efm32_info->reg_lock = EFM32_MSC_REG_LOCK;
 		break;
 	case 1:
-		efm32x_info->reg_base = EFM32_MSC_REGBASE_SERIES1;
-		efm32x_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1;
+		efm32_info->reg_base = EFM32_MSC_REGBASE_SERIES1;
+		efm32_info->reg_lock = EFM32_MSC_REG_LOCK_SERIES1;
 		break;
 	}
 
-	if (efm32_info->family_data->msc_regbase != 0)
-		efm32x_info->reg_base = efm32_info->family_data->msc_regbase;
+	if (efm32_mcu_info->family_data->msc_regbase != 0)
+		efm32_info->reg_base = efm32_mcu_info->family_data->msc_regbase;
 
-	if (efm32_info->family_data->page_size != 0) {
-		efm32_info->page_size = efm32_info->family_data->page_size;
+	if (efm32_mcu_info->family_data->page_size != 0) {
+		efm32_mcu_info->page_size = efm32_mcu_info->family_data->page_size;
 	} else {
 		uint8_t pg_size = 0;
 		ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE, &pg_size);
 		if (ret != ERROR_OK)
 			return ret;
 
-		efm32_info->page_size = BIT((pg_size + 10) & 0xff);
+		efm32_mcu_info->page_size = BIT((pg_size + 10) & 0xff);
 
-		if (efm32_info->part_family == EFM_FAMILY_ID_GIANT_GECKO ||
-				efm32_info->part_family == EFM_FAMILY_ID_LEOPARD_GECKO) {
+		if (efm32_mcu_info->part_family == EFM_FAMILY_ID_GIANT_GECKO ||
+				efm32_mcu_info->part_family == EFM_FAMILY_ID_LEOPARD_GECKO) {
 			/* Giant or Leopard Gecko */
-			if (efm32_info->prod_rev < 18) {
+			if (efm32_mcu_info->prod_rev < 18) {
 				/* EFM32 GG/LG errata: MEM_INFO_PAGE_SIZE is invalid
 				   for MCUs with PROD_REV < 18 */
-				if (efm32_info->flash_sz_kib < 512)
-					efm32_info->page_size = 2048;
+				if (efm32_mcu_info->flash_sz_kib < 512)
+					efm32_mcu_info->page_size = 2048;
 				else
-					efm32_info->page_size = 4096;
+					efm32_mcu_info->page_size = 4096;
 			}
 		}
 
-		if (efm32_info->page_size != 2048 &&
-		    efm32_info->page_size != 4096) {
-			LOG_ERROR("Invalid page size %u", efm32_info->page_size);
+		if (efm32_mcu_info->page_size != 2048 &&
+		    efm32_mcu_info->page_size != 4096) {
+			LOG_ERROR("Invalid page size %u", efm32_mcu_info->page_size);
 			return ERROR_FAIL;
 		}
 	}
@@ -329,14 +329,14 @@ static int efm32x_read_info(struct flash_bank *bank)
 }
 
 /* flash bank efm32 <base> <size> 0 0 <target#> */
-FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
+FLASH_BANK_COMMAND_HANDLER(efm32_flash_bank_command)
 {
-	struct efm32x_flash_chip *efm32x_info = NULL;
+	struct efm32_flash_chip *efm32_info = NULL;
 
 	if (CMD_ARGC < 6)
 		return ERROR_COMMAND_SYNTAX_ERROR;
 
-	int bank_index = efm32x_get_bank_index(bank->base);
+	int bank_index = efm32_get_bank_index(bank->base);
 	if (bank_index < 0) {
 		LOG_ERROR("Flash bank with base address %" PRIx32 " is not supported",
 			(uint32_t)bank->base);
@@ -348,20 +348,20 @@ FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
 		if (bank_iter->driver == &efm32_flash
 			&& bank_iter->target == bank->target
 			&& bank->driver_priv) {
-			efm32x_info = bank->driver_priv;
+			efm32_info = bank->driver_priv;
 			break;
 		}
 	}
 
-	if (!efm32x_info) {
+	if (!efm32_info) {
 		/* target not matched, make a new one */
-		efm32x_info = calloc(1, sizeof(struct efm32x_flash_chip));
+		efm32_info = calloc(1, sizeof(struct efm32_flash_chip));
 
-		memset(efm32x_info->lb_page, 0xff, LOCKWORDS_SZ);
+		memset(efm32_info->lb_page, 0xff, LOCKWORDS_SZ);
 	}
 
-	++efm32x_info->refcount;
-	bank->driver_priv = efm32x_info;
+	++efm32_info->refcount;
+	bank->driver_priv = efm32_info;
 
 	return ERROR_OK;
 }
@@ -370,31 +370,31 @@ FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
  * Remove flash structure corresponding to this bank, if and only if it's not
  * used by any others
  */
-static void efm32x_free_driver_priv(struct flash_bank *bank)
+static void efm32_free_driver_priv(struct flash_bank *bank)
 {
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
-	if (efm32x_info) {
+	if (efm32_info) {
 		/* Use ref count to determine if it can be freed; scanning bank
 		 * list doesn't work, because this function can be called after
 		 * some banks in the list have been already destroyed.
 		 */
-		--efm32x_info->refcount;
-		if (efm32x_info->refcount == 0) {
-			free(efm32x_info);
+		--efm32_info->refcount;
+		if (efm32_info->refcount == 0) {
+			free(efm32_info);
 			bank->driver_priv = NULL;
 		}
 	}
 }
 
 /* set or reset given bits in a register */
-static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
+static int efm32_set_reg_bits(struct flash_bank *bank, uint32_t reg,
 			      uint32_t bitmask, int set)
 {
 	int ret = 0;
 	uint32_t reg_val = 0;
 
-	ret = efm32x_read_reg_u32(bank, reg, &reg_val);
+	ret = efm32_read_reg_u32(bank, reg, &reg_val);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -403,31 +403,31 @@ static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
 	else
 		reg_val &= ~bitmask;
 
-	return efm32x_write_reg_u32(bank, reg, reg_val);
+	return efm32_write_reg_u32(bank, reg, reg_val);
 }
 
-static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
+static int efm32_set_wren(struct flash_bank *bank, int write_enable)
 {
-	return efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
+	return efm32_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
 				  EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
 }
 
-static int efm32x_msc_lock(struct flash_bank *bank, int lock)
+static int efm32_msc_lock(struct flash_bank *bank, int lock)
 {
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
-	return efm32x_write_reg_u32(bank, efm32x_info->reg_lock,
+	return efm32_write_reg_u32(bank, efm32_info->reg_lock,
 		(lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
 }
 
-static int efm32x_wait_status(struct flash_bank *bank, int timeout,
+static int efm32_wait_status(struct flash_bank *bank, int timeout,
 			     uint32_t wait_mask, int wait_for_set)
 {
 	int ret = 0;
 	uint32_t status = 0;
 
 	while (1) {
-		ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
+		ret = efm32_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 		if (ret != ERROR_OK)
 			break;
 
@@ -452,7 +452,7 @@ static int efm32x_wait_status(struct flash_bank *bank, int timeout,
 	return ret;
 }
 
-static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
+static int efm32_erase_page(struct flash_bank *bank, uint32_t addr)
 {
 	/* this function DOES NOT set WREN; must be set already */
 	/* 1. write address to ADDRB
@@ -466,16 +466,16 @@ static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
 
 	LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
 
-	ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
+	ret = efm32_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
+	ret = efm32_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
 				 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
+	ret = efm32_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -489,16 +489,16 @@ static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
 		return ERROR_FAIL;
 	}
 
-	ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
+	ret = efm32_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
 				 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
 	if (ret != ERROR_OK)
 		return ret;
 
-	return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
+	return efm32_wait_status(bank, EFM32_FLASH_ERASE_TMO,
 				 EFM32_MSC_STATUS_BUSY_MASK, 0);
 }
 
-static int efm32x_erase(struct flash_bank *bank, unsigned int first,
+static int efm32_erase(struct flash_bank *bank, unsigned int first,
 		       unsigned int last)
 {
 	struct target *target = bank->target;
@@ -509,26 +509,26 @@ static int efm32x_erase(struct flash_bank *bank, unsigned int first,
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	efm32x_msc_lock(bank, 0);
-	ret = efm32x_set_wren(bank, 1);
+	efm32_msc_lock(bank, 0);
+	ret = efm32_set_wren(bank, 1);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to enable MSC write");
 		return ret;
 	}
 
 	for (unsigned int i = first; i <= last; i++) {
-		ret = efm32x_erase_page(bank, bank->base + bank->sectors[i].offset);
+		ret = efm32_erase_page(bank, bank->base + bank->sectors[i].offset);
 		if (ret != ERROR_OK)
 			LOG_ERROR("Failed to erase page %d", i);
 	}
 
-	ret = efm32x_set_wren(bank, 0);
-	efm32x_msc_lock(bank, 1);
+	ret = efm32_set_wren(bank, 0);
+	efm32_msc_lock(bank, 1);
 	if (ret != ERROR_OK)
 		return ret;
 
 	if (bank->base == EFM32_MSC_LOCK_BITS) {
-		ret = efm32x_write_only_lockbits(bank);
+		ret = efm32_write_only_lockbits(bank);
 		if (ret != ERROR_OK)
 			LOG_ERROR("Failed to restore lockbits after erase");
 	}
@@ -536,9 +536,9 @@ static int efm32x_erase(struct flash_bank *bank, unsigned int first,
 	return ret;
 }
 
-static int efm32x_read_lock_data(struct flash_bank *bank)
+static int efm32_read_lock_data(struct flash_bank *bank)
 {
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	struct target *target = bank->target;
 	int data_size = 0;
 	uint32_t *ptr = NULL;
@@ -549,7 +549,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 	/* calculate the number of 32-bit words to read (one lock bit per sector) */
 	data_size = (bank->num_sectors + 31) / 32;
 
-	ptr = efm32x_info->lb_page;
+	ptr = efm32_info->lb_page;
 
 	for (int i = 0; i < data_size; i++, ptr++) {
 		ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + i * 4, ptr);
@@ -562,7 +562,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 	/* also, read ULW, DLW, MLW, ALW and CLW words */
 
 	/* ULW, word 126 */
-	ptr = efm32x_info->lb_page + 126;
+	ptr = efm32_info->lb_page + 126;
 	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + 126 * 4, ptr);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read ULW");
@@ -570,7 +570,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 	}
 
 	/* DLW, word 127 */
-	ptr = efm32x_info->lb_page + 127;
+	ptr = efm32_info->lb_page + 127;
 	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + 127 * 4, ptr);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read DLW");
@@ -578,7 +578,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 	}
 
 	/* MLW, word 125, present in GG, LG, PG, JG, EFR32 */
-	ptr = efm32x_info->lb_page + 125;
+	ptr = efm32_info->lb_page + 125;
 	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + 125 * 4, ptr);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read MLW");
@@ -586,7 +586,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 	}
 
 	/* ALW, word 124, present in GG, LG, PG, JG, EFR32 */
-	ptr = efm32x_info->lb_page + 124;
+	ptr = efm32_info->lb_page + 124;
 	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + 124 * 4, ptr);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read ALW");
@@ -594,7 +594,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 	}
 
 	/* CLW1, word 123, present in EFR32 */
-	ptr = efm32x_info->lb_page + 123;
+	ptr = efm32_info->lb_page + 123;
 	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + 123 * 4, ptr);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read CLW1");
@@ -602,7 +602,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 	}
 
 	/* CLW0, word 122, present in GG, LG, PG, JG, EFR32 */
-	ptr = efm32x_info->lb_page + 122;
+	ptr = efm32_info->lb_page + 122;
 	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + 122 * 4, ptr);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read CLW0");
@@ -612,22 +612,22 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 	return ERROR_OK;
 }
 
-static int efm32x_write_only_lockbits(struct flash_bank *bank)
+static int efm32_write_only_lockbits(struct flash_bank *bank)
 {
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
-	return efm32x_priv_write(bank, (uint8_t *)efm32x_info->lb_page,
+	return efm32_priv_write(bank, (uint8_t *)efm32_info->lb_page,
 				EFM32_MSC_LOCK_BITS, LOCKWORDS_SZ);
 }
 
-static int efm32x_write_lock_data(struct flash_bank *bank)
+static int efm32_write_lock_data(struct flash_bank *bank)
 {
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	int ret = 0;
 
 	/* Preserve any data written to the high portion of the lockbits page */
-	assert(efm32x_info->info.page_size >= LOCKWORDS_SZ);
-	uint32_t extra_bytes = efm32x_info->info.page_size - LOCKWORDS_SZ;
+	assert(efm32_info->info.page_size >= LOCKWORDS_SZ);
+	uint32_t extra_bytes = efm32_info->info.page_size - LOCKWORDS_SZ;
 	uint8_t *extra_data = NULL;
 
 	if (extra_bytes) {
@@ -642,7 +642,7 @@ static int efm32x_write_lock_data(struct flash_bank *bank)
 		}
 	}
 
-	ret = efm32x_erase_page(bank, EFM32_MSC_LOCK_BITS);
+	ret = efm32_erase_page(bank, EFM32_MSC_LOCK_BITS);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to erase LB page");
 		if (extra_data)
@@ -651,7 +651,7 @@ static int efm32x_write_lock_data(struct flash_bank *bank)
 	}
 
 	if (extra_data) {
-		ret = efm32x_priv_write(bank, extra_data,
+		ret = efm32_priv_write(bank, extra_data,
 				       EFM32_MSC_LOCK_BITS_EXTRA,
 				       extra_bytes);
 		free(extra_data);
@@ -661,26 +661,26 @@ static int efm32x_write_lock_data(struct flash_bank *bank)
 		}
 	}
 
-	return efm32x_write_only_lockbits(bank);
+	return efm32_write_only_lockbits(bank);
 }
 
-static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
+static int efm32_get_page_lock(struct flash_bank *bank, size_t page)
 {
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	uint32_t dw = 0;
 	uint32_t mask = 0;
 
 	switch (bank->base) {
 	case EFM32_FLASH_BASE:
-		dw = efm32x_info->lb_page[page >> 5];
+		dw = efm32_info->lb_page[page >> 5];
 		mask = BIT(page & 0x1f);
 		break;
 	case EFM32_MSC_USER_DATA:
-		dw = efm32x_info->lb_page[126];
+		dw = efm32_info->lb_page[126];
 		mask = BIT(0);
 		break;
 	case EFM32_MSC_LOCK_BITS:
-		dw = efm32x_info->lb_page[126];
+		dw = efm32_info->lb_page[126];
 		mask = BIT(1);
 		break;
 	}
@@ -688,16 +688,16 @@ static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
 	return (dw & mask) ? 0 : 1;
 }
 
-static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
+static int efm32_set_page_lock(struct flash_bank *bank, size_t page, int set)
 {
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
 	if (bank->base != EFM32_FLASH_BASE) {
 		LOG_ERROR("Locking user and lockbits pages is not supported yet");
 		return ERROR_FAIL;
 	}
 
-	uint32_t *dw = &efm32x_info->lb_page[page >> 5];
+	uint32_t *dw = &efm32_info->lb_page[page >> 5];
 	uint32_t mask = 0;
 
 	mask = BIT(page & 0x1f);
@@ -710,7 +710,7 @@ static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
 	return ERROR_OK;
 }
 
-static int efm32x_protect(struct flash_bank *bank, int set, unsigned int first,
+static int efm32_protect(struct flash_bank *bank, int set, unsigned int first,
 			 unsigned int last)
 {
 	struct target *target = bank->target;
@@ -722,14 +722,14 @@ static int efm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 	}
 
 	for (unsigned int i = first; i <= last; i++) {
-		ret = efm32x_set_page_lock(bank, i, set);
+		ret = efm32_set_page_lock(bank, i, set);
 		if (ret != ERROR_OK) {
 			LOG_ERROR("Failed to set lock on page %d", i);
 			return ret;
 		}
 	}
 
-	ret = efm32x_write_lock_data(bank);
+	ret = efm32_write_lock_data(bank);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to write LB page");
 		return ret;
@@ -738,7 +738,7 @@ static int efm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 	return ERROR_OK;
 }
 
-static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
+static int efm32_write_block(struct flash_bank *bank, const uint8_t *buf,
 			     uint32_t address, uint32_t count)
 {
 	struct target *target = bank->target;
@@ -747,11 +747,11 @@ static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
 	struct working_area *source;
 	struct reg_param reg_params[5];
 	struct armv7m_algorithm armv7m_info;
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	int ret = ERROR_OK;
 
 	/* see contrib/loaders/flash/efm32.S for src */
-	static const uint8_t efm32x_flash_write_code[] = {
+	static const uint8_t efm32_flash_write_code[] = {
 		/* #define EFM32_MSC_WRITECTRL_OFFSET      0x008 */
 		/* #define EFM32_MSC_WRITECMD_OFFSET       0x00c */
 		/* #define EFM32_MSC_ADDRB_OFFSET          0x010 */
@@ -819,15 +819,15 @@ static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
 	};
 
 	/* flash write code */
-	if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
+	if (target_alloc_working_area(target, sizeof(efm32_flash_write_code),
 				      &write_algorithm) != ERROR_OK) {
 		LOG_WARNING("no working area available, can't do block memory writes");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
 	ret = target_write_buffer(target, write_algorithm->address,
-				  sizeof(efm32x_flash_write_code),
-				  efm32x_flash_write_code);
+				  sizeof(efm32_flash_write_code),
+				  efm32_flash_write_code);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -851,7 +851,7 @@ static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
 	init_reg_param(&reg_params[3], "r3", 32, PARAM_OUT);	/* buffer end */
 	init_reg_param(&reg_params[4], "r4", 32, PARAM_IN_OUT);	/* target address */
 
-	buf_set_u32(reg_params[0].value, 0, 32, efm32x_info->reg_base);
+	buf_set_u32(reg_params[0].value, 0, 32, efm32_info->reg_base);
 	buf_set_u32(reg_params[1].value, 0, 32, count);
 	buf_set_u32(reg_params[2].value, 0, 32, source->address);
 	buf_set_u32(reg_params[3].value, 0, 32, source->address + source->size);
@@ -894,7 +894,7 @@ static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
 	return ret;
 }
 
-static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
+static int efm32_write_word(struct flash_bank *bank, uint32_t addr,
 			    uint32_t val)
 {
 	/* this function DOES NOT set WREN; must be set already */
@@ -916,16 +916,16 @@ static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
 	/* if not called, GDB errors will be reported during large writes */
 	keep_alive();
 
-	ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
+	ret = efm32_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
+	ret = efm32_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
 				 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32x_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
+	ret = efm32_read_reg_u32(bank, EFM32_MSC_REG_STATUS, &status);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -939,27 +939,27 @@ static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
 		return ERROR_FAIL;
 	}
 
-	ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
+	ret = efm32_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
 				EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Wait for WDATAREADY failed");
 		return ret;
 	}
 
-	ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
+	ret = efm32_write_reg_u32(bank, EFM32_MSC_REG_WDATA, val);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("WDATA write failed");
 		return ret;
 	}
 
-	ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
+	ret = efm32_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
 				  EFM32_MSC_WRITECMD_WRITEONCE_MASK);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("WRITECMD write failed");
 		return ret;
 	}
 
-	ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
+	ret = efm32_wait_status(bank, EFM32_FLASH_WRITE_TMO,
 				EFM32_MSC_STATUS_BUSY_MASK, 0);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Wait for BUSY failed");
@@ -969,7 +969,7 @@ static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
 	return ERROR_OK;
 }
 
-static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
+static int efm32_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 			    uint32_t addr, uint32_t count)
 {
 	struct target *target = bank->target;
@@ -1003,13 +1003,13 @@ static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 	int retval, retval2;
 
 	/* unlock flash registers */
-	efm32x_msc_lock(bank, 0);
-	retval = efm32x_set_wren(bank, 1);
+	efm32_msc_lock(bank, 0);
+	retval = efm32_set_wren(bank, 1);
 	if (retval != ERROR_OK)
 		goto cleanup;
 
 	/* try using a block write */
-	retval = efm32x_write_block(bank, buffer, addr, words_remaining);
+	retval = efm32_write_block(bank, buffer, addr, words_remaining);
 
 	if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 		/* if block write failed (no sufficient working area),
@@ -1020,7 +1020,7 @@ static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 			uint32_t value;
 			memcpy(&value, buffer, sizeof(uint32_t));
 
-			retval = efm32x_write_word(bank, addr, value);
+			retval = efm32_write_word(bank, addr, value);
 			if (retval != ERROR_OK)
 				goto reset_pg_and_lock;
 
@@ -1031,8 +1031,8 @@ static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 	}
 
 reset_pg_and_lock:
-	retval2 = efm32x_set_wren(bank, 0);
-	efm32x_msc_lock(bank, 1);
+	retval2 = efm32_set_wren(bank, 0);
+	efm32_msc_lock(bank, 1);
 	if (retval == ERROR_OK)
 		retval = retval2;
 
@@ -1041,29 +1041,29 @@ cleanup:
 	return retval;
 }
 
-static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
+static int efm32_write(struct flash_bank *bank, const uint8_t *buffer,
 		       uint32_t offset, uint32_t count)
 {
 	if (bank->base == EFM32_MSC_LOCK_BITS && offset < LOCKWORDS_SZ) {
 		LOG_ERROR("Cannot write to lock words");
 		return ERROR_FAIL;
 	}
-	return efm32x_priv_write(bank, buffer, bank->base + offset, count);
+	return efm32_priv_write(bank, buffer, bank->base + offset, count);
 }
 
-static int efm32x_probe(struct flash_bank *bank)
+static int efm32_probe(struct flash_bank *bank)
 {
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
-	struct efm32_info *efm32_mcu_info = &efm32x_info->info;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
+	struct efm32_info *efm32_mcu_info = &efm32_info->info;
 	int ret;
-	int bank_index = efm32x_get_bank_index(bank->base);
+	int bank_index = efm32_get_bank_index(bank->base);
 
 	assert(bank_index >= 0);
 
-	efm32x_info->probed[bank_index] = false;
-	memset(efm32x_info->lb_page, 0xff, LOCKWORDS_SZ);
+	efm32_info->probed[bank_index] = false;
+	memset(efm32_info->lb_page, 0xff, LOCKWORDS_SZ);
 
-	ret = efm32x_read_info(bank);
+	ret = efm32_read_info(bank);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -1081,7 +1081,7 @@ static int efm32x_probe(struct flash_bank *bank)
 		bank->num_sectors = efm32_mcu_info->flash_sz_kib * 1024 / efm32_mcu_info->page_size;
 		assert(bank->num_sectors > 0);
 
-		ret = efm32x_read_lock_data(bank);
+		ret = efm32_read_lock_data(bank);
 		if (ret != ERROR_OK) {
 			LOG_ERROR("Failed to read LB data");
 			return ret;
@@ -1096,24 +1096,24 @@ static int efm32x_probe(struct flash_bank *bank)
 	if (!bank->sectors)
 		return ERROR_FAIL;
 
-	efm32x_info->probed[bank_index] = true;
+	efm32_info->probed[bank_index] = true;
 
 	return ERROR_OK;
 }
 
-static int efm32x_auto_probe(struct flash_bank *bank)
+static int efm32_auto_probe(struct flash_bank *bank)
 {
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
-	int bank_index = efm32x_get_bank_index(bank->base);
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
+	int bank_index = efm32_get_bank_index(bank->base);
 
 	assert(bank_index >= 0);
 
-	if (efm32x_info->probed[bank_index])
+	if (efm32_info->probed[bank_index])
 		return ERROR_OK;
-	return efm32x_probe(bank);
+	return efm32_probe(bank);
 }
 
-static int efm32x_protect_check(struct flash_bank *bank)
+static int efm32_protect_check(struct flash_bank *bank)
 {
 	struct target *target = bank->target;
 	int ret = 0;
@@ -1123,7 +1123,7 @@ static int efm32x_protect_check(struct flash_bank *bank)
 		return ERROR_TARGET_NOT_HALTED;
 	}
 
-	ret = efm32x_read_lock_data(bank);
+	ret = efm32_read_lock_data(bank);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read LB data");
 		return ret;
@@ -1132,29 +1132,29 @@ static int efm32x_protect_check(struct flash_bank *bank)
 	assert(bank->sectors);
 
 	for (unsigned int i = 0; i < bank->num_sectors; i++)
-		bank->sectors[i].is_protected = efm32x_get_page_lock(bank, i);
+		bank->sectors[i].is_protected = efm32_get_page_lock(bank, i);
 
 	return ERROR_OK;
 }
 
-static int get_efm32x_info(struct flash_bank *bank, struct command_invocation *cmd)
+static int get_efm32_info(struct flash_bank *bank, struct command_invocation *cmd)
 {
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 	int ret;
 
-	ret = efm32x_read_info(bank);
+	ret = efm32_read_info(bank);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read EFM32 info");
 		return ret;
 	}
 
 	command_print_sameline(cmd, "%s Gecko, rev %d",
-			       efm32x_info->info.family_data->name,
-			       efm32x_info->info.prod_rev);
+			       efm32_info->info.family_data->name,
+			       efm32_info->info.prod_rev);
 	return ERROR_OK;
 }
 
-COMMAND_HANDLER(efm32x_handle_debuglock_command)
+COMMAND_HANDLER(efm32_handle_debuglock_command)
 {
 	struct target *target = NULL;
 
@@ -1166,7 +1166,7 @@ COMMAND_HANDLER(efm32x_handle_debuglock_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+	struct efm32_flash_chip *efm32_info = bank->driver_priv;
 
 	target = bank->target;
 
@@ -1176,24 +1176,24 @@ COMMAND_HANDLER(efm32x_handle_debuglock_command)
 	}
 
 	uint32_t *ptr;
-	ptr = efm32x_info->lb_page + 127;
+	ptr = efm32_info->lb_page + 127;
 	*ptr = 0;
 
-	retval = efm32x_write_lock_data(bank);
+	retval = efm32_write_lock_data(bank);
 	if (retval != ERROR_OK) {
 		LOG_ERROR("Failed to write LB page");
 		return retval;
 	}
 
-	command_print(CMD, "efm32x debug interface locked, reset the device to apply");
+	command_print(CMD, "efm32 debug interface locked, reset the device to apply");
 
 	return ERROR_OK;
 }
 
-static const struct command_registration efm32x_exec_command_handlers[] = {
+static const struct command_registration efm32_exec_command_handlers[] = {
 	{
 		.name = "debuglock",
-		.handler = efm32x_handle_debuglock_command,
+		.handler = efm32_handle_debuglock_command,
 		.mode = COMMAND_EXEC,
 		.usage = "bank_id",
 		.help = "Lock the debug interface of the device.",
@@ -1201,29 +1201,29 @@ static const struct command_registration efm32x_exec_command_handlers[] = {
 	COMMAND_REGISTRATION_DONE
 };
 
-static const struct command_registration efm32x_command_handlers[] = {
+static const struct command_registration efm32_command_handlers[] = {
 	{
 		.name = "efm32",
 		.mode = COMMAND_ANY,
 		.help = "efm32 flash command group",
 		.usage = "",
-		.chain = efm32x_exec_command_handlers,
+		.chain = efm32_exec_command_handlers,
 	},
 	COMMAND_REGISTRATION_DONE
 };
 
 const struct flash_driver efm32_flash = {
 	.name               = "efm32",
-	.commands           = efm32x_command_handlers,
-	.flash_bank_command = efm32x_flash_bank_command,
-	.erase              = efm32x_erase,
-	.protect            = efm32x_protect,
-	.write              = efm32x_write,
+	.commands           = efm32_command_handlers,
+	.flash_bank_command = efm32_flash_bank_command,
+	.erase              = efm32_erase,
+	.protect            = efm32_protect,
+	.write              = efm32_write,
 	.read               = default_flash_read,
-	.probe              = efm32x_probe,
-	.auto_probe         = efm32x_auto_probe,
+	.probe              = efm32_probe,
+	.auto_probe         = efm32_auto_probe,
 	.erase_check        = default_flash_blank_check,
-	.protect_check      = efm32x_protect_check,
-	.info               = get_efm32x_info,
-	.free_driver_priv   = efm32x_free_driver_priv,
+	.protect_check      = efm32_protect_check,
+	.info               = get_efm32_info,
+	.free_driver_priv   = efm32_free_driver_priv,
 };

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 360 +++++++++++++++++++++++++-------------------------
 1 file changed, 180 insertions(+), 180 deletions(-)


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Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1456-ge434b4b92

From: openocd-gerrit <ope...@us...> - 2026-04-26 05:07:17

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  e434b4b929c3c9f54d2fe80884067416b7fe8810 (commit)
      from  90bf2ca294d58fb1c3f466cd51b44a2978386e9a (commit)

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not appeared on any other notification email; so we list those
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- Log -----------------------------------------------------------------
commit e434b4b929c3c9f54d2fe80884067416b7fe8810
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Wed Feb 4 16:46:57 2026 +0100

    flash/nor/efm32: Fix flash_sector allocation
    
    Let's takes advantage of alloc_block_array(). It will fix the bad
    initialisation value for is_protected and handle case where allocation
    fails.
    
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: Ia4ccf1cea3feb3843a82179bcfe2fd884beed613
    Reviewed-on: https://review.openocd.org/c/openocd/+/9441
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index 8ab2b7459..529d3541e 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -1090,14 +1090,11 @@ static int efm32x_probe(struct flash_bank *bank)
 		bank->num_sectors = 1;
 	}
 	bank->size = bank->num_sectors * efm32_mcu_info->page_size;
-	bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
-
-	for (uint32_t i = 0; i < bank->num_sectors; i++) {
-		bank->sectors[i].offset = i * efm32_mcu_info->page_size;
-		bank->sectors[i].size = efm32_mcu_info->page_size;
-		bank->sectors[i].is_erased = -1;
-		bank->sectors[i].is_protected = 1;
-	}
+	bank->sectors = alloc_block_array(0,
+					  efm32_mcu_info->page_size,
+					  bank->num_sectors);
+	if (!bank->sectors)
+		return ERROR_FAIL;
 
 	efm32x_info->probed[bank_index] = true;
 

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1455-g90bf2ca29

From: openocd-gerrit <ope...@us...> - 2026-04-26 05:06:29

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  90bf2ca294d58fb1c3f466cd51b44a2978386e9a (commit)
      from  7e508338ed0dd3ce2b5fb5b6654ff51125258812 (commit)

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- Log -----------------------------------------------------------------
commit 90bf2ca294d58fb1c3f466cd51b44a2978386e9a
Author: JÃ©rÃ´me Pouiller <jer...@si...>
Date:   Tue Jan 27 19:43:26 2026 +0100

    flash/nor/efm32: Fix coding style issues
    
    We going to do major changes in src/flash/nor/efm32.c. Let's fix all the
    warnigns reported by checkpatch.pl.
    
    This patch should not bring any functional changes.
    
    Signed-off-by: JÃ©rÃ´me Pouiller <jer...@si...>
    Change-Id: I6a54c7b7ef1d8ce0daef998272214d5ee56703a1
    Reviewed-on: https://review.openocd.org/c/openocd/+/9440
    Reviewed-by: Tomas Vanek <va...@fb...>
    Tested-by: jenkins

diff --git a/src/flash/nor/efm32.c b/src/flash/nor/efm32.c
index e40286791..8ab2b7459 100644
--- a/src/flash/nor/efm32.c
+++ b/src/flash/nor/efm32.c
@@ -40,22 +40,22 @@
 #define EFM32_FLASH_BASE                0
 
 /* size in bytes, not words; must fit all Gecko devices */
-#define LOCKWORDS_SZ                512
+#define LOCKWORDS_SZ                    512
 
 #define EFM32_MSC_INFO_BASE             0x0fe00000
 
 #define EFM32_MSC_USER_DATA             EFM32_MSC_INFO_BASE
-#define EFM32_MSC_LOCK_BITS             (EFM32_MSC_INFO_BASE+0x4000)
-#define EFM32_MSC_LOCK_BITS_EXTRA       (EFM32_MSC_LOCK_BITS+LOCKWORDS_SZ)
-#define EFM32_MSC_DEV_INFO              (EFM32_MSC_INFO_BASE+0x8000)
+#define EFM32_MSC_LOCK_BITS             (EFM32_MSC_INFO_BASE + 0x4000)
+#define EFM32_MSC_LOCK_BITS_EXTRA       (EFM32_MSC_LOCK_BITS + LOCKWORDS_SZ)
+#define EFM32_MSC_DEV_INFO              (EFM32_MSC_INFO_BASE + 0x8000)
 
 /* PAGE_SIZE is not present in Zero, Happy and the original Gecko MCU */
-#define EFM32_MSC_DI_PAGE_SIZE          (EFM32_MSC_DEV_INFO+0x1e7)
-#define EFM32_MSC_DI_FLASH_SZ           (EFM32_MSC_DEV_INFO+0x1f8)
-#define EFM32_MSC_DI_RAM_SZ             (EFM32_MSC_DEV_INFO+0x1fa)
-#define EFM32_MSC_DI_PART_NUM           (EFM32_MSC_DEV_INFO+0x1fc)
-#define EFM32_MSC_DI_PART_FAMILY        (EFM32_MSC_DEV_INFO+0x1fe)
-#define EFM32_MSC_DI_PROD_REV           (EFM32_MSC_DEV_INFO+0x1ff)
+#define EFM32_MSC_DI_PAGE_SIZE          (EFM32_MSC_DEV_INFO + 0x1e7)
+#define EFM32_MSC_DI_FLASH_SZ           (EFM32_MSC_DEV_INFO + 0x1f8)
+#define EFM32_MSC_DI_RAM_SZ             (EFM32_MSC_DEV_INFO + 0x1fa)
+#define EFM32_MSC_DI_PART_NUM           (EFM32_MSC_DEV_INFO + 0x1fc)
+#define EFM32_MSC_DI_PART_FAMILY        (EFM32_MSC_DEV_INFO + 0x1fe)
+#define EFM32_MSC_DI_PROD_REV           (EFM32_MSC_DEV_INFO + 0x1ff)
 
 #define EFM32_MSC_REGBASE               0x400c0000
 #define EFM32_MSC_REGBASE_SERIES1       0x400e0000
@@ -127,7 +127,7 @@ struct efm32_info {
 struct efm32x_flash_chip {
 	struct efm32_info info;
 	bool probed[EFM32_N_BANKS];
-	uint32_t lb_page[LOCKWORDS_SZ/4];
+	uint32_t lb_page[LOCKWORDS_SZ / 4];
 	uint32_t reg_base;
 	uint32_t reg_lock;
 	uint32_t refcount;
@@ -196,7 +196,7 @@ static const struct efm32_family_data efm32_families[] = {
 const struct flash_driver efm32_flash;
 
 static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
-	uint32_t addr, uint32_t count);
+			    uint32_t addr, uint32_t count);
 
 static int efm32x_write_only_lockbits(struct flash_bank *bank);
 
@@ -226,7 +226,7 @@ static int efm32x_get_prod_rev(struct flash_bank *bank, uint8_t *prev)
 }
 
 static int efm32x_read_reg_u32(struct flash_bank *bank, target_addr_t offset,
-			       uint32_t *value)
+			      uint32_t *value)
 {
 	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 	uint32_t base = efm32x_info->reg_base;
@@ -247,27 +247,27 @@ static int efm32x_read_info(struct flash_bank *bank)
 {
 	int ret;
 	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
-	struct efm32_info *efm32_info = &(efm32x_info->info);
+	struct efm32_info *efm32_info = &efm32x_info->info;
 
 	memset(efm32_info, 0, sizeof(struct efm32_info));
 
-	ret = efm32x_get_flash_size(bank, &(efm32_info->flash_sz_kib));
+	ret = efm32x_get_flash_size(bank, &efm32_info->flash_sz_kib);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32x_get_ram_size(bank, &(efm32_info->ram_sz_kib));
+	ret = efm32x_get_ram_size(bank, &efm32_info->ram_sz_kib);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32x_get_part_num(bank, &(efm32_info->part_num));
+	ret = efm32x_get_part_num(bank, &efm32_info->part_num);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32x_get_part_family(bank, &(efm32_info->part_family));
+	ret = efm32x_get_part_family(bank, &efm32_info->part_family);
 	if (ret != ERROR_OK)
 		return ret;
 
-	ret = efm32x_get_prod_rev(bank, &(efm32_info->prod_rev));
+	ret = efm32x_get_prod_rev(bank, &efm32_info->prod_rev);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -299,12 +299,11 @@ static int efm32x_read_info(struct flash_bank *bank)
 		efm32_info->page_size = efm32_info->family_data->page_size;
 	} else {
 		uint8_t pg_size = 0;
-		ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE,
-			&pg_size);
+		ret = target_read_u8(bank->target, EFM32_MSC_DI_PAGE_SIZE, &pg_size);
 		if (ret != ERROR_OK)
 			return ret;
 
-		efm32_info->page_size = (1 << ((pg_size+10) & 0xff));
+		efm32_info->page_size = BIT((pg_size + 10) & 0xff);
 
 		if (efm32_info->part_family == EFM_FAMILY_ID_GIANT_GECKO ||
 				efm32_info->part_family == EFM_FAMILY_ID_LEOPARD_GECKO) {
@@ -319,8 +318,8 @@ static int efm32x_read_info(struct flash_bank *bank)
 			}
 		}
 
-		if ((efm32_info->page_size != 2048) &&
-				(efm32_info->page_size != 4096)) {
+		if (efm32_info->page_size != 2048 &&
+		    efm32_info->page_size != 4096) {
 			LOG_ERROR("Invalid page size %u", efm32_info->page_size);
 			return ERROR_FAIL;
 		}
@@ -340,7 +339,7 @@ FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
 	int bank_index = efm32x_get_bank_index(bank->base);
 	if (bank_index < 0) {
 		LOG_ERROR("Flash bank with base address %" PRIx32 " is not supported",
-			(uint32_t) bank->base);
+			(uint32_t)bank->base);
 		return ERROR_FAIL;
 	}
 
@@ -368,17 +367,18 @@ FLASH_BANK_COMMAND_HANDLER(efm32x_flash_bank_command)
 }
 
 /**
- * Remove flash structure corresponding to this bank,
- * if and only if it's not used by any others
+ * Remove flash structure corresponding to this bank, if and only if it's not
+ * used by any others
  */
 static void efm32x_free_driver_priv(struct flash_bank *bank)
 {
 	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
 
 	if (efm32x_info) {
-		/* Use ref count to determine if it can be freed; scanning bank list doesn't work,
-		 * because this function can be called after some banks in the list have been
-		 * already destroyed */
+		/* Use ref count to determine if it can be freed; scanning bank
+		 * list doesn't work, because this function can be called after
+		 * some banks in the list have been already destroyed.
+		 */
 		--efm32x_info->refcount;
 		if (efm32x_info->refcount == 0) {
 			free(efm32x_info);
@@ -389,7 +389,7 @@ static void efm32x_free_driver_priv(struct flash_bank *bank)
 
 /* set or reset given bits in a register */
 static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
-	uint32_t bitmask, int set)
+			      uint32_t bitmask, int set)
 {
 	int ret = 0;
 	uint32_t reg_val = 0;
@@ -409,18 +409,19 @@ static int efm32x_set_reg_bits(struct flash_bank *bank, uint32_t reg,
 static int efm32x_set_wren(struct flash_bank *bank, int write_enable)
 {
 	return efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECTRL,
-		EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
+				  EFM32_MSC_WRITECTRL_WREN_MASK, write_enable);
 }
 
 static int efm32x_msc_lock(struct flash_bank *bank, int lock)
 {
 	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
+
 	return efm32x_write_reg_u32(bank, efm32x_info->reg_lock,
 		(lock ? 0 : EFM32_MSC_LOCK_LOCKKEY));
 }
 
 static int efm32x_wait_status(struct flash_bank *bank, int timeout,
-	uint32_t wait_mask, int wait_for_set)
+			     uint32_t wait_mask, int wait_for_set)
 {
 	int ret = 0;
 	uint32_t status = 0;
@@ -432,9 +433,9 @@ static int efm32x_wait_status(struct flash_bank *bank, int timeout,
 
 		LOG_DEBUG("status: 0x%" PRIx32, status);
 
-		if (((status & wait_mask) == 0) && (wait_for_set == 0))
+		if ((status & wait_mask) == 0 && wait_for_set == 0)
 			break;
-		else if (((status & wait_mask) != 0) && wait_for_set)
+		else if ((status & wait_mask) != 0 && wait_for_set)
 			break;
 
 		if (timeout-- <= 0) {
@@ -462,6 +463,7 @@ static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
 	 */
 	int ret = 0;
 	uint32_t status = 0;
+
 	LOG_DEBUG("erasing flash page at 0x%08" PRIx32, addr);
 
 	ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_ADDRB, addr);
@@ -469,7 +471,7 @@ static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
 		return ret;
 
 	ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
-		EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
+				 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -488,16 +490,16 @@ static int efm32x_erase_page(struct flash_bank *bank, uint32_t addr)
 	}
 
 	ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
-		EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
+				 EFM32_MSC_WRITECMD_ERASEPAGE_MASK, 1);
 	if (ret != ERROR_OK)
 		return ret;
 
 	return efm32x_wait_status(bank, EFM32_FLASH_ERASE_TMO,
-		EFM32_MSC_STATUS_BUSY_MASK, 0);
+				 EFM32_MSC_STATUS_BUSY_MASK, 0);
 }
 
 static int efm32x_erase(struct flash_bank *bank, unsigned int first,
-		unsigned int last)
+		       unsigned int last)
 {
 	struct target *target = bank->target;
 	int ret = 0;
@@ -550,7 +552,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 	ptr = efm32x_info->lb_page;
 
 	for (int i = 0; i < data_size; i++, ptr++) {
-		ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+i*4, ptr);
+		ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + i * 4, ptr);
 		if (ret != ERROR_OK) {
 			LOG_ERROR("Failed to read PLW %d", i);
 			return ret;
@@ -561,7 +563,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 
 	/* ULW, word 126 */
 	ptr = efm32x_info->lb_page + 126;
-	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+126*4, ptr);
+	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + 126 * 4, ptr);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read ULW");
 		return ret;
@@ -569,7 +571,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 
 	/* DLW, word 127 */
 	ptr = efm32x_info->lb_page + 127;
-	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+127*4, ptr);
+	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + 127 * 4, ptr);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read DLW");
 		return ret;
@@ -577,7 +579,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 
 	/* MLW, word 125, present in GG, LG, PG, JG, EFR32 */
 	ptr = efm32x_info->lb_page + 125;
-	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+125*4, ptr);
+	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + 125 * 4, ptr);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read MLW");
 		return ret;
@@ -585,7 +587,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 
 	/* ALW, word 124, present in GG, LG, PG, JG, EFR32 */
 	ptr = efm32x_info->lb_page + 124;
-	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+124*4, ptr);
+	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + 124 * 4, ptr);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read ALW");
 		return ret;
@@ -593,7 +595,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 
 	/* CLW1, word 123, present in EFR32 */
 	ptr = efm32x_info->lb_page + 123;
-	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+123*4, ptr);
+	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + 123 * 4, ptr);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read CLW1");
 		return ret;
@@ -601,7 +603,7 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 
 	/* CLW0, word 122, present in GG, LG, PG, JG, EFR32 */
 	ptr = efm32x_info->lb_page + 122;
-	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS+122*4, ptr);
+	ret = target_read_u32(target, EFM32_MSC_LOCK_BITS + 122 * 4, ptr);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Failed to read CLW0");
 		return ret;
@@ -613,7 +615,9 @@ static int efm32x_read_lock_data(struct flash_bank *bank)
 static int efm32x_write_only_lockbits(struct flash_bank *bank)
 {
 	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
-	return efm32x_priv_write(bank, (uint8_t *)efm32x_info->lb_page, EFM32_MSC_LOCK_BITS, LOCKWORDS_SZ);
+
+	return efm32x_priv_write(bank, (uint8_t *)efm32x_info->lb_page,
+				EFM32_MSC_LOCK_BITS, LOCKWORDS_SZ);
 }
 
 static int efm32x_write_lock_data(struct flash_bank *bank)
@@ -625,9 +629,12 @@ static int efm32x_write_lock_data(struct flash_bank *bank)
 	assert(efm32x_info->info.page_size >= LOCKWORDS_SZ);
 	uint32_t extra_bytes = efm32x_info->info.page_size - LOCKWORDS_SZ;
 	uint8_t *extra_data = NULL;
+
 	if (extra_bytes) {
 		extra_data = malloc(extra_bytes);
-		ret = target_read_buffer(bank->target, EFM32_MSC_LOCK_BITS_EXTRA, extra_bytes, extra_data);
+		ret = target_read_buffer(bank->target,
+					 EFM32_MSC_LOCK_BITS_EXTRA,
+					 extra_bytes, extra_data);
 		if (ret != ERROR_OK) {
 			LOG_ERROR("Failed to read extra contents of LB page");
 			free(extra_data);
@@ -644,7 +651,9 @@ static int efm32x_write_lock_data(struct flash_bank *bank)
 	}
 
 	if (extra_data) {
-		ret = efm32x_priv_write(bank, extra_data, EFM32_MSC_LOCK_BITS_EXTRA, extra_bytes);
+		ret = efm32x_priv_write(bank, extra_data,
+				       EFM32_MSC_LOCK_BITS_EXTRA,
+				       extra_bytes);
 		free(extra_data);
 		if (ret != ERROR_OK) {
 			LOG_ERROR("Failed to restore extra contents of LB page");
@@ -664,15 +673,15 @@ static int efm32x_get_page_lock(struct flash_bank *bank, size_t page)
 	switch (bank->base) {
 	case EFM32_FLASH_BASE:
 		dw = efm32x_info->lb_page[page >> 5];
-		mask = 1 << (page & 0x1f);
+		mask = BIT(page & 0x1f);
 		break;
 	case EFM32_MSC_USER_DATA:
 		dw = efm32x_info->lb_page[126];
-		mask = 0x1;
+		mask = BIT(0);
 		break;
 	case EFM32_MSC_LOCK_BITS:
 		dw = efm32x_info->lb_page[126];
-		mask = 0x2;
+		mask = BIT(1);
 		break;
 	}
 
@@ -691,7 +700,7 @@ static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
 	uint32_t *dw = &efm32x_info->lb_page[page >> 5];
 	uint32_t mask = 0;
 
-	mask = 1 << (page & 0x1f);
+	mask = BIT(page & 0x1f);
 
 	if (!set)
 		*dw |= mask;
@@ -702,7 +711,7 @@ static int efm32x_set_page_lock(struct flash_bank *bank, size_t page, int set)
 }
 
 static int efm32x_protect(struct flash_bank *bank, int set, unsigned int first,
-		unsigned int last)
+			 unsigned int last)
 {
 	struct target *target = bank->target;
 	int ret = 0;
@@ -730,7 +739,7 @@ static int efm32x_protect(struct flash_bank *bank, int set, unsigned int first,
 }
 
 static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
-	uint32_t address, uint32_t count)
+			     uint32_t address, uint32_t count)
 {
 	struct target *target = bank->target;
 	uint32_t buffer_size = 16384;
@@ -809,16 +818,16 @@ static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
 			0x00, 0xbe,    /* bkpt    #0 */
 	};
 
-
 	/* flash write code */
 	if (target_alloc_working_area(target, sizeof(efm32x_flash_write_code),
-			&write_algorithm) != ERROR_OK) {
+				      &write_algorithm) != ERROR_OK) {
 		LOG_WARNING("no working area available, can't do block memory writes");
 		return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
 	}
 
 	ret = target_write_buffer(target, write_algorithm->address,
-			sizeof(efm32x_flash_write_code), efm32x_flash_write_code);
+				  sizeof(efm32x_flash_write_code),
+				  efm32x_flash_write_code);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -852,15 +861,15 @@ static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
 	armv7m_info.core_mode = ARM_MODE_THREAD;
 
 	ret = target_run_flash_async_algorithm(target, buf, count, 4,
-			0, NULL,
-			5, reg_params,
-			source->address, source->size,
-			write_algorithm->address, 0,
-			&armv7m_info);
+					       0, NULL,
+					       5, reg_params,
+					       source->address, source->size,
+					       write_algorithm->address, 0,
+					       &armv7m_info);
 
 	if (ret == ERROR_FLASH_OPERATION_FAILED) {
-		LOG_ERROR("flash write failed at address 0x%"PRIx32,
-				buf_get_u32(reg_params[4].value, 0, 32));
+		LOG_ERROR("flash write failed at address 0x%" PRIx32,
+			  buf_get_u32(reg_params[4].value, 0, 32));
 
 		if (buf_get_u32(reg_params[0].value, 0, 32) &
 				EFM32_MSC_STATUS_LOCKED_MASK) {
@@ -886,7 +895,7 @@ static int efm32x_write_block(struct flash_bank *bank, const uint8_t *buf,
 }
 
 static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
-	uint32_t val)
+			    uint32_t val)
 {
 	/* this function DOES NOT set WREN; must be set already */
 	/* 1. write address to ADDRB
@@ -912,7 +921,7 @@ static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
 		return ret;
 
 	ret = efm32x_set_reg_bits(bank, EFM32_MSC_REG_WRITECMD,
-		EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
+				 EFM32_MSC_WRITECMD_LADDRIM_MASK, 1);
 	if (ret != ERROR_OK)
 		return ret;
 
@@ -931,7 +940,7 @@ static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
 	}
 
 	ret = efm32x_wait_status(bank, EFM32_FLASH_WDATAREADY_TMO,
-		EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
+				EFM32_MSC_STATUS_WDATAREADY_MASK, 1);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Wait for WDATAREADY failed");
 		return ret;
@@ -944,14 +953,14 @@ static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
 	}
 
 	ret = efm32x_write_reg_u32(bank, EFM32_MSC_REG_WRITECMD,
-		EFM32_MSC_WRITECMD_WRITEONCE_MASK);
+				  EFM32_MSC_WRITECMD_WRITEONCE_MASK);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("WRITECMD write failed");
 		return ret;
 	}
 
 	ret = efm32x_wait_status(bank, EFM32_FLASH_WRITE_TMO,
-		EFM32_MSC_STATUS_BUSY_MASK, 0);
+				EFM32_MSC_STATUS_BUSY_MASK, 0);
 	if (ret != ERROR_OK) {
 		LOG_ERROR("Wait for BUSY failed");
 		return ret;
@@ -961,7 +970,7 @@ static int efm32x_write_word(struct flash_bank *bank, uint32_t addr,
 }
 
 static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
-		uint32_t addr, uint32_t count)
+			    uint32_t addr, uint32_t count)
 {
 	struct target *target = bank->target;
 	uint8_t *new_buffer = NULL;
@@ -972,8 +981,7 @@ static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 	}
 
 	if (addr & 0x3) {
-		LOG_ERROR("addr 0x%" PRIx32 " breaks required 4-byte "
-			"alignment", addr);
+		LOG_ERROR("addr 0x%" PRIx32 " breaks required 4-byte alignment", addr);
 		return ERROR_FLASH_DST_BREAKS_ALIGNMENT;
 	}
 
@@ -982,12 +990,11 @@ static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 		count = (old_count | 3) + 1;
 		new_buffer = malloc(count);
 		if (!new_buffer) {
-			LOG_ERROR("odd number of bytes to write and no memory "
-				"for padding buffer");
+			LOG_ERROR("odd number of bytes to write and no memory for padding buffer");
 			return ERROR_FAIL;
 		}
-		LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %" PRIu32 " "
-			"and padding with 0xff", old_count, count);
+		LOG_INFO("odd number of bytes to write (%" PRIu32 "), extending to %"
+			 PRIu32 " and padding with 0xff", old_count, count);
 		memset(new_buffer, 0xff, count);
 		buffer = memcpy(new_buffer, buffer, old_count);
 	}
@@ -1007,8 +1014,7 @@ static int efm32x_priv_write(struct flash_bank *bank, const uint8_t *buffer,
 	if (retval == ERROR_TARGET_RESOURCE_NOT_AVAILABLE) {
 		/* if block write failed (no sufficient working area),
 		 * we use normal (slow) single word accesses */
-		LOG_WARNING("couldn't use block writes, falling back to single "
-			"memory accesses");
+		LOG_WARNING("couldn't use block writes, falling back to single memory accesses");
 
 		while (words_remaining > 0) {
 			uint32_t value;
@@ -1036,7 +1042,7 @@ cleanup:
 }
 
 static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
-		uint32_t offset, uint32_t count)
+		       uint32_t offset, uint32_t count)
 {
 	if (bank->base == EFM32_MSC_LOCK_BITS && offset < LOCKWORDS_SZ) {
 		LOG_ERROR("Cannot write to lock words");
@@ -1048,10 +1054,10 @@ static int efm32x_write(struct flash_bank *bank, const uint8_t *buffer,
 static int efm32x_probe(struct flash_bank *bank)
 {
 	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
-	struct efm32_info *efm32_mcu_info = &(efm32x_info->info);
+	struct efm32_info *efm32_mcu_info = &efm32x_info->info;
 	int ret;
-
 	int bank_index = efm32x_get_bank_index(bank->base);
+
 	assert(bank_index >= 0);
 
 	efm32x_info->probed[bank_index] = false;
@@ -1062,7 +1068,7 @@ static int efm32x_probe(struct flash_bank *bank)
 		return ret;
 
 	LOG_INFO("detected part: %s Gecko, rev %d",
-			efm32_mcu_info->family_data->name, efm32_mcu_info->prod_rev);
+		 efm32_mcu_info->family_data->name, efm32_mcu_info->prod_rev);
 	LOG_INFO("flash size = %d KiB", efm32_mcu_info->flash_sz_kib);
 	LOG_INFO("flash page size = %d B", efm32_mcu_info->page_size);
 
@@ -1072,8 +1078,7 @@ static int efm32x_probe(struct flash_bank *bank)
 	bank->sectors = NULL;
 
 	if (bank->base == EFM32_FLASH_BASE) {
-		bank->num_sectors = efm32_mcu_info->flash_sz_kib * 1024 /
-			efm32_mcu_info->page_size;
+		bank->num_sectors = efm32_mcu_info->flash_sz_kib * 1024 / efm32_mcu_info->page_size;
 		assert(bank->num_sectors > 0);
 
 		ret = efm32x_read_lock_data(bank);
@@ -1081,8 +1086,9 @@ static int efm32x_probe(struct flash_bank *bank)
 			LOG_ERROR("Failed to read LB data");
 			return ret;
 		}
-	} else
+	} else {
 		bank->num_sectors = 1;
+	}
 	bank->size = bank->num_sectors * efm32_mcu_info->page_size;
 	bank->sectors = malloc(sizeof(struct flash_sector) * bank->num_sectors);
 
@@ -1101,8 +1107,8 @@ static int efm32x_probe(struct flash_bank *bank)
 static int efm32x_auto_probe(struct flash_bank *bank)
 {
 	struct efm32x_flash_chip *efm32x_info = bank->driver_priv;
-
 	int bank_index = efm32x_get_bank_index(bank->base);
+
 	assert(bank_index >= 0);
 
 	if (efm32x_info->probed[bank_index])
@@ -1145,8 +1151,9 @@ static int get_efm32x_info(struct flash_bank *bank, struct command_invocation *c
 		return ret;
 	}
 
-	command_print_sameline(cmd, "%s Gecko, rev %d", efm32x_info->info.family_data->name,
-		efm32x_info->info.prod_rev);
+	command_print_sameline(cmd, "%s Gecko, rev %d",
+			       efm32x_info->info.family_data->name,
+			       efm32x_info->info.prod_rev);
 	return ERROR_OK;
 }
 
@@ -1209,17 +1216,17 @@ static const struct command_registration efm32x_command_handlers[] = {
 };
 
 const struct flash_driver efm32_flash = {
-	.name = "efm32",
-	.commands = efm32x_command_handlers,
+	.name               = "efm32",
+	.commands           = efm32x_command_handlers,
 	.flash_bank_command = efm32x_flash_bank_command,
-	.erase = efm32x_erase,
-	.protect = efm32x_protect,
-	.write = efm32x_write,
-	.read = default_flash_read,
-	.probe = efm32x_probe,
-	.auto_probe = efm32x_auto_probe,
-	.erase_check = default_flash_blank_check,
-	.protect_check = efm32x_protect_check,
-	.info = get_efm32x_info,
-	.free_driver_priv = efm32x_free_driver_priv,
+	.erase              = efm32x_erase,
+	.protect            = efm32x_protect,
+	.write              = efm32x_write,
+	.read               = default_flash_read,
+	.probe              = efm32x_probe,
+	.auto_probe         = efm32x_auto_probe,
+	.erase_check        = default_flash_blank_check,
+	.protect_check      = efm32x_protect_check,
+	.info               = get_efm32x_info,
+	.free_driver_priv   = efm32x_free_driver_priv,
 };

-----------------------------------------------------------------------

Summary of changes:
 src/flash/nor/efm32.c | 209 ++++++++++++++++++++++++++------------------------
 1 file changed, 108 insertions(+), 101 deletions(-)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1454-g7e508338e

From: openocd-gerrit <ope...@us...> - 2026-04-23 08:05:41

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  7e508338ed0dd3ce2b5fb5b6654ff51125258812 (commit)
      from  b07521d1847f368cb2d9d46297ecb61168f3f68b (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit 7e508338ed0dd3ce2b5fb5b6654ff51125258812
Author: Tomas Vanek <va...@fb...>
Date:   Sat Nov 29 20:16:29 2025 +0100

    target/riscv: add target_was_examined() checks
    
    If a RISC-V target does not pass initial examination
    some commands fail by assert() or log lot of hardly
    understandable errors.
    
    Check if target was examined otherwise fail early.
    Although command_print() is preferred in OpenOCD commands,
    use LOG_TARGET_ERROR() if the rest of command uses the same.
    
    Change-Id: I615e48f348a0f3bdaf71630a2fcd6fc7665115d5
    Signed-off-by: Tomas Vanek <va...@fb...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9275
    Tested-by: jenkins
    Reviewed-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/riscv/riscv.c b/src/target/riscv/riscv.c
index 3dffce50e..e92366d44 100644
--- a/src/target/riscv/riscv.c
+++ b/src/target/riscv/riscv.c
@@ -5007,6 +5007,11 @@ COMMAND_HANDLER(riscv_itrigger)
 	struct target *target = get_current_target(CMD_CTX);
 	const int ITRIGGER_UNIQUE_ID = -CSR_TDATA1_TYPE_ITRIGGER;
 
+	if (!target_was_examined(target)) {
+		LOG_TARGET_ERROR(target, "not examined");
+		return ERROR_TARGET_NOT_EXAMINED;
+	}
+
 	if (riscv_enumerate_triggers(target) != ERROR_OK)
 		return ERROR_FAIL;
 
@@ -5072,6 +5077,11 @@ COMMAND_HANDLER(riscv_icount)
 	struct target *target = get_current_target(CMD_CTX);
 	const int ICOUNT_UNIQUE_ID = -CSR_TDATA1_TYPE_ICOUNT;
 
+	if (!target_was_examined(target)) {
+		LOG_TARGET_ERROR(target, "not examined");
+		return ERROR_TARGET_NOT_EXAMINED;
+	}
+
 	if (riscv_enumerate_triggers(target) != ERROR_OK)
 		return ERROR_FAIL;
 
@@ -5137,6 +5147,11 @@ COMMAND_HANDLER(riscv_etrigger)
 	struct target *target = get_current_target(CMD_CTX);
 	const int ETRIGGER_UNIQUE_ID = -CSR_TDATA1_TYPE_ETRIGGER;
 
+	if (!target_was_examined(target)) {
+		LOG_TARGET_ERROR(target, "not examined");
+		return ERROR_TARGET_NOT_EXAMINED;
+	}
+
 	if (riscv_enumerate_triggers(target) != ERROR_OK)
 		return ERROR_FAIL;
 
@@ -5194,6 +5209,11 @@ COMMAND_HANDLER(riscv_etrigger)
 COMMAND_HANDLER(handle_repeat_read)
 {
 	struct target *target = get_current_target(CMD_CTX);
+	if (!target_was_examined(target)) {
+		LOG_TARGET_ERROR(target, "not examined");
+		return ERROR_TARGET_NOT_EXAMINED;
+	}
+
 	RISCV_INFO(r);
 
 	if (CMD_ARGC < 2 || CMD_ARGC > 3)
@@ -5408,6 +5428,11 @@ COMMAND_HANDLER(riscv_exec_progbuf)
 
 	struct target *target = get_current_target(CMD_CTX);
 
+	if (!target_was_examined(target)) {
+		LOG_TARGET_ERROR(target, "not examined");
+		return ERROR_TARGET_NOT_EXAMINED;
+	}
+
 	RISCV_INFO(r);
 	if (r->dtm_version != DTM_DTMCS_VERSION_1_0) {
 		LOG_TARGET_ERROR(target, "exec_progbuf: Program buffer is "
@@ -5514,6 +5539,11 @@ static COMMAND_HELPER(report_reserved_triggers, struct target *target)
 COMMAND_HANDLER(handle_reserve_trigger)
 {
 	struct target *target = get_current_target(CMD_CTX);
+	if (!target_was_examined(target)) {
+		command_print(CMD, "Error: Target not examined");
+		return ERROR_TARGET_NOT_EXAMINED;
+	}
+
 	if (CMD_ARGC == 0)
 		return CALL_COMMAND_HANDLER(report_reserved_triggers, target);
 

-----------------------------------------------------------------------

Summary of changes:
 src/target/riscv/riscv.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)


hooks/post-receive
-- 
Main OpenOCD repository

[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1453-gb07521d18

From: openocd-gerrit <ope...@us...> - 2026-04-23 08:04:27

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  b07521d1847f368cb2d9d46297ecb61168f3f68b (commit)
      from  21c759505787a48f913223d6cbdac67bb7a7a92c (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit b07521d1847f368cb2d9d46297ecb61168f3f68b
Author: Evgeniy Naydanov <eu...@gm...>
Date:   Wed Feb 25 19:16:38 2026 +0300

    target/xtensa: drop the call to `target_set_examined()`
    
    This is a valid change, since:
    * The flag is set in the type-independent code on success and reset on
      failure.
    * `xtensa_examine` only calls `xtensa_smpbreak_write()` after setting
      the flag, which in turn does not include `target_was_examined()` in
      it's call graph (see the review comment for details).
    
    Change-Id: Ie5895849a3c69ad8ee75d7b94b059ce532eb99d2
    Signed-off-by: Evgeniy Naydanov <eu...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9484
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/xtensa/xtensa.c b/src/target/xtensa/xtensa.c
index faf57fc2e..d1a08c3bd 100644
--- a/src/target/xtensa/xtensa.c
+++ b/src/target/xtensa/xtensa.c
@@ -907,7 +907,6 @@ int xtensa_examine(struct target *target)
 		return ERROR_TARGET_FAILURE;
 	}
 	LOG_DEBUG("OCD_ID = %08" PRIx32, xtensa->dbg_mod.device_id);
-	target_set_examined(target);
 	xtensa_smpbreak_write(xtensa, xtensa->smp_break);
 	return ERROR_OK;
 }

-----------------------------------------------------------------------

Summary of changes:
 src/target/xtensa/xtensa.c | 1 -
 1 file changed, 1 deletion(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1452-g21c759505

From: openocd-gerrit <ope...@us...> - 2026-04-23 08:04:04

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  21c759505787a48f913223d6cbdac67bb7a7a92c (commit)
      from  d8accabeeaac949d53b9d641ee1f791fb8789444 (commit)

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- Log -----------------------------------------------------------------
commit 21c759505787a48f913223d6cbdac67bb7a7a92c
Author: Evgeniy Naydanov <eu...@gm...>
Date:   Fri Feb 20 19:13:06 2026 +0300

    target/openrisc: drop the call to `target_set_examined()`
    
    This is a valid change, since:
    * The flag is set in the type-independent code on success and reset on
      failure.
    * `or1k_examine` does not include `target_was_examined()` in it's
      call graph (see the review comment for details).
    
    Change-Id: I1e4670d00df186d24ef59bde4826691607fda59f
    Signed-off-by: Evgeniy Naydanov <eu...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9483
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/openrisc/or1k.c b/src/target/openrisc/or1k.c
index 4aa2bd734..eab064140 100644
--- a/src/target/openrisc/or1k.c
+++ b/src/target/openrisc/or1k.c
@@ -1124,8 +1124,6 @@ static int or1k_examine(struct target *target)
 
 	if (!target_was_examined(target)) {
 
-		target_set_examined(target);
-
 		int running;
 
 		int retval = du_core->or1k_is_cpu_running(&or1k->jtag, &running);

-----------------------------------------------------------------------

Summary of changes:
 src/target/openrisc/or1k.c | 2 --
 1 file changed, 2 deletions(-)


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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1451-gd8accabee

From: openocd-gerrit <ope...@us...> - 2026-04-23 08:03:48

This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "Main OpenOCD repository".

The branch, master has been updated
       via  d8accabeeaac949d53b9d641ee1f791fb8789444 (commit)
      from  fe2f4aea85e4a852b424d59496279ba26b6a6373 (commit)

Those revisions listed above that are new to this repository have
not appeared on any other notification email; so we list those
revisions in full, below.

- Log -----------------------------------------------------------------
commit d8accabeeaac949d53b9d641ee1f791fb8789444
Author: Evgeniy Naydanov <eu...@gm...>
Date:   Fri Feb 20 19:05:03 2026 +0300

    target/dsp563xx: drop the call to `target_set_examined()`
    
    This is a valid change, since:
    * The flag is set in the type-independent code on success and reset on
      failure.
    * `dsp563xx_examine` does not include `target_was_examined()` in it's
      call graph (see the review comment for details).
    
    Change-Id: Ifdd79eb12e2a6337f8224469c8621484fa14c25d
    Signed-off-by: Evgeniy Naydanov <eu...@gm...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/9482
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <va...@fb...>

diff --git a/src/target/dsp563xx.c b/src/target/dsp563xx.c
index a989c331b..5b87da26e 100644
--- a/src/target/dsp563xx.c
+++ b/src/target/dsp563xx.c
@@ -915,8 +915,6 @@ static int dsp563xx_examine(struct target *target)
 	}
 
 	if (!target_was_examined(target)) {
-		target_set_examined(target);
-
 		/* examine core and chip derivate number */
 		chip = (target->tap->idcode>>12) & 0x3ff;
 		/* core number 0 means DSP563XX */

-----------------------------------------------------------------------

Summary of changes:
 src/target/dsp563xx.c | 2 --
 1 file changed, 2 deletions(-)


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