[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.12.0-1758-g67957fb77

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- Log -----------------------------------------------------------------
commit 67957fb77e06c634d310a8732f7aef5b86cc1583
Author: Ryan QIAN <jia...@hp...>
Date:   Tue Oct 13 08:13:22 2026 +0800

    tcl: add hpm5e00 and hpm5e00evk configs
    
    - add target and board config files for hpm5e00
    - the board declares two flash banks for the xpi0 nor: the standard
      0x80000000 window and the hybrid 0xB0000000 window, both mapping
      the same physical flash
    
    Change-Id: I7b5abf02bcd4d4eef885063d3bfce04194182446
    Signed-off-by: Ryan QIAN <jia...@hp...>
    Reviewed-on: https://review.openocd.org/c/openocd/+/10120
    Reviewed-by: Antonio Borneo <bor...@gm...>
    Tested-by: jenkins
    Reviewed-by: Tomas Vanek <tom...@gm...>

diff --git a/tcl/board/hpmicro/hpm5e00evk.cfg b/tcl/board/hpmicro/hpm5e00evk.cfg
new file mode 100644
index 000000000..1c65acc5d
--- /dev/null
+++ b/tcl/board/hpmicro/hpm5e00evk.cfg
@@ -0,0 +1,75 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2026 HPMicro
+
+adapter speed 10000
+source [find interface/hpmicro/hpmicro_evk.cfg]
+source [find target/hpmicro/hpm5e00.cfg]
+# openocd flash driver argument:
+#   - option0:
+#       [31:28] Flash probe type
+#         0 - SFDP SDR / 1 - SFDP DDR
+#         2 - 1-4-4 Read (0xEB, 24-bit address) / 3 - 1-2-2 Read(0xBB, 24-bit address)
+#         4 - HyperFLASH 1.8V / 5 - HyperFLASH 3V
+#         6 - OctaBus DDR (SPI -> OPI DDR)
+#         8 - Xccela DDR (SPI -> OPI DDR)
+#         10 - EcoXiP DDR (SPI -> OPI DDR)
+#       [27:24] Command Pads after Power-on Reset
+#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+#       [23:20] Command Pads after Configuring FLASH
+#         0 - SPI / 1 - DPI / 2 - QPI / 3 - OPI
+#       [19:16] Quad Enable Sequence (for the device support SFDP 1.0 only)
+#         0 - Not needed
+#         1 - QE bit is at bit6 in Status Register 1
+#         2 - QE bit is at bit1 in Status Register 2
+#         3 - QE bit is at bit7 in Status Register 2
+#         4 - QE bit is at bit1 in Status Register 2 and should be programmed by 0x31
+#       [15:8] Dummy cycles
+#         0 - Auto-probed / detected / default value
+#         Others - User specified value, for DDR read, the dummy cycles should be 2 * cycles on FLASH datasheet
+#       [7:4] Misc.
+#         0 - Not used
+#         1 - SPI mode
+#         2 - Internal loopback
+#         3 - External DQS
+#       [3:0] Frequency option
+#         1 - 30MHz / 2 - 50MHz / 3 - 66MHz / 4 - 80MHz / 5 - 100MHz / 6 - 120MHz / 7 - 133MHz / 8 - 166MHz
+#   - option1:
+#       [31:20]  Reserved
+#       [19:16] IO voltage
+#         0 - 3V / 1 - 1.8V
+#       [15:12] Pin group
+#         0 - 1st group / 1 - 2nd group
+#       [11:8] Connection selection
+#         0 - CA_CS0 / 1 - CB_CS0 / 2 - CA_CS0 + CB_CS0 (Two FLASH connected to CA and CB respectively)
+#       [7:0] Drive Strength
+#         0 - Default value
+
+# xpi0 configs
+#   - flash driver:     hpm_xpi
+#   - flash ctrl index: 0xF3000000
+#   - base address:     0x80000000
+#   - flash size:       0x2000000
+#   - flash option0:    0x5
+#   - flash option1:    0x1000
+flash bank xpi0 hpm_xpi 0x80000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000
+
+# xpi0_hybrid configs
+#   - flash driver:     hpm_xpi
+#   - flash ctrl index: 0xF3000000
+#   - base address:     0xB0000000
+#   - flash size:       0x2000000
+#   - flash option0:    0x5
+#   - flash option1:    0x1000
+flash bank xpi0_hybrid hpm_xpi 0xB0000000 0x2000000 1 1 $_TARGET0 0xF3000000 0x5 0x1000
+
+proc init_clock {} {
+	mww 0xF4000800 0xFFFFFFFF
+	mww 0xF4000810 0xFFFFFFFF
+	mww 0xF4000820 0xFFFFFFFF
+	mww 0xF4000830 0xFFFFFFFF
+	echo "clocks has been enabled!"
+}
+
+$_TARGET0 configure -event reset-init {
+	init_clock
+}
diff --git a/tcl/target/hpmicro/hpm5e00.cfg b/tcl/target/hpmicro/hpm5e00.cfg
new file mode 100644
index 000000000..4f3379986
--- /dev/null
+++ b/tcl/target/hpmicro/hpm5e00.cfg
@@ -0,0 +1,22 @@
+# SPDX-License-Identifier: BSD-3-Clause
+# Copyright (c) 2026 HPMicro
+
+if { [info exists CHIPNAME] } {
+	set _CHIP $CHIPNAME
+} else {
+	set _CHIP hpm5e00
+}
+set _CPUTAPID 0x1000563D
+jtag newtap $_CHIP cpu -irlen 5 -expected-id $_CPUTAPID
+
+set _TARGET0 $_CHIP.cpu0
+target create $_TARGET0 riscv -tap $_CHIP.cpu -coreid 0
+
+$_TARGET0 configure -work-area-phys 0x00000000 -work-area-size 0x20000 -work-area-backup 0
+
+source [find target/hpmicro/hpm_common.cfg]
+source [find target/hpmicro/hpm_common_csr.cfg]
+
+proc reset_soc {} {
+	sba_write_mem 0xF410001C 24000000
+}

-----------------------------------------------------------------------

Summary of changes:
 tcl/board/hpmicro/{hpm5301evklite.cfg => hpm5e00evk.cfg} | 13 +++++++++++--
 tcl/target/hpmicro/{hpm5100.cfg => hpm5e00.cfg}          |  6 +++---
 2 files changed, 14 insertions(+), 5 deletions(-)
 copy tcl/board/hpmicro/{hpm5301evklite.cfg => hpm5e00evk.cfg} (86%)
 copy tcl/target/hpmicro/{hpm5100.cfg => hpm5e00.cfg} (82%)


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