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From: openocd-gerrit <ope...@us...> - 2026-07-17 08:33:04
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via 7bb208c309203c70c43e5ad21a806b17894763c1 (commit)
from da6c65041fb9e299fe8f1cc9eb825c119c454c5c (commit)
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- Log -----------------------------------------------------------------
commit b63fc374f038a474fd0cbca2728138512d4f640e
Author: Anatoly Parshintsev <kup...@gm...>
Date: Sun Feb 1 13:30:19 2026 +0300
target/riscv: do not cache access to vxrm, vxsat and vcsr
vxrm and vxsat registers are mirrored in vcsr, so we can't cache any of
them.
Change-Id: I09760de5b76c330797caa99d2ef0ef151546e956
Signed-off-by: Anatoly Parshintsev <kup...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9422
Reviewed-by: Tomas Vanek <va...@fb...>
Tested-by: jenkins
diff --git a/src/target/riscv/riscv_reg_impl.h b/src/target/riscv/riscv_reg_impl.h
index f45af047d..d38d4146e 100644
--- a/src/target/riscv/riscv_reg_impl.h
+++ b/src/target/riscv/riscv_reg_impl.h
@@ -195,8 +195,6 @@ static inline bool riscv_reg_impl_gdb_regno_cacheable(enum gdb_regno regno,
* CSRs. */
switch (regno) {
case GDB_REGNO_DPC:
- case GDB_REGNO_VXSAT:
- case GDB_REGNO_VXRM:
case GDB_REGNO_VLENB:
case GDB_REGNO_MISA:
case GDB_REGNO_DCSR:
@@ -216,6 +214,9 @@ static inline bool riscv_reg_impl_gdb_regno_cacheable(enum gdb_regno regno,
case GDB_REGNO_VSTART: /* Changes value when vtype is changed. */
case GDB_REGNO_VL: /* Changes value when vtype is changed. */
case GDB_REGNO_VTYPE: /* Writes to vtype have side effects, so we don't cache it. */
+ case GDB_REGNO_VXSAT: /* Changes value when vcsr is changed. */
+ case GDB_REGNO_VXRM: /* Changes value when vcsr is changed. */
+ case GDB_REGNO_VCSR: /* Changes when vxrm or vxsat are changed. */
default:
return false;
}
commit 7bb208c309203c70c43e5ad21a806b17894763c1
Author: Anatoly Parshintsev <kup...@gm...>
Date: Thu Jan 29 21:34:27 2026 +0300
target/riscv: do not cache access to vtype
Writes to the vtype register are expected to have the side effect of
resetting vl and vstart. However, the current implementation caches the
vtype state on read, which prevents subsequent writes with
already-cached values from being issued.
Change-Id: I28beea6e2145bca52c5b37023399d6ae0937dfe0
Signed-off-by: Anatoly Parshintsev <kup...@gm...>
Reviewed-on: https://review.openocd.org/c/openocd/+/9416
Tested-by: jenkins
Reviewed-by: Tomas Vanek <va...@fb...>
diff --git a/src/target/riscv/riscv_reg_impl.h b/src/target/riscv/riscv_reg_impl.h
index 2948ef401..f45af047d 100644
--- a/src/target/riscv/riscv_reg_impl.h
+++ b/src/target/riscv/riscv_reg_impl.h
@@ -198,7 +198,6 @@ static inline bool riscv_reg_impl_gdb_regno_cacheable(enum gdb_regno regno,
case GDB_REGNO_VXSAT:
case GDB_REGNO_VXRM:
case GDB_REGNO_VLENB:
- case GDB_REGNO_VTYPE:
case GDB_REGNO_MISA:
case GDB_REGNO_DCSR:
case GDB_REGNO_MEPC:
@@ -216,6 +215,7 @@ static inline bool riscv_reg_impl_gdb_regno_cacheable(enum gdb_regno regno,
case GDB_REGNO_DSCRATCH1:
case GDB_REGNO_VSTART: /* Changes value when vtype is changed. */
case GDB_REGNO_VL: /* Changes value when vtype is changed. */
+ case GDB_REGNO_VTYPE: /* Writes to vtype have side effects, so we don't cache it. */
default:
return false;
}
-----------------------------------------------------------------------
Summary of changes:
src/target/riscv/riscv_reg_impl.h | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
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