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[PATCH]: f040a8ca54 loaders/espressif: add esp32c6 stub flasher application code
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From: <ge...@op...> - 2023-11-30 12:33:53
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This is an automated email from Gerrit. "Erhan Kurubas <erh...@es...>" just uploaded a new patch set to Gerrit, which you can find at https://review.openocd.org/c/openocd/+/8030 -- gerrit commit f040a8ca545396382b3b67a4467fa832f129e95e Author: Erhan Kurubas <erh...@es...> Date: Thu Nov 30 13:19:05 2023 +0100 loaders/espressif: add esp32c6 stub flasher application code Special binary program running on the target (ESP32-C6) to perform flash operations and communicate to the OpenOCD host. Camelcase symbols comes from esp-idf Checkpatch-ignore: CAMELCASE Signed-off-by: Erhan Kurubas <erh...@es...> Change-Id: I7db91a58700195006780a8f9c44354836b8b06f7 diff --git a/contrib/loaders/flash/espressif/esp32c6/Makefile b/contrib/loaders/flash/espressif/esp32c6/Makefile new file mode 100644 index 0000000000..77207c9dfc --- /dev/null +++ b/contrib/loaders/flash/espressif/esp32c6/Makefile @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +# Makefile to compile flasher stub program +# Copyright (C) 2022 Espressif Systems Ltd. + +# Prefix for ESP32-C6 cross compilers (can include a directory path) +CROSS ?= riscv32-esp-elf- + +# Path to the esp-idf root dir +IDF_PATH ?= ../.. + +STUB_ARCH := riscv +STUB_CHIP_PATH := $(shell pwd) +STUB_COMMON_PATH := $(STUB_CHIP_PATH)/.. +STUB_CHIP_ARCH_PATH := $(STUB_COMMON_PATH)/$(STUB_ARCH) +STUB_OBJ_DEPS := sdkconfig.h +STUB_LD_SCRIPT := stub.ld +STUB_CHIP := ESP32C6 + +SRCS := $(IDF_PATH)/components/esp_hw_support/port/esp32c6/rtc_clk_init.c \ + $(IDF_PATH)/components/esp_hw_support/port/esp32c6/rtc_clk.c \ + $(IDF_PATH)/components/esp_hw_support/port/esp32c6/rtc_time.c \ + $(IDF_PATH)/components/app_trace/port/$(STUB_ARCH)/port.c + +CFLAGS := -std=gnu17 + +INCLUDES := -I$(IDF_PATH)/components/soc/esp32c6/include -I$(IDF_PATH)/components/riscv/include \ + -I$(IDF_PATH)/components/hal/esp32c6/include \ + -I$(IDF_PATH)/components/esp32c6/include \ + -I$(IDF_PATH)/components/esp_hw_support/port/esp32c6/private_include \ + -I$(IDF_PATH)/components/esp_rom/include/esp32c6 \ + -I$(IDF_PATH)/components/esp_hw_support/port/esp32c6 \ + -I$(IDF_PATH)/components/spi_flash/include \ + -I$(IDF_PATH)/components/esp_rom/esp32c6 + +DEFINES := + +LDFLAGS += -T$(IDF_PATH)/components/esp_rom/esp32c6/ld/esp32c6.rom.ld -T$(IDF_PATH)/components/esp_rom/esp32c6/ld/esp32c6.rom.newlib.ld \ + -T$(IDF_PATH)/components/esp_rom/esp32c6/ld/esp32c6.rom.api.ld + +include ../stub_common.mk diff --git a/contrib/loaders/flash/espressif/esp32c6/sdkconfig.h b/contrib/loaders/flash/espressif/esp32c6/sdkconfig.h new file mode 100644 index 0000000000..dde51528bb --- /dev/null +++ b/contrib/loaders/flash/espressif/esp32c6/sdkconfig.h @@ -0,0 +1,39 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef _STUB_SDKCONFIG_H_ +#define _STUB_SDKCONFIG_H_ + +#define CONFIG_IDF_TARGET_ARCH_RISCV 1 +#define CONFIG_IDF_TARGET_ESP32C6 1 +#define CONFIG_FREERTOS_UNICORE 1 +/* Use ROM flash driver patch + * #define CONFIG_SPI_FLASH_ROM_DRIVER_PATCH 1 + * Disable application module multi-threading lock */ +#define CONFIG_APPTRACE_LOCK_ENABLE 0 +/* Enable apptarce module for flash data transfers */ +#define CONFIG_APPTRACE_DEST_JTAG 1 +#define CONFIG_APPTRACE_MEMBUFS_APPTRACE_PROTO_ENABLE 1 +#define CONFIG_APPTRACE_ENABLE 1 +#define CONFIG_APPTRACE_BUF_SIZE 16384 +#define CONFIG_APPTRACE_PENDING_DATA_SIZE_MAX 0 +/* Debug UART number */ +#define CONFIG_CONSOLE_UART_NUM 0 +/* Debug UART baudrate */ +#define CONFIG_CONSOLE_UART_BAUDRATE 115200 +/* alloc apptrace data buffers on stack */ +#define CONFIG_STUB_STACK_DATA_POOL_SIZE (2 * CONFIG_APPTRACE_BUF_SIZE) + +/* needed due to apptrace sources usage */ +#define CONFIG_LOG_MAXIMUM_LEVEL 0 +/* needed due to various checks in IDF headers */ +#define CONFIG_FREERTOS_MAX_TASK_NAME_LEN 16 +/* TODO: use current clk, get it from PLL settings */ +#define CONFIG_ESP32C6_DEFAULT_CPU_FREQ_MHZ 160 +/* Unused by stub, just for compilation of IDF */ +#define CONFIG_PARTITION_TABLE_OFFSET 0x8000 +#define CONFIG_MMU_PAGE_SIZE 0x10000 /* 64KB */ +#define CONFIG_HAL_DEFAULT_ASSERTION_LEVEL 0 /* no assert in the hal functions */ + +#define CONFIG_FREERTOS_TASK_NOTIFICATION_ARRAY_ENTRIES 1 + +#endif /*_STUB_SDKCONFIG_H_ */ diff --git a/contrib/loaders/flash/espressif/esp32c6/stub.ld b/contrib/loaders/flash/espressif/esp32c6/stub.ld new file mode 100644 index 0000000000..d92cfb5d69 --- /dev/null +++ b/contrib/loaders/flash/espressif/esp32c6/stub.ld @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * LD script for ESP32-C6 flasher stub * + * Copyright (C) 2022 Espressif Systems Ltd. * + * Author: Alexey Gerenkov <al...@es...> * + * * + ***************************************************************************/ + +MEMORY { + /* Place sections by starting from the HPSRAM. ESP32-C6 has unified i/d bus + 0x40800000 - code (OpenOCD workarea address) + 0x40804000 - data + */ + iram : org = 0x40800000, len = 0x4000 + dram : org = 0x40804000, len = 0x20000 +} + +INCLUDE stub_common.ld diff --git a/contrib/loaders/flash/espressif/esp32c6/stub_flasher_chip.c b/contrib/loaders/flash/espressif/esp32c6/stub_flasher_chip.c new file mode 100644 index 0000000000..a6c0bb7e5b --- /dev/null +++ b/contrib/loaders/flash/espressif/esp32c6/stub_flasher_chip.c @@ -0,0 +1,541 @@ +// SPDX-License-Identifier: GPL-2.0-or-later + +/*************************************************************************** + * ESP32-C6 specific flasher stub functions * + * Copyright (C) 2022 Espressif Systems Ltd. * + ***************************************************************************/ +#include <string.h> +#include "sdkconfig.h" +#include "soc/rtc.h" +#include "soc/efuse_periph.h" +#include "soc/spi_mem_reg.h" +#include "soc/extmem_reg.h" +#include "soc/gpio_reg.h" +#include "soc/system_reg.h" +#include "hal/mmu_ll.h" +#include "soc/pcr_reg.h" +#include "esp_app_trace_membufs_proto.h" +#include "esp_rom_efuse.h" +#include "stub_rom_chip.h" +#include "stub_logger.h" +#include "stub_flasher_int.h" +#include "stub_flasher_chip.h" +#include "stub_flasher.h" + +/* RTC related definitios */ +#define PCR_SOC_CLK_MAX 1 // CPU_CLK frequency is 160 MHz (source is PLL_CLK) + +/* Cache MMU related definitions */ +#define STUB_CACHE_CTRL_REG EXTMEM_L1_CACHE_CTRL_REG +#define STUB_CACHE_BUS (EXTMEM_L1_CACHE_SHUT_DBUS | EXTMEM_L1_CACHE_SHUT_IBUS) +#define STUB_MMU_DROM_PAGES_END MMU_ENTRY_NUM +#define STUB_MMU_DROM_PAGES_START (STUB_MMU_DROM_PAGES_END - 8) /* 8 pages will be more than enough */ + +#define ESP_APPTRACE_RISCV_BLOCK_LEN_MSK 0x7FFFUL +#define ESP_APPTRACE_RISCV_BLOCK_LEN(_l_) ((_l_) & ESP_APPTRACE_RISCV_BLOCK_LEN_MSK) +#define ESP_APPTRACE_RISCV_BLOCK_LEN_GET(_v_) ((_v_) & ESP_APPTRACE_RISCV_BLOCK_LEN_MSK) +#define ESP_APPTRACE_RISCV_BLOCK_ID_MSK 0x7FUL +#define ESP_APPTRACE_RISCV_BLOCK_ID(_id_) (((_id_) & ESP_APPTRACE_RISCV_BLOCK_ID_MSK) << 15) +#define ESP_APPTRACE_RISCV_BLOCK_ID_GET(_v_) (((_v_) >> 15) & ESP_APPTRACE_RISCV_BLOCK_ID_MSK) +#define ESP_APPTRACE_RISCV_HOST_DATA (BIT(22)) +#define ESP_APPTRACE_RISCV_HOST_CONNECT (BIT(23)) + +/** RISCV memory host iface control block */ +typedef struct { + uint32_t ctrl; + /* - Guard field. If this register is not zero then CPU is changing this struct and */ + /* this guard field holds address of the instruction which application will execute when + * CPU finishes with those modifications. */ + uint32_t stat; + esp_apptrace_mem_block_t *mem_blocks; +} esp_apptrace_riscv_ctrl_block_t; + +static esp_apptrace_riscv_ctrl_block_t *s_apptrace_ctrl; +#if CONFIG_STUB_STACK_DATA_POOL_SIZE > 0 +static uint8_t *s_stack_data_pool; +static size_t s_stack_data_pool_sz; +#endif + +/* SPI Flash map request data */ +struct spiflash_map_req { + /* Request mapping SPI Flash base address */ + uint32_t src_addr; + /* Request mapping SPI Flash size */ + uint32_t size; + /* Mapped memory pointer */ + void *ptr; + /* Mapped started MMU page index */ + uint32_t start_page; + /* Mapped MMU page count */ + uint32_t page_cnt; + /* Virtual addr */ + uint32_t vaddr_start; +}; + +typedef struct { + mmu_page_size_t page_size; + uint32_t vaddr0_start_addr; + uint32_t drom_page_start; + uint32_t drom_page_end; + int shift_count; +} cache_mmu_config_t; + +static cache_mmu_config_t s_cache_mmu_config; + +extern void spi_flash_attach(uint32_t ishspi, bool legacy); + +uint32_t g_stub_cpu_freq_hz = CONFIG_ESP32C6_DEFAULT_CPU_FREQ_MHZ * MHZ; + +void vPortEnterCritical(void) +{ +} + +void vPortExitCritical(void) +{ +} + +int xPortInIsrContext(void) +{ + return 0; +} + +void *esp_apptrace_uart_hw_get(int num, void **data) +{ + return NULL; +} + +#if STUB_LOG_ENABLE == 1 +void stub_print_cache_mmu_registers(void) +{ +} +#endif + +static inline uint32_t __attribute__((always_inline)) stub_mmu_hal_pages_to_bytes(uint32_t page_num) +{ + return page_num << s_cache_mmu_config.shift_count; +} + +static inline uint32_t __attribute__((always_inline)) stub_mmu_ll_format_paddr(uint32_t paddr) +{ + return paddr >> s_cache_mmu_config.shift_count; +} + +#define STUB_MMU_VADDR_MASK (s_cache_mmu_config.page_size * MMU_MAX_PADDR_PAGE_NUM - 1) +static inline uint32_t __attribute__((always_inline)) stub_mmu_ll_get_entry_id(uint32_t vaddr) +{ + return (vaddr & STUB_MMU_VADDR_MASK) >> s_cache_mmu_config.shift_count; +} + +static inline void __attribute__((always_inline)) stub_mmu_ll_write_entry(uint32_t entry_id, uint32_t mmu_val) +{ + uint32_t mmu_raw_value; + + if (stub_get_flash_encryption_mode() != ESP_FLASH_ENC_MODE_DISABLED) + mmu_val |= MMU_SENSITIVE; + + mmu_raw_value = mmu_val | MMU_VALID; + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), mmu_raw_value); +} + +static inline void __attribute__((always_inline)) stub_mmu_ll_set_entry_invalid(uint32_t entry_id) +{ + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + REG_WRITE(SPI_MEM_MMU_ITEM_CONTENT_REG(0), MMU_INVALID); +} + +static inline int __attribute__((always_inline)) stub_mmu_ll_read_entry(uint32_t entry_id) +{ + uint32_t mmu_raw_value; + REG_WRITE(SPI_MEM_MMU_ITEM_INDEX_REG(0), entry_id); + mmu_raw_value = REG_READ(SPI_MEM_MMU_ITEM_CONTENT_REG(0)); + + if (stub_get_flash_encryption_mode() != ESP_FLASH_ENC_MODE_DISABLED) + mmu_raw_value &= ~MMU_SENSITIVE; + + return mmu_raw_value; +} + +uint32_t stub_flash_get_id(void) +{ + uint32_t ret; + + STUB_LOGD("flash %x, cs %x, bs %x, ss %x, ps %x, sm %x\n", + rom_spiflash_legacy_data->chip.device_id, + rom_spiflash_legacy_data->chip.chip_size, + rom_spiflash_legacy_data->chip.block_size, + rom_spiflash_legacy_data->chip.sector_size, + rom_spiflash_legacy_data->chip.page_size, + rom_spiflash_legacy_data->chip.status_mask); + WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0, 0); /* clear register */ + WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_MEM_FLASH_RDID); + while (READ_PERI_REG(PERIPHS_SPI_FLASH_CMD) != 0) + ; + ret = READ_PERI_REG(PERIPHS_SPI_FLASH_C0) & 0xffffff; + STUB_LOGD("Flash ID read %x\n", ret); + return ret >> 16; +} + +void stub_flash_cache_flush(void) +{ + /* we do not know breakpoint program address here, so invalidate the + * whole ICache */ + Cache_Invalidate_ICache_All(); +} + +void stub_cache_configure(void) +{ + s_cache_mmu_config.page_size = mmu_ll_get_page_size(0); + s_cache_mmu_config.drom_page_start = STUB_MMU_DROM_PAGES_START; + s_cache_mmu_config.drom_page_end = STUB_MMU_DROM_PAGES_END; /* 256 */ + + switch (s_cache_mmu_config.page_size) { + case MMU_PAGE_64KB: + s_cache_mmu_config.shift_count = 16; + break; + case MMU_PAGE_32KB: + s_cache_mmu_config.shift_count = 15; + break; + case MMU_PAGE_16KB: + s_cache_mmu_config.shift_count = 14; + break; + case MMU_PAGE_8KB: + s_cache_mmu_config.shift_count = 13; + break; + default: + STUB_LOGE("Unknown page size!"); + return; + } + + s_cache_mmu_config.vaddr0_start_addr = SOC_DROM_LOW + + (s_cache_mmu_config.drom_page_start * s_cache_mmu_config.page_size); + + STUB_LOGI("MMU page size:%X drom_page_start:%d drom_page_end:%d vaddr0_start_addr:%X\n", + s_cache_mmu_config.page_size, + s_cache_mmu_config.drom_page_start, + s_cache_mmu_config.drom_page_end, + s_cache_mmu_config.vaddr0_start_addr); +} + +void stub_cache_init(void) +{ + STUB_LOGD("%s\n", __func__); + + SET_PERI_REG_MASK(PCR_CACHE_CONF_REG, PCR_CACHE_CLK_EN_M); + SET_PERI_REG_MASK(PCR_CACHE_CONF_REG, PCR_CACHE_RST_EN_M); + CLEAR_PERI_REG_MASK(PCR_CACHE_CONF_REG, PCR_CACHE_RST_EN_M); + + REG_CLR_BIT(STUB_CACHE_CTRL_REG, STUB_CACHE_BUS); + mmu_ll_set_page_size(0, CONFIG_MMU_PAGE_SIZE); + Cache_MMU_Init(); + Cache_Enable_ICache(0); +} + +static bool stub_is_cache_enabled(void) +{ + int cache_ctrl_reg = REG_READ(STUB_CACHE_CTRL_REG); + STUB_LOGD("cache_ctrl_reg:%X MMU_VALID:%x\n", cache_ctrl_reg, MMU_VALID); + + /* if any of the entry is valid and busses are enabled we can consider that cache is enabled */ + for (int i = 0; i < MMU_ENTRY_NUM; ++i) { + uint32_t mmu_raw_value = stub_mmu_ll_read_entry(i); + if ((mmu_raw_value & MMU_VALID) == MMU_VALID) + return !(cache_ctrl_reg & STUB_CACHE_BUS); + } + return false; +} + +void stub_flash_state_prepare(struct stub_flash_state *state) +{ + const uint32_t spiconfig = 0; /* esp_rom_efuse_get_flash_gpio_info(); */ + + state->cache_enabled = stub_is_cache_enabled(); + if (!state->cache_enabled) { + STUB_LOGI("Cache needs to be enabled\n"); + stub_cache_init(); + } + spi_flash_attach(spiconfig, false); + stub_cache_configure(); +} + +void stub_flash_state_restore(struct stub_flash_state *state) +{ + /* we do not disable or store the cache settings. So, nothing to restore*/ +} + +int stub_cpu_clock_configure(int conf_reg_val) +{ + uint32_t pcr_sysclk_conf_reg = 0; + + /* set to maximum possible value */ + if (conf_reg_val == -1) { + pcr_sysclk_conf_reg = REG_READ(PCR_SYSCLK_CONF_REG); + REG_WRITE(PCR_SYSCLK_CONF_REG, + (pcr_sysclk_conf_reg & ~PCR_SOC_CLK_SEL_M) | (PCR_SOC_CLK_MAX << PCR_SOC_CLK_SEL_S)); + } else { // restore old value + pcr_sysclk_conf_reg = conf_reg_val; + REG_WRITE(PCR_SYSCLK_CONF_REG, + (REG_READ(PCR_SYSCLK_CONF_REG) & ~PCR_SOC_CLK_SEL_M) | (pcr_sysclk_conf_reg & PCR_SOC_CLK_SEL_M)); + } + + STUB_LOGD("pcr_sysclk_conf_reg %x\n", pcr_sysclk_conf_reg); + + return pcr_sysclk_conf_reg; +} + +#if STUB_LOG_ENABLE == 1 +extern uint32_t ets_clk_get_xtal_freq(void); +void stub_uart_console_configure(int dest) +{ + /* set the default parameter to UART module, but don't enable RX interrupt */ + uartAttach(NULL); + /* first enable uart0 as printf channel */ + uint32_t clock = ets_clk_get_xtal_freq(); + ets_update_cpu_frequency(clock / 1000000); + + Uart_Init(0, APB_CLK_FREQ_ROM); + /* install to print later + * Non-Flash Boot can print + * Flash Boot can print when RTC_CNTL_STORE4_REG bit0 is 0 (can be 1 after deep sleep, software reset) + * and printf boot. + * print boot determined by GPIO and efuse, see ets_is_print_boot + */ + ets_install_uart_printf(); +} +#endif + +uint32_t stub_esp_clk_cpu_freq(void) +{ + return CONFIG_ESP32C6_DEFAULT_CPU_FREQ_MHZ * 1000000; +} + +/* override apptrace control block advertising func, IDF's implementation issues syscall */ +int esp_apptrace_advertise_ctrl_block(void *ctrl_block_addr) +{ + s_apptrace_ctrl = ctrl_block_addr; + return 0; +} + +#if CONFIG_STUB_STACK_DATA_POOL_SIZE > 0 +void stub_stack_data_pool_init(uint8_t *data, size_t sz) +{ + STUB_LOGD("stack data pool %lu bytes @ 0x%x\n", sz, data); + s_stack_data_pool = data; + s_stack_data_pool_sz = sz; +} + +void esp_apptrace_get_up_buffers(esp_apptrace_mem_block_t mem_blocks_cfg[2]) +{ + /* use whole stack data pool for apptrace up buffers */ + mem_blocks_cfg[0].start = s_stack_data_pool; + mem_blocks_cfg[0].sz = s_stack_data_pool_sz / 2; + mem_blocks_cfg[1].start = s_stack_data_pool + mem_blocks_cfg[0].sz; + mem_blocks_cfg[1].sz = mem_blocks_cfg[0].sz; +} +#endif + +int stub_apptrace_prepare(void) +{ + /* imply that host is auto-connected */ + s_apptrace_ctrl->ctrl |= ESP_APPTRACE_RISCV_HOST_CONNECT; + return ESP_STUB_ERR_OK; +} + +int64_t esp_timer_get_time(void) +{ + /* + This function is used by apptrace code to implement timeouts. + unfortunately esp32c6 does not support CPU cycle counter, so we have two options: + 1) Use some HW timer. It can be hard, because we need to ensure that it is initialized and + possibly restore its state. + 2) Emulate timer by incrementing some var on every call. + Stub flasher uses ESP_APPTRACE_TMO_INFINITE only, so this function won't be called by apptrace at all. + */ + return 0; +} + +uint64_t stub_get_time(void) +{ + /* this function is used for perf measurements only. + unfortunately esp32c6 does not support CPU cycle counter and usage of HW timer is problematic */ + return 0; +} + +esp_rom_spiflash_result_t esp_rom_spiflash_erase_area(uint32_t start_addr, uint32_t area_len) +{ + int32_t total_sector_num; + int32_t head_sector_num; + uint32_t sector_no; + uint32_t sector_num_per_block; + + /* set read mode to Fastmode ,not QDIO mode for erase + * + * TODO: this is probably a bug as it doesn't re-enable QIO mode, not serious as this + * function is not used in IDF. + * esp_rom_spiflash_config_readmode(ESP_ROM_SPIFLASH_SLOWRD_MODE); */ + + /* check if area is oversize of flash */ + if ((start_addr + area_len) > rom_spiflash_legacy_data->chip.chip_size) + return ESP_ROM_SPIFLASH_RESULT_ERR; + + /* start_addr is aligned as sector boundary */ + if (0 != (start_addr % rom_spiflash_legacy_data->chip.sector_size)) + return ESP_ROM_SPIFLASH_RESULT_ERR; + + /* Unlock flash to enable erase */ + if (esp_rom_spiflash_unlock(/*&rom_spiflash_legacy_data->chip*/) != ESP_ROM_SPIFLASH_RESULT_OK) + return ESP_ROM_SPIFLASH_RESULT_ERR; + + sector_no = start_addr / rom_spiflash_legacy_data->chip.sector_size; + sector_num_per_block = rom_spiflash_legacy_data->chip.block_size / rom_spiflash_legacy_data->chip.sector_size; + total_sector_num = (0 == (area_len % rom_spiflash_legacy_data->chip.sector_size)) ? + area_len / rom_spiflash_legacy_data->chip.sector_size : + 1 + (area_len / rom_spiflash_legacy_data->chip.sector_size); + + /* check if erase area reach over block boundary */ + head_sector_num = sector_num_per_block - (sector_no % sector_num_per_block); + + head_sector_num = (head_sector_num >= total_sector_num) ? total_sector_num : head_sector_num; + + /* JJJ, BUG of 6.0 erase + * middle part of area is aligned by blocks */ + total_sector_num -= head_sector_num; + + /* head part of area is erased */ + while (head_sector_num > 0) { + if (esp_rom_spiflash_erase_sector(sector_no) != ESP_ROM_SPIFLASH_RESULT_OK) + return ESP_ROM_SPIFLASH_RESULT_ERR; + sector_no++; + head_sector_num--; + } + while (total_sector_num > sector_num_per_block) { + if (ESP_ROM_SPIFLASH_RESULT_OK != + esp_rom_spiflash_erase_block(sector_no / sector_num_per_block)) + return ESP_ROM_SPIFLASH_RESULT_ERR; + sector_no += sector_num_per_block; + total_sector_num -= sector_num_per_block; + } + + /* tail part of area burn */ + while (total_sector_num > 0) { + if (esp_rom_spiflash_erase_sector(sector_no) != ESP_ROM_SPIFLASH_RESULT_OK) + return ESP_ROM_SPIFLASH_RESULT_ERR; + sector_no++; + total_sector_num--; + } + + return ESP_ROM_SPIFLASH_RESULT_OK; +} + +static inline bool esp_flash_encryption_enabled(void) +{ + uint32_t flash_crypt_cnt = REG_GET_FIELD(EFUSE_RD_REPEAT_DATA1_REG, EFUSE_SPI_BOOT_CRYPT_CNT); + + /* __builtin_parity is in flash, so we calculate parity inline */ + bool enabled = false; + while (flash_crypt_cnt) { + if (flash_crypt_cnt & 1) + enabled = !enabled; + flash_crypt_cnt >>= 1; + } + return enabled; +} + +esp_flash_enc_mode_t stub_get_flash_encryption_mode(void) +{ + static esp_flash_enc_mode_t s_mode = ESP_FLASH_ENC_MODE_DEVELOPMENT; + static bool s_first = true; + + if (s_first) { + if (!esp_flash_encryption_enabled()) + s_mode = ESP_FLASH_ENC_MODE_DISABLED; + s_first = false; + STUB_LOGD("flash_encryption_mode: %d\n", s_mode); + } + return s_mode; +} + +static void stub_mmu_hal_map_region(uint32_t vaddr, uint32_t paddr, uint32_t len) +{ + uint32_t page_size_in_bytes = stub_mmu_hal_pages_to_bytes(1); + uint32_t page_num = (len + page_size_in_bytes - 1) / page_size_in_bytes; + uint32_t entry_id = 0; + uint32_t mmu_val = stub_mmu_ll_format_paddr(paddr); /* This is the physical address in the format that MMU + * supported */ + + while (page_num) { + entry_id = stub_mmu_ll_get_entry_id(vaddr); + stub_mmu_ll_write_entry(entry_id, mmu_val); + Cache_Invalidate_Addr(vaddr, page_size_in_bytes); + STUB_LOGD("mmap page_num:%d entry_id:%d vaddr:%x mmu_val:%x size:%d page_size_in_bytes:%x\n", + page_num, entry_id, vaddr, mmu_val, len, page_size_in_bytes); + vaddr += page_size_in_bytes; + mmu_val++; + page_num--; + } +} + +static void stub_mmu_hal_unmap_region(uint32_t vaddr, uint32_t len) +{ + uint32_t page_size_in_bytes = stub_mmu_hal_pages_to_bytes(1); + uint32_t page_num = (len + page_size_in_bytes - 1) / page_size_in_bytes; + uint32_t entry_id = 0; + + while (page_num) { + entry_id = stub_mmu_ll_get_entry_id(vaddr); + stub_mmu_ll_set_entry_invalid(entry_id); + STUB_LOGD("unmap page_num:%d entry_id:%d vaddr:%x page_size_in_bytes:%x\n", + page_num, entry_id, vaddr, page_size_in_bytes); + vaddr += page_size_in_bytes; + page_num--; + } +} + +static int stub_flash_mmap(struct spiflash_map_req *req) +{ + uint32_t map_src = req->src_addr & (~(s_cache_mmu_config.page_size - 1)); /* start of the page */ + uint32_t map_size = req->src_addr - map_src + req->size; + uint32_t saved_state = Cache_Suspend_ICache(); + + req->vaddr_start = s_cache_mmu_config.vaddr0_start_addr; + req->ptr = (void *)req->vaddr_start + req->src_addr - map_src; + + STUB_LOGD("map_ptr: %x size:%d req->src_addr:%x map_src:%x map_size:%x\n", + req->ptr, req->size, req->src_addr, map_src, map_size); + + stub_mmu_hal_map_region(req->vaddr_start, req->src_addr, map_size); + + REG_CLR_BIT(STUB_CACHE_CTRL_REG, STUB_CACHE_BUS); + + Cache_Resume_ICache(saved_state); + + return 0; +} + +static void stub_flash_ummap(const struct spiflash_map_req *req) +{ + uint32_t map_src = req->src_addr & (~(s_cache_mmu_config.page_size - 1)); /* start of the page */ + uint32_t map_size = req->src_addr - map_src + req->size; + uint32_t saved_state = Cache_Suspend_ICache(); + stub_mmu_hal_unmap_region(req->vaddr_start, map_size); + Cache_Resume_ICache(saved_state); +} + +int stub_flash_read_buff(uint32_t addr, void *buffer, uint32_t size) +{ + struct spiflash_map_req req = { + .src_addr = addr, + .size = size, + }; + + int ret = stub_flash_mmap(&req); + + if (ret) + return ret; + + memcpy(buffer, req.ptr, size); + + stub_flash_ummap(&req); + + return ESP_ROM_SPIFLASH_RESULT_OK; +} diff --git a/contrib/loaders/flash/espressif/esp32c6/stub_flasher_chip.h b/contrib/loaders/flash/espressif/esp32c6/stub_flasher_chip.h new file mode 100644 index 0000000000..2a26806a96 --- /dev/null +++ b/contrib/loaders/flash/espressif/esp32c6/stub_flasher_chip.h @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/*************************************************************************** + * ESP32-C6 flasher stub definitions * + * Copyright (C) 2022 Espressif Systems Ltd. * + ***************************************************************************/ +#ifndef ESP32C6_FLASHER_STUB_H +#define ESP32C6_FLASHER_STUB_H + +#include "sdkconfig.h" + +#ifndef SOC_MMU_PAGE_SIZE +#define SOC_MMU_PAGE_SIZE CONFIG_MMU_PAGE_SIZE +#endif + +#define STUB_FLASH_SECTOR_SIZE 0x1000 +/* Flash geometry constants */ +#define STUB_FLASH_BLOCK_SIZE 0x10000 +#define STUB_FLASH_PAGE_SIZE 0x100 +#define STUB_FLASH_STATUS_MASK 0xFFFF + +struct stub_flash_state { + uint32_t cache_flags[2]; + bool cache_enabled; +}; + +#define ESP_APPTRACE_USR_DATA_LEN_MAX (CONFIG_APPTRACE_BUF_SIZE - 2) +#define RISCV_EBREAK 0x9002 + +extern bool ets_efuse_flash_octal_mode(void); + +uint32_t stub_esp_clk_cpu_freq(void); + +static inline uint8_t stub_get_insn_size(uint8_t *insn) +{ + /* we use 16bit `c.ebreak`. it works perfectly with either 32bit and 16bit code */ + return 2; +} + +static inline uint32_t stub_get_break_insn(uint8_t insn_sz) +{ + return RISCV_EBREAK; +} + +void stub_stack_data_pool_init(uint8_t *data, size_t sz); + +#endif /*ESP32C6_FLASHER_STUB_H */ diff --git a/contrib/loaders/flash/espressif/esp32c6/stub_flasher_code.inc b/contrib/loaders/flash/espressif/esp32c6/stub_flasher_code.inc new file mode 100644 index 0000000000..e7ca350f1b --- /dev/null +++ b/contrib/loaders/flash/espressif/esp32c6/stub_flasher_code.inc @@ -0,0 +1,328 @@ +/* Autogenerated with ../../../../../src/helper/bin2char.sh */ +0x83,0x47,0x05,0x00,0x85,0x8b,0x99,0xc7,0x83,0xd7,0xc5,0xff,0x01,0x45,0x23,0x9f, +0xf5,0xfe,0x82,0x80,0x13,0x05,0x30,0x10,0x82,0x80,0x83,0x47,0x05,0x00,0x85,0x8b, +0x81,0xcb,0x50,0xd5,0x10,0xd5,0x23,0x28,0x05,0x02,0x4c,0xd1,0x23,0x2a,0x05,0x02, +0x82,0x80,0x83,0x47,0x05,0x00,0x85,0x8b,0x81,0xe7,0x13,0x05,0x30,0x10,0x82,0x80, +0x01,0x45,0x82,0x80,0x83,0x47,0x05,0x00,0x85,0x8b,0x81,0xcb,0xb7,0x47,0x80,0x40, +0x03,0xa5,0x47,0x14,0x5d,0x81,0x05,0x89,0x82,0x80,0x01,0x45,0x82,0x80,0xb7,0x47, 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-0,0 +1,543 @@ +/* Autogenerated with ../../../../../src/helper/bin2char.sh */ +0x83,0x47,0x05,0x00,0x85,0x8b,0x99,0xc7,0x83,0xd7,0xc5,0xff,0x01,0x45,0x23,0x9f, +0xf5,0xfe,0x82,0x80,0x13,0x05,0x30,0x10,0x82,0x80,0x83,0x47,0x05,0x00,0x85,0x8b, +0x81,0xcb,0x50,0xd5,0x10,0xd5,0x23,0x28,0x05,0x02,0x4c,0xd1,0x23,0x2a,0x05,0x02, +0x82,0x80,0x83,0x47,0x05,0x00,0x85,0x8b,0x81,0xe7,0x13,0x05,0x30,0x10,0x82,0x80, +0x01,0x45,0x82,0x80,0x83,0x47,0x05,0x00,0x85,0x8b,0x81,0xcb,0xb7,0x57,0x80,0x40, +0x03,0xa5,0x07,0x14,0x5d,0x81,0x05,0x89,0x82,0x80,0x01,0x45,0x82,0x80,0xb7,0x57, +0x80,0x40,0x23,0xa2,0x07,0x14,0x82,0x80,0xb7,0x57,0x80,0x40,0x37,0x07,0x80,0x40, +0x93,0x87,0x07,0x14,0x13,0x07,0x67,0x06,0xd8,0xc3,0x98,0x43,0xb7,0x07,0x80,0x00, +0xf9,0x8f,0x9d,0xc3,0x93,0x57,0xf7,0x00,0xa9,0x8f,0x46,0x07,0x93,0xf7,0xf7,0x07, +0x45,0x83,0xd9,0x8f,0x01,0x45,0x99,0xcb,0x41,0x11,0x06,0xc6,0xc9,0x37,0xb2,0x40, +0x13,0x05,0x10,0x10,0x41,0x01,0x82,0x80,0x01,0x45,0x82,0x80,0x82,0x80,0x37,0x57, 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