[OpenOCD-devel] [PATCH]: cf2de3a arm_adi_v5: Split CSW bits into AHB/APB/AXI

[<ge...@op...>]

This is an automated email from Gerrit.

Leonard Crestez (leo...@nx...) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5124

-- gerrit

commit cf2de3a55b0db8236d1639bce466c50c125d4322
Author: Leonard Crestez <leo...@nx...>
Date:   Tue Apr 16 22:12:18 2019 +0300

    arm_adi_v5: Split CSW bits into AHB/APB/AXI
    
    The implementation-defined bits have different semantics for each bus
    and different recommended defaults.
    
    Change-Id: I562fe24643bb1f3abc696339e382a75ccf2f2873
    Signed-off-by: Leonard Crestez <leo...@nx...>

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 9a641fc..6c25bcc 100644
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1745,7 +1745,7 @@ COMMAND_HANDLER(dap_apcsw_command)
 		return ERROR_OK;
 	case 1:
 		if (strcmp(CMD_ARGV[0], "default") == 0)
-			csw_val = CSW_DEFAULT;
+			csw_val = CSW_AHB_DEFAULT;
 		else
 			COMMAND_PARSE_NUMBER(u32, CMD_ARGV[0], csw_val);
 
diff --git a/src/target/arm_adi_v5.h b/src/target/arm_adi_v5.h
index 96291a7..9ca2966 100644
--- a/src/target/arm_adi_v5.h
+++ b/src/target/arm_adi_v5.h
@@ -112,15 +112,34 @@
 #define CSW_ADDRINC_PACKED  (2UL << 4)
 #define CSW_DEVICE_EN       (1UL << 6)
 #define CSW_TRIN_PROG       (1UL << 7)
-/* all fields in bits 12 and above are implementation-defined! */
+
+/* All fields in bits 12 and above are implementation-defined
+ * Defaults for AHB/AXI in "Standard Memory Access Port Definitions" from ADI
+ * Some bits are shared between buses
+ */
 #define CSW_SPIDEN          (1UL << 23)
-#define CSW_HPROT1          (1UL << 25) /* AHB: Privileged */
-#define CSW_MASTER_DEBUG    (1UL << 29) /* AHB: set HMASTER signals to AHB-AP ID */
-#define CSW_SPROT           (1UL << 30)
 #define CSW_DBGSWENABLE     (1UL << 31)
 
-/* initial value of csw_default used for MEM-AP transfers */
-#define CSW_DEFAULT			(CSW_HPROT1 | CSW_MASTER_DEBUG | CSW_DBGSWENABLE)
+/* AHB: Privileged */
+#define CSW_AHB_HPROT1          (1UL << 25)
+/* AHB: set HMASTER signals to AHB-AP ID */
+#define CSW_AHB_MASTER_DEBUG    (1UL << 29)
+/* AHB5: non-secure access via HNONSEC
+ * AHB3: SBO, UNPREDICTABLE if zero */
+#define CSW_AHB_SPROT           (1UL << 30)
+/* AHB: initial value of csw_default */
+#define CSW_AHB_DEFAULT         (CSW_AHB_HPROT1 | CSW_AHB_MASTER_DEBUG | CSW_DBGSWENABLE)
+
+/* AXI: Privileged */
+#define CSW_AXI_ARPROT0_PRIV    (1UL << 28)
+/* AXI: Non-secure */
+#define CSW_AXI_ARPROT1_NONSEC  (1UL << 29)
+/* AXI: initial value of csw_default */
+#define CSW_AXI_DEFAULT         (CSW_AXI_ARPROT0_PRIV | CSW_AXI_ARPROT1_NONSEC | CSW_DBGSWENABLE)
+
+/* APB: initial value of csw_default */
+#define CSW_APB_DEFAULT         (CSW_DBGSWENABLE)
+
 
 /* Fields of the MEM-AP's IDR register */
 #define IDR_REV     (0xFUL << 28)
diff --git a/src/target/arm_dap.c b/src/target/arm_dap.c
index dd7ec9b..17a8208 100644
--- a/src/target/arm_dap.c
+++ b/src/target/arm_dap.c
@@ -56,7 +56,7 @@ static void dap_instance_init(struct adiv5_dap *dap)
 		/* Number of bits for tar autoincrement, impl. dep. at least 10 */
 		dap->ap[i].tar_autoincr_block = (1<<10);
 		/* default CSW value */
-		dap->ap[i].csw_default = CSW_DEFAULT;
+		dap->ap[i].csw_default = CSW_AHB_DEFAULT;
 	}
 	INIT_LIST_HEAD(&dap->cmd_journal);
 }

--