[OpenOCD-devel] [PATCH]: 561a057 target/cortex_a: check dscr before timeout

[<ge...@op...>]

This is an automated email from Gerrit.

Antonio Borneo (bor...@gm...) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5112

-- gerrit

commit 561a057276d3086978e4fe7f7d1a27379564a2a3
Author: Antonio Borneo <bor...@gm...>
Date:   Mon Apr 15 22:32:32 2019 +0200

    target/cortex_a: check dscr before timeout
    
    In function cortex_a_wait_dscr_bits() the last read on dscr gets
    ignored in case of timeout, even if it finally provides the value
    that would trigger a successful return.
    
    Check the returned value before testing the timeout.
    Also, print a message on failure reading dscr.
    
    Change-Id: I261ac1545113db39374833a55be911a4da71d893
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c
index b68b030..d881c74 100644
--- a/src/target/cortex_a.c
+++ b/src/target/cortex_a.c
@@ -1767,14 +1767,22 @@ static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask,
 {
 	/* Waits until the specified bit(s) of DSCR take on a specified value. */
 	struct armv7a_common *armv7a = target_to_armv7a(target);
-	int64_t then = timeval_ms();
+	int64_t then;
 	int retval;
 
-	while ((*dscr & mask) != value) {
+	if ((*dscr & mask) == value)
+		return ERROR_OK;
+
+	then = timeval_ms();
+	while (1) {
 		retval = mem_ap_read_atomic_u32(armv7a->debug_ap,
 				armv7a->debug_base + CPUDBG_DSCR, dscr);
-		if (retval != ERROR_OK)
+		if (retval != ERROR_OK) {
+			LOG_ERROR("Could not read DSCR register");
 			return retval;
+		}
+		if ((*dscr & mask) == value)
+			break;
 		if (timeval_ms() > then + 1000) {
 			LOG_ERROR("timeout waiting for DSCR bit change");
 			return ERROR_FAIL;

--