[OpenOCD-devel] [PATCH]: b2b2baf target/armv4_5_cache: change prototype of armv4_5_handle_cache_info_command()

[<ge...@op...>]

This is an automated email from Gerrit.

Antonio Borneo (bor...@gm...) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/5068

-- gerrit

commit b2b2baf4218e61de5668cb30bf223f25ba2f9c91
Author: Paul Fertser <fer...@gm...>
Date:   Mon Apr 1 04:42:23 2019 +0200

    target/armv4_5_cache: change prototype of armv4_5_handle_cache_info_command()
    
    To prepare for handling TCL return values consistently, all calls
    to command_print/command_print_sameline should be ready to switch
    to CMD as first parameter.
    
    Change prototype of armv4_5_handle_cache_info_command() to pass
    CMD instead of CMD_CTX.
    
    This change was part of http://openocd.zylin.com/1815 from Paul
    Fertser and has been extracted and rebased to simplify the review.
    
    Change-Id: Ib6ab3ec2fc6504c2a0635b654697a4b6e12a3750
    Signed-off-by: Paul Fertser <fer...@gm...>
    Signed-off-by: Tomas Vanek <va...@fb...>
    Signed-off-by: Antonio Borneo <bor...@gm...>

diff --git a/src/target/arm920t.c b/src/target/arm920t.c
index 7052a72..88a0395 100644
--- a/src/target/arm920t.c
+++ b/src/target/arm920t.c
@@ -1585,7 +1585,7 @@ COMMAND_HANDLER(arm920t_handle_cache_info_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	return armv4_5_handle_cache_info_command(CMD_CTX,
+	return armv4_5_handle_cache_info_command(CMD,
 		&arm920t->armv4_5_mmu.armv4_5_cache);
 }
 
diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 429db44..01ce176 100644
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -733,7 +733,7 @@ COMMAND_HANDLER(arm926ejs_handle_cache_info_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	return armv4_5_handle_cache_info_command(CMD_CTX, &arm926ejs->armv4_5_mmu.armv4_5_cache);
+	return armv4_5_handle_cache_info_command(CMD, &arm926ejs->armv4_5_mmu.armv4_5_cache);
 }
 
 static int arm926ejs_virt2phys(struct target *target, target_addr_t virtual, target_addr_t *physical)
diff --git a/src/target/armv4_5_cache.c b/src/target/armv4_5_cache.c
index bd0091d..6a16925 100644
--- a/src/target/armv4_5_cache.c
+++ b/src/target/armv4_5_cache.c
@@ -76,23 +76,23 @@ int armv4_5_identify_cache(uint32_t cache_type_reg, struct armv4_5_cache_common
 	return ERROR_OK;
 }
 
-int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx, struct armv4_5_cache_common *armv4_5_cache)
+int armv4_5_handle_cache_info_command(struct command_invocation *cmd, struct armv4_5_cache_common *armv4_5_cache)
 {
 	if (armv4_5_cache->ctype == -1) {
-		command_print(cmd_ctx, "cache not yet identified");
+		command_print(cmd->ctx, "cache not yet identified");
 		return ERROR_OK;
 	}
 
-	command_print(cmd_ctx, "cache type: 0x%1.1x, %s", armv4_5_cache->ctype,
+	command_print(cmd->ctx, "cache type: 0x%1.1x, %s", armv4_5_cache->ctype,
 		(armv4_5_cache->separate) ? "separate caches" : "unified cache");
 
-	command_print(cmd_ctx, "D-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
+	command_print(cmd->ctx, "D-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
 		armv4_5_cache->d_u_size.linelen,
 		armv4_5_cache->d_u_size.associativity,
 		armv4_5_cache->d_u_size.nsets,
 		armv4_5_cache->d_u_size.cachesize);
 
-	command_print(cmd_ctx, "I-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
+	command_print(cmd->ctx, "I-Cache: linelen %i, associativity %i, nsets %i, cachesize 0x%x",
 		armv4_5_cache->i_size.linelen,
 		armv4_5_cache->i_size.associativity,
 		armv4_5_cache->i_size.nsets,
diff --git a/src/target/armv4_5_cache.h b/src/target/armv4_5_cache.h
index 2fd1ca3..768938f 100644
--- a/src/target/armv4_5_cache.h
+++ b/src/target/armv4_5_cache.h
@@ -19,7 +19,7 @@
 #ifndef OPENOCD_TARGET_ARMV4_5_CACHE_H
 #define OPENOCD_TARGET_ARMV4_5_CACHE_H
 
-struct command_context;
+struct command_invocation;
 
 struct armv4_5_cachesize {
 	int linelen;
@@ -42,7 +42,7 @@ int armv4_5_identify_cache(uint32_t cache_type_reg,
 int armv4_5_cache_state(uint32_t cp15_control_reg,
 		struct armv4_5_cache_common *cache);
 
-int armv4_5_handle_cache_info_command(struct command_context *cmd_ctx,
+int armv4_5_handle_cache_info_command(struct command_invocation *cmd,
 		struct armv4_5_cache_common *armv4_5_cache);
 
 enum {
diff --git a/src/target/xscale.c b/src/target/xscale.c
index cd81b0b..8263f12 100644
--- a/src/target/xscale.c
+++ b/src/target/xscale.c
@@ -3090,7 +3090,7 @@ COMMAND_HANDLER(xscale_handle_cache_info_command)
 	if (retval != ERROR_OK)
 		return retval;
 
-	return armv4_5_handle_cache_info_command(CMD_CTX, &xscale->armv4_5_mmu.armv4_5_cache);
+	return armv4_5_handle_cache_info_command(CMD, &xscale->armv4_5_mmu.armv4_5_cache);
 }
 
 static int xscale_virt2phys(struct target *target,

--