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From: OpenOCD-Gerrit <ope...@us...> - 2018-07-31 14:57:30
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- Log -----------------------------------------------------------------
commit dcf977c89a24b02fd8200af633be1fdd3add4ae7
Author: Antony Pavlov <ant...@gm...>
Date: Sun Sep 20 16:52:37 2015 +0300
tcl/target|board: move common AR9331 code to atheros_ar9331.cfg
The ar9331_25mhz_pll_init and ar9331_ddr1_init routines
can be used not only for TP-Link MR3020 board,
so move them to the common atheros_ar9331.cfg file.
Change-Id: I04090856b08151d6bb0f5ef9cc654efae1c81835
Signed-off-by: Antony Pavlov <ant...@gm...>
Reviewed-on: http://openocd.zylin.com/2999
Tested-by: jenkins
Reviewed-by: Paul Fertser <fer...@gm...>
diff --git a/tcl/board/tp-link_tl-mr3020.cfg b/tcl/board/tp-link_tl-mr3020.cfg
index 7e040b325..48fb69893 100644
--- a/tcl/board/tp-link_tl-mr3020.cfg
+++ b/tcl/board/tp-link_tl-mr3020.cfg
@@ -1,39 +1,5 @@
source [find target/atheros_ar9331.cfg]
-proc ar9331_25mhz_pll_init {} {
- mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4
- mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
- mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL
- ;# OUTDIV | REFDIV | DIV_INT
- mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register
- ;# (disabled?)
- mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT
- mww 0xb8050008 0x00008000 ;# remove bypass;
- ;# AHB_POST_DIV - ratio 2
-}
-
-proc ar9331_ddr1_init {} {
- mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs
- mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs
-
- mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
- mww 0xb8000008 0x133 ;# mode reg: 0x133 - default
- mww 0xb8000010 0x1 ;# Forces an MRS update cycl
- mww 0xb800000c 0x2 ;# Extended mode register value.
- ;# default 0x2 - Reset to weak driver, DLL on
- mww 0xb8000010 0x2 ;# Forces an EMRS update cycle
- mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
- mww 0xb8000008 0x33 ;# mode reg: remove some bit?
- mww 0xb8000010 0x1 ;# Forces an MRS update cycl
- mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate
- mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0,
- ;# DQ[7:0], DQS_0
- mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1,
- ;# DQ[15:8], DQS_1.
- mww 0xb8000018 0xff ;# DDR read and capture bit mask.
- ;# Each bit represents a cycle of valid data.
-}
-
$_TARGETNAME configure -event reset-init {
ar9331_25mhz_pll_init
sleep 1
diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg
index c5609bb1d..cd6918339 100644
--- a/tcl/target/atheros_ar9331.cfg
+++ b/tcl/target/atheros_ar9331.cfg
@@ -14,3 +14,37 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
+
+proc ar9331_25mhz_pll_init {} {
+ mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4
+ mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
+ mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL
+ ;# OUTDIV | REFDIV | DIV_INT
+ mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register
+ ;# (disabled?)
+ mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT
+ mww 0xb8050008 0x00008000 ;# remove bypass;
+ ;# AHB_POST_DIV - ratio 2
+}
+
+proc ar9331_ddr1_init {} {
+ mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs
+ mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs
+
+ mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
+ mww 0xb8000008 0x133 ;# mode reg: 0x133 - default
+ mww 0xb8000010 0x1 ;# Forces an MRS update cycl
+ mww 0xb800000c 0x2 ;# Extended mode register value.
+ ;# default 0x2 - Reset to weak driver, DLL on
+ mww 0xb8000010 0x2 ;# Forces an EMRS update cycle
+ mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
+ mww 0xb8000008 0x33 ;# mode reg: remove some bit?
+ mww 0xb8000010 0x1 ;# Forces an MRS update cycl
+ mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate
+ mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0,
+ ;# DQ[7:0], DQS_0
+ mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1,
+ ;# DQ[15:8], DQS_1.
+ mww 0xb8000018 0xff ;# DDR read and capture bit mask.
+ ;# Each bit represents a cycle of valid data.
+}
commit 87610a41790f3568720701008259c859e2d01ae2
Author: Oleksij Rempel <li...@re...>
Date: Wed Jan 31 11:58:50 2018 +0100
tcl/board: add config for 8devices LIMA board
More information about this board can be found here:
https://www.8devices.com/products/lima
Change-Id: Id35a35d3e986630d58d37b47828870afd107cc6a
Signed-off-by: Oleksij Rempel <li...@re...>
Reviewed-on: http://openocd.zylin.com/4406
Tested-by: jenkins
Reviewed-by: Paul Fertser <fer...@gm...>
diff --git a/tcl/board/8devices-lima.cfg b/tcl/board/8devices-lima.cfg
new file mode 100644
index 000000000..136f86197
--- /dev/null
+++ b/tcl/board/8devices-lima.cfg
@@ -0,0 +1,30 @@
+# Product page:
+# https://www.8devices.com/products/lima
+#
+# Location of JTAG pins:
+# J2 GPIO0 JTAG TCK
+# J2 GPIO1 JTAG TDI
+# J2 GPIO2 JTAG TDO
+# J2 GPIO3 JTAG TMS
+# J2 RST directly connected to RESET_L of the SoC and can be used as
+# JTAG SRST. Note: this pin will also reset the debug engine.
+# J1 +3,3V Can be use as JTAG Vref
+# J1 or J2 GND Can be used for JTAG GND
+#
+# This board is powered from mini USB connecter which is also used
+# as USB to UART converted based on FTDI FT230XQ chip
+
+source [find target/qualcomm_qca4531.cfg]
+
+proc board_init { } {
+ qca4531_ddr2_550_550_init
+}
+
+$_TARGETNAME configure -event reset-init {
+ board_init
+}
+
+set ram_boot_address 0xa0000000
+$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000
+
+flash bank flash0 ath79 0 0 0 0 $_TARGETNAME cs0
-----------------------------------------------------------------------
Summary of changes:
tcl/board/8devices-lima.cfg | 30 ++++++++++++++++++++++++++++++
tcl/board/tp-link_tl-mr3020.cfg | 34 ----------------------------------
tcl/target/atheros_ar9331.cfg | 34 ++++++++++++++++++++++++++++++++++
3 files changed, 64 insertions(+), 34 deletions(-)
create mode 100644 tcl/board/8devices-lima.cfg
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