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From: <ge...@op...> - 2018-05-02 20:40:54
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This is an automated email from Gerrit. Jean-Christian de Rivaz (jca...@gm...) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4515 -- gerrit commit ae75d66ed77e65bc14bcff5ddef91172b1cd86e4 Author: Jean-Christian de Rivaz <jca...@gm...> Date: Wed May 2 18:07:28 2018 +0200 Add LPC8N04 and NHS3xx support. Change-Id: I0bdbca8dd9b234aca355230af7269463c9f70bd1 Signed-off-by: Jean-Christian de Rivaz <jca...@gm...> diff --git a/doc/openocd.texi b/doc/openocd.texi index 3944572..5410c37 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -5754,8 +5754,8 @@ Command disables watchdog timer. @deffn {Flash Driver} lpc2000 This is the driver to support internal flash of all members of the LPC11(x)00 and LPC1300 microcontroller families and most members of -the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000 and LPC54100 -microcontroller families from NXP. +the LPC800, LPC1500, LPC1700, LPC1800, LPC2000, LPC4000, LPC54100, +LPC8N04 and NHS31xx microcontroller families from NXP. @quotation Note There are LPC2000 devices which are not supported by the @var{lpc2000} @@ -5780,7 +5780,7 @@ LPC43x[2357]) @option{lpc54100} (LPC541xx) @option{lpc4000} (LPC40xx) or @option{auto} - automatically detects flash variant and size for LPC11(x)00, -LPC8xx, LPC13xx, LPC17xx and LPC40xx +LPC8N04, LPC8xx, LPC13xx, LPC17xx, LPC40xx and NHS31xx @item @var{clock_kHz} ... the frequency, in kiloHertz, at which the core is running @item @option{calc_checksum} ... optional (but you probably want to provide this!), diff --git a/src/flash/nor/lpc2000.c b/src/flash/nor/lpc2000.c index 8e15c31..3a3f6fd 100644 --- a/src/flash/nor/lpc2000.c +++ b/src/flash/nor/lpc2000.c @@ -257,6 +257,11 @@ #define LPC824_201 0x00008241 #define LPC824_201_1 0x00008242 +#define LPC8N04 0x00008A04 +#define NHS3100 0x4e310020 +#define NHS3152 0x4e315220 +#define NHS3153 0x4e315320 + #define IAP_CODE_LEN 0x34 #define LPC11xx_REG_SECTORS 24 @@ -526,6 +531,10 @@ static int lpc2000_build_sector_list(struct flash_bank *bank) case 16 * 1024: bank->num_sectors = 16; break; + case 30 * 1024: + lpc2000_info->cmd51_max_buffer = 1024; /* For LPC8N04 and NHS31xx, have 8kB of SRAM */ + bank->num_sectors = 30; /* There have only 30kB of writable Flash out of 32kB */ + break; case 32 * 1024: lpc2000_info->cmd51_max_buffer = 1024; /* For LPC824, has 8kB of SRAM */ bank->num_sectors = 32; @@ -1458,6 +1467,15 @@ static int lpc2000_auto_probe_flash(struct flash_bank *bank) bank->size = 32 * 1024; break; + case LPC8N04: + case NHS3100: + case NHS3152: + case NHS3153: + lpc2000_info->variant = lpc800; + lpc2000_info->calc_checksum = 0; + bank->size = 30 * 1024; + break; + default: LOG_ERROR("BUG: unknown Part ID encountered: 0x%" PRIx32, part_id); exit(-1); diff --git a/tcl/target/lpc8nxx.cfg b/tcl/target/lpc8nxx.cfg new file mode 100644 index 0000000..31012ef --- /dev/null +++ b/tcl/target/lpc8nxx.cfg @@ -0,0 +1,10 @@ +# NXP LPC8Nxx Cortex-M0+ with at least 1kB SRAM +if { ![info exists CHIPNAME] } { + set CHIPNAME lpc8xx +} +set CHIPSERIES lpc800 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x1000 +} + +source [find target/lpc1xxx.cfg] diff --git a/tcl/target/nhs31xx.cfg b/tcl/target/nhs31xx.cfg new file mode 100644 index 0000000..7bf3c1d --- /dev/null +++ b/tcl/target/nhs31xx.cfg @@ -0,0 +1,10 @@ +# NXP NHS31xx Cortex-M0+ with at least 1kB SRAM +if { ![info exists CHIPNAME] } { + set CHIPNAME lpc8xx +} +set CHIPSERIES lpc800 +if { ![info exists WORKAREASIZE] } { + set WORKAREASIZE 0x1000 +} + +source [find target/lpc1xxx.cfg] -- |