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From: <ge...@op...> - 2018-04-27 18:14:09
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This is an automated email from Gerrit. Philipp Tomsich (phi...@th...) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4506 -- gerrit commit c072fbed2c28149bd1a6d0ad77b15e6a5cf9115b Author: Philipp Tomsich <phi...@th...> Date: Fri Apr 27 19:59:56 2018 +0200 arm_dpm: flush both scratch registers (R0 and R1) Neither the initial loop to clear dirty registers (which visits all registers starting at R2 and counting upwards) nor the final explicit flushes ensure a write-back in arm_dpm_write_dirty_registers. This change makes sure that both our scratch registers (i.e. R0 and R1) are written back to the target. Change-Id: If65be4f371cd40af9a0cfa97f3730b070b92e981 Signed-off-by: Philipp Tomsich <phi...@th...> diff --git a/src/target/arm_dpm.c b/src/target/arm_dpm.c index 6579099..f9b30c1 100644 --- a/src/target/arm_dpm.c +++ b/src/target/arm_dpm.c @@ -587,11 +587,13 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp) goto done; arm->pc->dirty = false; - /* flush R0 -- it's *very* dirty by now */ - retval = dpm_write_reg(dpm, &cache->reg_list[0], 0); - if (retval != ERROR_OK) - goto done; - cache->reg_list[0].dirty = false; + /* flush R0 and R1 (our scratch registers) */ + for (unsigned i = 0; i < 2; i++) { + retval = dpm_write_reg(dpm, &cache->reg_list[i], i); + if (retval != ERROR_OK) + goto done; + cache->reg_list[i].dirty = false; + } /* (void) */ dpm->finish(dpm); done: -- |