[OpenOCD-devel] [PATCH]: 3d748de aarch64: support for aarch32 ARM_MODE_SYS

[<ge...@op...>]

This is an automated email from Gerrit.

Matthias Welwarsky (mat...@we...) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4494

-- gerrit

commit 3d748de2422c8d93852ee50dcdb70e5479cb551a
Author: Matthias Welwarsky <mat...@sy...>
Date:   Wed Apr 18 10:06:29 2018 +0200

    aarch64: support for aarch32 ARM_MODE_SYS
    
    Treat ARM_MODE_SYS like all other Aarch32 processor modes,
    except for the special case of missing SPSR.
    
    Change-Id: I60b21703659b264f552884cdc0f85fd45f7836de
    Signed-off-by: Matthias Welwarsky <mat...@sy...>

diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index cd83502..00def8a 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -99,6 +99,7 @@ static int aarch64_restore_system_control_reg(struct target *target)
 		case ARM_MODE_ABT:
 		case ARM_MODE_FIQ:
 		case ARM_MODE_IRQ:
+		case ARM_MODE_SYS:
 			instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
 			break;
 
@@ -171,6 +172,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
 	case ARM_MODE_ABT:
 	case ARM_MODE_FIQ:
 	case ARM_MODE_IRQ:
+	case ARM_MODE_SYS:
 		instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
 		break;
 
@@ -1022,6 +1024,7 @@ static int aarch64_post_debug_entry(struct target *target)
 	case ARM_MODE_ABT:
 	case ARM_MODE_FIQ:
 	case ARM_MODE_IRQ:
+	case ARM_MODE_SYS:
 		instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
 		break;
 
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 3ea95b8..0e67907 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -70,6 +70,10 @@ static const struct {
 		.psr = ARM_MODE_ABT,
 	},
 	{
+		.name = "SYS",
+		.psr = ARM_MODE_SYS,
+	},
+	{
 		.name = "EL0T",
 		.psr = ARMV8_64_EL0T,
 	},
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index 162892d..081eed2 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -573,6 +573,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 	case ARM_MODE_ABT:
 	case ARM_MODE_IRQ:
 	case ARM_MODE_FIQ:
+	case ARM_MODE_SYS:
 		target_el = 1;
 		break;
 	/*
@@ -790,6 +791,10 @@ int armv8_dpm_read_current_registers(struct arm_dpm *dpm)
 				dpm->last_el != armv8_curel_from_core_mode(arm_reg->mode))
 			continue;
 
+		/* Special case: ARM_MODE_SYS has no SPSR at EL1 */
+		if (r->number == ARMV8_SPSR_EL1 && arm->core_mode == ARM_MODE_SYS)
+			continue;
+
 		retval = dpmv8_read_reg(dpm, r, i);
 		if (retval != ERROR_OK)
 			goto fail;

--