Re: [OpenOCD-user] Altera Cyclone V Configuration

[Paul F. <fer...@gm...>]

On Thu, Mar 29, 2018 at 11:31:55AM -0700, cob...@se... wrote:
> I need a bit stream similar to the one created by xilinx_bscan_spi.py to
> facilitate the FPGA to flash memory communication.

Correct. I suggest you just try 0.10.0 and implement the FPGA
configuration in Verilog or VHDL as described in the manual, it should
be really trivial, a ten minutes work or so, worth a try.

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