Re: [OpenOCD-user] Cortex M7/ATSAME70, breakpoints and cache

[Thomas D. <tho...@em...>]

Am 22.02.2018 um 10:04 schrieb Matthias Welwarsky:
> On Donnerstag, 22. Februar 2018 09:36:19 CET Thomas Doerfler wrote:
>> Hi Matthias,
>>
>> just a short note: It's the icache which bothers me, not the dcache...
>> and therefore an i-cache invalidate would be sufficent.
> 
> Unfortunately not. The i-cache is on top of the d-cache, so to modify code you 
> need to clean&invalidate the d-cache to the point-of-unification (which is RAM 
> in our case), then modify the code, then invalidate the i-cache

But does the JTAG/SWD IF really write into dcache? I thought the code
modifications happen directly in RAM, so, at least for the breakpoint
issue, syncing RAM with icache is sufficent (unless the CPU also tries
to overwrite its own code... which is a rare issue, I guess).

Anyway I understand, dcache must be synced with external RAM for debugging.

Another delicate thing I am not sure about: It's the famous open source
"we". I germany, we often call it the nurse "we" ("we will get an
medical injection now..."). Is there something I can do to get it
properly integrated? I might change the openOCD code to sync the caches,
but I am not quite sure whether my patch would be in an acceptable state
for the project...

OTOH, I can definitively test solutions in our environment.

How can we proceed?

wkr,

Thomas.