[OpenOCD-devel] [PATCH]: 2aa10d3 mips64: add mips64mode32 command to automatically sign extend 32 bit addresses

[<ge...@op...>]

This is an automated email from Gerrit.

Peter Mamonov (pma...@gm...) just uploaded a new patch set to Gerrit, which you can find at http://openocd.zylin.com/4035

-- gerrit

commit 2aa10d3aa8b7ee1f6c58294d4afeab76cac80c6a
Author: Peter Mamonov <pma...@gm...>
Date:   Wed Jun 1 13:27:51 2016 +0300

    mips64: add mips64mode32 command to automatically sign extend 32 bit addresses
    
    Change-Id: I46e65bfee7011a299fc32a03f6ba0d5b0d5624d2
    Signed-off-by: Peter Mamonov <pma...@gm...>

diff --git a/src/target/mips64.c b/src/target/mips64.c
index ef742ea..d8c4f11 100644
--- a/src/target/mips64.c
+++ b/src/target/mips64.c
@@ -442,6 +442,8 @@ int mips64_init_arch_info(struct target *target, struct mips64_common *mips64, s
 
 	mips64->fast_data_area = NULL;
 
+	mips64->mips64mode32 = 0;
+
 	return ERROR_OK;
 }
 
diff --git a/src/target/mips64.h b/src/target/mips64.h
index 70520ff..d92b046 100644
--- a/src/target/mips64.h
+++ b/src/target/mips64.h
@@ -112,6 +112,8 @@ struct mips64_common {
 	/* register cache to processor synchronization */
 	int (*read_core_reg)(struct target *target, int num);
 	int (*write_core_reg)(struct target *target, int num);
+
+	int mips64mode32;
 };
 
 struct mips64_core_reg {
diff --git a/src/target/mips_mips64.c b/src/target/mips_mips64.c
index 23426b2..98f5b7e 100644
--- a/src/target/mips_mips64.c
+++ b/src/target/mips_mips64.c
@@ -42,6 +42,15 @@ static int mips_mips64_set_breakpoint(struct target *target,
 static int mips_mips64_unset_breakpoint(struct target *target,
 		struct breakpoint *breakpoint);
 
+static uint64_t mips64_extend_sign(uint64_t addr)
+{
+	if (addr >> 32)
+		return addr;
+	if (addr >> 31)
+		return addr | (ULLONG_MAX << 32);
+	return addr;
+}
+
 static int mips_mips64_examine_debug_reason(struct target *target)
 {
 	if ((target->debug_reason != DBG_REASON_DBGRQ)
@@ -241,6 +250,9 @@ static int mips_mips64_resume(struct target *target, int current, uint64_t addre
 	struct breakpoint *breakpoint = NULL;
 	uint64_t resume_pc;
 
+	if (mips64->mips64mode32)
+		address = mips64_extend_sign(address);
+
 	if (target->state != TARGET_HALTED) {
 		LOG_WARNING("target not halted %d", target->state);
 		return ERROR_TARGET_NOT_HALTED;
@@ -305,6 +317,9 @@ static int mips_mips64_step(struct target *target, int current, uint64_t address
 	struct mips_ejtag *ejtag_info = &mips64->ejtag_info;
 	struct breakpoint *breakpoint = NULL;
 
+	if (mips64->mips64mode32)
+		address = mips64_extend_sign(address);
+
 	if (target->state != TARGET_HALTED) {
 		LOG_WARNING("target not halted");
 		return ERROR_TARGET_NOT_HALTED;
@@ -508,6 +523,9 @@ static int mips_mips64_add_breakpoint(struct target *target, struct breakpoint *
 {
 	struct mips64_common *mips64 = target->arch_info;
 
+	if (mips64->mips64mode32)
+		breakpoint->address = mips64_extend_sign(breakpoint->address);
+
 	if (breakpoint->type == BKPT_HARD) {
 		if (mips64->num_inst_bpoints_avail < 1) {
 			LOG_INFO("no hardware breakpoint available");
@@ -684,6 +702,9 @@ static int mips_mips64_read_memory(struct target *target, uint64_t address,
 	struct mips64_common *mips64 = target->arch_info;
 	struct mips_ejtag *ejtag_info = &mips64->ejtag_info;
 
+	if (mips64->mips64mode32)
+		address = mips64_extend_sign(address);
+
 	LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
 
 	if (target->state != TARGET_HALTED) {
@@ -815,6 +836,9 @@ static int mips_mips64_write_memory(struct target *target, uint64_t address,
 	struct mips_ejtag *ejtag_info = &mips64->ejtag_info;
 	int retval;
 
+	if (mips64->mips64mode32)
+		address = mips64_extend_sign(address);
+
 	LOG_DEBUG("address: 0x%16.16" PRIx64 ", size: 0x%8.8" PRIx32 ", count: 0x%8.8" PRIx32 "", address, size, count);
 
 	if (target->state != TARGET_HALTED) {
@@ -943,6 +967,34 @@ static int mips_mips64_checksum_memory(struct target *target, uint64_t address,
 	return ERROR_FAIL; /* use bulk read method */
 }
 
+COMMAND_HANDLER(handle_mips64mode32)
+{
+	struct target *target = get_current_target(CMD_CTX);
+	struct mips64_common *mips64 = target->arch_info;
+
+	if (CMD_ARGC > 0)
+		COMMAND_PARSE_NUMBER(int, CMD_ARGV[0], mips64->mips64mode32);
+
+	if (mips64->mips64mode32)
+		command_print(CMD_CTX, "enabled");
+	else
+		command_print(CMD_CTX, "disabled");
+
+	return ERROR_OK;
+}
+
+
+static const struct command_registration mips64_commands_handlers[] = {
+	{
+		.name = "mips64mode32",
+		.mode = COMMAND_EXEC,
+		.help = "Enable/disable 32 bit mode",
+		.usage = "[1|0]",
+		.handler = handle_mips64mode32
+	},
+	COMMAND_REGISTRATION_DONE
+};
+
 struct target_type mips_mips64_target = {
 	.name = "mips_mips64",
 
@@ -976,6 +1028,8 @@ struct target_type mips_mips64_target = {
 	.target_create = mips_mips64_target_create,
 	.init_target = mips_mips64_init_target,
 	.examine = mips_mips64_examine,
+
+	.commands = mips64_commands_handlers,
 };
 
 #endif /* BUILD_TARGET64 */

--