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[OpenOCD-commit] Main OpenOCD repository branch, master, updated. v0.10.0-79-gfa8700c
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From: OpenOCD-Gerrit <ope...@us...> - 2017-02-24 09:13:50
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- Log -----------------------------------------------------------------
commit fa8700cdd58752671fb8d60ef65bf767e4aa1bc5
Author: Matthias Welwarsky <mat...@sy...>
Date: Mon Nov 14 21:54:26 2016 +0100
aarch64: reduce debug output to improve legibility
Suppress some very verbose LOG_DEBUG's that are not really useful
any more.
Change-Id: I67f10ba9510a9e34a027f378f4b62b8901ddc8a4
Signed-off-by: Matthias Welwarsky <mat...@sy...>
Reviewed-on: http://openocd.zylin.com/3984
Tested-by: jenkins
Reviewed-by: Paul Fertser <fer...@gm...>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 7bd3d3c..d3ed57c 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -1333,9 +1333,6 @@ static int aarch64_write_apb_ap_memory(struct target *target,
uint32_t dscr;
uint8_t *tmp_buff = NULL;
- LOG_DEBUG("Writing APB-AP memory address 0x%" PRIx64 " size %" PRIu32 " count %" PRIu32,
- address, size, count);
-
if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
@@ -1484,9 +1481,6 @@ static int aarch64_read_apb_ap_memory(struct target *target,
uint8_t *u8buf_ptr;
uint32_t value;
- LOG_DEBUG("Reading APB-AP memory address 0x%" TARGET_PRIxADDR " size %" PRIu32 " count %" PRIu32,
- address, size, count);
-
if (target->state != TARGET_HALTED) {
LOG_WARNING("target not halted");
return ERROR_TARGET_NOT_HALTED;
@@ -1634,8 +1628,6 @@ static int aarch64_read_phys_memory(struct target *target,
uint32_t count, uint8_t *buffer)
{
int retval = ERROR_COMMAND_SYNTAX_ERROR;
- LOG_DEBUG("Reading memory at real address 0x%" TARGET_PRIxADDR "; size %" PRId32 "; count %" PRId32,
- address, size, count);
if (count && buffer) {
/* read memory through APB-AP */
@@ -1653,10 +1645,6 @@ static int aarch64_read_memory(struct target *target, target_addr_t address,
int mmu_enabled = 0;
int retval;
- /* aarch64 handles unaligned memory access */
- LOG_DEBUG("Reading memory at address 0x%" TARGET_PRIxADDR "; size %" PRId32 "; count %" PRId32, address,
- size, count);
-
/* determine if MMU was enabled on target stop */
retval = aarch64_mmu(target, &mmu_enabled);
if (retval != ERROR_OK)
@@ -1680,9 +1668,6 @@ static int aarch64_write_phys_memory(struct target *target,
{
int retval = ERROR_COMMAND_SYNTAX_ERROR;
- LOG_DEBUG("Writing memory to real address 0x%" TARGET_PRIxADDR "; size %" PRId32 "; count %" PRId32, address,
- size, count);
-
if (count && buffer) {
/* write memory through APB-AP */
retval = aarch64_mmu_modify(target, 0);
@@ -1700,10 +1685,6 @@ static int aarch64_write_memory(struct target *target, target_addr_t address,
int mmu_enabled = 0;
int retval;
- /* aarch64 handles unaligned memory access */
- LOG_DEBUG("Writing memory at address 0x%" TARGET_PRIxADDR "; size %" PRId32
- "; count %" PRId32, address, size, count);
-
/* determine if MMU was enabled on target stop */
retval = aarch64_mmu(target, &mmu_enabled);
if (retval != ERROR_OK)
diff --git a/src/target/armv8.c b/src/target/armv8.c
index 94a0e8e..7ae8cc9 100644
--- a/src/target/armv8.c
+++ b/src/target/armv8.c
@@ -1086,9 +1086,6 @@ static int armv8_get_core_reg32(struct reg *reg)
struct reg *reg64;
int retval;
- LOG_DEBUG("reg.name:%s number:%i arm.num:%i value:0x%08" PRIx64,
- reg->name, reg->number, armv8_reg->num, buf_get_u64(reg->value, 0, 32));
-
/* get the corresponding Aarch64 register */
reg64 = cache->reg_list + armv8_reg->num;
if (reg64->valid) {
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index acfd1bc..56e2eb8 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -71,7 +71,6 @@ enum arm_state armv8_dpm_get_core_state(struct arm_dpm *dpm)
static int dpmv8_write_dcc(struct armv8_common *armv8, uint32_t data)
{
- LOG_DEBUG("write DCC 0x%08" PRIx32, data);
return mem_ap_write_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DTRRX, data);
}
@@ -79,7 +78,6 @@ static int dpmv8_write_dcc(struct armv8_common *armv8, uint32_t data)
static int dpmv8_write_dcc_64(struct armv8_common *armv8, uint64_t data)
{
int ret;
- LOG_DEBUG("write DCC 0x%016" PRIx64, data);
ret = mem_ap_write_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DTRRX, data);
if (ret == ERROR_OK)
@@ -116,7 +114,6 @@ static int dpmv8_read_dcc(struct armv8_common *armv8, uint32_t *data,
data);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
if (dscr_p)
*dscr_p = dscr;
@@ -161,7 +158,6 @@ static int dpmv8_read_dcc_64(struct armv8_common *armv8, uint64_t *data,
return retval;
*data = *(uint32_t *)data | (uint64_t)higher << 32;
- LOG_DEBUG("read DCC 0x%16.16" PRIx64, *data);
if (dscr_p)
*dscr_p = dscr;
@@ -220,8 +216,6 @@ static int dpmv8_exec_opcode(struct arm_dpm *dpm,
uint32_t dscr = dpm->dscr;
int retval;
- LOG_DEBUG("exec opcode 0x%08" PRIx32, opcode);
-
if (p_dscr)
dscr = *p_dscr;
commit 06ba5492df66e997eafe294fced505b11e67f2fc
Author: Matthias Welwarsky <mat...@sy...>
Date: Mon Nov 14 12:23:24 2016 +0100
aarch64: remove mrs/msr functions from struct arm
No longer needed, no users.
Change-Id: I0cc82a0ef11e1b72101fa9145f014e5d5d76df0e
Signed-off-by: Matthias Welwarsky <mat...@sy...>
Reviewed-on: http://openocd.zylin.com/3983
Tested-by: jenkins
Reviewed-by: Paul Fertser <fer...@gm...>
diff --git a/src/target/arm.h b/src/target/arm.h
index e5e336d..d63ead2 100644
--- a/src/target/arm.h
+++ b/src/target/arm.h
@@ -189,18 +189,6 @@ struct arm {
uint32_t CRn, uint32_t CRm,
uint32_t value);
- /** Read coprocessor register. */
- int (*mrs)(struct target *target, uint32_t op0,
- uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm,
- uint32_t *value);
-
- /** Write coprocessor register. */
- int (*msr)(struct target *target, uint32_t cpnum,
- uint32_t op1, uint32_t op2,
- uint32_t CRn, uint32_t CRm,
- uint32_t value);
-
void *arch_info;
/** For targets conforming to ARM Debug Interface v5,
diff --git a/src/target/armv8_dpm.c b/src/target/armv8_dpm.c
index b06e456..acfd1bc 100644
--- a/src/target/armv8_dpm.c
+++ b/src/target/armv8_dpm.c
@@ -551,62 +551,6 @@ static int dpmv8_mcr(struct target *target, int cpnum,
return retval;
}
-static int dpmv8_mrs(struct target *target, uint32_t op0,
- uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
- uint32_t *value)
-{
- struct arm *arm = target_to_arm(target);
- struct arm_dpm *dpm = arm->dpm;
- int retval;
- uint32_t op_code;
-
- retval = dpm->prepare(dpm);
- if (retval != ERROR_OK)
- return retval;
- op_code = ((op0 & 0x3) << 19 | (op1 & 0x7) << 16 | (CRn & 0xF) << 12 |\
- (CRm & 0xF) << 8 | (op2 & 0x7) << 5);
- op_code >>= 5;
- LOG_DEBUG("MRS p%d, %d, r0, c%d, c%d, %d", (int)op0,
- (int) op1, (int) CRn,
- (int) CRm, (int) op2);
- /* read coprocessor register into R0; return via DCC */
- retval = dpm->instr_read_data_r0(dpm,
- ARMV8_MRS(op_code, 0),
- value);
-
- /* (void) */ dpm->finish(dpm);
- return retval;
-}
-
-static int dpmv8_msr(struct target *target, uint32_t op0,
- uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm,
- uint32_t value)
-{
- struct arm *arm = target_to_arm(target);
- struct arm_dpm *dpm = arm->dpm;
- int retval;
- uint32_t op_code;
-
- retval = dpm->prepare(dpm);
- if (retval != ERROR_OK)
- return retval;
-
- op_code = ((op0 & 0x3) << 19 | (op1 & 0x7) << 16 | (CRn & 0xF) << 12 |\
- (CRm & 0xF) << 8 | (op2 & 0x7) << 5);
- op_code >>= 5;
- LOG_DEBUG("MSR p%d, %d, r0, c%d, c%d, %d", (int)op0,
- (int) op1, (int) CRn,
- (int) CRm, (int) op2);
-
- /* read DCC into r0; then write coprocessor register from R0 */
- retval = dpm->instr_write_data_r0(dpm,
- ARMV8_MSR_GP(op_code, 0),
- value);
-
- /* (void) */ dpm->finish(dpm);
- return retval;
-}
-
/*----------------------------------------------------------------------*/
/*
@@ -1449,8 +1393,6 @@ int armv8_dpm_setup(struct arm_dpm *dpm)
/* coprocessor access setup */
arm->mrc = dpmv8_mrc;
arm->mcr = dpmv8_mcr;
- arm->mrs = dpmv8_mrs;
- arm->msr = dpmv8_msr;
dpm->prepare = dpmv8_dpm_prepare;
dpm->finish = dpmv8_dpm_finish;
commit f988f5960450cf9e8c456bf8e3b4d2008e35a207
Author: Matthias Welwarsky <mat...@sy...>
Date: Mon Nov 14 12:18:43 2016 +0100
aarch64: refactor SCTLR manipulation
Reduce SLOCs in SCTLR retrieval and modification functions and make them
less complex.
Change-Id: Ida1a99c223743247f171b52eef80dc9886802101
Signed-off-by: Matthias Welwarsky <mat...@sy...>
Reviewed-on: http://openocd.zylin.com/3982
Tested-by: jenkins
Reviewed-by: Paul Fertser <fer...@gm...>
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 833dc7a..7bd3d3c 100644
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -49,7 +49,9 @@ static int aarch64_read_apb_ap_memory(struct target *target,
static int aarch64_restore_system_control_reg(struct target *target)
{
+ enum arm_mode target_mode = ARM_MODE_ANY;
int retval = ERROR_OK;
+ uint32_t instr;
struct aarch64_common *aarch64 = target_to_aarch64(target);
struct armv8_common *armv8 = target_to_armv8(target);
@@ -59,41 +61,45 @@ static int aarch64_restore_system_control_reg(struct target *target)
/* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_v8->cp15_control_reg); */
switch (armv8->arm.core_mode) {
- case ARMV8_64_EL0T:
- case ARMV8_64_EL1T:
- case ARMV8_64_EL1H:
- retval = armv8->arm.msr(target, 3, /*op 0*/
- 0, 1, /* op1, op2 */
- 0, 0, /* CRn, CRm */
- aarch64->system_control_reg);
- if (retval != ERROR_OK)
- return retval;
+ case ARMV8_64_EL0T:
+ target_mode = ARMV8_64_EL1H;
+ /* fall through */
+ case ARMV8_64_EL1T:
+ case ARMV8_64_EL1H:
+ instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL1, 0);
break;
- case ARMV8_64_EL2T:
- case ARMV8_64_EL2H:
- retval = armv8->arm.msr(target, 3, /*op 0*/
- 4, 1, /* op1, op2 */
- 0, 0, /* CRn, CRm */
- aarch64->system_control_reg);
- if (retval != ERROR_OK)
- return retval;
+ case ARMV8_64_EL2T:
+ case ARMV8_64_EL2H:
+ instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL2, 0);
break;
- case ARMV8_64_EL3H:
- case ARMV8_64_EL3T:
- retval = armv8->arm.msr(target, 3, /*op 0*/
- 6, 1, /* op1, op2 */
- 0, 0, /* CRn, CRm */
- aarch64->system_control_reg);
- if (retval != ERROR_OK)
- return retval;
+ case ARMV8_64_EL3H:
+ case ARMV8_64_EL3T:
+ instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0);
break;
- default:
- retval = armv8->arm.mcr(target, 15, 0, 0, 1, 0, aarch64->system_control_reg);
- if (retval != ERROR_OK)
- return retval;
- break;
- }
+
+ case ARM_MODE_SVC:
+ case ARM_MODE_ABT:
+ case ARM_MODE_FIQ:
+ case ARM_MODE_IRQ:
+ instr = ARMV4_5_MCR(15, 0, 0, 1, 0, 0);
+ break;
+
+ default:
+ LOG_INFO("cannot read system control register in this mode");
+ return ERROR_FAIL;
+ }
+
+ if (target_mode != ARM_MODE_ANY)
+ armv8_dpm_modeswitch(&armv8->dpm, target_mode);
+
+ retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr, aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (target_mode != ARM_MODE_ANY)
+ armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
}
+
return retval;
}
@@ -112,6 +118,7 @@ static int aarch64_mmu_modify(struct target *target, int enable)
struct aarch64_common *aarch64 = target_to_aarch64(target);
struct armv8_common *armv8 = &aarch64->armv8_common;
int retval = ERROR_OK;
+ uint32_t instr = 0;
if (enable) {
/* if mmu enabled at target stop and mmu not enable */
@@ -119,86 +126,42 @@ static int aarch64_mmu_modify(struct target *target, int enable)
LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
return ERROR_FAIL;
}
- if (!(aarch64->system_control_reg_curr & 0x1U)) {
+ if (!(aarch64->system_control_reg_curr & 0x1U))
aarch64->system_control_reg_curr |= 0x1U;
- switch (armv8->arm.core_mode) {
- case ARMV8_64_EL0T:
- case ARMV8_64_EL1T:
- case ARMV8_64_EL1H:
- retval = armv8->arm.msr(target, 3, /*op 0*/
- 0, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- aarch64->system_control_reg_curr);
- if (retval != ERROR_OK)
- return retval;
- break;
- case ARMV8_64_EL2T:
- case ARMV8_64_EL2H:
- retval = armv8->arm.msr(target, 3, /*op 0*/
- 4, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- aarch64->system_control_reg_curr);
- if (retval != ERROR_OK)
- return retval;
- break;
- case ARMV8_64_EL3H:
- case ARMV8_64_EL3T:
- retval = armv8->arm.msr(target, 3, /*op 0*/
- 6, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- aarch64->system_control_reg_curr);
- if (retval != ERROR_OK)
- return retval;
- break;
- default:
- LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
- }
- }
} else {
if (aarch64->system_control_reg_curr & 0x4U) {
/* data cache is active */
aarch64->system_control_reg_curr &= ~0x4U;
- /* flush data cache armv7 function to be called */
+ /* flush data cache armv8 function to be called */
if (armv8->armv8_mmu.armv8_cache.flush_all_data_cache)
armv8->armv8_mmu.armv8_cache.flush_all_data_cache(target);
}
if ((aarch64->system_control_reg_curr & 0x1U)) {
aarch64->system_control_reg_curr &= ~0x1U;
- switch (armv8->arm.core_mode) {
- case ARMV8_64_EL0T:
- case ARMV8_64_EL1T:
- case ARMV8_64_EL1H:
- retval = armv8->arm.msr(target, 3, /*op 0*/
- 0, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- aarch64->system_control_reg_curr);
- if (retval != ERROR_OK)
- return retval;
- break;
- case ARMV8_64_EL2T:
- case ARMV8_64_EL2H:
- retval = armv8->arm.msr(target, 3, /*op 0*/
- 4, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- aarch64->system_control_reg_curr);
- if (retval != ERROR_OK)
- return retval;
- break;
- case ARMV8_64_EL3H:
- case ARMV8_64_EL3T:
- retval = armv8->arm.msr(target, 3, /*op 0*/
- 6, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- aarch64->system_control_reg_curr);
- if (retval != ERROR_OK)
- return retval;
- break;
- default:
- LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
- break;
- }
}
}
+
+ switch (armv8->arm.core_mode) {
+ case ARMV8_64_EL0T:
+ case ARMV8_64_EL1T:
+ case ARMV8_64_EL1H:
+ instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL1, 0);
+ break;
+ case ARMV8_64_EL2T:
+ case ARMV8_64_EL2H:
+ instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL2, 0);
+ break;
+ case ARMV8_64_EL3H:
+ case ARMV8_64_EL3T:
+ instr = ARMV8_MSR_GP(SYSTEM_SCTLR_EL3, 0);
+ break;
+ default:
+ LOG_DEBUG("unknown cpu state 0x%x" PRIx32, armv8->arm.core_state);
+ break;
+ }
+
+ retval = armv8->dpm.instr_write_data_r0(&armv8->dpm, instr,
+ aarch64->system_control_reg_curr);
return retval;
}
@@ -714,51 +677,47 @@ static int aarch64_post_debug_entry(struct target *target)
struct aarch64_common *aarch64 = target_to_aarch64(target);
struct armv8_common *armv8 = &aarch64->armv8_common;
int retval;
+ enum arm_mode target_mode = ARM_MODE_ANY;
+ uint32_t instr;
switch (armv8->arm.core_mode) {
- case ARMV8_64_EL0T:
- armv8_dpm_modeswitch(&armv8->dpm, ARMV8_64_EL1H);
- /* fall through */
- case ARMV8_64_EL1T:
- case ARMV8_64_EL1H:
- retval = armv8->arm.mrs(target, 3, /*op 0*/
- 0, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- &aarch64->system_control_reg);
- if (retval != ERROR_OK)
- return retval;
+ case ARMV8_64_EL0T:
+ target_mode = ARMV8_64_EL1H;
+ /* fall through */
+ case ARMV8_64_EL1T:
+ case ARMV8_64_EL1H:
+ instr = ARMV8_MRS(SYSTEM_SCTLR_EL1, 0);
break;
- case ARMV8_64_EL2T:
- case ARMV8_64_EL2H:
- retval = armv8->arm.mrs(target, 3, /*op 0*/
- 4, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- &aarch64->system_control_reg);
- if (retval != ERROR_OK)
- return retval;
+ case ARMV8_64_EL2T:
+ case ARMV8_64_EL2H:
+ instr = ARMV8_MRS(SYSTEM_SCTLR_EL2, 0);
break;
- case ARMV8_64_EL3H:
- case ARMV8_64_EL3T:
- retval = armv8->arm.mrs(target, 3, /*op 0*/
- 6, 0, /* op1, op2 */
- 1, 0, /* CRn, CRm */
- &aarch64->system_control_reg);
- if (retval != ERROR_OK)
- return retval;
+ case ARMV8_64_EL3H:
+ case ARMV8_64_EL3T:
+ instr = ARMV8_MRS(SYSTEM_SCTLR_EL3, 0);
break;
- case ARM_MODE_SVC:
- retval = armv8->arm.mrc(target, 15, 0, 0, 1, 0, &aarch64->system_control_reg);
- if (retval != ERROR_OK)
- return retval;
- break;
+ case ARM_MODE_SVC:
+ case ARM_MODE_ABT:
+ case ARM_MODE_FIQ:
+ case ARM_MODE_IRQ:
+ instr = ARMV4_5_MRC(15, 0, 0, 1, 0, 0);
+ break;
- default:
- LOG_INFO("cannot read system control register in this mode");
- break;
+ default:
+ LOG_INFO("cannot read system control register in this mode");
+ return ERROR_FAIL;
}
- armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
+ if (target_mode != ARM_MODE_ANY)
+ armv8_dpm_modeswitch(&armv8->dpm, target_mode);
+
+ retval = armv8->dpm.instr_read_data_r0(&armv8->dpm, instr, &aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+
+ if (target_mode != ARM_MODE_ANY)
+ armv8_dpm_modeswitch(&armv8->dpm, ARM_MODE_ANY);
LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
aarch64->system_control_reg_curr = aarch64->system_control_reg;
diff --git a/src/target/armv8_opcodes.h b/src/target/armv8_opcodes.h
index 94694bc..2d8ddd8 100644
--- a/src/target/armv8_opcodes.h
+++ b/src/target/armv8_opcodes.h
@@ -42,6 +42,10 @@
#define SYSTEM_ELR_EL2 0b1110001000000001
#define SYSTEM_ELR_EL3 0b1111001000000001
+#define SYSTEM_SCTLR_EL1 0b1100000010000000
+#define SYSTEM_SCTLR_EL2 0b1110000010000000
+#define SYSTEM_SCTLR_EL3 0b1111000010000000
+
#define SYSTEM_FPCR 0b1101101000100000
#define SYSTEM_FPSR 0b1101101000100001
#define SYSTEM_DAIF 0b1101101000010001
-----------------------------------------------------------------------
Summary of changes:
src/target/aarch64.c | 248 +++++++++++++++++----------------------------
src/target/arm.h | 12 ---
src/target/armv8.c | 3 -
src/target/armv8_dpm.c | 64 ------------
src/target/armv8_opcodes.h | 4 +
5 files changed, 98 insertions(+), 233 deletions(-)
hooks/post-receive
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