Re: [OpenOCD-user] lpc2148 no halt

[Steve F. <bah...@gm...>]

On Thu, Jan 30, 2014 at 2:11 AM, Spencer Oliver <sp...@sp...>wrote:

> On 29 January 2014 23:05, Steve Franks <bah...@gm...> wrote:
> > On 29 Jan 2014 22:45, "Steve Franks" <bah...@gm...> wrote:
> >>
> >> >
> >> > Also note that I don't appear to be able to access the ISP bootloader
> >> > without a hard power-cycle either. I don't know if that's a clue or
> not.
> >> >
> >> >
> >>
> >> Could be a clue.
> >
> > Only after an aborted attempt at openocd, that is. Works normally when I
> > don't.
> >
> >>
> >> Do you have a schematic of your board?
> >> Or can you describe the srst/tsrt wiring.
> >>
> >> Spen
> >
> > Well, SRST goes to the jtag pod. TRST isn't connected anywhere, but I
> read
> > somewhere on google that all the LPC2000 chips implicitly act as though
> > trst_follows_srst?
> >
>
> Firstly I would recommend at least a pullup resistor on your SRST
> line, so we can guarantee a safe reset.
>
> As I mentioned before reset handling needs to understand not just your
> target, but also your board.
> So 'srst_pulls_trst' means one thing to OpenOCD however two situations
> can cause it.
> 1. The hardware engineer has physically connected SRST and TRST on the
> board - Olimex did this quite a bit in the early days - unsure why.
> 2. The target internally connects SRST and TRST - the ST STR7 did this.
>
> So as your board does not connect SRST and TRST together we do not
> need this option.
>
> Now the only other thing I have spotted is that you have no resistors
> on the JTAG lines.
> Now according to NXP these have internal pullups which may be more
> than enough in most situations, personally I always add resistors.
>
> TCK would normally be pulled low to ensure a safe jtag reset.
> I have never used LPC devices in anger so my knowledge is not the best.
>
> Cheers
> Spen
>
>
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Incidentally, I can't program flash either (possibly proc init_targets{}
isn't being overridden?) ; looks like garbage and I'm running at 100kHz (I
think)...

What's with the 'IR capture' errors, if the 'cpu/tap device' gets found
right after that?

Cfg:

source [find interface/ftdi/olimex-arm-usb-ocd.cfg]
source [find target/lpc2148.cfg]

proc init_board {} {

    #gdb_memory_map disable
    #gdb_flash_program enable

    # change the cfg default reset_config
    reset_config srst_only srst_open_drain
    #reset_config trst_and_srst srst_pulls_trst srst_open_drain

    # for initial script debugging change default adapter speed
    adapter_khz 100
    #core_freq_khz 14745
}

proc init_targets {} {
    # default to core clocked with 12MHz crystal
    # echo "Warning - assuming default core clock 12MHz! Flashing may fail
if actual core clock is different."

    # setup_lpc2148 <core_freq_khz> <adapter_freq_khz>
    # setup_lpc2148 14745 1500

    setup_lpc2xxx lpc2138 "0x3f0f0f0f 0x4f1f0f0f" 0x7d000 lpc2000_v2 0x8000
14745 100
}

program Main.elf verify reset

Result:

Open On-Chip Debugger 0.8.0-dev-00328-g0b26376 (2014-01-20-15:29)
Licensed under GNU GPL v2
For bug reports, read
    http://openocd.sourceforge.net/doc/doxygen/bugs.html
Info : only one transport option; autoselect 'jtag'
trst_and_srst separate srst_gates_jtag trst_push_pull srst_open_drain
connect_deassert_srst
adapter_nsrst_delay: 100
jtag_ntrst_delay: 100
adapter speed: 100 kHz
srst_only separate srst_gates_jtag srst_open_drain connect_deassert_srst
adapter speed: 100 kHz
Info : clock speed 100 kHz
Error: JTAG scan chain interrogation failed: all ones
Error: Check JTAG interface, timings, target power, etc.
Error: Trying to use configured scan chain anyway...
Error: lpc2138.cpu: IR capture error; saw 0x0f not 0x01
Warn : Bypassing JTAG setup events due to errors
Info : Embedded ICE version 15
Error: unknown EmbeddedICE version (comms ctrl: 0xffffffff)
Info : lpc2138.cpu: hardware has 2 breakpoint/watchpoint units
Warn : ThumbEE -- incomplete support
Info : JTAG tap: lpc2138.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787,
part: 0xf1f0, ver: 0x4)
target state: halted
target halted in ARM state due to debug-request, current mode: Supervisor
cpsr: 0x000000d3 pc: 0x00000000
Warn : NOTE! DCC downloads have not been enabled, defaulting to slow memory
writes. Type 'help dcc'.
Warn : NOTE! Severe performance degradation without fast memory access
enabled. Type 'help fast'.
** Programming Started **
auto erase enabled
Info : Padding image section 0 with 4 bytes
Warn : Verification will fail since checksum in image (0xe1a00000) to be
written to flash is different from calculated vector checksum (0xb9205f88).
Warn : To remove this warning modify build tools on developer PC to inject
correct LPC vector checksum.
wrote 163840 bytes from file Main.elf in 44.463242s (3.598 KiB/s)
** Programming Finished **
** Verify Started **
Error: checksum mismatch - attempting binary compare
diff 0 address 0x00000000. Was 0x34 instead of 0x18
diff 1 address 0x00000001. Was 0x40 instead of 0xf0
diff 2 address 0x00000004. Was 0x02 instead of 0x18
diff 3 address 0x00000005. Was 0x50 instead of 0xf0
diff 4 address 0x00000006. Was 0xa0 instead of 0x9f
diff 5 address 0x00000007. Was 0xe3 instead of 0xe5
diff 6 address 0x00000008. Was 0x00 instead of 0x18
diff 7 address 0x00000009. Was 0x50 instead of 0xf0
diff 8 address 0x0000000a. Was 0x84 instead of 0x9f
diff 9 address 0x0000000c. Was 0x03 instead of 0x18
diff 10 address 0x0000000d. Was 0x50 instead of 0xf0
diff 11 address 0x0000000e. Was 0xa0 instead of 0x9f
diff 12 address 0x0000000f. Was 0xe3 instead of 0xe5
diff 13 address 0x00000010. Was 0x04 instead of 0x18
diff 14 address 0x00000011. Was 0x50 instead of 0xf0
diff 15 address 0x00000012. Was 0x84 instead of 0x9f
diff 16 address 0x00000014. Was 0x1c instead of 0x00
diff 17 address 0x00000015. Was 0x20 instead of 0x00
diff 18 address 0x00000016. Was 0x9f instead of 0xa0
diff 19 address 0x00000017. Was 0xe5 instead of 0xe1
diff 20 address 0x00000018. Was 0x00 instead of 0xf0
diff 21 address 0x00000019. Was 0x30 instead of 0xff
diff 22 address 0x0000001a. Was 0xa0 instead of 0x1f
diff 23 address 0x0000001b. Was 0xe3 instead of 0xe5
diff 24 address 0x0000001c. Was 0x93 instead of 0x10
diff 25 address 0x0000001d. Was 0x00 instead of 0xf0
diff 26 address 0x0000001e. Was 0x02 instead of 0x9f
diff 27 address 0x0000001f. Was 0xe1 instead of 0xe5
diff 28 address 0x00000020. Was 0x28 instead of 0x3c
diff 29 address 0x00000021. Was 0x20 instead of 0x00
diff 30 address 0x00000022. Was 0x82 instead of 0x00
diff 31 address 0x00000023. Was 0xe2 instead of 0x00
diff 32 address 0x00000024. Was 0x93 instead of 0xa8
diff 33 address 0x00000025. Was 0x10 instead of 0x09
diff 34 address 0x00000026. Was 0x02 instead of 0x00
diff 35 address 0x00000027. Was 0xe1 instead of 0x00
diff 36 address 0x00000028. Was 0x07 instead of 0x9c
diff 37 address 0x00000029. Was 0x30 instead of 0x09
diff 38 address 0x0000002a. Was 0xc0 instead of 0x00
diff 39 address 0x0000002b. Was 0xe3 instead of 0x00
diff 40 address 0x0000002c. Was 0x28 instead of 0xa8
diff 41 address 0x0000002d. Was 0x30 instead of 0x09
diff 42 address 0x0000002e. Was 0x02 instead of 0x00
diff 43 address 0x0000002f. Was 0xe5 instead of 0x00
diff 44 address 0x00000030. Was 0x04 instead of 0xa8
diff 45 address 0x00000031. Was 0xf0 instead of 0x09
diff 46 address 0x00000032. Was 0x1f instead of 0x00
diff 47 address 0x00000033. Was 0xe5 instead of 0x00
diff 48 address 0x00000034. Was 0xc4 instead of 0x94
diff 49 address 0x00000035. Was 0xd1 instead of 0x09
diff 50 address 0x00000036. Was 0xff instead of 0x00
diff 51 address 0x00000037. Was 0x7f instead of 0x00
diff 52 address 0x00000038. Was 0x14 instead of 0x00
diff 53 address 0x00000039. Was 0xc0 instead of 0x00
diff 54 address 0x0000003a. Was 0x02 instead of 0x00
diff 55 address 0x0000003b. Was 0xe0 instead of 0x00
diff 56 address 0x0000003c. Was 0x00 instead of 0xdb
diff 57 address 0x0000003d. Was 0xc0 instead of 0xf0
diff 58 address 0x0000003e. Was 0x1f instead of 0x21
diff 59 address 0x0000003f. Was 0xe0 instead of 0xe3
No more differences found.
** Verify Failed **
** Resetting Target **
Info : JTAG tap: lpc2138.cpu tap/device found: 0x4f1f0f0f (mfg: 0x787,
part: 0xf1f0, ver: 0x4)
Warn : NOTE! DCC downloads have not been enabled, defaulting to slow memory
writes. Type 'help dcc'.
Warn : NOTE! Severe performance degradation without fast memory access
enabled. Type 'help fast'.
shutdown command invoked
steve@dystant$