Re: [Openocd-development] Incorrect chain detection for SoC...

[Michael S. <rin...@di...>]

Øyvind Harboe wrote:
>>
>> Sounds strange to me. If you want to read the value of a signal changing
>> with a rising clock edge, the only reliable way is to read it *before* the
>> edge.
> 
> A bitbang/software driver really can't address the finer points of
> clocked signals, you'll
> need hw to do that.

I agree with Georg that bitbang *can* do that as long as the PC is the only clock source, ie. no RCLK is needed - it is slower than a real flipflop, but if you do the timing right, it should work 100% of the time. A real flipflop is faster, but if you violate its setup/hold times by changing the data input exactly at the clock edge, you will also get random data (or worse, metastability).

Usually, it should be specified how this is to be handled - like latch input data on the rising edge, and change output data on the falling edge. I do not have a copy of the 1149 spec to check how it is supposed to work in JTAG.

> I'm not a hw guy, but I know that the whole jtag clocked signal
> business is more subtle
> than one might think and especially with arm11 & many devices in the
> chain I've seen
> quirky behaviour that can be hard for sw/bitbang implementations to
> deal with fully.

Can you elaborate that a bit? I have seen JTAG fail due to signal integrity issues on a PCB, but have no experience regarding multiple ARM11.

cu
Michael