Re: [Openocd-development] Incorrect chain detection for SoC...

[Duane E. <op...@du...>]

 > But this lead me to the conclusion that the wiggler parport has no 
analog  problems (aside from the perfectly digital levels at the scope). 
So I've looked into jtag/bitbang.c and read that comment in bitbang_scan():

 >> " Because there is no way to read the signal exactly at the rising 
edge, read after the rising edge."

 > Sounds strange to me. If you want to read the value of a signal 
changing with a rising clock edge, the only reliable way is to read it 
*before* the edge.

Agreed.  Seems 100% wrong to me, and does not match urjtag-0.8

Comparing this with "urjtag" - it is quite different.

----
openocd does it this way:

    src/jtag/bitbang.c - line 181/182
    1)  bitbang_interface-> write(  0, tms, tdi );
          which has a delay internal.
    2)  bitbang_interface-> write(   1, tms,tdi );
          which has a delay internal
    3) Then @ bitbang.c line 200
          it does a read.

Which seems exactly 100% wrong.

I would have expected, this sequence.

        write( 0, tms, tdi );
         tdo =  read()
         write( 1, tms, tdi );

=====
In contrast, (urjtag 0.8 is the version I have)

    UrJtag, does this:
    1)  wiggler_get_tdo() - wiggler.c line 262 file:
        setclock low - [via: PRM_TCK_INACT(cable)]
    2) cable_wait() - line 264
    3)  get_status() [does the read] line 265     

Elsewhere, it sets the clock high.

Which is exactly correct, as I would expect.
======

Interesting comment I saw in the urjtag package, "certain Macraigor 
Wigglers appear to use one of the unused data lines as a power line so 
set all unused pins high".

Q: How are you powering your wiggler?

=====

Do you have any other jtag adapter you can use?

-Duane.