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From: Michael S. <rin...@di...> - 2008-09-14 20:20:13
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Hi, I did some digging - it seems that the write to NVIC_AIRCR in cortex_m3_assert_reset causes the error: >value captured during scan didn't pass the requested check: captured: 0x00 check_value: 0x01 check_mask: 0x0f >in_handler reported a failed check >Invalid ACK in SWJDP transaction I still have no solution for that problem. However, with the attached patch, I can now "reset halt" the CPU, the target stops at the reset vector, *and* resume/step work fine without causing a NMI. It seems any access to NVIC_AIRCR works to fix the problem - either a read, or a write with only the key value but no reset bits set. This looks like some synchronization problem to me, but I will leave that to someone who knows more about the details. I chose a read, since that should have least impact on previously working targets. cu Michael |