From: Werner A. <we...@op...> - 2008-04-29 11:30:43
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Ville Voipio wrote: > - there are planty of parallel port programmers for MSP430, and there > are FT2232-based programmers for MSP430; very very few pieces of > programming hardware actually guarantee the timing to the accuracy given Flash programming parameters get violated all the time. Cypress, for their PSoC parts, even specify the parameters as a function of voltage and temperature. Everybody just shrugs and uses "safe" defaults ;-) The question is just how much the Flash resents those violations ... > A possibility is that the MSP430 flash memory controller clock is > somehow connected to TCK. If this is the case, then another approach has > to be taken (i.e., similar to that with ARM). While under JTAG control, they bit-bang TDI to generate the core clock :-( - Werner |