[Openocd-development] Delay beforte jtag verification for devices withe a very slow startup.

[Magnus L. <lu...@ml...>]

Hello

I have problems connecting openocd to a Stellaris Cortex processor using 
a different JTAG interface than the one embedded on the 811 evalutaion 
board.
The problem is that the processor has a 30ms startup period after reset 
low is released.

My FTDI jtag interface lowers the reset line on USB reset, happens 
wenever OpenOCD is restarted, initializes the  MPSSE mode and then tries 
to verify  the JTAG  connection. This fails because the processor has 
not yet started up. So I have to add a 30-40ms delay between jtag 
interface initialisation and verification of jtag communication.

The reason the evaluation board works is that there is an active high 
jtagenable signal that works as a reset enable and keeps the 
uninitilised ftdi2232 from driving reset low.

This can be made into yet another configuration option or we can 
increase the startup time of OpenOCD by 40ms.

Comments ?

Regards,

Magnus