target/riscv: fix riscv exec_progbuf for SMP targets
flash/stm32l4x: Fix permanent write protection on STM32WBA5
target: rework target_checksum_memory()
flash/nor/bl602: add bl602 flash driver
tcl/target/gd32vf103: adjust reset workaround to new riscv target
tcl/target/gd32vf103: simplify passing of reset halt option
target/riscv: tcl/target: move the WA for GD32VF103 to Tcl
target/aarch64, armv8: avoid adding of error return codes
jtag: xds110: Add libusb_open() result to error log
Thank you!
Please check the discussion on https://review.openocd.org/c/openocd/+/8891, The overlap is there and due to limited space allocated for JEP106 banks (4 bits) we cannot discriminate between "AMD" and "Shenzhen JIEQING Technology Co Ltd". Same issue with all the IDCODE in banks 0 and 16
Clarification on the use of the IDCODE
doc: add hpm_xpi flash driver description
tcl: add config file for hpmicro devices and boards
src/flash/nor: add hpmicro xpi support
contrib/loaders/flash/hpmicro: add hpmicro device xpi support
Change default WORKAREASIZE to 12kbytes for stm32f3x.
tcl: file_renaming: add missing rename ti_beaglebone-base
tcl: file_renaming: drop automatic replecement check
startup.tcl: extend the file search among rename
tcl/board/ti/*: Rename files using "-" separator
board/ti: Rename _swd_native.cfg as -self-hosted.cfg
board/ti_*.cfg: Move TI evm platform configurations to board/ti folder
tcl/board/ti_beagle* move to board/beagle/ folder
tcl/target: Move TI targets to ti folder
tcl/target/stm32l4, tcl/target/stm32w*: Fix clock configuration
tcl/target/gd32vf103: copy a few minor settings from riscv-openocd
target/esirisc_trace: drop macro BIT_MASK() conflicting with bits.h
adapter/gpio: Use command_print() instead of LOG_ERROR()
server: fix a new double free()
Support two-wire cJTAG OSCAN1 and JScan3 using FTDI adapters
target/breakpoints.c: add breakpoint intersection detection
target: cortex-m: defer cache identification on Cortex-M7 under reset
target/cortex_a: emit 'resumed' event for all SMP cores
flash/nor/stm32lx: Add 'option_load' command
rtos: server/gdb_server: fix missing thread ID in stop reply
rtos: server: target: ask the RTOS which target to set swbp on.
jtag/drivers/jtag_dpi: fix wraparound bug in runtest
rtt/tcl: fix format specifiers
doc:style: do not use multiple empty lines
target/cortex_a: fix HW breakpoint length for gdb kind 3
target, breakpoints: report hit watchpoint in trivial case
semihosting: fix memory leak and double free
flash/nor/stm32h7x: Change 'option_read' output
target/cortex_m: do not expose BASEPRI and FAULTMASK registers
target: semihosting: refresh URI to semihosting documentation
helper: command: use COMMAND_HELPER for converted functions
command: return OpenOCD error code as Tcl 'errorCode'
command: on syntax error, run 'usage' inside the same cmd_ctx
command: let 'help' and 'usage' to use command_print()
target/arm_dpm: report vector catch as breakpoint
target/armv4_5: mark registers as 'save-restore'
target/armv4_5: fix register numbering overlap
target/cortex_a: report target in some LOG_xx calls
tcl/interface/raspberrypi-native: adjust speed offsets
jtag/drivers/bcm2835gpio: Support all 54 GPIO pins
target/riscv: fix progbuf memory writes in case last write is busy
tcl/target: update riscv commands in configs
target/riscv: fix SV57 translation for kernel address space
server: rtos: don't fake step for hwthread rtos.
target: riscv: move the SMP commands under riscv
target: riscv: fix double free() in parse_reg_ranges()
target: riscv: fix memory leak in riscv_openocd_step_impl()
checkpatch: enable check for switch/case alignment
target/riscv: fix get mode filed for vsatp and hgatp
target/riscv: fix address translation in hypervisor mode
target/riscv: improve error messaging in case `sbasize` is zero
target/riscv: check nextdm address in abits range
gdb_server,rtos: Differentiate rtos_get_gdb_reg failing and not implemented
rtos: introduce rtos_put_gdb_reg()
doc: riscv: minor fixes in openocd.texi
target/riscv: fix checking of number of parameters
doc: import document changes relevant to riscv code update
target, flash: utility for riscv repeat_read command
target/riscv: return ERROR_TARGET_NOT_HALTED
rtos: Dynamically allocate memory for RTOS registers
target/breakpoints: better wording for error reason
target: riscv-011: don't change 'debug_level' during target polling
target: riscv: don't test 'debug_level' directly
target: riscv: align switch and case statements
target: riscv: Drop new typedefs added by the updated riscv-debug-spec files
target: riscv: Sync with the RISC-V fork
Hello. I think I ve submit a pull request on that. Let me know if the project accepts.
target: cortex-m: don't query cache on hla targets
doc: update copyright year
tcl: add Espressif RISC-V config files
ipdbg: simplify command chains
tcl/target/stm32h7x: modify speed at OpenOCD initialization and
flash/stm32h7x: support STM32H7R/H7Sx
flash/stm32h7x: use BIT macro whenever possible
flash/stm32h7x: Rename functions and variable names
flash/stm32h7x: Refactor STM32H7 flash register definitions to use enum
I've had massive problems with an LPC-Link2 CMSIS adapter on the black USB 2.0 ports of a Raspberry Pi 4. It works flawlessly on the blue USB 3.0 ports. Best regards, Daniel
On Wed, Nov 05, 2025 at 10:57:53AM -0000, Mark W wrote: How did you route around it if you're talking about the USB hub integrated on RaspberryPi 5 board? First of all, it's not a full speed hub there (so the forum thread doesn't apply), second, as seen in doc/usb_adapters/stlink/0483_3757_stlinkv3pwr.txt it's a high speed device so no translation is needed in any case. Are you connecting it via an additional full speed hub? It's a rPi CM5, with the TI USB hub on the parent PCB. I understand how...
This problem appears to be caused by a TI USB hub chip. https://forums.raspberrypi.com/viewtopic.php?t=246248 There is no problem when I route around it, so I'll call this problem solved for the moment. Thanks.
How did you route around it if you're talking about the USB hub integrated on RaspberryPi 5 board? First of all, it's not a full speed hub there (so the forum thread doesn't apply), second, as seen in doc/usb_adapters/stlink/0483_3757_stlinkv3pwr.txt it's a high speed device so no translation is needed in any case. Are you connecting it via an additional full speed hub? It's a rPi CM5, with the TI USB hub on the parent PCB. I understand how that would have been confusing, my apologies. I'm not that...
How did you route around it if you're talking about the USB hub integrated on RaspberryPi 5 board? First of all, it's not a full speed hub there (so the forum thread doesn't apply), second, as seen in doc/usb_adapters/stlink/0483_3757_stlinkv3pwr.txt it's a high speed device so no translation is needed in any case. Are you connecting it via an additional full speed hub? It's a rPi CM5, with the TI USB hub on the parent PCB. I understand how that would have been confusing, my apologies.
If you are asking about the same issue in different forums, it is useful (and polite) to mention this and provide links. https://github.com/libusb/libusb/issues/1717
On Wed, Nov 05, 2025 at 04:36:11AM -0000, Mark W wrote: This problem appears to be caused by a TI UBS hub chip. [1]https://forums.raspberrypi.com/viewtopic.php?t=246248 Hm, but this whole forum discussion doesn't seem to be related, and it's all strange. They reference a forum post on TI E2E that confirms that a certain USB hub model is full speed so naturally it doesn't have any TT (transaction translators) from full/low speed to high speed since it doesn't support any high speed connections at...
This problem appears to be caused by a TI UBS hub chip. https://forums.raspberrypi.com/viewtopic.php?t=246248 There is no problem when I route around it, so I'll call this problem solved for the moment. Thanks.