#547 Limit OPL4 I/O access


Currently, the limits on accessing the I/O of the OPL4 are not emulated.

The limitations are described on page 8 of the application manual:


Address write: 56 cycles (FM) / 88 cycles (PCM)
Data write: 56 cycles (FM) / 88 cycles (PCM)

Loading PCM header data requires a wait of approx 300 µs, see page 10 and 16.

Reading and writing external memory requires these waits, see page 16:

Data write: 28 cycles
Data read: 38 cycles

These are quite specific numbers, but probably some further testing is required to confirm them, as well as the behaviour when access is too fast.


  • SD Snatcher

    SD Snatcher - 2014-09-24

    It's important to mention that those cycles are related to this chip clock: 33.8688MHz.

  • Laurens Holst

    Laurens Holst - 2015-03-07

    After a test with cycle-accurate timing on turboR, I have established that:

    The required wait after an FM address write is 12 R800 clock cycles (6 3.58 MHz bus cycles, 56,77 OPL4 clocks).

    The required wait after a PCM address write is 18 R800 clock cycles (9 3.58 MHz bus cycles, 85,16 OPL4 clocks).

  • Laurens Holst

    Laurens Holst - 2015-03-07

    Regarding the discrepancy between the PCM wait (85.16 clocks vs. 88 clocks in the documentation), note that the R800 outputs the I/O data on the bus for 3 whole bus cycles (28,39 OPL4 clocks), so the OPL4 probably just catches on to the tail of the I/O signal.