Currently, the limits on accessing the I/O of the OPL4 are not emulated.
The limitations are described on page 8 of the application manual:
Address write: 56 cycles (FM) / 88 cycles (PCM)
Data write: 56 cycles (FM) / 88 cycles (PCM)
Loading PCM header data requires a wait of approx 300 µs, see page 10 and 16.
Reading and writing external memory requires these waits, see page 16:
Data write: 28 cycles
Data read: 38 cycles
These are quite specific numbers, but probably some further testing is required to confirm them, as well as the behaviour when access is too fast.