Re: [Openbts-discuss] [USRP-users] USRP clock

[Nghia P. <ngh...@gm...>]

Hello Ian,

 

Does your statement apply to the USRP1 also?

 

i.e: A/D sample clock=DSP clock=52Mhz for the OpenBTS users.

 

Maybe I mixing A/D sample clock (52Mhz) and sample rate (270.833kHz)?

 

Thanks

Nghia

 

 

From: Ian Buckley [mailto:ia...@io...] 
Sent: Tuesday, November 08, 2011 9:31 PM
To: Nghia Phan
Cc: jo...@et...; usr...@li...
Subject: Re: [USRP-users] USRP clock

 

The A/D sample clock and the DSP clock are always the same clock (with
Frequency as Josh stated).

 

On Nov 8, 2011, at 12:16 PM, Nghia Phan wrote:





Hello Josh.

 

OK, so the timestamp increments at a rate of 52Mhz and not 270.833kHz?

 

I'm confused: I have read in the inband_signaling_usb the following:

 

  Timestamp: 32-bit timestamp.

      On IN packets, the timestamp indicates the time at which the

      first sample of the packet was produced by the A/D converter(s)

        for that channel.  On OUT packets, the timestamp specifies the

        time at which the first sample in the packet should go out the

        D/A converter(s) for that channel.  If a packet reaches the

      head of the transmit queue, and the current time is later than

      the timestamp, an error is assumed to have occurred and the

      packet is discarded.  As a special case, the timestamp

      0xffffffff is interpreted as "Now".

 

      The time base is a free running 32-bit counter that is

      incremented by the A/D sample-clock.

 

 

I think the A/D sample-clock is 270.833kHz, right?

 

 

Thanks for your clarification.

Rgds

Nghia

 

-----Original Message-----
From: Josh Blum [mailto:jo...@jo...] On Behalf Of Josh Blum
Sent: Tuesday, November 08, 2011 9:09 PM
To: nghia phan
Cc: usr...@li...
Subject: Re: [USRP-users] USRP clock

 

 

 

On 11/08/2011 12:00 PM, nghia phan wrote:

> Hello Josh,

> 

> How is this DSP clock generated? Its frequency is 270.8333Hkz in the case

> of the OpenBTS application, right?

> 

> 

 

The clock is generated via clock synthesizer chip.

 

On USRP2/N-series the FPGA/DSP clock is 100Mhz

 

On E-series and B-series, the FPGA/DSP clock is configurable. Most

often, OpenBTS users will pick 52Mhz.

 

-Josh

 

> Thanks

> Nghia

> 

> 2011/11/8 Josh Blum <jo...@et...>

> 

>> 

>> 

>> On 11/08/2011 07:02 AM, nghia phan wrote:

>>> Hello,

>>> 

>>> I have a question about the 32-bit counter in the fpga which is used as

>>> timestamp for the samples before being sent to the host.

>>> This counter is incremented using a clock which is derived from the

>>> received data? Or is such clock produced locally?

>>> 

>> 

>> It is a tick counter for the DSP clock. Each clock cycle, +1

>> 

>>> A related question: besides receiving the samples (in IQ format) does
the

>>> host need a clock information ?

>>> 

>> 

>> The host knows the dsp clock rate, so it can convert from ticks to
seconds.

>> 

>> -josh

>> 

>>> Thanks

>>> Nghia

>>> 

>>> 

>>> 

>>> 

>>> _______________________________________________

>>> USRP-users mailing list

>>> USR...@li...

>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

>> 

>> _______________________________________________

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>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com

>> 

> 

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