From: Alexander C. <ale...@gm...> - 2010-06-22 03:50:15
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Hi Ranier, Search mailing list archives. IIRC someone posted the source code a while ago. On Fri, Jun 18, 2010 at 13:55, Ranier Yap <wal...@ya...> wrote: > Hi there, > > I'm interested in obtaining the verilog code for the USRP fpga configured > for the use of OpenBTS. I've realized in your code > (USRPDevice.cpp) that you're using an Altera raw bit file named > "std_inband.rbf" to configure the USRP fpga. However, I'm unable to > find the the "std_inband" module (& submodules) in the repository at > Ettus.com. I believe the verilog modules and/or configurations > probably differs from those on the Ettus website. Would you be able to link > me the website or send me the verilog code? > > Thanks in advance. > > ------------------------------------------------------------------------------ > ThinkGeek and WIRED's GeekDad team up for the Ultimate > GeekDad Father's Day Giveaway. ONE MASSIVE PRIZE to the > lucky parental unit. See the prize list and enter to win: > http://p.sf.net/sfu/thinkgeek-promo > _______________________________________________ > Openbts-discuss mailing list > Ope...@li... > https://lists.sourceforge.net/lists/listinfo/openbts-discuss > > -- Regards, Alexander Chemeris. http://www.fairwaves.ru |