[Ngspice-devel] Re: [Help-gnucap] "binning" of models (fwd)

[<mcm...@mt...>]

hope this helps

-dan


---------- Forwarded message ----------
Date: Thu, 10 Jan 2002 11:31:41 -0500 (EST)
From: mcm...@mt...
To: Al Davis <al...@ie...>
Cc: hel...@gn...
Subject: Re: [Help-gnucap] "binning" of models



HI Al,

took me a bit to get this reply sent, but better late than never....

On Wed, 21 Nov 2001, Al Davis wrote:

> On Wednesday 14 November 2001 07:25 pm, mcm...@mt... wrote:
> > Is it possible to have a library of "binned" models?  Ie, in hspice
> > and spectre, you can have different bsim3v3 model parameters for
> > devices of different widths and the simulator automatically selects
> > the correct model.  For example, you might have a 1um to 5um model,
> > a 5um to 10um, and a >10um model.
> >
> > specifying a 7.5/0.35 um device would automatically choose the 5-10
> > model.
> 
> Not now.
> 
> As to when ....  I have higher priorities that will keep me busy for 
> a while, but I would welcome it if you or someone else could do it.
> 
> It would be easy to add the  LMIN, LMAX, WMIN, WMAX, LREF, WREF 
> parameters, but resolving the multiple models is significant work.  
> It is not clear from the HSpice manual what the syntax is when there 
> are multiple bins.   Multiple .model cards with the same name??  It 
> is also not clear how discontinuities at bin boundaries are resolved. 
>  Apparently, only certain parameters can be binned.


Here's a shortened example (I can't give out the detailed parameters):

this particular library lets you select process corners by doing things
like:

.lib 'mylib.l' TT

for typical NMOS, typical PMOS

.lib 'mylib.l' FS

for fast NMOS, slow PMOS, etc.

Then in the library file there are things like:

.LIB TT
* this sets up the parameters which are varied to
* simulate different process corners
.param
+toxn   = 4.08E-09        toxp   = 4.08E-09       
+dvthn  = 0               dvthp  = 0              
+dxl    = 0               dxw    = 0              
+cjn    = 0.001           cjp    = 0.001       
+cjswn  = 2.0E-10         cjswp  = 2.4E-10      
+cjswgn = 3.3E-10         cjswgp = 4.2E-10      
+cgon   = 3.6E-10         cgop   = 3.2E-10      
+hdifn  = 2E-07           hdifp  = 2E-07          
.lib 'mylib.l' MOS
.ENDL TT

there are different sections for the TT,SS,FF, SF, and FS

Then in the MOS section you see things like:

.LIB MOS
.MODEL nch.1            NMOS   (     LMIN     =  '1.2E-06-dxl'   
+LMAX    = 2.1E-05        WMIN     = '1.01E-05-dxw' WMAX     = 0.000101       
+NLEV     = 3             AF       = 0.8            KF       = 9.3E-25
+LEVEL   = 49             TNOM     = 25             VERSION  = 3.1            
+TOX     = toxn           XJ       = 1.6E-07        NCH      = 3.9E+17        
+VTH0    = '0.4+dvthn'    LVTH0    = 4.0E-08        WVTH0    = -1.4E-07   
* rest of model not shown....
)

.MODEL nch.2            NMOS   (                    LMIN     = '5E-07-dxl'      
+LMAX    = '1.2E-06-dxl'  WMIN     = '1.01E-05-dxw' WMAX     = 0.000101       
+NLEV     = 3             AF       = 0.82           KF       = 9.9E-25
+LEVEL   = 49             TNOM     = 25             VERSION  = 3.1            
+TOX     = toxn           XJ       = 1.6E-07        NCH      = 3.9E+17        
+VTH0    = '0.5+dvthn'    LVTH0    = 1.3E-08        WVTH0    =1.03-07    
* rest of model not shown....
)

*and then there are a handful more models (nch.{3,4,5...}) and also
*ones for pmos.  
.ENDL MOS

When you call out 'nch' as the model when you instantiate a NMOS in your
netlist, hspice uses the LMIN,LMAX,WMIN,WMAX to figure out which model to
actually use for that device.  Also, the parameters listed in the process
corner section are substituted to give an appropriate process skew.

No effort is made to ensure a nice transition between bins in the models.
I think they just make a few devices in each range and do a full model
extraction and treat them as different devices.

Hope this helps shed some light on how hspice handles it.

-Dan