Re: [Ngspice-devel] IBIS model support

[j s <j....@gm...>]

On 4/21/14, 3:17 PM, Francesco Lannutti wrote:
> Hi Simon,
> as far as I know, and as you said, IBIS model is just a connection of simple SPICE components, which acts together to model an FPGA, for instance.
> So, IMHO, it’s better to have a program which outputs a subcircuit for NGSPICE and use components already present in it.
IBIS buffers may have capacitors on their load, but for the most part 
they are table driven models.  There are tables for the rising and 
falling voltage wave forms versus time.  The currents through the 
pullup, pulldown, ground clamps, and power clamps are current vs voltage 
tables for different load conditions.  These tables have to somehow be 
averaged together.

It is not an easy prospect.  It is a standard:
http://www.vhdl.org/ibis/about/

An older implementation in Verilog A is here:
http://www.vhdl.org/ibis/macromodel_wip/archive/20051005/arpadmuranyiintel/Verilog-A%20sample%20buffer%20data/IBIS_macro_library.va


Good Luck!



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> Fra
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