Hi All:
Zet processor is written in verilog. http://zet.aluzina.org/index.php/Zet_processor
I want to use it as a model in ngspice. Can I use adms change verilog into C, and use Zet processor in ngspice?
Thanks!
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The processor is most certainly described at the gate or RTL level.
To simulate this reasonably you need a verilog simulator. From the free software world I would recommend icarus verilog, which I know myself to work well.
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Thanks!
But I still want to know that can I use ADMS to change verilog into C, and use it in ngspice?For example, the verilog files from OpenCore http://opencores.org/.
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opencores too is talking about digital circuits. adms is a tool to translate
device models written in verilog-a to c code wich can be linked with various
spice's to make those models available in these spice's.
These models are "analog" models, decribing nonlinear differential equations.
The sort of things you are talking about really doesn't have anything to do with verilog-a or spice. Again, look at the icarus verilog simulator, which will at least help you to understand what the original digital verilog is meant to be about.
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Thanks!
I asked this question because I already have an eda software which can simulate spice file. And I notice that xspice have AND/OR/NOT gate models. If I can synthesis verilog files to gate level and change it into spice file with gates models, I can simulate verilog with my eda software.
Last edit: fiveight 2017-01-17
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This might work from a purely functional viewpoint, but xpice models might
not tell you all you want to know about timing violations, so tread
carefully. Presumably you have other software that does this?
I once worked for a large semiconductor company who for smallish digital
circuits on mixed signal IC's would synthesize to gate level then use this
to create a Spice netlist at transistor level which could then be used in
mixed signal Monte Carlo simulations.
Yes, I don't care timing violations and other aspects, I just want a purely functinal simulation.
Is there any open source software which can synthesize verilog file to spice netlist file?
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And I notice that xspice have AND/OR/NOT gate models.
Please note this remark that I found in a commercial SPICE manual:
"Gate delays in XSPICE are stored i.e. like a transmission line not like a real gate. Gate delays in other simulators may be inertial, so that if a pulse shorter than the propagation delay is received, it is swallowed and not transmitted."
-marcel
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Hi fiveight,
what you need to create is called CDL. Basically you need to map your gate level to a technology (if not already) and then substitute each gate with the equivalent SPICE subcircuit and then run the simulation.
I don't know if it exists a free tool for doing that, but most of the commercial LVS tools do it.
Fra
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Hi All:
Zet processor is written in verilog. http://zet.aluzina.org/index.php/Zet_processor
I want to use it as a model in ngspice. Can I use adms change verilog into C, and use Zet processor in ngspice?
Thanks!
The processor is most certainly described at the gate or RTL level.
To simulate this reasonably you need a verilog simulator. From the free software world I would recommend icarus verilog, which I know myself to work well.
Thanks!
But I still want to know that can I use ADMS to change verilog into C, and use it in ngspice?For example, the verilog files from OpenCore http://opencores.org/.
opencores too is talking about digital circuits. adms is a tool to translate
device models written in verilog-a to c code wich can be linked with various
spice's to make those models available in these spice's.
These models are "analog" models, decribing nonlinear differential equations.
The sort of things you are talking about really doesn't have anything to do with verilog-a or spice. Again, look at the icarus verilog simulator, which will at least help you to understand what the original digital verilog is meant to be about.
Thanks!
I asked this question because I already have an eda software which can simulate spice file. And I notice that xspice have AND/OR/NOT gate models. If I can synthesis verilog files to gate level and change it into spice file with gates models, I can simulate verilog with my eda software.
Last edit: fiveight 2017-01-17
This might work from a purely functional viewpoint, but xpice models might
not tell you all you want to know about timing violations, so tread
carefully. Presumably you have other software that does this?
I once worked for a large semiconductor company who for smallish digital
circuits on mixed signal IC's would synthesize to gate level then use this
to create a Spice netlist at transistor level which could then be used in
mixed signal Monte Carlo simulations.
--
Kind regards,
Justin Fisher.
Yes, I don't care timing violations and other aspects, I just want a purely functinal simulation.
Is there any open source software which can synthesize verilog file to spice netlist file?
Please note this remark that I found in a commercial SPICE manual:
"Gate delays in XSPICE are stored i.e. like a transmission line not like a real gate. Gate delays in other simulators may be inertial, so that if a pulse shorter than the propagation delay is received, it is swallowed and not transmitted."
-marcel
Hi fiveight,
what you need to create is called CDL. Basically you need to map your gate level to a technology (if not already) and then substitute each gate with the equivalent SPICE subcircuit and then run the simulation.
I don't know if it exists a free tool for doing that, but most of the commercial LVS tools do it.
Fra
Does this be of help?
https://www.reddit.com/r/yosys/comments/488k8h/writing_spice_output/
http://www.clifford.at/yosys/
Holger
Yosys is used in Tim Edwards Qflow which is very much worth looking into.
http://opencircuitdesign.com/
--
Kind regards,
Justin Fisher.
On Wed, Jan 18, 2017 at 2:40 PM, Holger Vogt h_vogt@users.sf.net wrote:
Thanks!
I will try yosys.