Menu
▾
▴
1 Attachments
#641 Digital components simulation issue
System: Windows 11 x64.
I use ngspice .exe.
For the attached schema file, set the compatibility mode to "set ngbehavior=ltpsa".
Run the simulation.
We display the signals "C", "D", "C_AND_D" and see that the signal "C_AND_D" has needles, but this should not be the case.
Sorry, signals "QC", "QD" and "C_AND_D".
Please explain why you considers this being a bug (QC and QD are slightly overlapping).
Assume that the rise and fall times of both signals are the same, for example 15 nanoseconds.
For the moment where the needle is present:
QC, start of fall: signal level 1
QD, start of rise: signal level 0
QC AND QD = 0
QC, end of fall: signal level 0
QD, end of rise: signal level 1
QC AND QD = 0
Maybe I'm wrong, but I think so.
The simulation tells me that there is a 2ns overlap of qc and qd, that is qd is rising, and only 2ns later qc start falling.
See attached your input file modified with somewhat scaled time axis, to allow better plotting, and with a .control section for standard ngspice.
The vcd file is made for plotting with gtkwave.
I do not know if a 2ns overlap and a thus resulting glitch is reasonable. Asynchronous logic with fast devices (LS) is prone to glitches.
Last edit: Holger Vogt 2023-07-28
I tried connecting a 74LS42 - pin graphs have needles that appear on even pins. I tried to reproduce this circuit on MicroCap 12 - I have only one needle on the "O8" signal graph :( I understand that this behavior is related to the replacement of PSPICE with logic elements. I don't think it can be fixed.
Holger, Sergij, the glitches that still appear in Holger's improved example (with the clock pulse changes) are due to the timing delays that are estimated for the JKFF instances when translating from Pspice to Xspice in ngspice. In the 74LS90 subckt the JKFF instances specify D0_EFF Pspice timing models. When these timing models are translated the Xspice delays should be as close to zero as possible (that is 1.0e-12) rather than leaving the delays unspecified in the current ngspice (they default to 1ns). The other delays in 74LS90 are estimated as 26ns from the DELAYs in the PINDLY statement and will add to the JKFF delays (1ns default).
Holger, I have changed setting the JKFF (also dff and latches) Pspice zero timing delays to specify the 1.0e-12 minimum Xspice delay values. Then the glitches on C_AND_D disappear.
If you like, the change on bt_dev could go into the upcoming ngspice-41 release.
Sergij, with the delay changes I have made your digi_74LS90_74LS42.cir runs more cleanly. However, you could insert DFFs between the 74LS90 outputs and the 74LS42 inputs, with a sampling clock on the DFFs timed to be just after all the 74LS90 outputs have become stable.
One point I forgot to mention concerns inertial delays in digital simulation. To completely suppress the glitch on C_AND_D, use this model:
.model And_U d_and (
The glitch with the 1.0e-12 delays is now small enough to be completely suppressed by this AND gate model. This will apply to ngspice-40 and a build from the latest github master branch.
When we think about real devices, is inertial delay something that is happening (sometimes or always)?
If yes, should we make it standard (and make "no inertial delay" the option)?
The 74LS42 datasheets from TI and ONSemi show a design where glitches should be expected. The outputs are from NAND gates with inputs of varying delays from the inputs, as some inputs are inverted and others direct. There are no extra buffers to equalise delay. Glitches are acceptable if driving Nixie tubes!
So a problem with setting inertial delay throughout is that such behaviour may be suppressed. A possible, but complicating, fix might be for the logic primitives to have separate values for transport and inertial delays.
Sergij, I have attached an updated digi_74LS90_74LS42.cir which includes subckt sampler4. This subckt (instance X_15) samples the Q outputs of 74LS90 60ns after the falling edges of CLOCK when the Q outputs are stable. The outputs of the sampler4 are used as the inputs to 74LS42 whose outputs now do not have glitches. The subckt sampler4 uses Xspice digital primitives since at the moment we don't support Pspice DLYLINE devices.
Brian, thank you for your help with the sync issue. I also made a circuit like yours, but I forgot to add the timing on the inverter, so my signal was slightly off in time.
But I wonder what will happen with the inertial delay (what Giles wrote about).
Sergij, the new ngspice-41 release will convert a PSpice DLYLINE into an XSPICE equivalent. The attached circuit file contains .subckt delayed4 with U devices which ngspice-41 can handle. You will need to comment out the .control...endc section for MicroCap. There are no plans I am aware of for changing the delays of the XSPICE gate primitives that Giles mentioned. The current ngspice behavior is to use inertial delays for gate primitives that are generated when U devices in a .subckt are translated to XSPICE. This matches how PSpice and MicroCap behave for digital simulation of gates. In ngspice-41, a U DLYLINE is translated into a buffer with transport delay so that glitches are not swallowed and propagate through.
Last edit: Brian Taylor 2023-08-16
Sergij, Holger I have made a change in commit 5d34d6fd032e3c5ed9c2c4e00814177a554eeebb
which makes the original testcase digi_74LS90_74LS42.cir behave very similarly in ngspice and MicroCap 12. No extra sampling instance is necessary. The not_y8 signal is the only one with a glitch in both ngspice and MicroCap.
Run: gtkwave --script=nggtk.tcl digi_74LS90_74LS42.vcd
to see the latest ngspice behavior.
Here is the vcd file
Fixed in ngspice 42